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Bradley Evans bradley-evans

  • University of California, Riverside
  • Riverside, CA
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#include <stdio.h>
int timer() {
int runtime = 0;
int a = 10;
asm volatile("fence\n"
"rdtime x10\n"
"lw x13, %[temp]\n"
"rdtime x11\n"
"sub %[result], x11, x10\n"
linux-vdso.so.1 (0x00007ffc7bac4000)
libmpc.so.3 => /usr/lib/x86_64-linux-gnu/libmpc.so.3 (0x00007fb994e9d000)
libmpfr.so.6 => /usr/lib/x86_64-linux-gnu/libmpfr.so.6 (0x00007fb994c1d000)
libgmp.so.10 => /usr/lib/x86_64-linux-gnu/libgmp.so.10 (0x00007fb99499c000)
libdl.so.2 => /lib/x86_64-linux-gnu/libdl.so.2 (0x00007fb994798000)
libz.so.1 => /lib/x86_64-linux-gnu/libz.so.1 (0x00007fb99457b000)
libm.so.6 => /lib/x86_64-linux-gnu/libm.so.6 (0x00007fb9941dd000)
libc.so.6 => /lib/x86_64-linux-gnu/libc.so.6 (0x00007fb993dec000)
/lib64/ld-linux-x86-64.so.2 (0x00007fb9950b5000)
/dts-v1/;
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
compatible = "enjoy-digital,litex-vexriscv-soclinux";
model = "VexRiscv SoCLinux";
chosen {
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2020-03-03 13:41:05)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
make: Entering directory '/home/brad/dev/linux-on-litex-vexriscv/build/arty/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/brad/dev/linux-on-litex-vexriscv/build/arty/software/libcompiler_rt'
make: Entering directory '/home/brad/dev/linux-on-litex-vexriscv/build/arty/software/libbase'
CC exception.o
CC system.o
CC id.o
CC uart.o
CC time.o
CC spiflash.o
make: Entering directory '/home/brad/dev/linux-on-litex-vexriscv/build/arty/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/brad/dev/linux-on-litex-vexriscv/build/arty/software/libcompiler_rt'
make: Entering directory '/home/brad/dev/linux-on-litex-vexriscv/build/arty/software/libbase'
CC exception.o
CC system.o
CC id.o
CC uart.o
CC time.o
CC spiflash.o
[200~INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2020-03-03 13:49:14)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
make: Entering directory '/home/brad/dev/linux-on-litex-vexriscv/build/arty/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/brad/dev/linux-on-litex-vexriscv/build/arty/software/libcompiler_rt'
make: Entering directory '/home/brad/dev/linux-on-litex-vexriscv/build/arty/software/libbase'
CC exception.o
CC system.o
CC id.o
CC uart.o
CC time.o
CC spiflash.o
ZINFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2020-03-03 13:51:07)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
cd /home/brad/dev/fpga-zynq/common/../testchipip && java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar ~/dev/chipyard/generators/rocket-chip/sbt-launch.jar ++2.11.12 package
OpenJDK 64-Bit Server VM warning: Ignoring option MaxPermSize; support was removed in 8.0
[info] Loading project definition from /home/brad/dev/fpga-zynq/testchipip/project
[info] Loading settings from build.sbt ...
[info] Set current project to testchipip (in build file:/home/brad/dev/fpga-zynq/testchipip/)
[info] Setting Scala version to 2.11.12 on 0 projects.
[info] Excluded 1 projects, run ++ 2.11.12 -v for more details.
[info] Reapplying settings...
[info] Set current project to testchipip (in build file:/home/brad/dev/fpga-zynq/testchipip/)
[info] Compiling 19 Scala sources to /home/brad/dev/fpga-zynq/testchipip/target/scala-2.12/classes ...