corecode

% sigrok-cli -d maynuo-m97 -c conn=/dev/ttyUSB1 -l 5 --scan
sr: [00:00.000001] log: libsigrok loglevel set to 5.
sr: [00:00.000088] backend: libsigrok 0.5.0-git-efde67a/3:0:0 (rt: 0.5.0-git-efde67a/3:0:0).
sr: [00:00.000150] backend: Libs: glib 2.48.2 (rt: 2.48.2/4802:2), libzip 1.1.3, libserialport 0.1.1/1:0:1 (rt: 0.1.1/1:0:1), libusb-1.0 1.0.20.11004, libftdi 1.3.
sr: [00:00.000183] backend: Host: x86_64-unknown-linux-gnu, little-endian.
sr: [00:00.000210] backend: SCPI backends: TCP, RPC, serial, USBTMC.
sr: [00:00.000294] backend: Sanity-checking all drivers.
sr: [00:00.000323] backend: Sanity-checking all input modules.
sr: [00:00.000367] backend: Sanity-checking all output modules.
sr: [00:00.000386] backend: Sanity-checking all transform modules.

corecode

module por
  #(
    parameter cycles = 2
    )
(
 output por,
 input clk
 );

corecode

#include <stdio.h>
#include <unistd.h>
#include <time.h>
#include <stdint.h>
#include <pthread.h>

int p[2];
int n = 100000;

void *

corecode

module pulse
  (
   clk,
   cathode,
   anode
   );

parameter on_time = 100;
parameter off_time = 10000;

corecode

#include <mchck.h>

PORT_Type *
pin_physport_from_pin(enum pin_id pin)
{
        switch (pin_port_from_pin(pin)) {
        case PIN_PORTA:
                return (PORTA);
        case PIN_PORTB:
                return (PORTB);

corecode

Bus 001 Device 103: ID 15a2:0073 Freescale Semiconductor, Inc. 
Device Descriptor:
  bLength                18
  bDescriptorType         1
  bcdUSB               2.00
  bDeviceClass            0 
  bDeviceSubClass         0 
  bDeviceProtocol         0 
  bMaxPacketSize0        16
  idVendor           0x15a2 Freescale Semiconductor, Inc.

corecode

    if @program_word_code
      startaddr = 0x20000000
      dataaddr = startaddr + @program_word_code.length * 4
      @dap.write(startaddr, @program_word_code + data)
      self.set_register!(:r0, dataaddr)
      self.set_register!(:r1, addr | 0x06000000)
      self.set_register!(:r2, data.length)
      self.set_register!(:pc, startaddr)
      self.continue!
      while !self.core_halted?

corecode

;;;  -*- lexical-binding: t; -*-

(defmacro mkclosure ()
  (lambda (a) 1))

(mkclosure)

corecode

package main;

type inst struct {
	store map[idx]*valT
}

type idx struct {
	a,b int
}

corecode

c$$$  APPENDIX G
c$$$  DESICCANT PROGRAM LISTING
c$$$
c$$$  A iisting of the computer code DESICCANT is given in this
c$$$  Appendix. Various modeis for the performance of siiica ge1 beds
c$$$  can be tested through choice of appropriate control parameters.
c$$$  Modeis 1 and 2 can be obtained by setting SSR = O with appropri-
c$$$  ate vaiues for NW and Le. Mode] 3 can be obtained by setting SSR
c$$$  equal to unity and NUDSEN equal to zero. Resuits for Model 4 can
c$$$  be obtained by setting both SSR and NUDSEN equa} to unity. If it