corecode

#include <mchck.h>

extern void main(void);

static uint8_t stack[2048] __attribute__((aligned(16), used));

__attribute__((__externally_visible__))
void
_start(void)
{

corecode

#ifndef USE_PCH

#include <iostream>
#include <sstream>

#include <boost/spirit/include/qi.hpp>
#include <boost/spirit/include/phoenix.hpp>

#else

corecode

#include "headers.hpp"

namespace qi = boost::spirit::qi;
namespace phoenix = boost::phoenix;

namespace sexp {
        namespace qi = boost::spirit::qi;
        namespace ascii = boost::spirit::ascii;

        template <typename Iterator>

corecode

#include <mchck.h>

#include "queue.h"


struct exception_frame {
        /* saved by scheduler entry */
        uint32_t r4, r5, r6, r7, r8, r9, r10, r11;
        /* saved by CPU */
        uint32_t r0, r1, r2, r3, r12, lr, ret, xpsr;

corecode

#include <mchck.h>

#include "queue.h"


struct exception_frame {
        /* saved by scheduler entry */
        uint32_t r4, r5, r6, r7, r8, r9, r10, r11;
        /* saved by CPU */
        uint32_t r0, r1, r2, r3, r12, lr, ret, xpsr;

corecode

#include <mchck.h>

#include "queue.h"


struct exception_frame {
        /* saved by scheduler entry */
        uint32_t r4, r5, r6, r7, r8, r9, r10, r11;
        /* saved by CPU */
        uint32_t r0, r1, r2, r3, r12, lr, ret, xpsr;

corecode

#include <mchck.h>

#include "queue.h"


struct thread {
        uint32_t sp;
        STAILQ_ENTRY(thread) runq;
};

corecode

#include <mchck.h>

struct thread *runq;
struct thread *active;

struct thread {
        struct thread *next;
        uint32_t r4, r5, r6, r7, r8, r9, r10, r11;
        uint32_t sp;
};

corecode

Dump of assembler code for function semihosting_write:
   0x00000008 <+0>:     sub     sp, #16
   0x0000000a <+2>:     mov     r3, r1
   0x0000000c <+4>:     movs    r0, #5
   0x0000000e <+6>:     add     r1, sp, #4
=> 0x00000010 <+8>:     bkpt    0x00ab
   0x00000012 <+10>:    mov     r0, r3
   0x00000014 <+12>:    add     sp, #16
   0x00000016 <+14>:    bx      lr
End of assembler dump.

corecode

static int
semihosting_op(enum semihosting_op op, const void *args)
{
        register uint32_t op_ asm ("r0") = op;
        register uint32_t args_ asm ("r1") = (uintptr_t)args;
        register int ret asm ("r0");

        __asm__ volatile ("bkpt 0xab" : "=r" (ret) : "0" (op_), "r" (args_));
        return (ret);
}