cr1901

CFLAGS=
CPPFLAGS=
LDFLAGS=
LIBS=
RM=rm
RMFLAGS=-f
INSTALL=install


i2ceprog: i2ceprog.c 

cr1901

#!/usr/bin/env python

if __name__ == '__main__':
	#Python 3 compatibility stuff
	try:
		input = raw_input
	except:
		pass
	
	data_setup_time = 10

cr1901

`ifdef LM32_CONFIG_V
`else
`define LM32_CONFIG_V

//
// EXCEPTION VECTORS BASE ADDRESS
//

// Base address for exception vectors
`define CFG_EBA_RESET 32'h00000000

cr1901

#include "libgccvb/libgccvb.h"
#include "gamectl.h"
#include <limits.h>

void draw_line(short start_x, short start_y, short start_z, \
	short end_x, short end_y, short end_z);
void inline plot_point(short x, short y, short z);
/* void inline convert_octant(short * dx, short * dy, short * z); */
int sign(int i);
int iabs(int i);

cr1901

HC=ghc
CFLAGS=-std=c99 -DIVORY_TEST

.c.o:
        $(CC) $(CFLAGS) -c -o $@ $*.c

fib.out: fib_tutorial.o fib_main.o
        $(CC) $(LDFLAGS) -o fib.out fib_main.o fib_tutorial.o

fib_main.o: fib_tutorial.c fib_tutorial.h ivory.h ivory_asserts.h

cr1901

Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> WARNING:Xst:1583 - You are using an internal switch '-use_new_parser'.
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution
   for the specified device family. You are free to use it in order to take
   advantage of its enhanced HDL parsing/elaboration capabilities. However,
   please be aware that you may be impacted by  language support differences.
   This version may also result in circuit performance and device utilization
   differences for your particular design. You can always revert back to the
   default XST solution by setting the "use_new_parser" option to value "no" 

cr1901

class MercXCVRs(Module):
    def __init__(self, pads):
        self.pin_in = Signal(30)  # Create the input bus from the FPGA pins
        self.pin_out = Signal(30) # The output bus to the FPGA pins
        self.pin_oe = Signal(30)  # Output enable for FPGA pins         
        self.iobufs = [TSTriple() for i in range(30)]
        # self.pins = pads.raw_bits()
        self.mem_cen = Signal(1)
        self.bussw_oen = Signal(1)
        

cr1901

#lang racket
(define (my_closure x) ;Return a fcn which adds x to its input.
  (define copy-of-x x)
  (lambda (y)
    (set! copy-of-x (+ copy-of-x y))
    copy-of-x
    )
  )

(define copy-of-my-closure (my_closure 4))

cr1901

#!/bin/sh

if [ $# -le 1 ]; then
  echo "Please specify a start URL and an output file..."
  exit 1
fi

TW_URL=$1

# Yes, I am parsing HTML with regex. I don't care!

cr1901

from migen.fhdl.std import *
from migen.fhdl import verilog

class ModB(Module):
    def __init__(self):
        self.out_b = Signal()

        ###
        
        self.sync += [self.out_b.eq(~self.out_b)]