duck2

<?xml version="1.0"?>
<xsd:schema xmlns:xsd="http://www.w3.org/2001/XMLSchema">

  <xsd:complexType name="hello">
    <xsd:sequence>
      <xsd:element name="greeting" type="xsd:string"></xsd:element>
      <xsd:element name="name" type="xsd:string" maxOccurs="unbounded"></xsd:element>
    </xsd:sequence>
  </xsd:complexType>

duck2

#include <cstring>
#include <memory>
#include <iostream>
#include <string>
#include <vector>

#include "pugixml.hpp"

struct t_hello;

duck2

Difference between XSD-generated and hand-written arch structures

Metadata

Hand-written structure:

struct t_metadata_dict : std::unordered_map<
                             std::string,
                             std::vector<t_metadata_value>>

duck2

#include <memory>
#include <string>
#include <vector>

namespace fpga_architecture {

struct t_meta;
struct t_port;
struct t_model_type;
struct t_fill;

duck2

#include <cstring>
#include <fstream>
#include <iostream>
#include <unordered_map>
#include <stack>
#include <vector>

#include <libxml/parser.h>
#pragma pack(1)

duck2

/* A Verilog VGA module without state machines or weird bit assignments.
 * Works with 50MHz clock, 800x600@72Hz. */
module vga(clk, in_R, in_G, in_B, out_R, out_G, out_B, Hsync, Vsync, video_on, x, y);

input clk, in_R, in_G, in_B;

output wire out_R, out_G, out_B, Hsync, Vsync, video_on;
output reg[9:0] x, y;

/* counters. increment y at the start of hsync. reset x at the end of front porch. */