-
Install Quartus and ModelSim - get the Combined Files tar archive from here
-
Add Quartus bin dir to PATH, e.g.
/space/eda/intelFPGA_lite/19.1/quartus/bin
-
Add ModelSim bin dir to PATH, e.g.
/space/eda/intelFPGA_lite/19.1/modelsim_ase/linuxaloem
-
Install 32-bit ncurses for ModelSim
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# Simply change the project settings in this section | |
# for each new project. There should be no need to | |
# modify the rest of the script. | |
set tb_name tb_top | |
set library_file_list [list \ | |
work [list \ | |
../../src/rtl/top.v \ | |
../../src/tb/$tb_name.v] \ |
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#!/usr/bin/env python3 | |
''' | |
Script to calculate STM32F0x RTC calibration values based on a measured time variation. | |
All references to STM32 RM0091: 25.4.12 RTC smooth digital calibration | |
''' | |
from datetime import datetime | |
# set rtc ideal freq |
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sudo dpkg --add-architecture i386 | |
sudo apt update | |
sudo apt install -y libc6:i386 libxtst6:i386 libncurses5:i386 libxft2:i386 libstdc++6:i386 libc6-dev-i386 lib32z1 libqt5xml5 liblzma-dev | |
wget https://download.altera.com/akdlm/software/acdsinst/20.1std/711/ib_installers/ModelSimSetup-20.1.0.711-linux.run | |
chmod +x ModelSimSetup-20.1.0.711-linux.run | |
./ModelSimSetup-20.1.0.711-linux.run --mode unattended --accept_eula 1 --installdir $HOME/ModelSim-20.1.0 --unattendedmodeui none | |
# Here you need to add "$HOME/ModelSim-20.1.0/modelsim_ase/bin" to your PATH |
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# Prepare system | |
FROM ubuntu:20.04 | |
RUN apt-get update | |
RUN apt-get install -y build-essential flex gperf bison libreadline6-dev libncurses5-dev autoconf | |
# Copy sources | |
COPY ./iverilog /src/iverilog | |
COPY ./pint_iverilog /src/pint_iverilog | |
WORKDIR /src |
Can't find EBYTE test board E73-TBM-01 V1.0 schematic, so figured out connections by myself:
NRF52832 | E73-2G4M04S1B | Connected to |
---|---|---|
P0.05 | 21 | CH340G CTS |
P0.06 | 22 | CH340G RX |
P0.07 | 23 | CH340G RTS |
P0.08 | 24 | CH340G TX |
P0.13 | 29 | SW2 (act. low) |
P0.14 | 30 | SW1 (act. low) |
Use Verible Code Obfuscator for obfuscation.
Obfuscate foo.v
and save dictionary with all replacements:
verible-verilog-obfuscate --save_map obf.map < foo.v > foo_obf.v
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[alias] | |
a = add | |
b = branch | |
s = status --short | |
c = commit -m | |
d = diff | |
co = checkout | |
dc = diff --cached | |
dw = diff --word-diff | |
ds = diff --stat |
Based on pep8-git-hook.
Every staged Python file will be checked.
Installation:
- Install the pycodestyle (formally called pep8) program:
$ pip install pycodestyle
- Save pre-commit as your_project/.git/hooks/pre-commit
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#!/bin/bash | |
# Create virtual environment | |
virtualenv .venv | |
# Install Jupyter Notebook | |
.venv/bin/pip install jupyter notebook tornado\<6 | |
# Install scientific packages | |
.venv/bin/pip install numpy scipy matplotlib |
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