fcayci

import numpy as np
from PIL import Image as im

a = im.open('s2.png')
b = np.array(a)
print('loaded image with shape:', b.shape)


# print color matrix
for i in range(b.shape[0]):

fcayci

-- Lab1 for FPGA course
library ieee;
use ieee.std_logic_1164.all;

entity lab1 is
-- btns are inputs of the circuit
-- leds are outputs of the circuit
port (
    btn : in std_logic_vector(3 downto 0);
    led : out std_logic_vector(3 downto 0)

fcayci

-- 1-bit full adder
library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
    -- x, y, cin are inputs of the adder
    -- s (sum), cout (carry) are outputs of the adder
    port ( x, y : in  std_logic; cin : in std_logic; 
           s : out std_logic; cout : out std_logic );
end full_adder;

fcayci

## This file is a general .xdc for the ARTY Z7-20 Rev.B
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

## Clock Signal
#set_property -dict { PACKAGE_PIN H16    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set

## Switches

fcayci

#include <stdio.h>
#include "xparameters.h"
#include "platform.h"
#include "xil_printf.h"

// Get these from xparamters.h
#define BRAMBASE XPAR_BRAM_0_BASEADDR
#define BRAMHIGH XPAR_BRAM_0_HIGHADDR

int main()

fcayci

/*
 * gpio_test.c
 *
 *  Created on: Nov 23, 2018
 *      Author: fcayci
 */

#include <stdio.h>
#include "xparameters.h"
#include "xil_printf.h"

fcayci

library ieee;
use ieee.std_logic_1164.all;

entity fsm_tb is
end fsm_tb;

architecture rtl of fsm_tb is
    component fsma is
    port(
        clk, rst : in std_logic;

fcayci

## This file is a general .xdc for the Arty-Z20, PYQN-Z1 and PYNQ-Z2 boards

## Clock signal 125 MHz

set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];

##Switches

#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L7N_T1_AD2N_35 Sch=sw[0]

fcayci

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
port (
    clk, rst, en : in std_logic;
    count : out std_logic_vector(3 downto 0)
    );
end counter;

fcayci

# Make sure ghdl and gtkwave is in your PATH
SRCS = design.vhd
TB = design_tb.vhd

CC = ghdl
SIM = gtkwave

ARCHNAME=$(shell grep architecture $(TB) | cut -f 4 -d ' ')
SIMNAME = wave.vcd