Skip to content

Instantly share code, notes, and snippets.

View ikwzm's full-sized avatar

KAWAZOME Ichiro ikwzm

  • Japan
  • 20:24 (UTC +09:00)
View GitHub Profile

ethernet

group 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77
ethernet0_0_grp - - - - - - - - - - - - - - - - - - - - - - - - - - x x x x x x x x x x x x - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ethernet1_0_grp - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - x x x x x x x x x x x x - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ethernet2_0_grp - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@ikwzm
ikwzm / Makefile
Created March 17, 2012 08:32
VHDL package for MT19937AR(Mersenne Twister pseudo random number generator).
GHDL=ghdl
GHDLFLAGS=--mb-comments
WORK=work
TEST_BENCH = test_bench \
$(END_LIST)
all: $(TEST_BENCH)
clean:
@ikwzm
ikwzm / debootstrap.log
Last active October 1, 2021 03:48
build-debian11-rootfs-error-log
qemu: Unsupported syscall: 403
qemu: Unsupported syscall: 403
qemu: Unsupported syscall: 412
dpkg: warning: parsing file '/var/lib/dpkg/status' near line 5 package 'dpkg':
missing 'Description' field
dpkg: warning: parsing file '/var/lib/dpkg/status' near line 5 package 'dpkg':
missing 'Architecture' field
qemu: Unsupported syscall: 403
qemu: Unsupported syscall: 403
qemu: Unsupported syscall: 412
@ikwzm
ikwzm / strcmp.vhd
Last active December 5, 2020 13:31
strcmp() with VHDL
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity test is
end test;
architecture model of test is
function strcmp(s1,s2:string) return integer is
alias str_1 : string(1 to s1'length) is s1;
alias str_2 : string(1 to s2'length) is s2;
variable i : integer;
@ikwzm
ikwzm / README.md
Created March 14, 2012 11:58
vhdl-mode.el if begin at end of line then back to indentation

vhdl-mode.el if begin at end of line then back to indention

オリジナルの vhdl-mode.el で VHDLコードを編集してると、今ひとつ begin 〜 end のインデントが気に入りません。 なぜか次のようになってしまいます。

process (CLK) begin
    if (CLK'event and CLK = '1') then
        :

:

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stddef.h>
#include <time.h>
#include <unistd.h>
#include <fcntl.h>
#include <error.h>
#include <errno.h>
#include <sys/mman.h>
@ikwzm
ikwzm / Makefile
Created April 4, 2012 12:13
Data Path Reducer (Data Width Converter) VHDL Model.
GHDL=ghdl
GHDLFLAGS=--mb-comments
WORK=work
TEST_BENCH = test_bench_dwc_w08_i1_o1_q0_j0 \
test_bench_dwc_w08_i1_o2_q0_j0 \
test_bench_dwc_w08_i1_o3_q0_j0 \
test_bench_dwc_w08_i1_o4_q0_j0 \
test_bench_dwc_w08_i2_o1_q0_j0 \
test_bench_dwc_w08_i2_o2_q0_j0 \
@ikwzm
ikwzm / dpu-load.md
Last active August 28, 2019 07:40
dpu-load.md

Edge-AI-Platform-Tutorials for ZynqMP-FPGA-Linux

Install

fpga@debian-fpga:~/test$ dtc -I dts -O dtb -o fpga-load.dtb fpga-load.dts
fpga@debian-fpga:~/test$ dtc -I dts -O dtb -o dpu.dtb       dpu.dts
dpu.dtb: Warning (avoid_unnecessary_addr_size): /fragment@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
dpu.dtb: Warning (avoid_unnecessary_addr_size): /fragment@0/__overlay__: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
@ikwzm
ikwzm / ultra96v2_wilc3000_error.log
Last active July 24, 2019 06:33
ultra96v2_wilc3000_error.log
```devicetree
&sdhci1 {
status = "okay";
bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio_bank = <0>;
non-removable;
disable-wp;
vqmmc-supply = <&wmmcsdio_fixed>;
@ikwzm
ikwzm / wave.do
Created January 11, 2019 02:34
Sample do file for ModelSim Wave Viewer
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider TOP(SERIAL)
add wave -noupdate -format Logic /Test/DUT/TX
add wave -noupdate -format Logic /Test/DUT/TX_
add wave -noupdate -format Logic /Test/DUT/RX
add wave -noupdate -format Logic /Test/DUT/RX_
add wave -noupdate -format Logic /Test/DUT/sys_rst_n
add wave -noupdate -format Logic /Test/DUT/sys_clk_p
add wave -noupdate -format Logic /Test/DUT/sys_clk_n