inkwisit

module fpr_add(A,B,C);

input [31:0]A;
input [31:0]B;
output [31:0]C;

reg diff_sign;
wire [8:0]AgB; // exponential for A greater than B
wire [8:0]BgA; // exponential for B greater than A
wire [7:0]exp_diff; // difference of the exponentials

inkwisit

`timescale 1ns / 1ps

module clock(clk_in,rst,clk_out,clk_select_line);

input clk_in;
input [2:0]clk_select_line;
input rst;

output reg clk_out;