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#!/usr/bin/env python3 | |
import sys | |
import os | |
import re | |
def slice_log(outdir, linesIt): | |
start_xform_re = re.compile(r'\s*====*\s+Starting\s+Transform\s+(.+)\s+====*\s*') | |
annos_start_re = re.compile(r'\s*Annotations:\s*') | |
circuit_start_re = re.compile(r'\s*Circuit:\s*') |
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The FIRRTL project admins request that You sign a Contributor License Agreement ("CLA") | |
regarding any software code and/or documentation You desire to contribute to | |
the FIRRTL Project ("Contribution"). | |
If you are submitting your Contribution to the FIRRTL Project on behalf of the Regents | |
of the University of California, You hearby agree to license your Contribution under | |
the 3-Clause BSD License, and to include the appropriate copyright notice required by | |
the license. | |
If you are submitting your Contribution to the FIRRTL Project on behalf of yourself or |
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{ | |
"name": { | |
"title": "Full Name", | |
"type": "string", | |
"githubKey": "name", | |
"require": true | |
}, | |
"email": { | |
"title": "E-Mail", | |
"type": "string", |
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#!/usr/bin/python | |
import sys | |
import os | |
import re | |
from collections import defaultdict | |
from split_firrtl import split_firrtl | |
def get_submods(modules): | |
submods = defaultdict(list) |
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#!/usr/bin/python | |
import sys | |
import os | |
import re | |
from collections import defaultdict | |
# Takes firrtl text, returns a dict from module name to module definition | |
def split_firrtl(firrtl_lines): | |
modules = defaultdict(list) |
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Nonequivalent refers to objects that are case class different (!=) | |
Unique refers to objects that are different references (ne) | |
A difference between nonequivalent and unique node counts shows object duplication in the compiler. | |
Ideally these numbers would always be the same. | |
Here is a measure using an old version of BOOMs ROB. | |
*New* unique nodes is a way to measure object duplication, how many nodes in the new circuit are not | |
found in the old circuit (by reference: ne) |
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133573,133577c133573 | |
< if (reset) begin | |
< pending_0 <= 1'h0; | |
< end else begin | |
< pending_0 <= 1'h0; | |
< end | |
--- | |
> pending_0 <= 1'h0; | |
169978,169982c169974 | |
< if (reset) begin |
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case class Foo(name: String, value: Int) | |
val foo = Foo("hi", 3) | |
foo match { | |
case foo: Foo => // Gets a ref | |
} | |
foo match { | |
case Foo(n, v) => // Have refs to the fields of Foo | |
} |
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module Test : | |
input a : UInt<10> | |
input b : UInt<2> | |
output z : UInt<10> | |
wire w : UInt<10> | |
w <= dshl(a, b) | |
; Replace with | |
node w = bits(dshl(a, b), 9, 0) | |
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circuit TLSPIFlash_qspi : | |
module Queue_6 : | |
input clock : Clock | |
input reset : UInt<1> | |
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}, count : UInt<4>} | |
io is invalid | |
io is invalid | |
cmem ram : UInt<8> [8] @[Decoupled.scala 182:24] | |
reg value : UInt<3>, clock with : (reset => (reset, UInt<3>("h0"))) @[Counter.scala 17:33] |