jeremytregunna

defmodule Api.Authorize do
  alias Account.Models.User

  def board?(board_id, %User{} = user, available_permissions, required_permissions) do
    with {:ok, board} <- Tracker.Board.find(board_id),
         true <-
           Tracker.OrganizationMembers.user_in_organization?(user.id, board.organization_id),
         ^required_permissions <-
           Enum.to_list(
             MapSet.intersection(

jeremytregunna

[    0.016937] mce: CPU supports 23 MCE banks
[    0.313343] mce: [Hardware Error]: Machine check events logged
[    0.313344] mce: [Hardware Error]: CPU 8: Machine Check: 0 Bank 0: baa0400000070135
[    0.313348] mce: [Hardware Error]: TSC 0 MISC d012000101000000 SYND 104c180167 IPID b000000000
[    0.313353] mce: [Hardware Error]: PROCESSOR 2:800f11 TIME 1517570945 SOCKET 0 APIC 8 microcode 8001129
[    0.340011] mce: [Hardware Error]: Machine check events logged
[    0.340011] mce: [Hardware Error]: CPU 9: Machine Check: 0 Bank 5: bea0000000000108
[    0.340016] mce: [Hardware Error]: TSC 0 ADDR 1ffffbb681dd4 MISC d012000101000000 SYND 4d000000 IPID 500b000000000
[    0.340021] mce: [Hardware Error]: PROCESSOR 2:800f11 TIME 1517570945 SOCKET 0 APIC 9 microcode 8001129

jeremytregunna

SERVER ID           IMAGE                       ZONE                CREATED             STATUS              PORTS               NAME                COMMERCIAL TYPE
ea26208b            Ubuntu_Xenial_16_04_lates   par1                36 hours            running             51.15.X.Y       proxy0              VC1S
208338ad            Ubuntu_Xenial_16_04_lates   par1                36 hours            running                                 master1             C2S
2c4a87b0            Ubuntu_Xenial_16_04_lates   par1                36 hours            running                                 master2             C2S
f6af16b4            Ubuntu_Xenial_16_04_lates   par1                36 hours            running                                 master0             C2S
99b83c2e            Ubuntu_Xenial_16_04_lates   par1                36 hours            running                                 proxy1              VC1S
978d2833            Ubuntu_Xenial_16_04_lates   par1                36 hours            running       

jeremytregunna

SERVER ID           IMAGE                       ZONE                CREATED             STATUS              PORTS               NAME                COMMERCIAL TYPE
ea26208b            Ubuntu_Xenial_16_04_lates   par1                36 hours            running             51.15.217.107       proxy0              VC1S
208338ad            Ubuntu_Xenial_16_04_lates   par1                36 hours            running                                 master1             C2S
2c4a87b0            Ubuntu_Xenial_16_04_lates   par1                36 hours            running                                 master2             C2S
f6af16b4            Ubuntu_Xenial_16_04_lates   par1                36 hours            running                                 master0             C2S
99b83c2e            Ubuntu_Xenial_16_04_lates   par1                36 hours            running                                 proxy1              VC1S
978d2833            Ubuntu_Xenial_16_04_lates   par1                36 hours            running   

jeremytregunna

<student> Yes I am 
<ZipCPU> You asked a question on ##verilog some time ago, and then left before I noticed and answered the question.
<ZipCPU> I wanted to make certain you were on line before I commented on any of your issues.
<ZipCPU> Further, because the ##fpga discussion is struggling to handle about 3 topics at once, I thought it might be simpler to leave the discussion channel.
<student> Yea that's right, I left before receiving any answers, I waited a lot but none answered.
<ZipCPU> You were asking some fascinating questions on ##fpga.
<ZipCPU> May I try my hand at answering any of them?
<student> Yea sure, I would be too thankful for that as I'm starting my way in digital design and I have multiple issues that I didn't find answer on edaboard forums, and IRC as well! 
<ZipCPU> So ... I started digital design in earnest almost two years ago.  In many ways, I'm a newbie.  On the other hand, I do have a graduate degree in computer engineering, so ... I might know a thing or two ...
<ZipCPU> At one time,

jeremytregunna

export PASS_RECIPIENT="you@your-gpg-identity.com"
export PASS_HOME=$HOME/.secret-or-some-other-place-you-want-to-keep-the-files

jeremytregunna

mappings in Universal ++= contentOf("data")

dockerfile in docker := {
  val appDir: File = stage.value
  val targetDir = "/app"

  new Dockerfile {
    from("openjdk:latest")
    entryPoint(s"$targetDir/bin/${executableScriptName.value}")
    copy(appDir, targetDir)

jeremytregunna

precedencegroup BindingPrecedence {
    associativity: left
    lowerThan: DefaultPrecedence
    higherThan: TernaryPrecedence
}

infix operator |>: BindingPrecedence
public func |>(f1: @escaping Filter, f2: @escaping Filter) -> Filter {
    return { image in
        f2(f1(image))

jeremytregunna

Keybase proof

I hereby claim:

• I am jeremytregunna on github.
• I am jer (https://keybase.io/jer) on keybase.
• I have a public key whose fingerprint is 5C6A A4DF 33A2 3BBE 82E2 50A8 1278 B36B A6F5 D5E4

To claim this, I am signing this object:

jeremytregunna

LogLevel

Log := Object clone do(
  with := method(file,
    logger := Log clone
    logger logfile := file
    logger logfile openForUpdating
    return logger
  )