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NuttX on Ox64 BL808: UART Input and PLIC are OK yay! See https://github.com/lupyuen/nuttx-ox64
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| 0 | |
| switch to partitions #0, OK | |
| mmc0 is current device | |
| Scanning mmc 0:2... | |
| Found /extlinux/extlinux.conf | |
| Retrieving file: /extlinux/extlinux.conf | |
| Select the boot mode | |
| 1:.Pine64 0X64 Kernel | |
| 2:.Sipeed M1SDock Kernel | |
| Enter choice: 1:.Pine64 0X64 Kernel | |
| Retrieving file: /extlinux/../Image | |
| append: root=PARTLABEL=rootfs rootwait rw rootfstype=ext4 console=ttyS0,2000000 loglevel=8 earlycon=sbi | |
| Retrieving file: /extlinux/../bl808-pine64-ox64.dtb | |
| ## Flattened Device Tree blob at 51ff8000 | |
| Booting using the fdt blob at 0x51ff8000 | |
| Working FDT set to 51ff8000 | |
| Loading Device Tree to 0000000053f22000, end 0000000053f25fab ... OK | |
| Working FDT set to 53f22000 | |
| Starting kernel ... | |
| 123jh7110_copy_ramdisk: _edata=0x50400258, _sbss=0x50400290, _ebss=0x50H7110_IDLESTACK_TOP=0x50407c00 | |
| jh7110_copy_ramdisk: ramdisk_addr=0x50410281 | |
| jh7110_copy_ramdisk: size=8192000 | |
| ABCjh7110_mm_init: Test Interrupt Priority | |
| test_interrupt_priority: before50=0, before54=0, after50=1, after54=0 | |
| jh7110_kernel_mappings: map I/O regions | |
| mmu_ln_setentry: vaddr=0, lntable[index]=0xf8000000000000e7 | |
| jh7110_kernel_mappings: map PLIC as Interrupt L2 | |
| mmu_ln_setentry: vaddr=0xe0000000, lntable[index]=0xf8000000380000e7 | |
| mmu_ln_setentry: vaddr=0xe0200000, lntable[index]=0xf8000000380800e7 | |
| mmu_ln_setentry: vaddr=0xe0400000, lntable[index]=0xf8000000381000e7 | |
| mmu_ln_setentry: vaddr=0xe0600000, lntable[index]=0xf8000000381800e7 | |
| mmu_ln_setentry: vaddr=0xe0800000, lntable[index]=0xf8000000382000e7 | |
| mmu_ln_setentry: vaddr=0xe0a00000, lntable[index]=0xf8000000382800e7 | |
| mmu_ln_setentry: vaddr=0xe0c00000, lntable[index]=0xf8000000383000e7 | |
| mmu_ln_setentry: vaddr=0xe0e00000, lntable[index]=0xf8000000383800e7 | |
| mmu_ln_setentry: vaddr=0xe1000000, lntable[index]=0xf8000000384000e7 | |
| mmu_ln_setentry: vaddr=0xe1200000, lntable[index]=0xf8000000384800e7 | |
| mmu_ln_setentry: vaddr=0xe1400000, lntable[index]=0xf8000000385000e7 | |
| mmu_ln_setentry: vaddr=0xe1600000, lntable[index]=0xf8000000385800e7 | |
| mmu_ln_setentry: vaddr=0xe1800000, lntable[index]=0xf8000000386000e7 | |
| mmu_ln_setentry: vaddr=0xe1a00000, lntable[index]=0xf8000000386800e7 | |
| mmu_ln_setentry: vaddr=0xe1c00000, lntable[index]=0xf8000000387000e7 | |
| mmu_ln_setentry: vaddr=0xe1e00000, lntable[index]=0xf8000000387800e7 | |
| mmu_ln_setentry: vaddr=0xe2000000, lntable[index]=0xf8000000388000e7 | |
| mmu_ln_setentry: vaddr=0xe2200000, lntable[index]=0xf8000000388800e7 | |
| mmu_ln_setentry: vaddr=0xe2400000, lntable[index]=0xf8000000389000e7 | |
| mmu_ln_setentry: vaddr=0xe2600000, lntable[index]=0xf8000000389800e7 | |
| mmu_ln_setentry: vaddr=0xe2800000, lntable[index]=0xf800000038a000e7 | |
| mmu_ln_setentry: vaddr=0xe2a00000, lntable[index]=0xf800000038a800e7 | |
| mmu_ln_setentry: vaddr=0xe2c00000, lntable[index]=0xf800000038b000e7 | |
| mmu_ln_setentry: vaddr=0xe2e00000, lntable[index]=0xf800000038b800e7 | |
| mmu_ln_setetry: vaddr=0xe3000000, lntable[index]=0xf800000038c000e7 | |
| mmu_ln_setentry: vaddr=0xe3200000, lntable[index]=0xf800000038c800e7 | |
| mmu_ln_setentry: vaddr=0xe3400000, lntable[index]=0xf800000038d000e7 | |
| mmu_ln_setentry: vaddr=0xe3600000, lntable[index]=0xf800000038d800e7 | |
| mmu_ln_setentry: vaddr=0xe3800000, lntable[index]=0xf800000038e000e7 | |
| mmu_ln_setentry: vaddr=0xe3a00000, lntable[index]=0xf800000038e800e7 | |
| mmu_ln_setentry: vaddr=0xe3c00000, lntable[index]=0xf800000038f000e7 | |
| mmu_ln_setentry: vaddr=0xe3e00000, lntable[index]=0xf800000038f800e7 | |
| mmu_ln_setentry: vaddr=0xe4000000, lntable[index]=0xf8000000390000e7 | |
| mmu_ln_setentry: vaddr=0xe4200000, lntable[index]=0xf8000000390800e7 | |
| mmu_ln_setentry: vaddr=0xe4400000, lntable[index]=0xf8000000391000e7 | |
| mmu_ln_setentry: vaddr=0xe4600000, lntable[index]=0xf8000000391800e7 | |
| mmu_ln_setentry: vaddr=0xe4800000, lntable[index]=0xf8000000392000e7 | |
| mmu_ln_setentry: vaddr=0xe4a00000, lntable[index]=0xf8000000392800e7 | |
| mmu_ln_setentry: vaddr=0xe4c00000, lntable[index]=0xf8000000393000e7 | |
| mmu_ln_setentry: vaddr=0xe4e00000, lntable[index]=0xf8000000393800e7 | |
| mmu_ln_setentry: vaddr=0xe5000000, lntable[index]=0xf8000000394000e7 | |
| mmu_ln_setentry: vaddr=0xe5200000, lntable[index]=0xf8000000394800e7 | |
| mmu_ln_setentry: vaddr=0xe5400000, lntable[index]=0xf8000000395000e7 | |
| mmu_ln_setentry: vaddr=0xe5600000, lntable[index]=0xf8000000395800e7 | |
| mmu_ln_setentry: vaddr=0xe5800000, lntable[index]=0xf8000000396000e7 | |
| mmu_ln_setentry: vaddr=0xe5a00000, lntable[index]=0xf8000000396800e7 | |
| mmu_ln_setentry: vaddr=0xe5c00000, lntable[index]=0xf8000000397000e7 | |
| mmu_ln_setentry: vaddr=0xe5e00000, lntable[index]=0xf8000000397800e7 | |
| mmu_ln_setentry: vaddr=0xe6000000, lntable[index]=0xf8000000398000e7 | |
| mmu_ln_setentry: vaddr=0xe6200000, lntable[index]=0xf8000000398800e7 | |
| mmu_ln_setentry: vaddr=0xe6400000, lntable[index]=0xf8000000399000e7 | |
| mmu_ln_setentry: vaddr=0xe6600000, lntable[index]=0xf8000000399800e7 | |
| mmu_ln_setentry: vaddr=0xe6800000, lntable[index]=0xf800000039a000e7 | |
| mmu_ln_setentry: vaddr=0xe6a00000, lntable[index]=0xf800000039a800e7 | |
| mmu_ln_setentry: vaddr=0xe6c00000, lntable[index]=0xf800000039b000e7 | |
| mmu_ln_setentry: vaddr=0xe6e00000, lntable[index]=0xf800000039b800e7 | |
| mmu_ln_setentry: vaddr=0xe7000000, lntable[index]=0xf800000039c000e7 | |
| mmu_ln_setentry: vaddr=0xe7200000, lntable[index]=0xf800000039c800e7 | |
| mmu_ln_setentry: vaddr=0xe7400000, lntable[index]=0xf800000039d000e7 | |
| mmu_ln_setentry: vaddr=0xe7600000, lntable[index]=0xf800000039d800e7 | |
| mmu_ln_setentry: vaddr=0xe7800000, lntable[index]=0xf800000039e000e7 | |
| mmu_ln_setentry: vaddr=0xe7a00000, lntable[index]=0xf800000039e800e7 | |
| mmu_ln_setentry: vaddr=0xe7c00000, lntable[index]=0xf800000039f000e7 | |
| mmu_ln_setentry: vaddr=0xe7e00000, lntable[index]=0xf800000039f800e7 | |
| mmu_ln_setentry: vaddr=0xe8000000, lntable[index]=0xf80000003a0000e7 | |
| mmu_ln_setentry: vaddr=0xe8200000, lntable[index]=0xf80000003a0800e7 | |
| mmu_ln_setentry: vaddr=0xe8400000, lntable[index]=0xf80000003a1000e7 | |
| mmu_ln_setentry: vaddr=0xe8600000, lntable[index]=0xf80000003a1800e7 | |
| mmu_ln_setentry: vaddr=0xe8800000, lntable[index]=0xf80000003a2000e7 | |
| mmu_ln_setentry: vaddr=0xe8a00000, lntable[index]=0xf80000003a2800e7 | |
| mmu_ln_setentry: vaddr=0xe8c00000, lntable[index]=0xf80000003a3000e7 | |
| mmu_ln_setentry: vaddr=0xe8e00000, lntable[index]=0xf80000003a3800e7 | |
| mmu_ln_setentry: vaddr=0xe9000000, lntable[index]=0xf80000003a4000e7 | |
| mmu_ln_setentry: vaddr=0xe9200000, lntable[index]=0xf80000003a4800e7 | |
| mmu_ln_setentry: vaddr=0xe9400000, lntable[index]=0xf80000003a5000e7 | |
| mmu_ln_setentry: vaddr=0xe9600000, lntable[index]=0xf80000003a5800e7 | |
| mmu_ln_setentry: vaddr=0xe9800000, lntable[index]=0xf80000003a6000e7 | |
| mmu_ln_setentry: vaddr=0xe9a00000, lntable[index]=0xf80000003a6800e7 | |
| mmu_ln_setentry: vaddr=0xe9c00000, lntable[index]=0xf80000003a7000e7 | |
| mmu_ln_setentry: vaddr=0xe9e00000, lntable[index]=0xf80000003a7800e7 | |
| mmu_ln_setentry: vaddr=0xea000000, lntable[index]=0xf80000003a8000e7 | |
| mmu_ln_setentry: vaddr=0xea200000, lntable[index]=0xf80000003a8800e7 | |
| mmu_ln_setentry: vaddr=0xea400000, lntable[index]=0xf80000003a9000e7 | |
| mmu_ln_setentry: vaddr=0xea600000, lntable[index]=0xf80000003a9800e7 | |
| mmu_ln_setentry: vaddr=0xea800000, lntable[index]=0xf80000003aa000e7 | |
| mmu_ln_setentry: vaddr=0xeaa00000, lntable[index]=0xf80000003aa800e7 | |
| mmu_ln_setentry: vaddr=0xeac00000, lntable[index]=0xf80000003ab000e7 | |
| mmu_ln_setentry: vaddr=0xeae00000, lntable[index]=0xf80000003ab800e7 | |
| mmu_ln_setentry: vaddr=0xeb000000, lntable[index]=0xf80000003ac000e7 | |
| mmu_ln_setentry: vaddr=0xeb200000, lntable[index]=0xf80000003ac800e7 | |
| mmu_ln_setentry: vaddr=0xeb400000, lntable[index]=0xf80000003ad000e7 | |
| mmu_ln_setentry: vaddr=0xeb600000, lntable[index]=0xf80000003ad800e7 | |
| mmu_ln_setentry: vaddr=0xeb800000, lntable[index]=0xf80000003ae000e7 | |
| mmu_ln_setentry: vaddr=0xeba00000, lntable[index]=0xf80000003ae800e7 | |
| mmu_ln_setentry: vaddr=0xebc00000, lntable[index]=0xf80000003af000e7 | |
| mmu_ln_setentry: vaddr=0xebe00000, lntable[index]=0xf80000003af800e7 | |
| mmu_ln_setentry: vaddr=0xec000000, lntable[index]=0xf80000003b0000e7 | |
| mmu_ln_setentry: vaddr=0xec200000, lntable[index]=0xf80000003b0800e7 | |
| mmu_ln_setentry: vaddr=0xec400000, lntable[index]=0xf80000003b1000e7 | |
| mmu_ln_setentry: vaddr=0xec600000, lntable[index]=0xf80000003b1800e7 | |
| mmu_ln_setentry: vaddr=0xec800000, lntable[index]=0xf80000003b2000e7 | |
| mmu_ln_setentry: vaddr=0xeca00000, lntable[index]=0xf80000003b2800e7 | |
| mmu_ln_setentry: vaddr=0xecc00000, lntable[index]=0xf80000003b3000e7 | |
| mmu_ln_setentry: vaddr=0xece00000, lntable[index]=0xf80000003b3800e7 | |
| mmu_ln_setentry: vaddr=0xed000000, lntable[index]=0xf80000003b4000e7 | |
| mmu_ln_setentry: vaddr=0xed200000, lntable[index]=0xf80000003b4800e7 | |
| mmu_ln_setentry: vaddr=0xed400000, lntable[index]=0xf80000003b5000e7 | |
| mmu_ln_setentry: vaddr=0xed600000, lntable[index]=0xf80000003b5800e7 | |
| mmu_ln_setentry: vaddr=0xed800000, lntable[index]=0xf80000003b6000e7 | |
| mmu_ln_setentry: vaddr=0xeda00000, lntable[index]=0xf80000003b6800e7 | |
| mmu_ln_setentry: vaddr=0xedc00000, lntable[index]=0xf80000003b7000e7 | |
| mmu_ln_setentry: vaddr=0xede00000, lntable[index]=0xf80000003b7800e7 | |
| mmu_ln_setentry: vaddr=0xee000000, lntable[index]=0xf80000003b8000e7 | |
| mmu_ln_setentry: vaddr=0xee200000, lntable[index]=0xf80000003b8800e7 | |
| mmu_ln_setentry: vaddr=0xee400000, lntable[index]=0xf80000003b9000e7 | |
| mmu_ln_setentry: vaddr=0xee600000, lntable[index]=0xf80000003b9800e7 | |
| mmu_ln_setentry: vaddr=0xee800000, lntable[index]=0xf80000003ba000e7 | |
| mmu_ln_setentry: vaddr=0xeea00000, lntable[index]=0xf80000003ba800e7 | |
| mmu_ln_setentry: vaddr=0xeec00000, lntable[index]=0xf80000003bb000e7 | |
| mmu_ln_setentry: vaddr=0xeee00000, lntable[index]=0xf80000003bb800e7 | |
| mmu_ln_setentry: vaddr=0xef000000, lntable[index]=0xf80000003bc000e7 | |
| mmu_ln_setentry: vaddr=0xef200000, lntable[index]=0xf80000003bc800e7 | |
| mmu_ln_setentry: vaddr=0xef400000, lntable[index]=0xf80000003bd000e7 | |
| mmu_ln_setentry: vaddr=0xef600000, lntable[index]=0xf80000003bd800e7 | |
| mmu_ln_setentry: vaddr=0xef800000, lntable[index]=0xf80000003be000e7 | |
| mmu_ln_setentry: vaddr=0xefa00000, lntable[index]=0xf80000003be800e7 | |
| mmu_ln_setentry: vaddr=0xefc00000, lntable[index]=0xf80000003bf000e7 | |
| mmu_ln_setentry: vaddr=0xefe00000, lntable[index]=0xf80000003bf800e7 | |
| jh7110_kernel_mappings: connect the L1 and Interrupt L2 page tables for PLIC | |
| jh7110_kernel_mappings: map kernel text | |
| jh7110_kernel_mappings: map kernel data | |
| jh7110_kernel_mappings: connect the L1 and L2 page tables | |
| jh7110_kernel_mappings: mapge pool | |
| mmu_satp_reg: pgbase=0xsid=0x0, reg=0x8000000000050406 | |
| mmu_write_satp: reg=0x8000000000050406 | |
| nx_start: Entry | |
| up_irqinitialize: | |
| PLIC Interrupt Priority: Before (0xe0000004): | |
| 0000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0040 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 ................ | |
| 0050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ............... | |
| 0060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0080 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 00a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 00b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 00c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 00d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 00e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 00f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0100 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0110 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0120 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0130 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| PLIC Interrupt Priority: After (0xe0000004): | |
| 0000 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0010 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0020 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0030 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0040 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0050 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0060 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0070 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0080 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0090 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00a0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00b0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00c0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00d0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00e0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00f0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0100 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0110 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0120 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0130 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| irq_attach: irq=0, isr=0x502016ec | |
| irq_attach: irq=1, isr=0x502016ec | |
| irq_attach: irq=2, isr=0x502016ec | |
| irq_attach: irq=3, isr=0x502016ec | |
| irq_attach: irq=5, isr=0x502016ec | |
| irq_attach: irq=7, isr=0x502016ec | |
| irq_attach: irq=4, isr=0x502016ec | |
| irq_attach: irq=6, isr=0x502016ec | |
| irq_attach: irq=8, isr=0x5020190a | |
| irq_attach: irq=9, isr=0x502016ec | |
| irq_attach: irq=10, isr=0x502016ec | |
| irq_attach: irq=11, isr=0x502016ec | |
| irq_attach: irq=12, isr=0x502016ec | |
| irq_attach: irq=13, isr=0x502016ec | |
| irq_attach: irq=14, isr=0x502016ec | |
| irq_attach: irq=15, isr=0x502016ec | |
| irq_attach: irq=19, isr=0x502016ec | |
| up_irq_enable: | |
| irq_attach: irq=17, isr=0x5020adac | |
| up_enable_irq: irq=17 | |
| uart_register: Registering /dev/console | |
| irq_attach: irq=45, isr=0x50200cd4 | |
| up_enable_irq: irq=45 | |
| PLIC Hart 0 S-Mode Interrupt Enable: Before (0xe0002080): | |
| 0000 00 00 00 00 00 00 00 00 ........ | |
| up_enable_irq: extirq=20, addr=0xe0002080, val=0x1048576 | |
| PLIC Hart 0 S-Mode Interrupt Enable: After (0xe0002080): | |
| 0000 00 00 10 00 00 00 00 00 ........ | |
| bl602_attach: BL602_UART_INT_STS=0x4 | |
| bl602_attach: BL602_UART_INT_MASK=0xfff | |
| bl602_attach: BL602_UART_INT_CLEAR=0x0 | |
| bl602_attach: BL602_UART_INT_EN=0xfff | |
| bl602_attach: BL602_UART_FIFO_CONFIG_0=0x0 | |
| UART Registers (0x30002000): | |
| 0000 05 00 00 00 01 00 00 00 13 00 00 00 00 00 00 00 ................ | |
| 0010 70 00 00 00 6f 00 00 00 0f 00 00 00 00 00 00 00 p...o........... | |
| 0020 04 00 00 00 ff 00 00 00 00 00 00 00 ff 00 00 00 ................ | |
| 0030 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0040 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 ................ | |
| 0050 ff 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 0080 00 00 00 00 1a 00 00 00 0a 00 00 00 00 00 00 00 ................ | |
| 0090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 00a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 00b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 00c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | |
| 00d0 00 00 00 00 00 00 00 00 ........ | |
| PLIC Interrupt Priority (0xe0000004): | |
| 0000 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0010 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0020 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0030 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0040 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0050 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0060 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0070 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0080 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0090 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00a0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00b0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00c0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00d0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ............... | |
| 00e0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00f0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0100 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0110 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0120 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0130 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| PLIC Interrupt Pending (0xe0001000): | |
| 0000 00 00 00 00 00 00 00 00 ........ | |
| PLIC Hart 0 S-Mode Interrupt Enable (0xe0002080): | |
| 0000 00 00 10 00 00 00 00 00 ........ | |
| PLIC Hart 0 S-Mode Priority Threshold (0xe0201000): | |
| 0000 00 00 00 00 00 00 00 00 ........ | |
| PLIC Hart 0 S-Mode Claim / Complete (0xe0201004): | |
| 0000 00 00 00 00 .... | |
| Interrupt Pending (0xe0001000): | |
| 0000 00 00 00 00 00 00 00 00 ........ | |
| PLIC Hart 0 M-Mode Interrupt Enable (0xe0002000): | |
| 0000 00 00 00 00 00 00 00 00 ........ | |
| PLIC Hart 0 M-Mode Priority Threshold (0xe0200000): | |
| 0000 07 00 00 00 00 00 00 00 ........ | |
| PLIC Hart 0 M-Mode Claim / Complete (0xe0200004): | |
| 0000 00 00 00 00 .... | |
| bl602_attach: Claim / Complete M-Mode: claim=0 | |
| PLIC Hart 0 M-Mode Claim / Complete (0xe0200004): | |
| 0000 00 00 00 00 .... | |
| bl602_attach: Test Interrupt Priority | |
| test_interrupt_priority: before50=1, before54=1, after50=1, after54=1 | |
| bl602_attach: Set PLIC Interrupt Priority to 1 | |
| PLIC Interrupt Priority (0xe0000004): | |
| 0000 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0010 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0020 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0030 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0040 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0050 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0060 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0070 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0080 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0090 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00a0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00b0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00c0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00d0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00e0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 00f0 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0100 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0110 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0120 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| 0130 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 ................ | |
| PLIC Interrupt Pending (0xe0001000): | |
| 0000 00 00 00 00 00 00 00 00 ........ | |
| work_start_lowpri: Starting low-priority kernel worker thread(s) | |
| nx_start_application: Starting init task: /system/bin/init | |
| up_addrenv_create: textsize=0x15b80, datasize=0x584, heapsize=0x80000, addrenv=0x5040b880 | |
| mmu_satp_reg: pgbase=0x50600000, asid=0x0, reg=0x8000000000050600 | |
| up_addrenv_select: addrenv=0x5040b880, satp=0x8000000000050600 | |
| mmu_write_satp: reg=0x8000000000050600 | |
| elf_symname: Symbol has no name | |
| elf_symvalue: SHN_UNDEF: Failed to get symbol name: -3 | |
| elf_relocateadd: Section 2 reloc 2: Undefined symbol[0] has no name: -3 | |
| up_exit: TCB=0x50409900 exiting | |
| NuttShell (NSH) NuttX-12.0.3 | |
| nsh> nx_start: CPU0: Beginning Idle Loop | |
| nsh> | |
| nsh> uname -a | |
| posix_spawn: pid=0x80202978 path=uname file_actions=0x80202980 attr=0x80202988 argv=0x80202a28 | |
| exec_internal: ERROR: Failed to load program 'uname': -2 | |
| nxposix_spawn_exec: ERROR: exec failed: 2 | |
| NuttX 12.0.3 fd05b07 Nov 24 2023 07:42:54 risc-v star64 | |
| nsh> | |
| nsh> ls /dev | |
| posix_spawn: pid=0x80202978 path=ls file_actions=0x80202980 attr=0x80202988 argv=0x80202a28 | |
| exec_internal: ERROR: Failed to load program 'ls': -2 | |
| nxposix_spawn_exec: ERROR: exec failed: 2 | |
| /dev: | |
| console | |
| null | |
| ram0 | |
| zero | |
| nsh> | |
| nsh> hello | |
| posix_spawn: pid=0x80202978 path=hello file_actions=0x80202980 attr=0x80202988 argv=0x80202a28 | |
| up_addrenv_create: textsize=0xeec, datasize=0xc, heapsize=0x80000, addrenv=0x504099b0 | |
| mmu_satp_reg: pgbase=0x5069d000, asid=0x0, reg=0x800000000005069d | |
| up_addrenv_select: addrenv=0x504099b0, satp=0x800000000005069d | |
| mmu_write_satp: reg=0x800000000005069d | |
| up_addrenv_select: addrenv=0x5040b880, satp=0x8000000000050600 | |
| mmu_write_satp: reg=0x8000000000050600 | |
| up_addrenv_select: addrenv=0x504099b0, satp=0x800000000005069d | |
| mmu_write_satp: reg=0x800000000005069d | |
| elf_symname: Symbol has no name | |
| elf_symvalue: SHN_UNDEF: Failed to get symbol name: -3 | |
| elf_relocateadd: Section 2 reloc 1: Undefined symbol[0] has no name: -3 | |
| up_addrenv_select: addrenv=0x5040b880, satp=0x8000000000050600 | |
| mmu_write_satp: reg=0x8000000000050600 | |
| up_addrenv_select: addrenv=0x504099b0, satp=0x800000000005069d | |
| mmu_write_satp: reg=0x800000000005069d | |
| up_addrenv_select: addrenv=0x5040b880, satp=0x8000000000050600 | |
| mmu_write_satp: reg=0x8000000000050600 | |
| up_addrenv_select: addrenv=0x504099b0, satp=0x800000000005069d | |
| mmu_write_satp: reg=0x800000000005069d | |
| Hello, World!! | |
| group_drop: Keep group 0x50409ba0 (waiters > 0) | |
| up_exit: TCB=0x50409a30 exiting | |
| up_addrenv_select: addrenv=0x5040b880, satp=0x8000000000050600 | |
| mmu_write_satp: reg=0x8000000000050600 | |
| nsh> | |
| nsh> |
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