mkatsimpris

#!/bin/python
from myhdl import *

ACTIVE_LOW, INACTIVE_HIGH = False, True
INACTIVE_LOW, ACTIVE_HIGH = False, True


def sintbv(value, nbits):
    nbits -= 1
    min_value = -1 << nbits

mkatsimpris

#!/usr/bin/env python
# coding=utf-8


from myhdl import *
from math import *
from ram import *
from myhdl.conversion import *

class buf_fifo_int_in(object):

mkatsimpris

#!/usr/bin/env python
# coding=utf-8

from myhdl import *

@block
def RAM(dout, din, raddr,waddr, we, clk,addr_width=8, data_width=24):

    """  Ram model """
    mem = [Signal(intbv(0)[data_width:]) for i in range(int(2**addr_width))]

mkatsimpris

#!/usr/bin/env python
# coding=utf-8


from myhdl import *
from math import *
from ram import *

class buf_fifo_int_in(object):

mkatsimpris

 
  constant C_Y_1       : signed(14 downto 0) := to_signed(4899,  15);
  constant C_Y_2       : signed(14 downto 0) := to_signed(9617,  15);
  constant C_Y_3       : signed(14 downto 0) := to_signed(1868,  15);
  constant C_Cb_1      : signed(14 downto 0) := to_signed(-2764, 15);
  constant C_Cb_2      : signed(14 downto 0) := to_signed(-5428, 15);
  constant C_Cb_3      : signed(14 downto 0) := to_signed(8192,  15);
  constant C_Cr_1      : signed(14 downto 0) := to_signed(8192,  15);
  constant C_Cr_2      : signed(14 downto 0) := to_signed(-6860, 15);
  constant C_Cr_3      : signed(14 downto 0) := to_signed(-1332, 15);

mkatsimpris

from myhdl import *



def mul(ina,inb,out1,clk,reset,width=8):

  ina_reg,inb_reg=[intbv(0,-2**width,2**(width-1)) for i in range(2)]
  out_reg=intbv(0,-2**(2*width),2**(2*width-1))
  @always_seq(clk.posedge, reset=reset)
  def logic():