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From 4c528abd9c9331475920c49f5f51c22dad4204c3 Mon Sep 17 00:00:00 2001 | |
From: Roman Dubtsov <dubtsov@gmail.com> | |
Date: Sun, 2 Jul 2017 14:24:31 +0700 | |
Subject: [PATCH] unofficial: update build system to support OSX | |
I'm pretty sure Xbyak does not work... | |
--- | |
CMakeLists.txt | 33 +++++++++++++++++++++++---------- | |
cmake/MKL.cmake | 20 +++++++++++++++++--- | |
examples/simple_net.c | 4 ++-- |
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From 683903c2f3f774ea626668869352a6fd6a07b002 Mon Sep 17 00:00:00 2001 | |
From: "Fomenko, Evarist M" <evarist.m.fomenko@intel.com> | |
Date: Wed, 5 Jul 2017 18:56:44 +0000 | |
Subject: fixup: cpu: reorder: jit 8i8o to 8o8i | |
--- | |
src/cpu/jit_reorder.hpp | 3 ++- | |
1 file changed, 2 insertions(+), 1 deletion(-) | |
diff --git a/src/cpu/jit_reorder.hpp b/src/cpu/jit_reorder.hpp |
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From 48e0f053bd21363211b8901582c07952fed025f8 Mon Sep 17 00:00:00 2001 | |
From: Roman Dubtsov <roman.s.dubtsov@intel.com> | |
Date: Wed, 9 Aug 2017 12:35:23 +0300 | |
Subject: cpu: pooling: generate proper movups when zeroing diff_src | |
--- | |
src/cpu/jit_uni_pool_kernel_f32.cpp | 2 +- | |
1 file changed, 1 insertion(+), 1 deletion(-) | |
diff --git a/src/cpu/jit_uni_pool_kernel_f32.cpp b/src/cpu/jit_uni_pool_kernel_f32.cpp |
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From 52157cef4c98294b96dfb14ed476a59e647dba57 Mon Sep 17 00:00:00 2001 | |
From: Roman Dubtsov <roman.s.dubtsov@intel.com> | |
Date: Tue, 29 May 2018 10:24:14 -0700 | |
Subject: tentative: cpu: jit: add vzeroupper to postamble() | |
--- | |
src/cpu/jit_avx512_common_conv_winograd_kernel_f32.cpp | 3 +++ | |
src/cpu/jit_avx512_core_conv_winograd_kernel_f32.cpp | 2 ++ | |
src/cpu/jit_generator.hpp | 14 +++++++++++++- | |
src/cpu/jit_uni_1x1_conv_utils.hpp | 1 + |
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mkldnn_verbose,exec,reorder,simple:any,undef,in:f32_hwio out:f32_Ohwi16o,num:1,12x1x5x5,0.480957 | |
mkldnn_verbose,exec,convolution,jit:avx512_common,forward_training,fsrc:nchw fwei:Ohwi16o fbia:x fdst:nChw16c,alg:convolution_direct,mb1_g1ic1oc12_ih640oh640kh5sh1dh0ph2_iw1024ow1024kw5sw1dw0pw2,1.02783 | |
mkldnn_verbose,exec,eltwise,ref:any,forward_training,fdata:nChw16c fdiff:undef,alg:eltwise_relu,mb1ic12ih640iw1024,2.83276 | |
mkldnn_verbose,exec,reorder,simple:any,undef,in:f32_hwio out:f32_OIhw16i16o,num:1,12x12x3x3,0.350098 | |
mkldnn_verbose,exec,reorder,simple:any,undef,in:f32_hwio out:f32_Ohwi16o,num:1,12x1x5x5,1.14111 | |
mkldnn_verbose,exec,convolution,jit:avx512_common,forward_training,fsrc:nchw fwei:Ohwi16o fbia:x fdst:nChw16c,alg:convolution_direct,mb1_g1ic1oc12_ih640oh640kh5sh1dh0ph2_iw1024ow1024kw5sw1dw0pw2,1.9248 | |
mkldnn_verbose,exec,convolution,jit:avx512_common,forward_training,fsrc:nChw16c fwei:OIhw16i16o fbia:undef fdst:nChw16c,alg:convolution_direct,mb1_g1ic12oc12_ih640oh640kh3sh1dh0ph1_iw1024ow1024kw3sw1dw0 |
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/******************************************************************************* | |
* Copyright 2018-2019 Intel Corporation | |
* | |
* Licensed under the Apache License, Version 2.0 (the "License"); | |
* you may not use this file except in compliance with the License. | |
* You may obtain a copy of the License at | |
* | |
* http://www.apache.org/licenses/LICENSE-2.0 | |
* | |
* Unless required by applicable law or agreed to in writing, software |