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Samuel A. Falvo II sam-falvo

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sam-falvo / gist:6008929
Created July 16, 2013 13:57
generic data structure and type-specific specialization in Go (example; not the only way to do it, but closest to what Java does).
package main
import "fmt"
// ====== Generic Stack implementation
package genericStack
type GenericStack struct {
space []interface{}
@sam-falvo
sam-falvo / gist:a049f9be36b3e51e8cc2
Created October 8, 2014 23:55
Example of decent quality assembly language (ancient code from Dolphin OS project, dating back to 1998 or so. Those were the days.)
[global add64]
[global sub64]
;
; This function adds two 64-bit values, passed by reference on the
; stack. The values are passed by reference because the LCC compiler
; does not support 64 bit integers like GCC does.
;
; result
@sam-falvo
sam-falvo / gist:f8920f8a7c91fad4b601
Created November 9, 2014 04:16
A quick and dirty prototype of the Kestrel OS, STS 2. This implementation takes on a distinctly more Unix- or Plan-9-like flavor to the user and coder.
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
/****** fsobj.h ******/
struct scb;
@sam-falvo
sam-falvo / gist:ddc8470700e0e33acfb2
Created December 20, 2014 17:40
RISC-V Code Generated From Test Forth Code
$ bin/fc from m1.fc list /Users/sfalvo/git/kestrel/3 :: Sat Dec 20 09:38:10 PST 2014
This is fc, the machine Forth compiler.
Version 0.1.0
cold: ($00000000)
6F 00 00 00 JAL X0, 0 ($00000004)
.cold: ($00000004)
23 30 17 00 SD X1, X14, 0
13 07 87 FF ADDI X14, X14, -8
@sam-falvo
sam-falvo / gist:4da38d0ab3f7fe740c83
Created December 20, 2014 17:41
Test Code
\ Milestone 1 -- Basic Liveness Test
DEFER cold
: .cold 65 $FFFF00 C! BIS ;
' .cold IS cold
@sam-falvo
sam-falvo / keybase.md
Created May 19, 2015 20:05

Keybase proof

I hereby claim:

  • I am sam-falvo on github.
  • I am saf2 (https://keybase.io/saf2) on keybase.
  • I have a public key whose fingerprint is 07B8 1461 A0DE C658 D4F3 ED4C 62C5 0196 16AF 1914

To claim this, I am signing this object:

@sam-falvo
sam-falvo / Generated Assembly Listing.txt
Created September 8, 2015 05:33
RISC-V Output for given subForth source code
align 8
dword $0E00000000000000
emit:
ld x16 , 0(dsp)
addi dsp, dsp, 8
LGP1 :
auipc gp, 0
ld x17 , (emit-LGP1 )-8 (gp)
sb x16 , 0(x17 )
jalr x0, 0(ra)
@sam-falvo
sam-falvo / sort-benchmarks.fs
Created April 2, 2016 00:56
500000 constant //dataset
//dataset value /dataset
: /dataset-1
/dataset 1 cells - ;
create unsorted ( rely on random contents from ASLR )
16 , 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 ,
//dataset allot
@sam-falvo
sam-falvo / prez.txt
Created August 28, 2016 03:13
Presentation material for SVFIG 2016-Aug-27 meeting.
Intel Decodes CISC to RISC,
Can We Decode RISC-V to MISC?
Samuel A. Falvo II
2016-Aug-27
@sam-falvo
sam-falvo / gist:6d18be9fa564edf7df2fec5d6d1c7da2
Created October 30, 2016 05:34
SIE in software for RISC-V?
The first thing we need to do when invoking SIE is save the current thread state.
The invokING thread called us via an ECALL, so some of this state is in mstatus and mepc.
So, save it.
_SIE: ; A0 -> SIEBK to invoke.
csrrw t0, mscratch, x0 ; mscratch = t0, t0 = pointer to current SIEBK.
sd x1, _X1(t0)
sd x2, _X2(t0)
...
sd x31, _X31(t0)