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# Copyright wulfboy_95 2022, All Rights Reserved. | |
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import board | |
import keypad | |
import struct |
These are just some notes on my current understanding of the subtleties of the AGX memory model and the TLB/caching issues I'm seeing.
TLBI instructions do not broadcast to the GPU from EL1 with stage 2 translation enabled. That's it. That's what the bug was.