DDPP8_56.v

module DDPP8_56(CLK, RST, ENA, DIGI);
  input CLK, RST, ENA;
  output [7:0] DIGI;
  reg [7:0] DIGI;
  wire tmp;

  assign tmp = {DIGI[6:0]==7'b1111111}?0:1;

  always @(posedge CLK)
    begin
      if (RST) DIGI <= 8'b11111110;
      else
      case (ENA)
        1: DIGI <= {DIGI[6:0],tmp};
        0: DIGI <= DIGI;
      endcase
    end
 endmodule