Using make command and makefile

Makefile

# Suppose we have two or more file to compile
# Suppose we need to include the necessary libraries for the same

# Eg : gcc -o obj ojb.c objfunc.c -I

# Everytime we make changes to our code or if we change our system. We have re-run the command which is not best use of our time
# This is where makefile comes into limelight. We just go to directory which has makefile and type command $make and its done
# This might look small but while handling long repos/directories/files we need something easy and user friendly. So makefile

# Steps for building makefile

# name of the file : makefile/Makefile


# Describing set of rules

# Rules have structure like this 
# If no flag is provided first rule will be executed

# target : prerequisites
#       <commands>

# prerequisites are optional
# For example we have one C file(obj.c) in our directory
# then

obj.o : obj.c
    gcc -o obj.o obj.c

# There is a tab infront of gcc
# We use obj.c file as prerequisite. The output will be 'obj.o' executable object created.
# Here target 'obj.o' depends on obj.c

# There are special constants that communicate to make on how to compile the files
# Like CC for gcc, CFLAGS for any flags

# For example we have three files in same directory
# obj.c - main file
# objfunc.c - functions file
# objlib.h - library file  
#Makefile will be

#More stuff will be added :)