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17twenty/beaglebone_patch

Created May 24, 2012 11:15
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beaglebone_patch
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diff -PurN linux-stable-23d8c3f/arch/arm/boot/compressed/Makefile kernel_3.2.14_patched/arch/arm/boot/compressed/Makefile
--- linux-stable-23d8c3f/arch/arm/boot/compressed/Makefile 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/boot/compressed/Makefile 2012-05-16 13:40:12.000000000 +0100
@@ -123,7 +123,7 @@
endif
ccflags-y := -fpic -fno-builtin -I$(obj)
-asflags-y := -Wa,-march=all
+asflags-y := -Wa,-march=armv7-a
# Supply kernel BSS size to the decompressor via a linker symbol.
KBSS_SZ = $(shell size $(obj)/../../../../vmlinux | awk 'END{print $$3}')
diff -PurN linux-stable-23d8c3f/arch/arm/boot/compressed/Makefile.rej kernel_3.2.14_patched/arch/arm/boot/compressed/Makefile.rej
--- linux-stable-23d8c3f/arch/arm/boot/compressed/Makefile.rej 2012-05-24 11:28:16.597950831 +0100
+++ kernel_3.2.14_patched/arch/arm/boot/compressed/Makefile.rej 1970-01-01 01:00:00.000000000 +0100
@@ -1,11 +0,0 @@
---- arch/arm/boot/compressed/Makefile 2012-05-16 13:40:12.000000000 +0100
-+++ arch/arm/boot/compressed/Makefile 2012-04-02 17:53:31.000000000 +0100
-@@ -123,7 +123,7 @@
- endif
-
- ccflags-y := -fpic -fno-builtin -I$(obj)
--asflags-y := -Wa,-march=armv7-a
-+asflags-y := -Wa,-march=all
-
- # Supply kernel BSS size to the decompressor via a linker symbol.
- KBSS_SZ = $(shell size $(obj)/../../../../vmlinux | awk 'END{print $$3}')
diff -PurN linux-stable-23d8c3f/arch/arm/boot/dts/omap2.dtsi kernel_3.2.14_patched/arch/arm/boot/dts/omap2.dtsi
--- linux-stable-23d8c3f/arch/arm/boot/dts/omap2.dtsi 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/boot/dts/omap2.dtsi 2012-05-16 12:10:46.000000000 +0100
@@ -0,0 +1,67 @@
+/*
+ * Device Tree Source for OMAP2 SoC
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ };
+
+ cpus {
+ cpu@0 {
+ compatible = "arm,arm1136jf-s";
+ };
+ };
+
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap2-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ ocp {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main";
+
+ intc: interrupt-controller@1 {
+ compatible = "ti,omap2-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart1: serial@4806a000 {
+ compatible = "ti,omap2-uart";
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ };
+
+ uart2: serial@4806c000 {
+ compatible = "ti,omap2-uart";
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ };
+
+ uart3: serial@4806e000 {
+ compatible = "ti,omap2-uart";
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ };
+ };
+};
diff -PurN linux-stable-23d8c3f/arch/arm/boot/dts/omap3-beagle.dts kernel_3.2.14_patched/arch/arm/boot/dts/omap3-beagle.dts
--- linux-stable-23d8c3f/arch/arm/boot/dts/omap3-beagle.dts 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/boot/dts/omap3-beagle.dts 2012-05-16 12:10:46.000000000 +0100
@@ -13,15 +13,6 @@
model = "TI OMAP3 BeagleBoard";
compatible = "ti,omap3-beagle", "ti,omap3";
- /*
- * Since the initial device tree board file does not create any
- * devices (MMC, network...), the only way to boot is to provide a
- * ramdisk.
- */
- chosen {
- bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk";
- };
-
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
diff -PurN linux-stable-23d8c3f/arch/arm/boot/dts/omap3.dtsi kernel_3.2.14_patched/arch/arm/boot/dts/omap3.dtsi
--- linux-stable-23d8c3f/arch/arm/boot/dts/omap3.dtsi 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/boot/dts/omap3.dtsi 2012-05-16 12:10:46.000000000 +0100
@@ -13,6 +13,13 @@
/ {
compatible = "ti,omap3430", "ti,omap3";
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ };
+
cpus {
cpu@0 {
compatible = "arm,cortex-a8";
@@ -59,5 +66,29 @@
interrupt-controller;
#interrupt-cells = <1>;
};
+
+ uart1: serial@0x4806a000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ };
+
+ uart2: serial@0x4806c000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ };
+
+ uart3: serial@0x49020000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ };
+
+ uart4: serial@0x49042000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
};
};
diff -PurN linux-stable-23d8c3f/arch/arm/boot/dts/omap4.dtsi kernel_3.2.14_patched/arch/arm/boot/dts/omap4.dtsi
--- linux-stable-23d8c3f/arch/arm/boot/dts/omap4.dtsi 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/boot/dts/omap4.dtsi 2012-05-16 12:10:46.000000000 +0100
@@ -21,6 +21,10 @@
interrupt-parent = <&gic>;
aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
};
cpus {
@@ -99,5 +103,29 @@
reg = <0x48241000 0x1000>,
<0x48240100 0x0100>;
};
+
+ uart1: serial@0x4806a000 {
+ compatible = "ti,omap4-uart";
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ };
+
+ uart2: serial@0x4806c000 {
+ compatible = "ti,omap4-uart";
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ };
+
+ uart3: serial@0x48020000 {
+ compatible = "ti,omap4-uart";
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ };
+
+ uart4: serial@0x4806e000 {
+ compatible = "ti,omap4-uart";
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
};
};
diff -PurN linux-stable-23d8c3f/arch/arm/boot/dts/omap4-panda.dts kernel_3.2.14_patched/arch/arm/boot/dts/omap4-panda.dts
--- linux-stable-23d8c3f/arch/arm/boot/dts/omap4-panda.dts 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/boot/dts/omap4-panda.dts 2012-05-16 12:10:46.000000000 +0100
@@ -13,15 +13,6 @@
model = "TI OMAP4 PandaBoard";
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
- /*
- * Since the initial device tree board file does not create any
- * devices (MMC, network...), the only way to boot is to provide a
- * ramdisk.
- */
- chosen {
- bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
- };
-
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
diff -PurN linux-stable-23d8c3f/arch/arm/boot/dts/omap4-sdp.dts kernel_3.2.14_patched/arch/arm/boot/dts/omap4-sdp.dts
--- linux-stable-23d8c3f/arch/arm/boot/dts/omap4-sdp.dts 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/boot/dts/omap4-sdp.dts 2012-05-16 12:10:46.000000000 +0100
@@ -13,15 +13,6 @@
model = "TI OMAP4 SDP board";
compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
- /*
- * Since the initial device tree board file does not create any
- * devices (MMC, network...), the only way to boot is to provide a
- * ramdisk.
- */
- chosen {
- bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
- };
-
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
diff -PurN linux-stable-23d8c3f/arch/arm/common/edma.c kernel_3.2.14_patched/arch/arm/common/edma.c
--- linux-stable-23d8c3f/arch/arm/common/edma.c 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/common/edma.c 2012-05-16 12:10:46.000000000 +0100
@@ -0,0 +1,1740 @@
+/*
+ * EDMA3 Driver
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/pm_runtime.h>
+
+#include <mach/edma.h>
+
+/* Offsets matching "struct edmacc_param" */
+#define PARM_OPT 0x00
+#define PARM_SRC 0x04
+#define PARM_A_B_CNT 0x08
+#define PARM_DST 0x0c
+#define PARM_SRC_DST_BIDX 0x10
+#define PARM_LINK_BCNTRLD 0x14
+#define PARM_SRC_DST_CIDX 0x18
+#define PARM_CCNT 0x1c
+
+#define PARM_SIZE 0x20
+
+/* Offsets for EDMA CC global channel registers and their shadows */
+#define SH_ER 0x00 /* 64 bits */
+#define SH_ECR 0x08 /* 64 bits */
+#define SH_ESR 0x10 /* 64 bits */
+#define SH_CER 0x18 /* 64 bits */
+#define SH_EER 0x20 /* 64 bits */
+#define SH_EECR 0x28 /* 64 bits */
+#define SH_EESR 0x30 /* 64 bits */
+#define SH_SER 0x38 /* 64 bits */
+#define SH_SECR 0x40 /* 64 bits */
+#define SH_IER 0x50 /* 64 bits */
+#define SH_IECR 0x58 /* 64 bits */
+#define SH_IESR 0x60 /* 64 bits */
+#define SH_IPR 0x68 /* 64 bits */
+#define SH_ICR 0x70 /* 64 bits */
+#define SH_IEVAL 0x78
+#define SH_QER 0x80
+#define SH_QEER 0x84
+#define SH_QEECR 0x88
+#define SH_QEESR 0x8c
+#define SH_QSER 0x90
+#define SH_QSECR 0x94
+#define SH_SIZE 0x200
+
+/* Offsets for EDMA CC global registers */
+#define EDMA_REV 0x0000
+#define EDMA_CCCFG 0x0004
+#define EDMA_QCHMAP 0x0200 /* 8 registers */
+#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
+#define EDMA_QDMAQNUM 0x0260
+#define EDMA_QUETCMAP 0x0280
+#define EDMA_QUEPRI 0x0284
+#define EDMA_EMR 0x0300 /* 64 bits */
+#define EDMA_EMCR 0x0308 /* 64 bits */
+#define EDMA_QEMR 0x0310
+#define EDMA_QEMCR 0x0314
+#define EDMA_CCERR 0x0318
+#define EDMA_CCERRCLR 0x031c
+#define EDMA_EEVAL 0x0320
+#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
+#define EDMA_QRAE 0x0380 /* 4 registers */
+#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
+#define EDMA_QSTAT 0x0600 /* 2 registers */
+#define EDMA_QWMTHRA 0x0620
+#define EDMA_QWMTHRB 0x0624
+#define EDMA_CCSTAT 0x0640
+
+#define EDMA_M 0x1000 /* global channel registers */
+#define EDMA_ECR 0x1008
+#define EDMA_ECRH 0x100C
+#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
+#define EDMA_PARM 0x4000 /* 128 param entries */
+
+#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
+
+#define EDMA_DCHMAP 0x0100 /* 64 registers */
+#define CHMAP_EXIST BIT(24)
+
+
+/*function that maps the cross bar events to channels */
+int (*xbar_event_to_channel_map)(unsigned event, unsigned *channel,
+ struct event_to_channel_map *xbar_event_map) = NULL;
+
+/*****************************************************************************/
+
+static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
+
+static inline unsigned int edma_read(unsigned ctlr, int offset)
+{
+ return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
+}
+
+static inline void edma_write(unsigned ctlr, int offset, int val)
+{
+ __raw_writel(val, edmacc_regs_base[ctlr] + offset);
+}
+static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
+ unsigned or)
+{
+ unsigned val = edma_read(ctlr, offset);
+ val &= and;
+ val |= or;
+ edma_write(ctlr, offset, val);
+}
+static inline void edma_and(unsigned ctlr, int offset, unsigned and)
+{
+ unsigned val = edma_read(ctlr, offset);
+ val &= and;
+ edma_write(ctlr, offset, val);
+}
+static inline void edma_or(unsigned ctlr, int offset, unsigned or)
+{
+ unsigned val = edma_read(ctlr, offset);
+ val |= or;
+ edma_write(ctlr, offset, val);
+}
+static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
+{
+ return edma_read(ctlr, offset + (i << 2));
+}
+static inline unsigned int edma_read_array2(unsigned ctlr, int offset, int i,
+ int j)
+{
+ return edma_read(ctlr, offset + ((i*2 + j) << 2));
+}
+static inline void edma_write_array(unsigned ctlr, int offset, int i,
+ unsigned val)
+{
+ edma_write(ctlr, offset + (i << 2), val);
+}
+static inline void edma_modify_array(unsigned ctlr, int offset, int i,
+ unsigned and, unsigned or)
+{
+ edma_modify(ctlr, offset + (i << 2), and, or);
+}
+static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
+{
+ edma_or(ctlr, offset + (i << 2), or);
+}
+static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
+ unsigned or)
+{
+ edma_or(ctlr, offset + ((i*2 + j) << 2), or);
+}
+static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
+ unsigned val)
+{
+ edma_write(ctlr, offset + ((i*2 + j) << 2), val);
+}
+static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
+{
+ return edma_read(ctlr, EDMA_SHADOW0 + offset);
+}
+static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
+ int i)
+{
+ return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
+}
+static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
+{
+ edma_write(ctlr, EDMA_SHADOW0 + offset, val);
+}
+static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
+ unsigned val)
+{
+ edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
+}
+static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
+ int param_no)
+{
+ return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
+}
+static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
+ unsigned val)
+{
+ edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
+}
+static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
+ unsigned and, unsigned or)
+{
+ edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
+}
+static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
+ unsigned and)
+{
+ edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
+}
+static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
+ unsigned or)
+{
+ edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
+}
+
+static inline void set_bits(int offset, int len, unsigned long *p)
+{
+ for (; len > 0; len--)
+ set_bit(offset + (len - 1), p);
+}
+
+static inline void clear_bits(int offset, int len, unsigned long *p)
+{
+ for (; len > 0; len--)
+ clear_bit(offset + (len - 1), p);
+}
+
+/*****************************************************************************/
+
+struct edma *edma_cc[EDMA_MAX_CC];
+static int arch_num_cc;
+
+/* dummy param set used to (re)initialize parameter RAM slots */
+static const struct edmacc_param dummy_paramset = {
+ .link_bcntrld = 0xffff,
+ .ccnt = 1,
+};
+
+/*****************************************************************************/
+
+static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
+ enum dma_event_q queue_no)
+{
+ int bit = (ch_no & 0x7) * 4;
+
+ /* default to low priority queue */
+ if (queue_no == EVENTQ_DEFAULT)
+ queue_no = edma_cc[ctlr]->default_queue;
+
+ queue_no &= 7;
+ edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
+ ~(0x7 << bit), queue_no << bit);
+}
+
+static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
+{
+ int bit = queue_no * 4;
+ edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
+}
+
+static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
+ int priority)
+{
+ int bit = queue_no * 4;
+ edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
+ ((priority & 0x7) << bit));
+}
+
+/**
+ * map_dmach_param - Maps channel number to param entry number
+ *
+ * This maps the dma channel number to param entry numberter. In
+ * other words using the DMA channel mapping registers a param entry
+ * can be mapped to any channel
+ *
+ * Callers are responsible for ensuring the channel mapping logic is
+ * included in that particular EDMA variant (Eg : dm646x)
+ *
+ */
+static void __init map_dmach_param(unsigned ctlr)
+{
+ int i;
+ for (i = 0; i < EDMA_MAX_DMACH; i++)
+ edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
+}
+
+static inline void
+setup_dma_interrupt(unsigned lch,
+ void (*callback)(unsigned channel, u16 ch_status, void *data),
+ void *data)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(lch);
+ lch = EDMA_CHAN_SLOT(lch);
+
+ if (!callback)
+ edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
+ BIT(lch & 0x1f));
+
+ edma_cc[ctlr]->intr_data[lch].callback = callback;
+ edma_cc[ctlr]->intr_data[lch].data = data;
+
+ if (callback) {
+ edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
+ BIT(lch & 0x1f));
+ edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
+ BIT(lch & 0x1f));
+ }
+}
+
+static int irq2ctlr(int irq)
+{
+ if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
+ return 0;
+ else if (irq >= edma_cc[1]->irq_res_start &&
+ irq <= edma_cc[1]->irq_res_end)
+ return 1;
+
+ return -1;
+}
+
+/******************************************************************************
+ *
+ * DMA interrupt handler
+ *
+ *****************************************************************************/
+static irqreturn_t dma_irq_handler(int irq, void *data)
+{
+ int i;
+ int ctlr;
+ unsigned int cnt = 0;
+
+ ctlr = irq2ctlr(irq);
+ if (ctlr < 0)
+ return IRQ_NONE;
+
+ dev_dbg(data, "dma_irq_handler\n");
+
+ if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) &&
+ (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
+ return IRQ_NONE;
+
+ while (1) {
+ int j;
+ if (edma_shadow0_read_array(ctlr, SH_IPR, 0) &
+ edma_shadow0_read_array(ctlr, SH_IER, 0))
+ j = 0;
+ else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) &
+ edma_shadow0_read_array(ctlr, SH_IER, 1))
+ j = 1;
+ else
+ break;
+ dev_dbg(data, "IPR%d %08x\n", j,
+ edma_shadow0_read_array(ctlr, SH_IPR, j));
+ for (i = 0; i < 32; i++) {
+ int k = (j << 5) + i;
+ if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i))
+ && (edma_shadow0_read_array(ctlr,
+ SH_IER, j) & BIT(i))) {
+ /* Clear the corresponding IPR bits */
+ edma_shadow0_write_array(ctlr, SH_ICR, j,
+ BIT(i));
+ if (edma_cc[ctlr]->intr_data[k].callback)
+ edma_cc[ctlr]->intr_data[k].callback(
+ k, DMA_COMPLETE,
+ edma_cc[ctlr]->intr_data[k].
+ data);
+ }
+ }
+ cnt++;
+ if (cnt > 10)
+ break;
+ }
+ edma_shadow0_write(ctlr, SH_IEVAL, 1);
+ return IRQ_HANDLED;
+}
+
+/******************************************************************************
+ *
+ * DMA error interrupt handler
+ *
+ *****************************************************************************/
+static irqreturn_t dma_ccerr_handler(int irq, void *data)
+{
+ int i;
+ int ctlr;
+ unsigned int cnt = 0;
+
+ ctlr = irq2ctlr(irq);
+ if (ctlr < 0)
+ return IRQ_NONE;
+
+ dev_dbg(data, "dma_ccerr_handler\n");
+
+ if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
+ (edma_read(ctlr, EDMA_QEMR) == 0) &&
+ (edma_read(ctlr, EDMA_CCERR) == 0))
+ return IRQ_NONE;
+
+ while (1) {
+ int j = -1;
+ if (edma_read_array(ctlr, EDMA_EMR, 0))
+ j = 0;
+ else if (edma_read_array(ctlr, EDMA_EMR, 1))
+ j = 1;
+ if (j >= 0) {
+ dev_dbg(data, "EMR%d %08x\n", j,
+ edma_read_array(ctlr, EDMA_EMR, j));
+ for (i = 0; i < 32; i++) {
+ int k = (j << 5) + i;
+ if (edma_read_array(ctlr, EDMA_EMR, j) &
+ BIT(i)) {
+ /* Clear the corresponding EMR bits */
+ edma_write_array(ctlr, EDMA_EMCR, j,
+ BIT(i));
+ /* Clear any SER */
+ edma_shadow0_write_array(ctlr, SH_SECR,
+ j, BIT(i));
+ if (edma_cc[ctlr]->intr_data[k].
+ callback) {
+ edma_cc[ctlr]->intr_data[k].
+ callback(k,
+ DMA_CC_ERROR,
+ edma_cc[ctlr]->intr_data
+ [k].data);
+ }
+ }
+ }
+ } else if (edma_read(ctlr, EDMA_QEMR)) {
+ dev_dbg(data, "QEMR %02x\n",
+ edma_read(ctlr, EDMA_QEMR));
+ for (i = 0; i < 8; i++) {
+ if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
+ /* Clear the corresponding IPR bits */
+ edma_write(ctlr, EDMA_QEMCR, BIT(i));
+ edma_shadow0_write(ctlr, SH_QSECR,
+ BIT(i));
+
+ /* NOTE: not reported!! */
+ }
+ }
+ } else if (edma_read(ctlr, EDMA_CCERR)) {
+ dev_dbg(data, "CCERR %08x\n",
+ edma_read(ctlr, EDMA_CCERR));
+ /* FIXME: CCERR.BIT(16) ignored! much better
+ * to just write CCERRCLR with CCERR value...
+ */
+ for (i = 0; i < 8; i++) {
+ if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
+ /* Clear the corresponding IPR bits */
+ edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
+
+ /* NOTE: not reported!! */
+ }
+ }
+ }
+ if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
+ (edma_read(ctlr, EDMA_QEMR) == 0) &&
+ (edma_read(ctlr, EDMA_CCERR) == 0))
+ break;
+ cnt++;
+ if (cnt > 10)
+ break;
+ }
+ edma_write(ctlr, EDMA_EEVAL, 1);
+ return IRQ_HANDLED;
+}
+
+/*-----------------------------------------------------------------------*/
+
+static int reserve_contiguous_slots(int ctlr, unsigned int id,
+ unsigned int num_slots,
+ unsigned int start_slot)
+{
+ int i, j;
+ unsigned int count = num_slots;
+ int stop_slot = start_slot;
+ DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
+
+ for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
+ j = EDMA_CHAN_SLOT(i);
+ if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
+ /* Record our current beginning slot */
+ if (count == num_slots)
+ stop_slot = i;
+
+ count--;
+ set_bit(j, tmp_inuse);
+
+ if (count == 0)
+ break;
+ } else {
+ clear_bit(j, tmp_inuse);
+
+ if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
+ stop_slot = i;
+ break;
+ } else {
+ count = num_slots;
+ }
+ }
+ }
+
+ /*
+ * We have to clear any bits that we set
+ * if we run out parameter RAM slots, i.e we do find a set
+ * of contiguous parameter RAM slots but do not find the exact number
+ * requested as we may reach the total number of parameter RAM slots
+ */
+ if (i == edma_cc[ctlr]->num_slots)
+ stop_slot = i;
+
+ for (j = start_slot; j < stop_slot; j++)
+ if (test_bit(j, tmp_inuse))
+ clear_bit(j, edma_cc[ctlr]->edma_inuse);
+
+ if (count)
+ return -EBUSY;
+
+ for (j = i - num_slots + 1; j <= i; ++j)
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
+ &dummy_paramset, PARM_SIZE);
+
+ return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
+}
+
+static int prepare_unused_channel_list(struct device *dev, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ int i, ctlr;
+
+ for (i = 0; i < pdev->num_resources; i++) {
+ if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
+ (int)pdev->resource[i].start >= 0) {
+ ctlr = EDMA_CTLR(pdev->resource[i].start);
+ /* confirm the range */
+ if (EDMA_CHAN_SLOT(pdev->resource[i].start <
+ EDMA_MAX_DMACH))
+ clear_bit(
+ EDMA_CHAN_SLOT(pdev->resource[i].start),
+ edma_cc[ctlr]->edma_unused);
+ }
+ }
+
+ return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+
+static bool unused_chan_list_done;
+
+/* Resource alloc/free: dma channels, parameter RAM slots */
+
+/**
+ * edma_alloc_channel - allocate DMA channel and paired parameter RAM
+ * @channel: specific channel to allocate; negative for "any unmapped channel"
+ * @callback: optional; to be issued on DMA completion or errors
+ * @data: passed to callback
+ * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
+ * Controller (TC) executes requests using this channel. Use
+ * EVENTQ_DEFAULT unless you really need a high priority queue.
+ *
+ * This allocates a DMA channel and its associated parameter RAM slot.
+ * The parameter RAM is initialized to hold a dummy transfer.
+ *
+ * Normal use is to pass a specific channel number as @channel, to make
+ * use of hardware events mapped to that channel. When the channel will
+ * be used only for software triggering or event chaining, channels not
+ * mapped to hardware events (or mapped to unused events) are preferable.
+ *
+ * DMA transfers start from a channel using edma_start(), or by
+ * chaining. When the transfer described in that channel's parameter RAM
+ * slot completes, that slot's data may be reloaded through a link.
+ *
+ * DMA errors are only reported to the @callback associated with the
+ * channel driving that transfer, but transfer completion callbacks can
+ * be sent to another channel under control of the TCC field in
+ * the option word of the transfer's parameter RAM set. Drivers must not
+ * use DMA transfer completion callbacks for channels they did not allocate.
+ * (The same applies to TCC codes used in transfer chaining.)
+ *
+ * Returns the number of the channel, else negative errno.
+ */
+int edma_alloc_channel(int channel,
+ void (*callback)(unsigned channel, u16 ch_status, void *data),
+ void *data,
+ enum dma_event_q eventq_no)
+{
+ unsigned i, done = 0, ctlr = 0;
+ int ret = 0;
+
+ if (!unused_chan_list_done) {
+ /*
+ * Scan all the platform devices to find out the EDMA channels
+ * used and clear them in the unused list, making the rest
+ * available for ARM usage.
+ */
+ ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
+ prepare_unused_channel_list);
+ if (ret < 0)
+ return ret;
+
+ unused_chan_list_done = true;
+ }
+
+ if (channel >= 0) {
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+ if (xbar_event_to_channel_map) {
+ ret = xbar_event_to_channel_map(channel,
+ &channel, edma_cc[ctlr]->
+ xbar_event_mapping);
+ if (ret != 0)
+ return ret;
+ }
+ }
+
+ if (channel < 0) {
+ for (i = 0; i < arch_num_cc; i++) {
+ channel = 0;
+ for (;;) {
+ channel = find_next_bit(edma_cc[i]->edma_unused,
+ edma_cc[i]->num_channels,
+ channel);
+ if (channel == edma_cc[i]->num_channels)
+ break;
+ if (!test_and_set_bit(channel,
+ edma_cc[i]->edma_inuse)) {
+ done = 1;
+ ctlr = i;
+ break;
+ }
+ channel++;
+ }
+ if (done)
+ break;
+ }
+ if (!done)
+ return -ENOMEM;
+ } else if (channel >= edma_cc[ctlr]->num_channels) {
+ return -EINVAL;
+ } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
+ return -EBUSY;
+ }
+
+ /* ensure access through shadow region 0 */
+ edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
+
+ /* ensure no events are pending */
+ edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
+ &dummy_paramset, PARM_SIZE);
+
+ if (callback)
+ setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
+ callback, data);
+
+ map_dmach_queue(ctlr, channel, eventq_no);
+
+ return EDMA_CTLR_CHAN(ctlr, channel);
+}
+EXPORT_SYMBOL(edma_alloc_channel);
+
+
+/**
+ * edma_free_channel - deallocate DMA channel
+ * @channel: dma channel returned from edma_alloc_channel()
+ *
+ * This deallocates the DMA channel and associated parameter RAM slot
+ * allocated by edma_alloc_channel().
+ *
+ * Callers are responsible for ensuring the channel is inactive, and
+ * will not be reactivated by linking, chaining, or software calls to
+ * edma_start().
+ */
+void edma_free_channel(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel >= edma_cc[ctlr]->num_channels)
+ return;
+
+ setup_dma_interrupt(channel, NULL, NULL);
+ /* REVISIT should probably take out of shadow region 0 */
+
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
+ &dummy_paramset, PARM_SIZE);
+ clear_bit(channel, edma_cc[ctlr]->edma_inuse);
+}
+EXPORT_SYMBOL(edma_free_channel);
+
+/**
+ * edma_alloc_slot - allocate DMA parameter RAM
+ * @slot: specific slot to allocate; negative for "any unused slot"
+ *
+ * This allocates a parameter RAM slot, initializing it to hold a
+ * dummy transfer. Slots allocated using this routine have not been
+ * mapped to a hardware DMA channel, and will normally be used by
+ * linking to them from a slot associated with a DMA channel.
+ *
+ * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
+ * slots may be allocated on behalf of DSP firmware.
+ *
+ * Returns the number of the slot, else negative errno.
+ */
+int edma_alloc_slot(unsigned ctlr, int slot)
+{
+ if (slot >= 0)
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < 0) {
+ slot = edma_cc[ctlr]->num_channels;
+ for (;;) {
+ slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
+ edma_cc[ctlr]->num_slots, slot);
+ if (slot == edma_cc[ctlr]->num_slots)
+ return -ENOMEM;
+ if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
+ break;
+ }
+ } else if (slot < edma_cc[ctlr]->num_channels ||
+ slot >= edma_cc[ctlr]->num_slots) {
+ return -EINVAL;
+ } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
+ return -EBUSY;
+ }
+
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
+ &dummy_paramset, PARM_SIZE);
+
+ return EDMA_CTLR_CHAN(ctlr, slot);
+}
+EXPORT_SYMBOL(edma_alloc_slot);
+
+/**
+ * edma_free_slot - deallocate DMA parameter RAM
+ * @slot: parameter RAM slot returned from edma_alloc_slot()
+ *
+ * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
+ * Callers are responsible for ensuring the slot is inactive, and will
+ * not be activated.
+ */
+void edma_free_slot(unsigned slot)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_channels ||
+ slot >= edma_cc[ctlr]->num_slots)
+ return;
+
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
+ &dummy_paramset, PARM_SIZE);
+ clear_bit(slot, edma_cc[ctlr]->edma_inuse);
+}
+EXPORT_SYMBOL(edma_free_slot);
+
+
+/**
+ * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
+ * The API will return the starting point of a set of
+ * contiguous parameter RAM slots that have been requested
+ *
+ * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
+ * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
+ * @count: number of contiguous Paramter RAM slots
+ * @slot - the start value of Parameter RAM slot that should be passed if id
+ * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
+ *
+ * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
+ * contiguous Parameter RAM slots from parameter RAM 64 in the case of
+ * DaVinci SOCs and 32 in the case of DA8xx SOCs.
+ *
+ * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
+ * set of contiguous parameter RAM slots from the "slot" that is passed as an
+ * argument to the API.
+ *
+ * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
+ * starts looking for a set of contiguous parameter RAMs from the "slot"
+ * that is passed as an argument to the API. On failure the API will try to
+ * find a set of contiguous Parameter RAM slots from the remaining Parameter
+ * RAM slots
+ */
+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
+{
+ /*
+ * The start slot requested should be greater than
+ * the number of channels and lesser than the total number
+ * of slots
+ */
+ if ((id != EDMA_CONT_PARAMS_ANY) &&
+ (slot < edma_cc[ctlr]->num_channels ||
+ slot >= edma_cc[ctlr]->num_slots))
+ return -EINVAL;
+
+ /*
+ * The number of parameter RAM slots requested cannot be less than 1
+ * and cannot be more than the number of slots minus the number of
+ * channels
+ */
+ if (count < 1 || count >
+ (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
+ return -EINVAL;
+
+ switch (id) {
+ case EDMA_CONT_PARAMS_ANY:
+ return reserve_contiguous_slots(ctlr, id, count,
+ edma_cc[ctlr]->num_channels);
+ case EDMA_CONT_PARAMS_FIXED_EXACT:
+ case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
+ return reserve_contiguous_slots(ctlr, id, count, slot);
+ default:
+ return -EINVAL;
+ }
+
+}
+EXPORT_SYMBOL(edma_alloc_cont_slots);
+
+/**
+ * edma_free_cont_slots - deallocate DMA parameter RAM slots
+ * @slot: first parameter RAM of a set of parameter RAM slots to be freed
+ * @count: the number of contiguous parameter RAM slots to be freed
+ *
+ * This deallocates the parameter RAM slots allocated by
+ * edma_alloc_cont_slots.
+ * Callers/applications need to keep track of sets of contiguous
+ * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
+ * API.
+ * Callers are responsible for ensuring the slots are inactive, and will
+ * not be activated.
+ */
+int edma_free_cont_slots(unsigned slot, int count)
+{
+ unsigned ctlr, slot_to_free;
+ int i;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_channels ||
+ slot >= edma_cc[ctlr]->num_slots ||
+ count < 1)
+ return -EINVAL;
+
+ for (i = slot; i < slot + count; ++i) {
+ ctlr = EDMA_CTLR(i);
+ slot_to_free = EDMA_CHAN_SLOT(i);
+
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
+ &dummy_paramset, PARM_SIZE);
+ clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(edma_free_cont_slots);
+
+/*-----------------------------------------------------------------------*/
+
+/* Parameter RAM operations (i) -- read/write partial slots */
+
+/**
+ * edma_set_src - set initial DMA source address in parameter RAM slot
+ * @slot: parameter RAM slot being configured
+ * @src_port: physical address of source (memory, controller FIFO, etc)
+ * @addressMode: INCR, except in very rare cases
+ * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
+ * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ *
+ * Note that the source address is modified during the DMA transfer
+ * according to edma_set_src_index().
+ */
+void edma_set_src(unsigned slot, dma_addr_t src_port,
+ enum address_mode mode, enum fifo_width width)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_slots) {
+ unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
+
+ if (mode) {
+ /* set SAM and program FWID */
+ i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
+ } else {
+ /* clear SAM */
+ i &= ~SAM;
+ }
+ edma_parm_write(ctlr, PARM_OPT, slot, i);
+
+ /* set the source port address
+ in source register of param structure */
+ edma_parm_write(ctlr, PARM_SRC, slot, src_port);
+ }
+}
+EXPORT_SYMBOL(edma_set_src);
+
+/**
+ * edma_set_dest - set initial DMA destination address in parameter RAM slot
+ * @slot: parameter RAM slot being configured
+ * @dest_port: physical address of destination (memory, controller FIFO, etc)
+ * @addressMode: INCR, except in very rare cases
+ * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
+ * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ *
+ * Note that the destination address is modified during the DMA transfer
+ * according to edma_set_dest_index().
+ */
+void edma_set_dest(unsigned slot, dma_addr_t dest_port,
+ enum address_mode mode, enum fifo_width width)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_slots) {
+ unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
+
+ if (mode) {
+ /* set DAM and program FWID */
+ i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
+ } else {
+ /* clear DAM */
+ i &= ~DAM;
+ }
+ edma_parm_write(ctlr, PARM_OPT, slot, i);
+ /* set the destination port address
+ in dest register of param structure */
+ edma_parm_write(ctlr, PARM_DST, slot, dest_port);
+ }
+}
+EXPORT_SYMBOL(edma_set_dest);
+
+/**
+ * edma_get_position - returns the current transfer points
+ * @slot: parameter RAM slot being examined
+ * @src: pointer to source port position
+ * @dst: pointer to destination port position
+ *
+ * Returns current source and destination addresses for a particular
+ * parameter RAM slot. Its channel should not be active when this is called.
+ */
+void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
+{
+ struct edmacc_param temp;
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
+ if (src != NULL)
+ *src = temp.src;
+ if (dst != NULL)
+ *dst = temp.dst;
+}
+EXPORT_SYMBOL(edma_get_position);
+
+/**
+ * edma_set_src_index - configure DMA source address indexing
+ * @slot: parameter RAM slot being configured
+ * @src_bidx: byte offset between source arrays in a frame
+ * @src_cidx: byte offset between source frames in a block
+ *
+ * Offsets are specified to support either contiguous or discontiguous
+ * memory transfers, or repeated access to a hardware register, as needed.
+ * When accessing hardware registers, both offsets are normally zero.
+ */
+void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_slots) {
+ edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
+ 0xffff0000, src_bidx);
+ edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
+ 0xffff0000, src_cidx);
+ }
+}
+EXPORT_SYMBOL(edma_set_src_index);
+
+/**
+ * edma_set_dest_index - configure DMA destination address indexing
+ * @slot: parameter RAM slot being configured
+ * @dest_bidx: byte offset between destination arrays in a frame
+ * @dest_cidx: byte offset between destination frames in a block
+ *
+ * Offsets are specified to support either contiguous or discontiguous
+ * memory transfers, or repeated access to a hardware register, as needed.
+ * When accessing hardware registers, both offsets are normally zero.
+ */
+void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_slots) {
+ edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
+ 0x0000ffff, dest_bidx << 16);
+ edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
+ 0x0000ffff, dest_cidx << 16);
+ }
+}
+EXPORT_SYMBOL(edma_set_dest_index);
+
+/**
+ * edma_set_transfer_params - configure DMA transfer parameters
+ * @slot: parameter RAM slot being configured
+ * @acnt: how many bytes per array (at least one)
+ * @bcnt: how many arrays per frame (at least one)
+ * @ccnt: how many frames per block (at least one)
+ * @bcnt_rld: used only for A-Synchronized transfers; this specifies
+ * the value to reload into bcnt when it decrements to zero
+ * @sync_mode: ASYNC or ABSYNC
+ *
+ * See the EDMA3 documentation to understand how to configure and link
+ * transfers using the fields in PaRAM slots. If you are not doing it
+ * all at once with edma_write_slot(), you will use this routine
+ * plus two calls each for source and destination, setting the initial
+ * address and saying how to index that address.
+ *
+ * An example of an A-Synchronized transfer is a serial link using a
+ * single word shift register. In that case, @acnt would be equal to
+ * that word size; the serial controller issues a DMA synchronization
+ * event to transfer each word, and memory access by the DMA transfer
+ * controller will be word-at-a-time.
+ *
+ * An example of an AB-Synchronized transfer is a device using a FIFO.
+ * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
+ * The controller with the FIFO issues DMA synchronization events when
+ * the FIFO threshold is reached, and the DMA transfer controller will
+ * transfer one frame to (or from) the FIFO. It will probably use
+ * efficient burst modes to access memory.
+ */
+void edma_set_transfer_params(unsigned slot,
+ u16 acnt, u16 bcnt, u16 ccnt,
+ u16 bcnt_rld, enum sync_dimension sync_mode)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_slots) {
+ edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
+ 0x0000ffff, bcnt_rld << 16);
+ if (sync_mode == ASYNC)
+ edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
+ else
+ edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
+ /* Set the acount, bcount, ccount registers */
+ edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
+ edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
+ }
+}
+EXPORT_SYMBOL(edma_set_transfer_params);
+
+/**
+ * edma_link - link one parameter RAM slot to another
+ * @from: parameter RAM slot originating the link
+ * @to: parameter RAM slot which is the link target
+ *
+ * The originating slot should not be part of any active DMA transfer.
+ */
+void edma_link(unsigned from, unsigned to)
+{
+ unsigned ctlr_from, ctlr_to;
+
+ ctlr_from = EDMA_CTLR(from);
+ from = EDMA_CHAN_SLOT(from);
+ ctlr_to = EDMA_CTLR(to);
+ to = EDMA_CHAN_SLOT(to);
+
+ if (from >= edma_cc[ctlr_from]->num_slots)
+ return;
+ if (to >= edma_cc[ctlr_to]->num_slots)
+ return;
+ edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
+ PARM_OFFSET(to));
+}
+EXPORT_SYMBOL(edma_link);
+
+/**
+ * edma_unlink - cut link from one parameter RAM slot
+ * @from: parameter RAM slot originating the link
+ *
+ * The originating slot should not be part of any active DMA transfer.
+ * Its link is set to 0xffff.
+ */
+void edma_unlink(unsigned from)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(from);
+ from = EDMA_CHAN_SLOT(from);
+
+ if (from >= edma_cc[ctlr]->num_slots)
+ return;
+ edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
+}
+EXPORT_SYMBOL(edma_unlink);
+
+/*-----------------------------------------------------------------------*/
+
+/* Parameter RAM operations (ii) -- read/write whole parameter sets */
+
+/**
+ * edma_write_slot - write parameter RAM data for slot
+ * @slot: number of parameter RAM slot being modified
+ * @param: data to be written into parameter RAM slot
+ *
+ * Use this to assign all parameters of a transfer at once. This
+ * allows more efficient setup of transfers than issuing multiple
+ * calls to set up those parameters in small pieces, and provides
+ * complete control over all transfer options.
+ */
+void edma_write_slot(unsigned slot, const struct edmacc_param *param)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot >= edma_cc[ctlr]->num_slots)
+ return;
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
+ PARM_SIZE);
+}
+EXPORT_SYMBOL(edma_write_slot);
+
+/**
+ * edma_read_slot - read parameter RAM data from slot
+ * @slot: number of parameter RAM slot being copied
+ * @param: where to store copy of parameter RAM data
+ *
+ * Use this to read data from a parameter RAM slot, perhaps to
+ * save them as a template for later reuse.
+ */
+void edma_read_slot(unsigned slot, struct edmacc_param *param)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot >= edma_cc[ctlr]->num_slots)
+ return;
+ memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
+ PARM_SIZE);
+}
+EXPORT_SYMBOL(edma_read_slot);
+
+/*-----------------------------------------------------------------------*/
+
+/* Various EDMA channel control operations */
+
+/**
+ * edma_pause - pause dma on a channel
+ * @channel: on which edma_start() has been called
+ *
+ * This temporarily disables EDMA hardware events on the specified channel,
+ * preventing them from triggering new transfers on its behalf
+ */
+void edma_pause(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_cc[ctlr]->num_channels) {
+ unsigned int mask = BIT(channel & 0x1f);
+
+ edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
+ }
+}
+EXPORT_SYMBOL(edma_pause);
+
+/**
+ * edma_resume - resumes dma on a paused channel
+ * @channel: on which edma_pause() has been called
+ *
+ * This re-enables EDMA hardware events on the specified channel.
+ */
+void edma_resume(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_cc[ctlr]->num_channels) {
+ unsigned int mask = BIT(channel & 0x1f);
+
+ edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
+ }
+}
+EXPORT_SYMBOL(edma_resume);
+
+/**
+ * edma_start - start dma on a channel
+ * @channel: channel being activated
+ *
+ * Channels with event associations will be triggered by their hardware
+ * events, and channels without such associations will be triggered by
+ * software. (At this writing there is no interface for using software
+ * triggers except with channels that don't support hardware triggers.)
+ *
+ * Returns zero on success, else negative errno.
+ */
+int edma_start(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_cc[ctlr]->num_channels) {
+ int j = channel >> 5;
+ unsigned int mask = BIT(channel & 0x1f);
+
+ /* EDMA channels without event association */
+ if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
+ pr_debug("EDMA: ESR%d %08x\n", j,
+ edma_shadow0_read_array(ctlr, SH_ESR, j));
+ edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
+ return 0;
+ }
+
+ /* EDMA channel with event association */
+ pr_debug("EDMA: ER%d %08x\n", j,
+ edma_shadow0_read_array(ctlr, SH_ER, j));
+ /* Clear any pending event or error */
+ edma_write_array(ctlr, EDMA_ECR, j, mask);
+ edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ /* Clear any SER */
+ edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+ edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
+ pr_debug("EDMA: EER%d %08x\n", j,
+ edma_shadow0_read_array(ctlr, SH_EER, j));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(edma_start);
+
+/**
+ * edma_stop - stops dma on the channel passed
+ * @channel: channel being deactivated
+ *
+ * When @lch is a channel, any active transfer is paused and
+ * all pending hardware events are cleared. The current transfer
+ * may not be resumed, and the channel's Parameter RAM should be
+ * reinitialized before being reused.
+ */
+void edma_stop(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_cc[ctlr]->num_channels) {
+ int j = channel >> 5;
+ unsigned int mask = BIT(channel & 0x1f);
+
+ edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
+ edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
+ edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+ edma_write_array(ctlr, EDMA_EMCR, j, mask);
+
+ pr_debug("EDMA: EER%d %08x\n", j,
+ edma_shadow0_read_array(ctlr, SH_EER, j));
+
+ /* REVISIT: consider guarding against inappropriate event
+ * chaining by overwriting with dummy_paramset.
+ */
+ }
+}
+EXPORT_SYMBOL(edma_stop);
+
+/******************************************************************************
+ *
+ * It cleans ParamEntry qand bring back EDMA to initial state if media has
+ * been removed before EDMA has finished.It is usedful for removable media.
+ * Arguments:
+ * ch_no - channel no
+ *
+ * Return: zero on success, or corresponding error no on failure
+ *
+ * FIXME this should not be needed ... edma_stop() should suffice.
+ *
+ *****************************************************************************/
+
+void edma_clean_channel(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_cc[ctlr]->num_channels) {
+ int j = (channel >> 5);
+ unsigned int mask = BIT(channel & 0x1f);
+
+ pr_debug("EDMA: EMR%d %08x\n", j,
+ edma_read_array(ctlr, EDMA_EMR, j));
+ edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
+ /* Clear the corresponding EMR bits */
+ edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ /* Clear any SER */
+ edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+ edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
+ }
+}
+EXPORT_SYMBOL(edma_clean_channel);
+
+/*
+ * edma_clear_event - clear an outstanding event on the DMA channel
+ * Arguments:
+ * channel - channel number
+ */
+void edma_clear_event(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel >= edma_cc[ctlr]->num_channels)
+ return;
+ if (channel < 32)
+ edma_write(ctlr, EDMA_ECR, BIT(channel));
+ else
+ edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
+}
+EXPORT_SYMBOL(edma_clear_event);
+
+/*-----------------------------------------------------------------------*/
+
+static int __init edma_probe(struct platform_device *pdev)
+{
+ struct edma_soc_info *info = pdev->dev.platform_data;
+ const s8 (*queue_priority_mapping)[2];
+ const s8 (*queue_tc_mapping)[2];
+ int i, j, off, ln, found = 0;
+ int status = -1;
+ const s16 (*rsv_chans)[2];
+ const s16 (*rsv_slots)[2];
+ int irq[EDMA_MAX_CC] = {0, 0};
+ int err_irq[EDMA_MAX_CC] = {0, 0};
+ struct resource *r[EDMA_MAX_CC] = {NULL};
+ resource_size_t len[EDMA_MAX_CC];
+ char res_name[10];
+ char irq_name[10];
+
+ if (!info)
+ return -ENODEV;
+
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_get_sync(&pdev->dev);
+
+ for (j = 0; j < EDMA_MAX_CC; j++) {
+ sprintf(res_name, "edma_cc%d", j);
+ r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ res_name);
+ if (!r[j]) {
+ if (found)
+ break;
+ else
+ return -ENODEV;
+ } else {
+ found = 1;
+ }
+
+ len[j] = resource_size(r[j]);
+
+ r[j] = request_mem_region(r[j]->start, len[j],
+ dev_name(&pdev->dev));
+ if (!r[j]) {
+ status = -EBUSY;
+ goto fail1;
+ }
+
+ edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
+ if (!edmacc_regs_base[j]) {
+ status = -EBUSY;
+ goto fail1;
+ }
+
+ edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
+ if (!edma_cc[j]) {
+ status = -ENOMEM;
+ goto fail1;
+ }
+
+ edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel,
+ EDMA_MAX_DMACH);
+ edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot,
+ EDMA_MAX_PARAMENTRY);
+ edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC);
+ edma_cc[j]->num_region = min_t(unsigned, info[j].n_region,
+ EDMA_MAX_REGION);
+
+ edma_cc[j]->bkp_prm_set = kzalloc((sizeof(struct edmacc_param) *
+ edma_cc[j]->num_slots),
+ GFP_KERNEL);
+ if (!edma_cc[j]->bkp_prm_set) {
+ status = -ENOMEM;
+ dev_err(&pdev->dev, "err: mem alloc bkp_prm_set\n");
+ goto fail1;
+ }
+
+ edma_cc[j]->bkp_ch_map = kzalloc((sizeof(unsigned int) *
+ edma_cc[j]->num_channels),
+ GFP_KERNEL);
+ if (!edma_cc[j]->bkp_ch_map) {
+ status = -ENOMEM;
+ dev_err(&pdev->dev, "err: mem alloc bkp_ch_map\n");
+ goto fail1;
+ }
+
+ edma_cc[j]->bkp_que_num = kzalloc((sizeof(unsigned int) * 8),
+ GFP_KERNEL);
+ if (!edma_cc[j]->bkp_que_num) {
+ status = -ENOMEM;
+ dev_err(&pdev->dev, "err: mem alloc bkp_que_num\n");
+ goto fail1;
+ }
+
+ edma_cc[j]->bkp_drae = kzalloc((sizeof(unsigned int) *
+ edma_cc[j]->num_region),
+ GFP_KERNEL);
+ if (!edma_cc[j]->bkp_drae) {
+ status = -ENOMEM;
+ dev_err(&pdev->dev, "err: mem alloc bkp_drae\n");
+ goto fail1;
+ }
+
+ edma_cc[j]->bkp_draeh = kzalloc((sizeof(unsigned int) *
+ edma_cc[j]->num_region),
+ GFP_KERNEL);
+ if (!edma_cc[j]->bkp_draeh) {
+ status = -ENOMEM;
+ dev_err(&pdev->dev, "err: mem alloc bkp_draeh\n");
+ goto fail1;
+ }
+
+ edma_cc[j]->bkp_qrae = kzalloc((sizeof(unsigned int) *
+ edma_cc[j]->num_region),
+ GFP_KERNEL);
+ if (!edma_cc[j]->bkp_qrae) {
+ status = -ENOMEM;
+ dev_err(&pdev->dev, "err: mem alloc bkp_qrae\n");
+ goto fail1;
+ }
+
+ edma_cc[j]->default_queue = info[j].default_queue;
+ if (!edma_cc[j]->default_queue)
+ edma_cc[j]->default_queue = EVENTQ_1;
+
+ dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
+ edmacc_regs_base[j]);
+
+ for (i = 0; i < edma_cc[j]->num_slots; i++)
+ memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
+ &dummy_paramset, PARM_SIZE);
+
+ /* Mark all channels as unused */
+ memset(edma_cc[j]->edma_unused, 0xff,
+ sizeof(edma_cc[j]->edma_unused));
+
+ /* Clear the reserved channels in unused list */
+ rsv_chans = info[j].rsv_chans;
+ if (rsv_chans) {
+ for (i = 0; rsv_chans[i][0] != -1; i++) {
+ off = rsv_chans[i][0];
+ ln = rsv_chans[i][1];
+ /* confirm the range */
+ if ((off+ln) < EDMA_MAX_DMACH)
+ clear_bits(off, ln,
+ edma_cc[j]->edma_unused);
+ }
+ }
+
+ /* Set the reserved channels/slots in inuse list */
+ rsv_slots = info[j].rsv_slots;
+ if (rsv_slots) {
+ for (i = 0; rsv_slots[i][0] != -1; i++) {
+ off = rsv_slots[i][0];
+ ln = rsv_slots[i][1];
+ set_bits(off, ln, edma_cc[j]->edma_inuse);
+ }
+ }
+
+ sprintf(irq_name, "edma%d", j);
+ irq[j] = platform_get_irq_byname(pdev, irq_name);
+ edma_cc[j]->irq_res_start = irq[j];
+ status = request_irq(irq[j], dma_irq_handler, 0, "edma",
+ &pdev->dev);
+ if (status < 0) {
+ dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+ irq[j], status);
+ goto fail;
+ }
+
+ sprintf(irq_name, "edma%d_err", j);
+ err_irq[j] = platform_get_irq_byname(pdev, irq_name);
+ edma_cc[j]->irq_res_end = err_irq[j];
+ status = request_irq(err_irq[j], dma_ccerr_handler, 0,
+ "edma_error", &pdev->dev);
+ if (status < 0) {
+ dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+ err_irq[j], status);
+ goto fail;
+ }
+
+ /* Everything lives on transfer controller 1 until otherwise
+ * specified. This way, long transfers on the low priority queue
+ * started by the codec engine will not cause audio defects.
+ */
+ for (i = 0; i < edma_cc[j]->num_channels; i++)
+ map_dmach_queue(j, i, EVENTQ_1);
+
+ queue_tc_mapping = info[j].queue_tc_mapping;
+ queue_priority_mapping = info[j].queue_priority_mapping;
+
+ /* Event queue to TC mapping */
+ for (i = 0; queue_tc_mapping[i][0] != -1; i++)
+ map_queue_tc(j, queue_tc_mapping[i][0],
+ queue_tc_mapping[i][1]);
+
+ /* Event queue priority mapping */
+ for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+ assign_priority_to_queue(j,
+ queue_priority_mapping[i][0],
+ queue_priority_mapping[i][1]);
+
+ /* Map the channel to param entry if channel mapping logic
+ * exist
+ */
+ if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
+ map_dmach_param(j);
+
+ for (i = 0; i < info[j].n_region; i++) {
+ edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
+ edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
+ edma_write_array(j, EDMA_QRAE, i, 0x0);
+ }
+
+ edma_cc[j]->is_xbar = info[j].is_xbar;
+
+ if (edma_cc[j]->is_xbar) {
+ edma_cc[j]->num_events = info[j].n_events;
+ edma_cc[j]->xbar_event_mapping =
+ info[j].xbar_event_mapping;
+ xbar_event_to_channel_map = info[j].map_xbar_channel;
+ }
+
+ arch_num_cc++;
+ }
+
+ return 0;
+
+fail:
+ for (i = 0; i < EDMA_MAX_CC; i++) {
+ if (err_irq[i])
+ free_irq(err_irq[i], &pdev->dev);
+ if (irq[i])
+ free_irq(irq[i], &pdev->dev);
+ }
+fail1:
+ for (i = 0; i < EDMA_MAX_CC; i++) {
+ if (r[i])
+ release_mem_region(r[i]->start, len[i]);
+ if (edmacc_regs_base[i])
+ iounmap(edmacc_regs_base[i]);
+ kfree(edma_cc[i]);
+ }
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ return status;
+}
+
+#ifdef CONFIG_PM
+static int edma3_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ int i, j;
+
+ for (i = 0; i < arch_num_cc; i++) {
+ /* backup channel data */
+ for (j = 0; j < edma_cc[i]->num_channels; j++) {
+ edma_cc[i]->bkp_ch_map[j] = edma_read_array(i,
+ EDMA_DCHMAP, j);
+ }
+
+ /* backup DMA Queue Number */
+ for (j = 0; j < 8; j++) {
+ edma_cc[i]->bkp_que_num[j] = edma_read_array(i,
+ EDMA_DMAQNUM, j);
+ }
+
+ for (j = 0; j < edma_cc[i]->num_region; j++) {
+ /* backup DMA DMA Region Access Enable data */
+ edma_cc[i]->bkp_drae[j] = edma_read_array2(i,
+ EDMA_DRAE, j, 0);
+ edma_cc[i]->bkp_draeh[j] = edma_read_array2(i,
+ EDMA_DRAE, j, 1);
+
+ /* backup DMA QDMA Region Access Enable data */
+ edma_cc[i]->bkp_qrae[j] = edma_read_array(i,
+ EDMA_QRAE, j);
+ }
+
+ /* backup DMA shadow Event Set data */
+ edma_cc[i]->bkp_sh_esr = edma_shadow0_read_array(i, SH_ESR, 0);
+ edma_cc[i]->bkp_sh_esrh = edma_shadow0_read_array(i, SH_ESR, 1);
+
+ /* backup DMA Shadow Event Enable Set data */
+ edma_cc[i]->bkp_sh_eesr = edma_shadow0_read_array(i,
+ SH_EER, 0);
+ edma_cc[i]->bkp_sh_eesrh = edma_shadow0_read_array(i,
+ SH_EER, 1);
+
+ /* backup DMA Shadow Interrupt Enable Set data */
+ edma_cc[i]->bkp_sh_iesr = edma_shadow0_read_array(i,
+ SH_IER, 0);
+ edma_cc[i]->bkp_sh_iesrh = edma_shadow0_read_array(i,
+ SH_IER, 1);
+
+ edma_cc[i]->bkp_que_tc_map = edma_read(i, EDMA_QUETCMAP);
+
+ /* backup DMA Queue Priority data */
+ edma_cc[i]->bkp_que_pri = edma_read(i, EDMA_QUEPRI);
+
+ /* backup paramset */
+ for (j = 0; j < edma_cc[i]->num_slots; j++) {
+ memcpy_fromio(&edma_cc[i]->bkp_prm_set[j],
+ edmacc_regs_base[i] + PARM_OFFSET(j),
+ PARM_SIZE);
+ }
+ }
+
+ pm_runtime_put_sync(&pdev->dev);
+
+ return 0;
+}
+
+static int edma3_resume(struct platform_device *pdev)
+{
+ int i, j;
+
+ pm_runtime_get_sync(&pdev->dev);
+
+ for (i = 0; i < arch_num_cc; i++) {
+
+ /* restore channel data */
+ for (j = 0; j < edma_cc[i]->num_channels; j++) {
+ edma_write_array(i, EDMA_DCHMAP, j,
+ edma_cc[i]->bkp_ch_map[j]);
+ }
+
+ /* restore DMA Queue Number */
+ for (j = 0; j < 8; j++) {
+ edma_write_array(i, EDMA_DMAQNUM, j,
+ edma_cc[i]->bkp_que_num[j]);
+ }
+
+ for (j = 0; j < edma_cc[i]->num_region; j++) {
+ /* restore DMA DMA Region Access Enable data */
+ edma_write_array2(i, EDMA_DRAE, j, 0,
+ edma_cc[i]->bkp_drae[j]);
+ edma_write_array2(i, EDMA_DRAE, j, 1,
+ edma_cc[i]->bkp_draeh[j]);
+
+ /* restore DMA QDMA Region Access Enable data */
+ edma_write_array(i, EDMA_QRAE, j,
+ edma_cc[i]->bkp_qrae[j]);
+ }
+
+ /* restore DMA shadow Event Set data */
+ edma_shadow0_write_array(i, SH_ESR, 0, edma_cc[i]->bkp_sh_esr);
+ edma_shadow0_write_array(i, SH_ESR, 1, edma_cc[i]->bkp_sh_esrh);
+
+ /* restore DMA Shadow Event Enable Set data */
+ edma_shadow0_write_array(i, SH_EESR, 0,
+ edma_cc[i]->bkp_sh_eesr);
+ edma_shadow0_write_array(i, SH_EESR, 1,
+ edma_cc[i]->bkp_sh_eesrh);
+
+ /* restore DMA Shadow Interrupt Enable Set data */
+ edma_shadow0_write_array(i, SH_IESR, 0,
+ edma_cc[i]->bkp_sh_iesr);
+ edma_shadow0_write_array(i, SH_IESR, 1,
+ edma_cc[i]->bkp_sh_iesrh);
+
+ edma_write(i, EDMA_QUETCMAP, edma_cc[i]->bkp_que_tc_map);
+
+ /* restore DMA Queue Priority data */
+ edma_write(i, EDMA_QUEPRI, edma_cc[i]->bkp_que_pri);
+
+ /* restore paramset */
+ for (j = 0; j < edma_cc[i]->num_slots; j++) {
+ memcpy_toio(edmacc_regs_base[i] + PARM_OFFSET(j),
+ &edma_cc[i]->bkp_prm_set[j], PARM_SIZE);
+ }
+ }
+
+ return 0;
+}
+
+#else
+#define edma3_suspend NULL
+#define edma3_resume NULL
+#endif
+
+static struct platform_driver edma_driver = {
+ .driver.name = "edma",
+ .suspend = edma3_suspend,
+ .resume = edma3_resume,
+};
+
+static int __init edma_init(void)
+{
+ return platform_driver_probe(&edma_driver, edma_probe);
+}
+subsys_initcall(edma_init);
diff -PurN linux-stable-23d8c3f/arch/arm/common/gic.c kernel_3.2.14_patched/arch/arm/common/gic.c
--- linux-stable-23d8c3f/arch/arm/common/gic.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/common/gic.c 2012-05-16 12:10:46.000000000 +0100
@@ -40,13 +40,36 @@
#include <linux/slab.h>
#include <asm/irq.h>
+#include <asm/exception.h>
#include <asm/mach/irq.h>
#include <asm/hardware/gic.h>
-static DEFINE_RAW_SPINLOCK(irq_controller_lock);
+union gic_base {
+ void __iomem *common_base;
+ void __percpu __iomem **percpu_base;
+};
-/* Address of GIC 0 CPU interface */
-void __iomem *gic_cpu_base_addr __read_mostly;
+struct gic_chip_data {
+ unsigned int irq_offset;
+ union gic_base dist_base;
+ union gic_base cpu_base;
+#ifdef CONFIG_CPU_PM
+ u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
+ u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
+ u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
+ u32 __percpu *saved_ppi_enable;
+ u32 __percpu *saved_ppi_conf;
+#endif
+#ifdef CONFIG_IRQ_DOMAIN
+ struct irq_domain domain;
+#endif
+ unsigned int gic_irqs;
+#ifdef CONFIG_GIC_NON_BANKED
+ void __iomem *(*get_base)(union gic_base *);
+#endif
+};
+
+static DEFINE_RAW_SPINLOCK(irq_controller_lock);
/*
* Supported arch specific GIC irq extension.
@@ -67,16 +90,48 @@
static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
+#ifdef CONFIG_GIC_NON_BANKED
+static void __iomem *gic_get_percpu_base(union gic_base *base)
+{
+ return *__this_cpu_ptr(base->percpu_base);
+}
+
+static void __iomem *gic_get_common_base(union gic_base *base)
+{
+ return base->common_base;
+}
+
+static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
+{
+ return data->get_base(&data->dist_base);
+}
+
+static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
+{
+ return data->get_base(&data->cpu_base);
+}
+
+static inline void gic_set_base_accessor(struct gic_chip_data *data,
+ void __iomem *(*f)(union gic_base *))
+{
+ data->get_base = f;
+}
+#else
+#define gic_data_dist_base(d) ((d)->dist_base.common_base)
+#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
+#define gic_set_base_accessor(d,f)
+#endif
+
static inline void __iomem *gic_dist_base(struct irq_data *d)
{
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
- return gic_data->dist_base;
+ return gic_data_dist_base(gic_data);
}
static inline void __iomem *gic_cpu_base(struct irq_data *d)
{
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
- return gic_data->cpu_base;
+ return gic_data_cpu_base(gic_data);
}
static inline unsigned int gic_irq(struct irq_data *d)
@@ -215,6 +270,32 @@
#define gic_set_wake NULL
#endif
+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+ u32 irqstat, irqnr;
+ struct gic_chip_data *gic = &gic_data[0];
+ void __iomem *cpu_base = gic_data_cpu_base(gic);
+
+ do {
+ irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
+ irqnr = irqstat & ~0x1c00;
+
+ if (likely(irqnr > 15 && irqnr < 1021)) {
+ irqnr = irq_domain_to_irq(&gic->domain, irqnr);
+ handle_IRQ(irqnr, regs);
+ continue;
+ }
+ if (irqnr < 16) {
+ writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
+#ifdef CONFIG_SMP
+ handle_IPI(irqnr, regs);
+#endif
+ continue;
+ }
+ break;
+ } while (1);
+}
+
static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct gic_chip_data *chip_data = irq_get_handler_data(irq);
@@ -225,7 +306,7 @@
chained_irq_enter(chip, desc);
raw_spin_lock(&irq_controller_lock);
- status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
+ status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
raw_spin_unlock(&irq_controller_lock);
gic_irq = (status & 0x3ff);
@@ -270,7 +351,7 @@
u32 cpumask;
unsigned int gic_irqs = gic->gic_irqs;
struct irq_domain *domain = &gic->domain;
- void __iomem *base = gic->dist_base;
+ void __iomem *base = gic_data_dist_base(gic);
u32 cpu = 0;
#ifdef CONFIG_SMP
@@ -330,8 +411,8 @@
static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
{
- void __iomem *dist_base = gic->dist_base;
- void __iomem *base = gic->cpu_base;
+ void __iomem *dist_base = gic_data_dist_base(gic);
+ void __iomem *base = gic_data_cpu_base(gic);
int i;
/*
@@ -368,7 +449,7 @@
BUG();
gic_irqs = gic_data[gic_nr].gic_irqs;
- dist_base = gic_data[gic_nr].dist_base;
+ dist_base = gic_data_dist_base(&gic_data[gic_nr]);
if (!dist_base)
return;
@@ -403,7 +484,7 @@
BUG();
gic_irqs = gic_data[gic_nr].gic_irqs;
- dist_base = gic_data[gic_nr].dist_base;
+ dist_base = gic_data_dist_base(&gic_data[gic_nr]);
if (!dist_base)
return;
@@ -439,8 +520,8 @@
if (gic_nr >= MAX_GIC_NR)
BUG();
- dist_base = gic_data[gic_nr].dist_base;
- cpu_base = gic_data[gic_nr].cpu_base;
+ dist_base = gic_data_dist_base(&gic_data[gic_nr]);
+ cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
if (!dist_base || !cpu_base)
return;
@@ -465,8 +546,8 @@
if (gic_nr >= MAX_GIC_NR)
BUG();
- dist_base = gic_data[gic_nr].dist_base;
- cpu_base = gic_data[gic_nr].cpu_base;
+ dist_base = gic_data_dist_base(&gic_data[gic_nr]);
+ cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
if (!dist_base || !cpu_base)
return;
@@ -491,6 +572,11 @@
int i;
for (i = 0; i < MAX_GIC_NR; i++) {
+#ifdef CONFIG_GIC_NON_BANKED
+ /* Skip over unused GICs */
+ if (!gic_data[i].get_base)
+ continue;
+#endif
switch (cmd) {
case CPU_PM_ENTER:
gic_cpu_save(i);
@@ -564,8 +650,9 @@
#endif
};
-void __init gic_init(unsigned int gic_nr, int irq_start,
- void __iomem *dist_base, void __iomem *cpu_base)
+void __init gic_init_bases(unsigned int gic_nr, int irq_start,
+ void __iomem *dist_base, void __iomem *cpu_base,
+ u32 percpu_offset)
{
struct gic_chip_data *gic;
struct irq_domain *domain;
@@ -575,8 +662,36 @@
gic = &gic_data[gic_nr];
domain = &gic->domain;
- gic->dist_base = dist_base;
- gic->cpu_base = cpu_base;
+#ifdef CONFIG_GIC_NON_BANKED
+ if (percpu_offset) { /* Frankein-GIC without banked registers... */
+ unsigned int cpu;
+
+ gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
+ gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
+ if (WARN_ON(!gic->dist_base.percpu_base ||
+ !gic->cpu_base.percpu_base)) {
+ free_percpu(gic->dist_base.percpu_base);
+ free_percpu(gic->cpu_base.percpu_base);
+ return;
+ }
+
+ for_each_possible_cpu(cpu) {
+ unsigned long offset = percpu_offset * cpu_logical_map(cpu);
+ *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
+ *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
+ }
+
+ gic_set_base_accessor(gic, gic_get_percpu_base);
+ } else
+#endif
+ { /* Normal, sane GIC... */
+ WARN(percpu_offset,
+ "GIC_NON_BANKED not enabled, ignoring %08x offset!",
+ percpu_offset);
+ gic->dist_base.common_base = dist_base;
+ gic->cpu_base.common_base = cpu_base;
+ gic_set_base_accessor(gic, gic_get_common_base);
+ }
/*
* For primary GICs, skip over SGIs.
@@ -584,8 +699,6 @@
*/
domain->hwirq_base = 32;
if (gic_nr == 0) {
- gic_cpu_base_addr = cpu_base;
-
if ((irq_start & 31) > 0) {
domain->hwirq_base = 16;
if (irq_start != -1)
@@ -597,7 +710,7 @@
* Find out how many interrupts are supported.
* The GIC only supports up to 1020 interrupt sources.
*/
- gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
+ gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
gic_irqs = (gic_irqs + 1) * 32;
if (gic_irqs > 1020)
gic_irqs = 1020;
@@ -645,7 +758,7 @@
dsb();
/* this always happens on GIC0 */
- writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
+ writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
}
#endif
@@ -656,6 +769,7 @@
{
void __iomem *cpu_base;
void __iomem *dist_base;
+ u32 percpu_offset;
int irq;
struct irq_domain *domain = &gic_data[gic_cnt].domain;
@@ -668,9 +782,12 @@
cpu_base = of_iomap(node, 1);
WARN(!cpu_base, "unable to map gic cpu registers\n");
+ if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
+ percpu_offset = 0;
+
domain->of_node = of_node_get(node);
- gic_init(gic_cnt, -1, dist_base, cpu_base);
+ gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset);
if (parent) {
irq = irq_of_parse_and_map(node, 0);
diff -PurN linux-stable-23d8c3f/arch/arm/common/Kconfig kernel_3.2.14_patched/arch/arm/common/Kconfig
--- linux-stable-23d8c3f/arch/arm/common/Kconfig 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/common/Kconfig 2012-05-16 12:10:46.000000000 +0100
@@ -1,8 +1,14 @@
config ARM_GIC
select IRQ_DOMAIN
+ select MULTI_IRQ_HANDLER
+ bool
+
+config GIC_NON_BANKED
bool
config ARM_VIC
+ select IRQ_DOMAIN
+ select MULTI_IRQ_HANDLER
bool
config ARM_VIC_NR
diff -PurN linux-stable-23d8c3f/arch/arm/common/Makefile kernel_3.2.14_patched/arch/arm/common/Makefile
--- linux-stable-23d8c3f/arch/arm/common/Makefile 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/common/Makefile 2012-05-16 12:10:46.000000000 +0100
@@ -17,3 +17,4 @@
obj-$(CONFIG_ARCH_IXP23XX) += uengine.o
obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
+obj-$(CONFIG_OMAP3_EDMA) += edma.o
diff -PurN linux-stable-23d8c3f/arch/arm/common/vic.c kernel_3.2.14_patched/arch/arm/common/vic.c
--- linux-stable-23d8c3f/arch/arm/common/vic.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/common/vic.c 2012-05-16 12:10:46.000000000 +0100
@@ -19,17 +19,22 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+#include <linux/export.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <linux/syscore_ops.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
+#include <asm/exception.h>
#include <asm/mach/irq.h>
#include <asm/hardware/vic.h>
-#ifdef CONFIG_PM
/**
* struct vic_device - VIC PM device
* @irq: The IRQ number for the base of the VIC.
@@ -40,6 +45,7 @@
* @int_enable: Save for VIC_INT_ENABLE.
* @soft_int: Save for VIC_INT_SOFT.
* @protect: Save for VIC_PROTECT.
+ * @domain: The IRQ domain for the VIC.
*/
struct vic_device {
void __iomem *base;
@@ -50,13 +56,13 @@
u32 int_enable;
u32 soft_int;
u32 protect;
+ struct irq_domain domain;
};
/* we cannot allocate memory when VICs are initially registered */
static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
static int vic_id;
-#endif /* CONFIG_PM */
/**
* vic_init2 - common initialisation code
@@ -156,39 +162,50 @@
return 0;
}
late_initcall(vic_pm_init);
+#endif /* CONFIG_PM */
/**
- * vic_pm_register - Register a VIC for later power management control
+ * vic_register() - Register a VIC.
* @base: The base address of the VIC.
* @irq: The base IRQ for the VIC.
* @resume_sources: bitmask of interrupts allowed for resume sources.
+ * @node: The device tree node associated with the VIC.
*
* Register the VIC with the system device tree so that it can be notified
* of suspend and resume requests and ensure that the correct actions are
* taken to re-instate the settings on resume.
+ *
+ * This also configures the IRQ domain for the VIC.
*/
-static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
+static void __init vic_register(void __iomem *base, unsigned int irq,
+ u32 resume_sources, struct device_node *node)
{
struct vic_device *v;
- if (vic_id >= ARRAY_SIZE(vic_devices))
+ if (vic_id >= ARRAY_SIZE(vic_devices)) {
printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
- else {
- v = &vic_devices[vic_id];
- v->base = base;
- v->resume_sources = resume_sources;
- v->irq = irq;
- vic_id++;
+ return;
}
+
+ v = &vic_devices[vic_id];
+ v->base = base;
+ v->resume_sources = resume_sources;
+ v->irq = irq;
+ vic_id++;
+
+ v->domain.irq_base = irq;
+ v->domain.nr_irq = 32;
+#ifdef CONFIG_OF_IRQ
+ v->domain.of_node = of_node_get(node);
+ v->domain.ops = &irq_domain_simple_ops;
+#endif /* CONFIG_OF */
+ irq_domain_add(&v->domain);
}
-#else
-static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
-#endif /* CONFIG_PM */
static void vic_ack_irq(struct irq_data *d)
{
void __iomem *base = irq_data_get_irq_chip_data(d);
- unsigned int irq = d->irq & 31;
+ unsigned int irq = d->hwirq;
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
/* moreover, clear the soft-triggered, in case it was the reason */
writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
@@ -197,14 +214,14 @@
static void vic_mask_irq(struct irq_data *d)
{
void __iomem *base = irq_data_get_irq_chip_data(d);
- unsigned int irq = d->irq & 31;
+ unsigned int irq = d->hwirq;
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
}
static void vic_unmask_irq(struct irq_data *d)
{
void __iomem *base = irq_data_get_irq_chip_data(d);
- unsigned int irq = d->irq & 31;
+ unsigned int irq = d->hwirq;
writel(1 << irq, base + VIC_INT_ENABLE);
}
@@ -226,7 +243,7 @@
static int vic_set_wake(struct irq_data *d, unsigned int on)
{
struct vic_device *v = vic_from_irq(d->irq);
- unsigned int off = d->irq & 31;
+ unsigned int off = d->hwirq;
u32 bit = 1 << off;
if (!v)
@@ -330,15 +347,9 @@
vic_set_irq_sources(base, irq_start, vic_sources);
}
-/**
- * vic_init - initialise a vectored interrupt controller
- * @base: iomem base address
- * @irq_start: starting interrupt number, must be muliple of 32
- * @vic_sources: bitmask of interrupt sources to allow
- * @resume_sources: bitmask of interrupt sources to allow for resume
- */
-void __init vic_init(void __iomem *base, unsigned int irq_start,
- u32 vic_sources, u32 resume_sources)
+static void __init __vic_init(void __iomem *base, unsigned int irq_start,
+ u32 vic_sources, u32 resume_sources,
+ struct device_node *node)
{
unsigned int i;
u32 cellid = 0;
@@ -375,5 +386,81 @@
vic_set_irq_sources(base, irq_start, vic_sources);
- vic_pm_register(base, irq_start, resume_sources);
+ vic_register(base, irq_start, resume_sources, node);
+}
+
+/**
+ * vic_init() - initialise a vectored interrupt controller
+ * @base: iomem base address
+ * @irq_start: starting interrupt number, must be muliple of 32
+ * @vic_sources: bitmask of interrupt sources to allow
+ * @resume_sources: bitmask of interrupt sources to allow for resume
+ */
+void __init vic_init(void __iomem *base, unsigned int irq_start,
+ u32 vic_sources, u32 resume_sources)
+{
+ __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
+}
+
+#ifdef CONFIG_OF
+int __init vic_of_init(struct device_node *node, struct device_node *parent)
+{
+ void __iomem *regs;
+ int irq_base;
+
+ if (WARN(parent, "non-root VICs are not supported"))
+ return -EINVAL;
+
+ regs = of_iomap(node, 0);
+ if (WARN_ON(!regs))
+ return -EIO;
+
+ irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
+ if (WARN_ON(irq_base < 0))
+ goto out_unmap;
+
+ __vic_init(regs, irq_base, ~0, ~0, node);
+
+ return 0;
+
+ out_unmap:
+ iounmap(regs);
+
+ return -EIO;
+}
+#endif /* CONFIG OF */
+
+/*
+ * Handle each interrupt in a single VIC. Returns non-zero if we've
+ * handled at least one interrupt. This does a single read of the
+ * status register and handles all interrupts in order from LSB first.
+ */
+static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
+{
+ u32 stat, irq;
+ int handled = 0;
+
+ stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
+ while (stat) {
+ irq = ffs(stat) - 1;
+ handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
+ stat &= ~(1 << irq);
+ handled = 1;
+ }
+
+ return handled;
+}
+
+/*
+ * Keep iterating over all registered VIC's until there are no pending
+ * interrupts.
+ */
+asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
+{
+ int i, handled;
+
+ do {
+ for (i = 0, handled = 0; i < vic_id; ++i)
+ handled |= handle_one_vic(&vic_devices[i], regs);
+ } while (handled);
}
diff -PurN linux-stable-23d8c3f/arch/arm/configs/am335x_evm_defconfig kernel_3.2.14_patched/arch/arm/configs/am335x_evm_defconfig
--- linux-stable-23d8c3f/arch/arm/configs/am335x_evm_defconfig 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/configs/am335x_evm_defconfig 2012-05-16 12:10:46.000000000 +0100
@@ -0,0 +1,2602 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 3.2.0 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_SCHED_CLOCK=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_HAVE_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+# CONFIG_SPARSE_IRQ is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TINY_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_CGROUPS is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EXPERT is not set
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+# CONFIG_EMBEDDED is not set
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+
+#
+# GCOV-based kernel profiling
+#
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_HIGHBANK is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_PRIMA2 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_PICOXCELL is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_TCC_926 is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_VT8500 is not set
+# CONFIG_ARCH_ZYNQ is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+
+#
+# TI OMAP Common Features
+#
+# CONFIG_ARCH_OMAP1 is not set
+CONFIG_ARCH_OMAP2PLUS=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_SMARTREFLEX is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_MUX=y
+CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_OMAP_MUX_WARNINGS=y
+# CONFIG_OMAP_MCBSP is not set
+CONFIG_OMAP_MBOX_FWK=y
+CONFIG_OMAP_MBOX_KFIFO_SIZE=256
+# CONFIG_OMAP_32K_TIMER is not set
+# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_PM_NOOP=y
+CONFIG_MACH_OMAP_GENERIC=y
+
+#
+# TI OMAP2/3/4 Specific Features
+#
+CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+# CONFIG_ARCH_OMAP4 is not set
+# CONFIG_SOC_OMAP3430 is not set
+CONFIG_SOC_OMAPTI81XX=y
+CONFIG_SOC_OMAPAM33XX=y
+CONFIG_OMAP_PACKAGE_CBB=y
+
+#
+# OMAP Board Type
+#
+CONFIG_MACH_OMAP3_BEAGLE=y
+# CONFIG_MACH_DEVKIT8000 is not set
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP3530_LV_SOM is not set
+# CONFIG_MACH_OMAP3_TORPEDO is not set
+# CONFIG_MACH_ENCORE is not set
+# CONFIG_MACH_OVERO is not set
+# CONFIG_MACH_OMAP3EVM is not set
+# CONFIG_MACH_OMAP3517EVM is not set
+# CONFIG_MACH_CRANEBOARD is not set
+# CONFIG_MACH_OMAP3_PANDORA is not set
+# CONFIG_MACH_OMAP3_TOUCHBOOK is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_NOKIA_RM680 is not set
+# CONFIG_MACH_NOKIA_RX51 is not set
+# CONFIG_MACH_OMAP_ZOOM2 is not set
+# CONFIG_MACH_OMAP_ZOOM3 is not set
+# CONFIG_MACH_CM_T35 is not set
+# CONFIG_MACH_CM_T3517 is not set
+# CONFIG_MACH_IGEP0020 is not set
+# CONFIG_MACH_IGEP0030 is not set
+# CONFIG_MACH_SBC3530 is not set
+# CONFIG_MACH_OMAP_3630SDP is not set
+CONFIG_MACH_TI8168EVM=y
+CONFIG_MACH_TI8148EVM=y
+CONFIG_MACH_AM335XEVM=y
+CONFIG_MACH_AM335XIAEVM=y
+# CONFIG_OMAP3_EMU is not set
+# CONFIG_OMAP3_SDRC_AC_TIMING is not set
+CONFIG_OMAP3_EDMA=y
+
+#
+# System MMU
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_SWP_EMULATE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_MULTI_IRQ_HANDLER=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_ARM_ERRATA_743622 is not set
+# CONFIG_ARM_ERRATA_751472 is not set
+# CONFIG_ARM_ERRATA_754322 is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HAVE_ARCH_PFN_VALID=y
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_CLEANCACHE is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+
+#
+# Boot options
+#
+CONFIG_USE_OF=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_ARM_APPENDED_DTB is not set
+CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO0,115200"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_AUTO_ZRELADDR is not set
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+
+#
+# ARM CPU frequency scaling drivers
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_CAN_PM_TRACE=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_HAS_OPP=y
+CONFIG_PM_OPP=y
+CONFIG_PM_CLK=y
+CONFIG_CPU_PM=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CONNTRACK_MARK is not set
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+# CONFIG_NF_CT_PROTO_DCCP is not set
+# CONFIG_NF_CT_PROTO_SCTP is not set
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+# CONFIG_NF_CONNTRACK_FTP is not set
+# CONFIG_NF_CONNTRACK_H323 is not set
+# CONFIG_NF_CONNTRACK_IRC is not set
+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
+# CONFIG_NF_CONNTRACK_SNMP is not set
+# CONFIG_NF_CONNTRACK_PPTP is not set
+# CONFIG_NF_CONNTRACK_SANE is not set
+# CONFIG_NF_CONNTRACK_SIP is not set
+# CONFIG_NF_CONNTRACK_TFTP is not set
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+# CONFIG_NETFILTER_XT_MARK is not set
+# CONFIG_NETFILTER_XT_CONNMARK is not set
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+
+#
+# Xtables matches
+#
+# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
+# CONFIG_NETFILTER_XT_MATCH_HL is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_STATE is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=y
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+CONFIG_IP_NF_FILTER=y
+# CONFIG_IP_NF_TARGET_REJECT is not set
+CONFIG_IP_NF_TARGET_LOG=y
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+# CONFIG_IP_NF_TARGET_NETMAP is not set
+# CONFIG_IP_NF_TARGET_REDIRECT is not set
+# CONFIG_NF_NAT_FTP is not set
+# CONFIG_NF_NAT_IRC is not set
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+# CONFIG_NF_NAT_SIP is not set
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_SECURITY is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+# CONFIG_CAN_GW is not set
+
+#
+# CAN Device Drivers
+#
+# CONFIG_CAN_VCAN is not set
+# CONFIG_CAN_SLCAN is not set
+CONFIG_CAN_DEV=y
+CONFIG_CAN_CALC_BITTIMING=y
+# CONFIG_CAN_TI_HECC is not set
+# CONFIG_CAN_MCP251X is not set
+# CONFIG_CAN_SJA1000 is not set
+# CONFIG_CAN_C_CAN is not set
+CONFIG_CAN_D_CAN=y
+CONFIG_CAN_D_CAN_PLATFORM=y
+
+#
+# CAN USB interfaces
+#
+# CONFIG_CAN_EMS_USB is not set
+# CONFIG_CAN_ESD_USB2 is not set
+# CONFIG_CAN_SOFTING is not set
+# CONFIG_CAN_DEBUG_DEVICES is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+# CONFIG_RFKILL_REGULATOR is not set
+# CONFIG_RFKILL_GPIO is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE="am335x-pm-firmware.bin"
+CONFIG_EXTRA_FIRMWARE_DIR="firmware"
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SPI=y
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_OF_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+CONFIG_MTD_OOPS=y
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PHYSMAP_OF is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_DOCG3 is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_ONENAND=y
+# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_DEBUG is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+
+#
+# Device Tree and Open Firmware support
+#
+CONFIG_PROC_DEVICETREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
+CONFIG_OF_NET=y
+CONFIG_OF_SPI=y
+CONFIG_OF_MDIO=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_BLK_DEV_RBD is not set
+CONFIG_SENSORS_LIS3LV02D=y
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+CONFIG_SENSORS_TSL2550=y
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+CONFIG_SENSORS_LIS3_I2C=y
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_MII=y
+# CONFIG_MACVLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+CONFIG_NET_VENDOR_CHELSIO=y
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+CONFIG_NET_VENDOR_FARADAY=y
+# CONFIG_FTMAC100 is not set
+# CONFIG_FTGMAC100 is not set
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_MARVELL=y
+CONFIG_NET_VENDOR_MICREL=y
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+CONFIG_NET_VENDOR_NATSEMI=y
+CONFIG_NET_VENDOR_8390=y
+# CONFIG_AX88796 is not set
+# CONFIG_ETHOC is not set
+CONFIG_NET_VENDOR_SEEQ=y
+# CONFIG_SEEQ8005 is not set
+CONFIG_NET_VENDOR_SMSC=y
+CONFIG_SMC91X=y
+# CONFIG_SMC911X is not set
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+CONFIG_NET_VENDOR_STMICRO=y
+# CONFIG_STMMAC_ETH is not set
+CONFIG_NET_VENDOR_TI=y
+# CONFIG_TI_DAVINCI_EMAC is not set
+CONFIG_TI_DAVINCI_MDIO=y
+CONFIG_TI_DAVINCI_CPDMA=y
+CONFIG_TI_CPSW=y
+CONFIG_TLK110_WORKAROUND=y
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_AX8817X is not set
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_CDC_EEM=y
+CONFIG_USB_NET_CDC_NCM=y
+CONFIG_USB_NET_DM9601=y
+# CONFIG_USB_NET_SMSC75XX is not set
+# CONFIG_USB_NET_SMSC95XX is not set
+# CONFIG_USB_NET_GL620A is not set
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+# CONFIG_USB_NET_RNDIS_HOST is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_USB_NET_CX82310_ETH is not set
+# CONFIG_USB_NET_KALMIA is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_USB_VL600 is not set
+CONFIG_WLAN=y
+CONFIG_USB_ZD1201=y
+# CONFIG_HOSTAP is not set
+CONFIG_WL12XX_PLATFORM_DATA=y
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_TCA6416 is not set
+CONFIG_KEYBOARD_MATRIX=y
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_TWL4030 is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+CONFIG_TOUCHSCREEN_TI_TSCADC=y
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_TWL4030_PWRBUTTON is not set
+# CONFIG_INPUT_TWL4030_VIBRA is not set
+# CONFIG_INPUT_TWL6040_VIBRA is not set
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_CMA3000 is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_OMAP=y
+CONFIG_SERIAL_OMAP_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_HVC_DCC is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_OC_TINY is not set
+CONFIG_SPI_OMAP24XX=y
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO drivers:
+#
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_TWL4030 is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+CONFIG_GPIO_TPS65910=y
+CONFIG_GENERIC_PWM=y
+CONFIG_DAVINCI_EHRPWM=y
+CONFIG_ECAP_PWM=y
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+CONFIG_SENSORS_LM75=y
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_CORE is not set
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_DW_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+# CONFIG_TWL4030_WATCHDOG is not set
+# CONFIG_MAX63XX_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+CONFIG_MFD_TPS65217=y
+# CONFIG_MFD_TPS6586X is not set
+CONFIG_MFD_TPS65910=y
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_TWL4030_MADC is not set
+CONFIG_TWL4030_POWER=y
+# CONFIG_MFD_TWL4030_AUDIO is not set
+# CONFIG_TWL6030_PWM is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+CONFIG_REGULATOR_DUMMY=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_GPIO is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_TWL4030 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+CONFIG_REGULATOR_TPS65217=y
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_REGULATOR_TPS65910=y
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_RC_CORE is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA827X=y
+CONFIG_MEDIA_TUNER_TDA18271=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_XC4000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+
+#
+# Encoders, decoders, sensors and other helper chips
+#
+
+#
+# Audio decoders, processors and mixers
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_AK881X is not set
+
+#
+# Camera sensor devices
+#
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+
+#
+# Flash devices
+#
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_VPFE_CAPTURE is not set
+# CONFIG_VIDEO_OMAP2_VOUT is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_RADIO_ADAPTERS is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+CONFIG_FB_DA8XX=y
+CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE=5
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_OMAP is not set
+# CONFIG_OMAP2_DSS is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_S6E63M0 is not set
+# CONFIG_LCD_LD9040 is not set
+# CONFIG_LCD_AMS369FG06 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+CONFIG_BACKLIGHT_TLC59108=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_ALOOP is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_6FIRE is not set
+CONFIG_SND_SOC=y
+# CONFIG_SND_SOC_CACHE_LZO is not set
+CONFIG_SND_AM33XX_SOC=y
+CONFIG_SND_DAVINCI_SOC_MCASP=y
+CONFIG_SND_AM335X_SOC_EVM=y
+# CONFIG_SND_OMAP_SOC is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_TLV320AIC3X=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=y
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+# CONFIG_HID_PRODIKEYS is not set
+CONFIG_HID_CYPRESS=y
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+CONFIG_HID_EZKEY=y
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+CONFIG_HID_KYE=y
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+CONFIG_HID_KENSINGTON=y
+# CONFIG_HID_LCPOWER is not set
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_LOGITECH_DJ=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGIG940_FF is not set
+# CONFIG_LOGIWHEELS_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB_ARCH_HAS_XHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+
+#
+# Platform Glue Layer
+#
+# CONFIG_USB_MUSB_TUSB6010_GLUE is not set
+# CONFIG_USB_MUSB_OMAP2PLUS_GLUE is not set
+# CONFIG_USB_MUSB_AM35X_GLUE is not set
+CONFIG_USB_MUSB_TI81XX_GLUE=y
+# CONFIG_USB_MUSB_DAVINCI is not set
+# CONFIG_USB_MUSB_DA8XX is not set
+# CONFIG_USB_MUSB_TUSB6010 is not set
+# CONFIG_USB_MUSB_OMAP2PLUS is not set
+# CONFIG_USB_MUSB_AM35X is not set
+CONFIG_USB_MUSB_TI81XX=y
+# CONFIG_USB_MUSB_BLACKFIN is not set
+# CONFIG_USB_MUSB_UX500 is not set
+CONFIG_USB_TI_CPPI41_DMA_HW=y
+# CONFIG_MUSB_PIO_ONLY is not set
+# CONFIG_USB_INVENTRA_DMA is not set
+# CONFIG_USB_TI_CPPI_DMA is not set
+CONFIG_USB_TI_CPPI41_DMA=y
+# CONFIG_USB_TUSB_OMAP_DMA is not set
+# CONFIG_USB_UX500_DMA is not set
+# CONFIG_USB_RENESAS_USBHS is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_UAS is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+# CONFIG_USB_FUSB300 is not set
+# CONFIG_USB_OMAP is not set
+# CONFIG_USB_R8A66597 is not set
+CONFIG_USB_GADGET_MUSB_HDRC=y
+# CONFIG_USB_M66592 is not set
+# CONFIG_USB_NET2272 is not set
+# CONFIG_USB_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+# CONFIG_USB_G_NCM is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_MASS_STORAGE=m
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_ACM_MS is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_TWL6030_USB is not set
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_OMAP is not set
+CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_TWL4030 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_OMAP=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_BALLOON is not set
+# CONFIG_VIRTIO_MMIO is not set
+# CONFIG_STAGING is not set
+CONFIG_CLKDEV_LOOKUP=y
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_CLKSRC_MMIO=y
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_PM_DEVFREQ is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QUOTA_DEBUG is not set
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_NEW_IDMAPPER is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_RING_BUFFER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_STRICT_DEVMEM is not set
+# CONFIG_ARM_UNWIND is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_JTAG_ENABLE=y
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_TOMOYO is not set
+# CONFIG_SECURITY_APPARMOR is not set
+# CONFIG_IMA is not set
+# CONFIG_EVM is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_USER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+# CONFIG_CRC8 is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
diff -PurN linux-stable-23d8c3f/arch/arm/configs/beaglebone_defconfig kernel_3.2.14_patched/arch/arm/configs/beaglebone_defconfig
--- linux-stable-23d8c3f/arch/arm/configs/beaglebone_defconfig 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/configs/beaglebone_defconfig 2012-05-16 16:49:34.000000000 +0100
@@ -0,0 +1,3581 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 3.2.14 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_SCHED_CLOCK=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_LZMA is not set
+CONFIG_KERNEL_LZO=y
+CONFIG_DEFAULT_HOSTNAME="BeagleBone"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_FHANDLE=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_HAVE_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_SPARSE_IRQ=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TINY_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
+CONFIG_CGROUP_MEM_RES_CTLR_SWAP_ENABLED=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+# CONFIG_DEBUG_BLK_CGROUP is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_THROTTLING=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CFQ_GROUP_IOSCHED=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_HIGHBANK is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_PRIMA2 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_PICOXCELL is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_TCC_926 is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_VT8500 is not set
+# CONFIG_ARCH_ZYNQ is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+
+#
+# TI OMAP Common Features
+#
+# CONFIG_ARCH_OMAP1 is not set
+CONFIG_ARCH_OMAP2PLUS=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_SMARTREFLEX is not set
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_MUX=y
+CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_OMAP_MUX_WARNINGS=y
+CONFIG_OMAP_MCBSP=y
+CONFIG_OMAP_MBOX_FWK=y
+CONFIG_OMAP_MBOX_KFIFO_SIZE=256
+# CONFIG_OMAP_32K_TIMER is not set
+# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_PM_NOOP=y
+CONFIG_MACH_OMAP_GENERIC=y
+
+#
+# TI OMAP2/3/4 Specific Features
+#
+CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+# CONFIG_ARCH_OMAP4 is not set
+# CONFIG_SOC_OMAP3430 is not set
+CONFIG_SOC_OMAPTI81XX=y
+CONFIG_SOC_OMAPAM33XX=y
+CONFIG_OMAP_PACKAGE_CBB=y
+
+#
+# OMAP Board Type
+#
+CONFIG_MACH_OMAP3_BEAGLE=y
+# CONFIG_MACH_DEVKIT8000 is not set
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP3530_LV_SOM is not set
+# CONFIG_MACH_OMAP3_TORPEDO is not set
+# CONFIG_MACH_ENCORE is not set
+# CONFIG_MACH_OVERO is not set
+# CONFIG_MACH_OMAP3EVM is not set
+# CONFIG_MACH_OMAP3517EVM is not set
+# CONFIG_MACH_CRANEBOARD is not set
+# CONFIG_MACH_OMAP3_PANDORA is not set
+# CONFIG_MACH_OMAP3_TOUCHBOOK is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_NOKIA_RM680 is not set
+# CONFIG_MACH_NOKIA_RX51 is not set
+# CONFIG_MACH_OMAP_ZOOM2 is not set
+# CONFIG_MACH_OMAP_ZOOM3 is not set
+# CONFIG_MACH_CM_T35 is not set
+# CONFIG_MACH_CM_T3517 is not set
+# CONFIG_MACH_IGEP0020 is not set
+# CONFIG_MACH_IGEP0030 is not set
+# CONFIG_MACH_SBC3530 is not set
+# CONFIG_MACH_OMAP_3630SDP is not set
+CONFIG_MACH_TI8168EVM=y
+CONFIG_MACH_TI8148EVM=y
+CONFIG_MACH_AM335XEVM=y
+CONFIG_MACH_AM335XIAEVM=y
+# CONFIG_OMAP3_EMU is not set
+# CONFIG_OMAP3_SDRC_AC_TIMING is not set
+CONFIG_OMAP3_EDMA=y
+
+#
+# System MMU
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_SWP_EMULATE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_ARM_ERRATA_430973=y
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_ARM_ERRATA_743622 is not set
+# CONFIG_ARM_ERRATA_751472 is not set
+# CONFIG_ARM_ERRATA_754322 is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_THUMB2_KERNEL=y
+CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y
+CONFIG_ARM_ASM_UNIFIED=y
+CONFIG_AEABI=y
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HAVE_ARCH_PFN_VALID=y
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_CLEANCACHE is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+
+#
+# Boot options
+#
+CONFIG_USE_OF=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_ARM_APPENDED_DTB is not set
+CONFIG_CMDLINE=" debug "
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_AUTO_ZRELADDR=y
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+
+#
+# ARM CPU frequency scaling drivers
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_ADVANCED_DEBUG is not set
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_CAN_PM_TRACE=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_HAS_OPP=y
+CONFIG_PM_OPP=y
+CONFIG_PM_CLK=y
+CONFIG_CPU_PM=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+CONFIG_IP_MROUTE=y
+# CONFIG_IP_PIMSM_V1 is not set
+# CONFIG_IP_PIMSM_V2 is not set
+CONFIG_ARPD=y
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_SIT_6RD=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+# CONFIG_NETFILTER_XT_MARK is not set
+
+#
+# Xtables targets
+#
+CONFIG_NETFILTER_XT_TARGET_AUDIT=m
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+
+#
+# Xtables matches
+#
+# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HL is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=m
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+# CONFIG_IP_NF_FILTER is not set
+# CONFIG_IP_NF_TARGET_LOG is not set
+# CONFIG_IP_NF_TARGET_ULOG is not set
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_SECURITY is not set
+CONFIG_IP_NF_ARPTABLES=m
+# CONFIG_IP_NF_ARPFILTER is not set
+# CONFIG_IP_NF_ARP_MANGLE is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV6 is not set
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+# CONFIG_NET_SCH_SFB is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=m
+CONFIG_CAN_GW=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+CONFIG_CAN_SLCAN=m
+CONFIG_CAN_DEV=y
+CONFIG_CAN_CALC_BITTIMING=y
+CONFIG_CAN_TI_HECC=m
+CONFIG_CAN_MCP251X=y
+# CONFIG_CAN_SJA1000 is not set
+# CONFIG_CAN_C_CAN is not set
+CONFIG_CAN_D_CAN=y
+CONFIG_CAN_D_CAN_PLATFORM=y
+
+#
+# CAN USB interfaces
+#
+CONFIG_CAN_EMS_USB=m
+CONFIG_CAN_ESD_USB2=m
+# CONFIG_CAN_SOFTING is not set
+CONFIG_CAN_DEBUG_DEVICES=y
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+CONFIG_IRNET=m
+CONFIG_IRCOMM=m
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+CONFIG_IRTTY_SIR=m
+
+#
+# Dongle support
+#
+# CONFIG_DONGLE is not set
+CONFIG_KINGSUN_DONGLE=m
+CONFIG_KSDAZZLE_DONGLE=m
+CONFIG_KS959_DONGLE=m
+
+#
+# FIR device drivers
+#
+CONFIG_USB_IRDA=m
+CONFIG_SIGMATEL_FIR=m
+CONFIG_MCS_FIR=m
+CONFIG_BT=m
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_ATH3K is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_WIMAX=m
+CONFIG_WIMAX_DEBUG_LEVEL=8
+CONFIG_RFKILL=m
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_REGULATOR=m
+CONFIG_RFKILL_GPIO=m
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+CONFIG_CEPH_LIB=m
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
+CONFIG_NFC=m
+CONFIG_NFC_NCI=m
+
+#
+# Near Field Communication (NFC) devices
+#
+CONFIG_PN544_NFC=m
+CONFIG_NFC_PN533=m
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE="am335x-pm-firmware.bin"
+CONFIG_EXTRA_FIRMWARE_DIR="firmware"
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SPI=y
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+# CONFIG_MTD is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+
+#
+# Device Tree and Open Firmware support
+#
+CONFIG_PROC_DEVICETREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
+CONFIG_OF_NET=y
+CONFIG_OF_SPI=y
+CONFIG_OF_MDIO=y
+CONFIG_PARPORT=m
+# CONFIG_PARPORT_PC is not set
+# CONFIG_PARPORT_GSC is not set
+# CONFIG_PARPORT_AX88796 is not set
+CONFIG_PARPORT_1284=y
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_DRBD is not set
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+CONFIG_CDROM_PKTCDVD_WCACHE=y
+CONFIG_ATA_OVER_ETH=m
+# CONFIG_MG_DISK is not set
+# CONFIG_VIRTIO_BLK is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+CONFIG_BMP085=m
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+# CONFIG_DM_THIN_PROVISIONING is not set
+CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+CONFIG_DM_FLAKEY=m
+# CONFIG_TARGET_CORE is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+CONFIG_BONDING=m
+CONFIG_DUMMY=m
+CONFIG_EQUALIZER=m
+CONFIG_MII=y
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+# CONFIG_VIRTIO_NET is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+CONFIG_NET_VENDOR_CHELSIO=y
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+CONFIG_NET_VENDOR_DLINK=y
+# CONFIG_DE600 is not set
+# CONFIG_DE620 is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+CONFIG_NET_VENDOR_NATSEMI=y
+CONFIG_NET_VENDOR_8390=y
+# CONFIG_AX88796 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_NET_VENDOR_SMSC=y
+CONFIG_SMC91X=y
+# CONFIG_SMC911X is not set
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_NET_VENDOR_TI=y
+# CONFIG_TI_DAVINCI_EMAC is not set
+CONFIG_TI_DAVINCI_MDIO=y
+CONFIG_TI_DAVINCI_CPDMA=y
+CONFIG_TI_CPSW=y
+# CONFIG_TLK110_WORKAROUND is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_SLIP=m
+CONFIG_SLHC=m
+# CONFIG_SLIP_COMPRESSED is not set
+CONFIG_SLIP_SMART=y
+# CONFIG_SLIP_MODE_SLIP6 is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=y
+CONFIG_USB_KAWETH=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_RTL8150=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+# CONFIG_USB_NET_CDC_EEM is not set
+CONFIG_USB_NET_CDC_NCM=y
+CONFIG_USB_NET_DM9601=y
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=y
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=y
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_HSO=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_AT76C50X_USB=m
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_RTL8187=m
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_ATH_COMMON is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_BRCMUTIL=m
+CONFIG_BRCMFMAC=m
+# CONFIG_BRCMDBG is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IWM is not set
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_SPI is not set
+CONFIG_LIBERTAS_DEBUG=y
+# CONFIG_LIBERTAS_MESH is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_SPI is not set
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+CONFIG_RTL8192CU=m
+CONFIG_RTLWIFI=m
+CONFIG_RTL8192C_COMMON=m
+# CONFIG_WL1251 is not set
+CONFIG_WL12XX_MENU=m
+CONFIG_WL12XX=m
+CONFIG_WL12XX_SPI=m
+CONFIG_WL12XX_SDIO=m
+# CONFIG_WL12XX_SDIO_TEST is not set
+CONFIG_WL12XX_PLATFORM_DATA=y
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+# CONFIG_MWIFIEX is not set
+
+#
+# WiMAX Wireless Broadband devices
+#
+CONFIG_WIMAX_I2400M=m
+CONFIG_WIMAX_I2400M_USB=m
+# CONFIG_WIMAX_I2400M_SDIO is not set
+CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8
+# CONFIG_WAN is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_POLLDEV=m
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+CONFIG_KEYBOARD_TWL4030=y
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+CONFIG_TOUCHSCREEN_TI_TSCADC=y
+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
+CONFIG_TOUCHSCREEN_USB_EGALAX=y
+CONFIG_TOUCHSCREEN_USB_PANJIT=y
+CONFIG_TOUCHSCREEN_USB_3M=y
+CONFIG_TOUCHSCREEN_USB_ITM=y
+CONFIG_TOUCHSCREEN_USB_ETURBO=y
+CONFIG_TOUCHSCREEN_USB_GUNZE=y
+CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
+CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
+CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
+CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
+CONFIG_TOUCHSCREEN_USB_GOTOP=y
+CONFIG_TOUCHSCREEN_USB_JASTEC=y
+CONFIG_TOUCHSCREEN_USB_E2I=y
+CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
+CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
+CONFIG_TOUCHSCREEN_USB_NEXIO=y
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+CONFIG_TOUCHSCREEN_TSC_SERIO=m
+CONFIG_TOUCHSCREEN_TSC2005=m
+CONFIG_TOUCHSCREEN_TSC2007=m
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_AD714X=m
+CONFIG_INPUT_AD714X_I2C=m
+CONFIG_INPUT_AD714X_SPI=m
+CONFIG_INPUT_BMA150=m
+CONFIG_INPUT_MMA8450=m
+CONFIG_INPUT_MPU3050=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_KXTJ9=m
+# CONFIG_INPUT_KXTJ9_POLLED_MODE is not set
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_CM109=m
+CONFIG_INPUT_TWL4030_PWRBUTTON=y
+CONFIG_INPUT_TWL4030_VIBRA=m
+CONFIG_INPUT_TWL6040_VIBRA=m
+CONFIG_INPUT_UINPUT=m
+CONFIG_INPUT_PCF8574=m
+# CONFIG_INPUT_PWM_BEEPER is not set
+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
+CONFIG_INPUT_ADXL34X=m
+CONFIG_INPUT_ADXL34X_I2C=m
+CONFIG_INPUT_ADXL34X_SPI=m
+CONFIG_INPUT_CMA3000=m
+CONFIG_INPUT_CMA3000_I2C=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PARKBD is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+# CONFIG_SERIAL_8250_DW is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_OF_PLATFORM is not set
+CONFIG_SERIAL_OMAP=y
+CONFIG_SERIAL_OMAP_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_PRINTER=m
+# CONFIG_LP_CONSOLE is not set
+# CONFIG_PPDEV is not set
+# CONFIG_HVC_DCC is not set
+# CONFIG_VIRTIO_CONSOLE is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_HW_RANDOM_VIRTIO is not set
+# CONFIG_R3964 is not set
+CONFIG_RAW_DRIVER=m
+CONFIG_MAX_RAW_DEVS=256
+# CONFIG_TCG_TPM is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+CONFIG_SPI_BITBANG=m
+# CONFIG_SPI_BUTTERFLY is not set
+CONFIG_SPI_GPIO=m
+# CONFIG_SPI_LM70_LLP is not set
+# CONFIG_SPI_OC_TINY is not set
+CONFIG_SPI_OMAP24XX=y
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO drivers:
+#
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+CONFIG_GPIO_TWL4030=y
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+CONFIG_GENERIC_PWM=y
+CONFIG_DAVINCI_EHRPWM=y
+CONFIG_ECAP_PWM=y
+CONFIG_W1=y
+CONFIG_W1_CON=y
+
+#
+# 1-wire Bus Masters
+#
+CONFIG_W1_MASTER_DS2490=m
+CONFIG_W1_MASTER_DS2482=m
+CONFIG_W1_MASTER_DS1WM=m
+CONFIG_W1_MASTER_GPIO=y
+# CONFIG_HDQ_MASTER_OMAP is not set
+
+#
+# 1-wire Slaves
+#
+CONFIG_W1_SLAVE_THERM=y
+CONFIG_W1_SLAVE_SMEM=m
+CONFIG_W1_SLAVE_DS2408=m
+CONFIG_W1_SLAVE_DS2423=m
+CONFIG_W1_SLAVE_DS2431=m
+CONFIG_W1_SLAVE_DS2433=m
+CONFIG_W1_SLAVE_DS2433_CRC=y
+CONFIG_W1_SLAVE_DS2760=m
+CONFIG_W1_SLAVE_DS2780=m
+CONFIG_W1_SLAVE_BQ27000=m
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ20Z75 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_ISP1704 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_TWL4030 is not set
+# CONFIG_CHARGER_GPIO is not set
+CONFIG_HWMON=y
+CONFIG_HWMON_VID=m
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+CONFIG_SENSORS_AD7314=m
+CONFIG_SENSORS_AD7414=m
+CONFIG_SENSORS_AD7418=m
+CONFIG_SENSORS_ADCXX=m
+CONFIG_SENSORS_ADM1021=m
+CONFIG_SENSORS_ADM1025=m
+CONFIG_SENSORS_ADM1026=m
+CONFIG_SENSORS_ADM1029=m
+CONFIG_SENSORS_ADM1031=m
+CONFIG_SENSORS_ADM9240=m
+CONFIG_SENSORS_ADT7411=m
+CONFIG_SENSORS_ADT7462=m
+CONFIG_SENSORS_ADT7470=m
+CONFIG_SENSORS_ADT7475=m
+CONFIG_SENSORS_ASC7621=m
+CONFIG_SENSORS_ATXP1=m
+CONFIG_SENSORS_DS620=m
+CONFIG_SENSORS_DS1621=m
+CONFIG_SENSORS_F71805F=m
+CONFIG_SENSORS_F71882FG=m
+CONFIG_SENSORS_F75375S=m
+CONFIG_SENSORS_G760A=m
+CONFIG_SENSORS_GL518SM=m
+CONFIG_SENSORS_GL520SM=m
+CONFIG_SENSORS_GPIO_FAN=m
+CONFIG_SENSORS_IT87=m
+CONFIG_SENSORS_JC42=m
+CONFIG_SENSORS_LINEAGE=m
+CONFIG_SENSORS_LM63=m
+CONFIG_SENSORS_LM70=m
+CONFIG_SENSORS_LM73=m
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_LM77=m
+CONFIG_SENSORS_LM78=m
+CONFIG_SENSORS_LM80=m
+CONFIG_SENSORS_LM83=m
+CONFIG_SENSORS_LM85=m
+CONFIG_SENSORS_LM87=m
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_LM92=m
+CONFIG_SENSORS_LM93=m
+CONFIG_SENSORS_LTC4151=m
+CONFIG_SENSORS_LTC4215=m
+CONFIG_SENSORS_LTC4245=m
+CONFIG_SENSORS_LTC4261=m
+CONFIG_SENSORS_LM95241=m
+CONFIG_SENSORS_LM95245=m
+CONFIG_SENSORS_MAX1111=m
+CONFIG_SENSORS_MAX16065=m
+CONFIG_SENSORS_MAX1619=m
+CONFIG_SENSORS_MAX1668=m
+CONFIG_SENSORS_MAX6639=m
+CONFIG_SENSORS_MAX6642=m
+CONFIG_SENSORS_MAX6650=m
+CONFIG_SENSORS_NTC_THERMISTOR=m
+CONFIG_SENSORS_PC87360=m
+CONFIG_SENSORS_PC87427=m
+CONFIG_SENSORS_PCF8591=m
+CONFIG_PMBUS=m
+CONFIG_SENSORS_PMBUS=m
+# CONFIG_SENSORS_ADM1275 is not set
+# CONFIG_SENSORS_LM25066 is not set
+CONFIG_SENSORS_LTC2978=m
+# CONFIG_SENSORS_MAX16064 is not set
+# CONFIG_SENSORS_MAX34440 is not set
+# CONFIG_SENSORS_MAX8688 is not set
+# CONFIG_SENSORS_UCD9000 is not set
+# CONFIG_SENSORS_UCD9200 is not set
+CONFIG_SENSORS_ZL6100=m
+CONFIG_SENSORS_SHT15=m
+CONFIG_SENSORS_SHT21=m
+CONFIG_SENSORS_SMM665=m
+CONFIG_SENSORS_DME1737=m
+CONFIG_SENSORS_EMC1403=m
+CONFIG_SENSORS_EMC2103=m
+CONFIG_SENSORS_EMC6W201=m
+CONFIG_SENSORS_SMSC47M1=m
+CONFIG_SENSORS_SMSC47M192=m
+CONFIG_SENSORS_SMSC47B397=m
+CONFIG_SENSORS_SCH56XX_COMMON=m
+CONFIG_SENSORS_SCH5627=m
+CONFIG_SENSORS_SCH5636=m
+CONFIG_SENSORS_ADS1015=m
+CONFIG_SENSORS_ADS7828=m
+CONFIG_SENSORS_ADS7871=m
+CONFIG_SENSORS_AMC6821=m
+CONFIG_SENSORS_THMC50=m
+CONFIG_SENSORS_TMP102=m
+CONFIG_SENSORS_TMP401=m
+CONFIG_SENSORS_TMP421=m
+CONFIG_SENSORS_VT1211=m
+CONFIG_SENSORS_W83781D=m
+CONFIG_SENSORS_W83791D=m
+CONFIG_SENSORS_W83792D=m
+CONFIG_SENSORS_W83793=m
+CONFIG_SENSORS_W83795=m
+# CONFIG_SENSORS_W83795_FANCTRL is not set
+CONFIG_SENSORS_W83L785TS=m
+CONFIG_SENSORS_W83L786NG=m
+CONFIG_SENSORS_W83627HF=m
+CONFIG_SENSORS_W83627EHF=m
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_DW_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+CONFIG_TWL4030_WATCHDOG=y
+# CONFIG_MAX63XX_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+CONFIG_MFD_TPS65217=y
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_TWL4030_MADC is not set
+CONFIG_TWL4030_POWER=y
+CONFIG_MFD_TWL4030_AUDIO=y
+# CONFIG_TWL6030_PWM is not set
+CONFIG_TWL6040_CORE=y
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+CONFIG_REGULATOR_DUMMY=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_USERSPACE_CONSUMER=y
+CONFIG_REGULATOR_GPIO=y
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+CONFIG_REGULATOR_TWL4030=y
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+CONFIG_REGULATOR_TPS65023=y
+CONFIG_REGULATOR_TPS6507X=y
+CONFIG_REGULATOR_TPS65217=y
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_V4L2_SUBDEV_API is not set
+CONFIG_DVB_CORE=m
+CONFIG_DVB_NET=y
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_RC_CORE=y
+CONFIG_LIRC=y
+CONFIG_RC_MAP=y
+CONFIG_IR_NEC_DECODER=y
+CONFIG_IR_RC5_DECODER=y
+CONFIG_IR_RC6_DECODER=y
+CONFIG_IR_JVC_DECODER=y
+CONFIG_IR_SONY_DECODER=y
+CONFIG_IR_RC5_SZ_DECODER=y
+CONFIG_IR_MCE_KBD_DECODER=y
+CONFIG_IR_LIRC_CODEC=y
+CONFIG_RC_ATI_REMOTE=m
+# CONFIG_IR_IMON is not set
+# CONFIG_IR_MCEUSB is not set
+# CONFIG_IR_REDRAT3 is not set
+# CONFIG_IR_STREAMZAP is not set
+# CONFIG_RC_LOOPBACK is not set
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_TUNER=m
+CONFIG_MEDIA_TUNER_CUSTOMISE=y
+
+#
+# Customize TV tuners
+#
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_MT2131=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEOBUF_DVB=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+CONFIG_VIDEO_IR_I2C=y
+
+#
+# Encoders, decoders, sensors and other helper chips
+#
+
+#
+# Audio decoders, processors and mixers
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+CONFIG_VIDEO_MSP3400=m
+# CONFIG_VIDEO_CS5345 is not set
+CONFIG_VIDEO_CS53L32A=m
+# CONFIG_VIDEO_TLV320AIC23B is not set
+CONFIG_VIDEO_WM8775=m
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+CONFIG_VIDEO_SAA711X=m
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_SAA717X is not set
+CONFIG_VIDEO_CX25840=m
+
+#
+# MPEG video encoders
+#
+CONFIG_VIDEO_CX2341X=m
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_AK881X is not set
+
+#
+# Camera sensor devices
+#
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+
+#
+# Flash devices
+#
+# CONFIG_VIDEO_ADP1653 is not set
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_M52790 is not set
+CONFIG_VIDEO_VIVI=m
+# CONFIG_VIDEO_VPFE_CAPTURE is not set
+# CONFIG_VIDEO_OMAP2_VOUT is not set
+# CONFIG_VIDEO_BWQCAM is not set
+# CONFIG_VIDEO_CQCAM is not set
+# CONFIG_VIDEO_W9966 is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_AU0828 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+CONFIG_USB_M5602=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_GL860=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+CONFIG_USB_GSPCA_KINECT=m
+CONFIG_USB_GSPCA_KONICA=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+CONFIG_USB_GSPCA_NW80X=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SE401=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_SPCA1528=m
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ905C=m
+CONFIG_USB_GSPCA_SQ930X=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TOPRO=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_VICAM=m
+CONFIG_USB_GSPCA_XIRLINK_CIT=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+CONFIG_VIDEO_EM28XX_RC=y
+CONFIG_VIDEO_TLG2300=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+# CONFIG_VIDEO_TM6000 is not set
+CONFIG_VIDEO_USBVISION=m
+CONFIG_USB_ET61X251=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_I2C_SI4713 is not set
+# CONFIG_RADIO_SI4713 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_RADIO_SAA7706H is not set
+# CONFIG_RADIO_TEF6862 is not set
+# CONFIG_RADIO_WL1273 is not set
+
+#
+# Texas Instruments WL128x FM driver (ST based)
+#
+# CONFIG_RADIO_WL128X is not set
+CONFIG_DVB_MAX_ADAPTERS=8
+# CONFIG_DVB_DYNAMIC_MINORS is not set
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
+
+#
+# Supported USB Adapters
+#
+# CONFIG_DVB_USB is not set
+# CONFIG_SMS_SIANO_MDTV is not set
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+# CONFIG_DVB_B2C2_FLEXCOP is not set
+
+#
+# Supported DVB Frontends
+#
+CONFIG_DVB_FE_CUSTOMISE=y
+
+#
+# Customise DVB Frontends
+#
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV6110x=m
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_TDA18271C2DD=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_TDA10071=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_S5H1432=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB9000=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_CXD2820R=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_S921=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_LGS8GL5=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_IT913X_FE=m
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+
+#
+# Graphics support
+#
+CONFIG_DRM=m
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FB_FOREIGN_ENDIAN=y
+CONFIG_FB_BOTH_ENDIAN=y
+# CONFIG_FB_BIG_ENDIAN is not set
+# CONFIG_FB_LITTLE_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=y
+# CONFIG_FB_WMT_GE_ROPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_TMIO is not set
+CONFIG_FB_SMSCUFX=m
+CONFIG_FB_UDL=m
+CONFIG_FB_DA8XX=y
+CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE=5
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_ST7735=y
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_OMAP2_VRAM=y
+CONFIG_OMAP2_VRFB=y
+CONFIG_OMAP2_DSS=m
+CONFIG_OMAP2_VRAM_SIZE=0
+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
+# CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set
+CONFIG_OMAP2_DSS_DPI=y
+CONFIG_OMAP2_DSS_RFBI=y
+CONFIG_OMAP2_DSS_VENC=y
+CONFIG_OMAP2_DSS_SDI=y
+CONFIG_OMAP2_DSS_DSI=y
+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
+CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y
+CONFIG_FB_OMAP2=m
+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
+CONFIG_FB_OMAP2_NUM_FBS=3
+
+#
+# OMAP2/3 Display Device Drivers
+#
+CONFIG_PANEL_GENERIC_DPI=m
+CONFIG_PANEL_DVI=m
+# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set
+CONFIG_PANEL_SHARP_LS037V7DW01=m
+CONFIG_PANEL_NEC_NL8048HL11_01B=m
+CONFIG_PANEL_PICODLP=m
+CONFIG_PANEL_TAAL=m
+CONFIG_PANEL_TPO_TD043MTEA1=m
+CONFIG_PANEL_ACX565AKM=m
+CONFIG_PANEL_N8X0=m
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=y
+# CONFIG_LCD_S6E63M0 is not set
+# CONFIG_LCD_LD9040 is not set
+# CONFIG_LCD_AMS369FG06 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_TLC59108 is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_JACK=y
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_SEQUENCER_OSS is not set
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_RAWMIDI_SEQ=m
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_ALOOP is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_MTS64 is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_PORTMAN2X4 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_6FIRE is not set
+CONFIG_SND_SOC=y
+# CONFIG_SND_SOC_CACHE_LZO is not set
+CONFIG_SND_AM33XX_SOC=y
+CONFIG_SND_DAVINCI_SOC_MCASP=m
+CONFIG_SND_AM335X_SOC_EVM=m
+# CONFIG_SND_OMAP_SOC is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_TLV320AIC3X=m
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_WIIMOTE is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB_ARCH_HAS_XHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_U132_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+
+#
+# Platform Glue Layer
+#
+# CONFIG_USB_MUSB_TUSB6010_GLUE is not set
+# CONFIG_USB_MUSB_OMAP2PLUS_GLUE is not set
+# CONFIG_USB_MUSB_AM35X_GLUE is not set
+CONFIG_USB_MUSB_TI81XX_GLUE=y
+# CONFIG_USB_MUSB_DAVINCI is not set
+# CONFIG_USB_MUSB_DA8XX is not set
+# CONFIG_USB_MUSB_TUSB6010 is not set
+# CONFIG_USB_MUSB_OMAP2PLUS is not set
+# CONFIG_USB_MUSB_AM35X is not set
+CONFIG_USB_MUSB_TI81XX=y
+# CONFIG_USB_MUSB_BLACKFIN is not set
+# CONFIG_USB_MUSB_UX500 is not set
+CONFIG_MUSB_PIO_ONLY=y
+# CONFIG_USB_INVENTRA_DMA is not set
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_TI_CPPI41_DMA is not set
+# CONFIG_USB_TUSB_OMAP_DMA is not set
+# CONFIG_USB_UX500_DMA is not set
+# CONFIG_USB_RENESAS_USBHS is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=y
+CONFIG_USB_PRINTER=y
+CONFIG_USB_WDM=y
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+CONFIG_USB_UAS=y
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+# CONFIG_USB_SERIAL_GENERIC is not set
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+# CONFIG_USB_SERIAL_MOS7715_PARPORT is not set
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+CONFIG_USB_SERIAL_WWAN=m
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
+CONFIG_USB_SERIAL_ZIO=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+CONFIG_USB_LED=m
+CONFIG_USB_CYPRESS_CY7C63=m
+CONFIG_USB_CYTHERM=m
+CONFIG_USB_IDMOUSE=m
+CONFIG_USB_FTDI_ELAN=m
+CONFIG_USB_APPLEDISPLAY=m
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_SISUSBVGA_CON=y
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+# CONFIG_USB_FUSB300 is not set
+# CONFIG_USB_OMAP is not set
+# CONFIG_USB_R8A66597 is not set
+CONFIG_USB_GADGET_MUSB_HDRC=y
+# CONFIG_USB_M66592 is not set
+# CONFIG_USB_NET2272 is not set
+# CONFIG_USB_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_AUDIO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_G_NCM=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FUNCTIONFS=m
+# CONFIG_USB_FUNCTIONFS_ETH is not set
+CONFIG_USB_FUNCTIONFS_RNDIS=y
+# CONFIG_USB_FUNCTIONFS_GENERIC is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+# CONFIG_USB_G_ACM_MS is not set
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_RNDIS=y
+# CONFIG_USB_G_MULTI_CDC is not set
+CONFIG_USB_G_HID=m
+CONFIG_USB_G_DBGP=m
+CONFIG_USB_G_DBGP_PRINTK=y
+# CONFIG_USB_G_DBGP_SERIAL is not set
+CONFIG_USB_G_WEBCAM=m
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_TWL4030_USB is not set
+# CONFIG_TWL6030_USB is not set
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_OMAP is not set
+CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_PWM is not set
+CONFIG_LEDS_REGULATOR=y
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_RENESAS_TPU is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_OMAP=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_PRUSS=m
+CONFIG_VIRTIO=m
+CONFIG_VIRTIO_RING=m
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_BALLOON is not set
+CONFIG_VIRTIO_MMIO=m
+CONFIG_STAGING=y
+# CONFIG_USBIP_CORE is not set
+CONFIG_W35UND=m
+CONFIG_PRISM2_USB=m
+# CONFIG_ECHO is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_PANEL is not set
+CONFIG_R8712U=m
+CONFIG_RTS5139=m
+# CONFIG_RTS5139_DEBUG is not set
+# CONFIG_TRANZPORT is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_LINE6_USB is not set
+CONFIG_USB_SERIAL_QUATECH2=m
+CONFIG_USB_SERIAL_QUATECH_USB2=m
+# CONFIG_VT6656 is not set
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_SW_RING=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16201 is not set
+# CONFIG_ADIS16203 is not set
+# CONFIG_ADIS16204 is not set
+# CONFIG_ADIS16209 is not set
+# CONFIG_ADIS16220 is not set
+# CONFIG_ADIS16240 is not set
+# CONFIG_KXSD9 is not set
+# CONFIG_LIS3L02DQ is not set
+# CONFIG_SCA3000 is not set
+
+#
+# Analog to digital converters
+#
+# CONFIG_AD7291 is not set
+# CONFIG_AD7298 is not set
+# CONFIG_AD7606 is not set
+# CONFIG_AD799X is not set
+# CONFIG_AD7476 is not set
+# CONFIG_AD7887 is not set
+# CONFIG_AD7780 is not set
+# CONFIG_AD7793 is not set
+# CONFIG_AD7816 is not set
+CONFIG_AD7192=m
+# CONFIG_ADT7310 is not set
+# CONFIG_ADT7410 is not set
+CONFIG_AD7280=m
+# CONFIG_MAX1363 is not set
+
+#
+# Analog digital bi-direction converters
+#
+# CONFIG_ADT7316 is not set
+
+#
+# Capacitance to digital converters
+#
+# CONFIG_AD7150 is not set
+# CONFIG_AD7152 is not set
+CONFIG_AD7746=m
+
+#
+# Digital to analog converters
+#
+CONFIG_AD5064=m
+CONFIG_AD5360=m
+# CONFIG_AD5624R_SPI is not set
+# CONFIG_AD5446 is not set
+# CONFIG_AD5504 is not set
+# CONFIG_AD5791 is not set
+# CONFIG_AD5686 is not set
+# CONFIG_MAX517 is not set
+
+#
+# Direct Digital Synthesis
+#
+# CONFIG_AD5930 is not set
+# CONFIG_AD9832 is not set
+# CONFIG_AD9834 is not set
+# CONFIG_AD9850 is not set
+# CONFIG_AD9852 is not set
+# CONFIG_AD9910 is not set
+# CONFIG_AD9951 is not set
+
+#
+# Digital gyroscope sensors
+#
+# CONFIG_ADIS16060 is not set
+# CONFIG_ADIS16080 is not set
+# CONFIG_ADIS16130 is not set
+# CONFIG_ADIS16260 is not set
+# CONFIG_ADXRS450 is not set
+
+#
+# Network Analyzer, Impedance Converters
+#
+CONFIG_AD5933=m
+
+#
+# Inertial measurement units
+#
+# CONFIG_ADIS16400 is not set
+
+#
+# Light sensors
+#
+# CONFIG_SENSORS_ISL29018 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_TSL2583 is not set
+
+#
+# Magnetometer sensors
+#
+# CONFIG_SENSORS_AK8975 is not set
+# CONFIG_SENSORS_HMC5843 is not set
+
+#
+# Active energy metering IC
+#
+# CONFIG_ADE7753 is not set
+# CONFIG_ADE7754 is not set
+# CONFIG_ADE7758 is not set
+# CONFIG_ADE7759 is not set
+# CONFIG_ADE7854 is not set
+
+#
+# Resolver to digital converters
+#
+# CONFIG_AD2S90 is not set
+CONFIG_AD2S1200=m
+# CONFIG_AD2S1210 is not set
+
+#
+# Triggers - standalone
+#
+# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set
+# CONFIG_IIO_GPIO_TRIGGER is not set
+# CONFIG_IIO_SYSFS_TRIGGER is not set
+CONFIG_IIO_DUMMY_EVGEN=m
+CONFIG_IIO_SIMPLE_DUMMY=m
+CONFIG_IIO_SIMPLE_DUMMY_EVENTS=y
+CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y
+# CONFIG_XVMALLOC is not set
+# CONFIG_ZRAM is not set
+# CONFIG_FB_SM7XX is not set
+# CONFIG_TIDSPBRIDGE is not set
+CONFIG_USB_ENESTORAGE=m
+# CONFIG_BCM_WIMAX is not set
+# CONFIG_FT1000 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+# CONFIG_STAGING_MEDIA is not set
+CONFIG_CLKDEV_LOOKUP=y
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_CLKSRC_MMIO=y
+CONFIG_IOMMU_API=y
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_OMAP_IOMMU=y
+CONFIG_OMAP_IOVMM=y
+CONFIG_OMAP_IOMMU_DEBUG=y
+# CONFIG_VIRT_DRIVERS is not set
+CONFIG_PM_DEVFREQ=y
+
+#
+# DEVFREQ Governors
+#
+# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+
+#
+# DEVFREQ Drivers
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=m
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+CONFIG_JFS_FS=m
+# CONFIG_JFS_POSIX_ACL is not set
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+CONFIG_GFS2_FS=m
+# CONFIG_GFS2_FS_LOCKING_DLM is not set
+CONFIG_BTRFS_FS=m
+# CONFIG_BTRFS_FS_POSIX_ACL is not set
+CONFIG_NILFS2_FS=m
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QUOTA_DEBUG is not set
+CONFIG_QUOTA_TREE=m
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=m
+CONFIG_QUOTACTL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=m
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_NEW_IDMAPPER is not set
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_CEPH_FS is not set
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+CONFIG_CIFS_WEAK_PW_HASH=y
+# CONFIG_CIFS_UPCALL is not set
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_CIFS_ACL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_RING_BUFFER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_ASYNC_RAID6_TEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_NONE=y
+# CONFIG_DEBUG_ICEDCC is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_DEBUG_JTAG_ENABLE=y
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_TOMOYO is not set
+# CONFIG_SECURITY_APPARMOR is not set
+# CONFIG_IMA is not set
+# CONFIG_EVM is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_USER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=m
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_OMAP_SHAM is not set
+# CONFIG_CRYPTO_DEV_OMAP_AES is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=m
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+# CONFIG_CRC8 is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
diff -PurN linux-stable-23d8c3f/arch/arm/configs/omap1_defconfig kernel_3.2.14_patched/arch/arm/configs/omap1_defconfig
--- linux-stable-23d8c3f/arch/arm/configs/omap1_defconfig 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/configs/omap1_defconfig 2012-05-16 12:10:46.000000000 +0100
@@ -48,7 +48,6 @@
CONFIG_MACH_NOKIA770=y
CONFIG_MACH_AMS_DELTA=y
CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_OMAP_ARM_182MHZ=y
# CONFIG_ARM_THUMB is not set
CONFIG_PCCARD=y
CONFIG_OMAP_CF=y
diff -PurN linux-stable-23d8c3f/arch/arm/configs/omap2plus_defconfig kernel_3.2.14_patched/arch/arm/configs/omap2plus_defconfig
--- linux-stable-23d8c3f/arch/arm/configs/omap2plus_defconfig 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/configs/omap2plus_defconfig 2012-05-16 12:10:46.000000000 +0100
@@ -21,7 +21,8 @@
CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_OMAP=y
-CONFIG_OMAP_RESET_CLOCKS=y
+# CONFIG_OMAP_RESET_CLOCKS is not set
+# CONFIG_OMAP_32K_TIMER is not set
CONFIG_OMAP_MUX_DEBUG=y
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_ERRATA_411920=y
@@ -81,6 +82,8 @@
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
@@ -89,6 +92,9 @@
CONFIG_NETDEVICES=y
CONFIG_SMSC_PHY=y
CONFIG_NET_ETHERNET=y
+CONFIG_TI_DAVINCI_MDIO=y
+CONFIG_TI_DAVINCI_CPDMA=y
+CONFIG_TI_CPSW=y
CONFIG_SMC91X=y
CONFIG_SMSC911X=y
CONFIG_KS8851=y
@@ -108,6 +114,7 @@
CONFIG_KEYBOARD_TWL4030=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
+CONFIG_TOUCHSCREEN_TI_TSCADC=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_TWL4030_PWRBUTTON=y
CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -151,14 +158,23 @@
CONFIG_PANEL_ACX565AKM=m
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+CONFIG_BACKLIGHT_TLC59108=y
CONFIG_LCD_PLATFORM=y
CONFIG_DISPLAY_SUPPORT=y
+CONFIG_FB_DA8XX=y
+CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE=4
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
CONFIG_SOUND=m
CONFIG_SND=m
CONFIG_SND_MIXER_OSS=m
@@ -225,6 +241,9 @@
CONFIG_DEBUG_SPINLOCK_SLEEP=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
+ONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_NONE=y
+CONFIG_EARLY_PRINTK=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SECURITY=y
CONFIG_CRYPTO_MICHAEL_MIC=y
diff -PurN linux-stable-23d8c3f/arch/arm/include/asm/cti.h kernel_3.2.14_patched/arch/arm/include/asm/cti.h
--- linux-stable-23d8c3f/arch/arm/include/asm/cti.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/include/asm/cti.h 2012-05-16 12:10:46.000000000 +0100
@@ -0,0 +1,179 @@
+#ifndef __ASMARM_CTI_H
+#define __ASMARM_CTI_H
+
+#include <asm/io.h>
+
+/* The registers' definition is from section 3.2 of
+ * Embedded Cross Trigger Revision: r0p0
+ */
+#define CTICONTROL 0x000
+#define CTISTATUS 0x004
+#define CTILOCK 0x008
+#define CTIPROTECTION 0x00C
+#define CTIINTACK 0x010
+#define CTIAPPSET 0x014
+#define CTIAPPCLEAR 0x018
+#define CTIAPPPULSE 0x01c
+#define CTIINEN 0x020
+#define CTIOUTEN 0x0A0
+#define CTITRIGINSTATUS 0x130
+#define CTITRIGOUTSTATUS 0x134
+#define CTICHINSTATUS 0x138
+#define CTICHOUTSTATUS 0x13c
+#define CTIPERIPHID0 0xFE0
+#define CTIPERIPHID1 0xFE4
+#define CTIPERIPHID2 0xFE8
+#define CTIPERIPHID3 0xFEC
+#define CTIPCELLID0 0xFF0
+#define CTIPCELLID1 0xFF4
+#define CTIPCELLID2 0xFF8
+#define CTIPCELLID3 0xFFC
+
+/* The below are from section 3.6.4 of
+ * CoreSight v1.0 Architecture Specification
+ */
+#define LOCKACCESS 0xFB0
+#define LOCKSTATUS 0xFB4
+
+/* write this value to LOCKACCESS will unlock the module, and
+ * other value will lock the module
+ */
+#define LOCKCODE 0xC5ACCE55
+
+/**
+ * struct cti - cross trigger interface struct
+ * @base: mapped virtual address for the cti base
+ * @irq: irq number for the cti
+ * @trig_out_for_irq: triger out number which will cause
+ * the @irq happen
+ *
+ * cti struct used to operate cti registers.
+ */
+struct cti {
+ void __iomem *base;
+ int irq;
+ int trig_out_for_irq;
+};
+
+/**
+ * cti_init - initialize the cti instance
+ * @cti: cti instance
+ * @base: mapped virtual address for the cti base
+ * @irq: irq number for the cti
+ * @trig_out: triger out number which will cause
+ * the @irq happen
+ *
+ * called by machine code to pass the board dependent
+ * @base, @irq and @trig_out to cti.
+ */
+static inline void cti_init(struct cti *cti,
+ void __iomem *base, int irq, int trig_out)
+{
+ cti->base = base;
+ cti->irq = irq;
+ cti->trig_out_for_irq = trig_out;
+}
+
+/**
+ * cti_map_trigger - use the @chan to map @trig_in to @trig_out
+ * @cti: cti instance
+ * @trig_in: trigger in number
+ * @trig_out: trigger out number
+ * @channel: channel number
+ *
+ * This function maps one trigger in of @trig_in to one trigger
+ * out of @trig_out using the channel @chan.
+ */
+static inline void cti_map_trigger(struct cti *cti,
+ int trig_in, int trig_out, int chan)
+{
+ void __iomem *base = cti->base;
+ unsigned long val;
+
+ val = __raw_readl(base + CTIINEN + trig_in * 4);
+ val |= BIT(chan);
+ __raw_writel(val, base + CTIINEN + trig_in * 4);
+
+ val = __raw_readl(base + CTIOUTEN + trig_out * 4);
+ val |= BIT(chan);
+ __raw_writel(val, base + CTIOUTEN + trig_out * 4);
+}
+
+/**
+ * cti_enable - enable the cti module
+ * @cti: cti instance
+ *
+ * enable the cti module
+ */
+static inline void cti_enable(struct cti *cti)
+{
+ __raw_writel(0x1, cti->base + CTICONTROL);
+}
+
+/**
+ * cti_disable - disable the cti module
+ * @cti: cti instance
+ *
+ * enable the cti module
+ */
+static inline void cti_disable(struct cti *cti)
+{
+ __raw_writel(0, cti->base + CTICONTROL);
+}
+
+/**
+ * cti_irq_ack - clear the cti irq
+ * @cti: cti instance
+ *
+ * clear the cti irq
+ */
+static inline void cti_irq_ack(struct cti *cti)
+{
+ void __iomem *base = cti->base;
+ unsigned long val;
+
+ val = __raw_readl(base + CTIINTACK);
+ val |= BIT(cti->trig_out_for_irq);
+ __raw_writel(val, base + CTIINTACK);
+}
+
+/**
+ * cti_unlock - unlock cti module
+ * @cti: cti instance
+ *
+ * unlock the cti module, or else any writes to the cti
+ * module is not allowed.
+ */
+static inline void cti_unlock(struct cti *cti)
+{
+ void __iomem *base = cti->base;
+ unsigned long val;
+
+ val = __raw_readl(base + LOCKSTATUS);
+
+ if (val & 1) {
+ val = LOCKCODE;
+ __raw_writel(val, base + LOCKACCESS);
+ }
+}
+
+/**
+ * cti_lock - lock cti module
+ * @cti: cti instance
+ *
+ * lock the cti module, so any writes to the cti
+ * module will be not allowed.
+ */
+static inline void cti_lock(struct cti *cti)
+{
+ void __iomem *base = cti->base;
+ unsigned long val;
+
+ val = __raw_readl(base + LOCKSTATUS);
+
+ if (!(val & 1)) {
+ val = ~LOCKCODE;
+ __raw_writel(val, base + LOCKACCESS);
+ }
+}
+#endif
diff -PurN linux-stable-23d8c3f/arch/arm/include/asm/entry-macro-vic2.S kernel_3.2.14_patched/arch/arm/include/asm/entry-macro-vic2.S
--- linux-stable-23d8c3f/arch/arm/include/asm/entry-macro-vic2.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/include/asm/entry-macro-vic2.S 1970-01-01 01:00:00.000000000 +0100
@@ -1,57 +0,0 @@
-/* arch/arm/include/asm/entry-macro-vic2.S
- *
- * Originally arch/arm/mach-s3c6400/include/mach/entry-macro.S
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Low-level IRQ helper macros for a device with two VICs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-/* This should be included from <mach/entry-macro.S> with the necessary
- * defines for virtual addresses and IRQ bases for the two vics.
- *
- * The code needs the following defined:
- * IRQ_VIC0_BASE IRQ number of VIC0's first IRQ
- * IRQ_VIC1_BASE IRQ number of VIC1's first IRQ
- * VA_VIC0 Virtual address of VIC0
- * VA_VIC1 Virtual address of VIC1
- *
- * Note, code assumes VIC0's virtual address is an ARM immediate constant
- * away from VIC1.
-*/
-
-#include <asm/hardware/vic.h>
-
- .macro disable_fiq
- .endm
-
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =VA_VIC0
- .endm
-
- .macro arch_ret_to_user, tmp1, tmp2
- .endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- @ check the vic0
- mov \irqnr, #IRQ_VIC0_BASE + 31
- ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
- teq \irqstat, #0
-
- @ otherwise try vic1
- addeq \tmp, \base, #(VA_VIC1 - VA_VIC0)
- addeq \irqnr, \irqnr, #(IRQ_VIC1_BASE - IRQ_VIC0_BASE)
- ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
- teqeq \irqstat, #0
-
- clzne \irqstat, \irqstat
- subne \irqnr, \irqnr, \irqstat
- .endm
diff -PurN linux-stable-23d8c3f/arch/arm/include/asm/hardware/asp.h kernel_3.2.14_patched/arch/arm/include/asm/hardware/asp.h
--- linux-stable-23d8c3f/arch/arm/include/asm/hardware/asp.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/include/asm/hardware/asp.h 2012-05-16 12:10:46.000000000 +0100
@@ -0,0 +1,143 @@
+/*
+ * <asm/hardware/asp.h> - DaVinci Audio Serial Port support
+ */
+#ifndef __ASM_HARDWARE_MCASP_H
+#define __ASM_HARDWARE_MCASP_H
+
+#include <mach/irqs.h>
+#include <mach/edma.h>
+
+/* Bases of dm644x and dm355 register banks */
+#define DAVINCI_ASP0_BASE 0x01E02000
+#define DAVINCI_ASP1_BASE 0x01E04000
+
+/* Bases of dm365 register banks */
+#define DAVINCI_DM365_ASP0_BASE 0x01D02000
+
+/* Bases of dm646x register banks */
+#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
+#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
+
+/* Bases of da850/da830 McASP0 register banks */
+#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
+
+/* Bases of da830 McASP1 register banks */
+#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
+
+/* EDMA channels of dm644x and dm355 */
+#define DAVINCI_DMA_ASP0_TX 2
+#define DAVINCI_DMA_ASP0_RX 3
+#define DAVINCI_DMA_ASP1_TX 8
+#define DAVINCI_DMA_ASP1_RX 9
+
+/* EDMA channels of dm646x */
+#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
+#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
+#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
+
+/* EDMA channels of da850/da830 McASP0 */
+#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
+#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
+
+/* EDMA channels of da830 McASP1 */
+#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
+#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
+
+/* Interrupts */
+#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
+#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
+#define DAVINCI_ASP1_RX_INT IRQ_MBRINT
+#define DAVINCI_ASP1_TX_INT IRQ_MBXINT
+
+struct snd_platform_data {
+ u32 tx_dma_offset;
+ u32 rx_dma_offset;
+ enum dma_event_q asp_chan_q; /* event queue number for ASP channel */
+ enum dma_event_q ram_chan_q; /* event queue number for RAM channel */
+ unsigned int codec_fmt;
+ /*
+ * Allowing this is more efficient and eliminates left and right swaps
+ * caused by underruns, but will swap the left and right channels
+ * when compared to previous behavior.
+ */
+ unsigned enable_channel_combine:1;
+ unsigned sram_size_playback;
+ unsigned sram_size_capture;
+
+ /*
+ * If McBSP peripheral gets the clock from an external pin,
+ * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
+ * and MCBSP_CLKS.
+ * Depending on different hardware connections it is possible
+ * to use this setting to change the behaviour of McBSP
+ * driver. The dm365_clk_input_pin enum is available for dm365
+ */
+ int clk_input_pin;
+
+ /*
+ * This flag works when both clock and FS are outputs for the cpu
+ * and makes clock more accurate (FS is not symmetrical and the
+ * clock is very fast.
+ * The clock becoming faster is named
+ * i2s continuous serial clock (I2S_SCK) and it is an externally
+ * visible bit clock.
+ *
+ * first line : WordSelect
+ * second line : ContinuousSerialClock
+ * third line: SerialData
+ *
+ * SYMMETRICAL APPROACH:
+ * _______________________ LEFT
+ * _| RIGHT |______________________|
+ * _ _ _ _ _ _ _ _
+ * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
+ * _ _ _ _ _ _ _ _
+ * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
+ * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
+ *
+ * ACCURATE CLOCK APPROACH:
+ * ______________ LEFT
+ * _| RIGHT |_______________________________|
+ * _ _ _ _ _ _ _ _ _
+ * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
+ * _ _ _ _ dummy cycles
+ * _/ \_ ... _/ \_/ \_ ... _/ \__________________
+ * \_/ \_/ \_/ \_/
+ *
+ */
+ bool i2s_accurate_sck;
+
+ /* McASP specific fields */
+ int tdm_slots;
+ u8 op_mode;
+ u8 num_serializer;
+ u8 *serial_dir;
+ u8 version;
+ u8 txnumevt;
+ u8 rxnumevt;
+};
+
+enum {
+ MCASP_VERSION_1 = 0, /* DM646x */
+ MCASP_VERSION_2, /* DA8xx/OMAPL1x */
+ MCASP_VERSION_3, /* AM33xx */
+};
+
+enum dm365_clk_input_pin {
+ MCBSP_CLKR = 0, /* DM365 */
+ MCBSP_CLKS,
+};
+
+#define INACTIVE_MODE 0
+#define TX_MODE 1
+#define RX_MODE 2
+
+#define DAVINCI_MCASP_IIS_MODE 0
+#define DAVINCI_MCASP_DIT_MODE 1
+
+#if (defined(CONFIG_SOC_OMAPAM33XX) && (defined(CONFIG_SND_AM33XX_SOC) \
+ || (defined(CONFIG_SND_AM33XX_SOC_MODULE))))
+#define davinci_gen_pool omap_gen_pool
+#endif
+
+#endif /* __ASM_HARDWARE_MCASP_H */
diff -PurN linux-stable-23d8c3f/arch/arm/include/asm/hardware/entry-macro-gic.S kernel_3.2.14_patched/arch/arm/include/asm/hardware/entry-macro-gic.S
--- linux-stable-23d8c3f/arch/arm/include/asm/hardware/entry-macro-gic.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/include/asm/hardware/entry-macro-gic.S 1970-01-01 01:00:00.000000000 +0100
@@ -1,60 +0,0 @@
-/*
- * arch/arm/include/asm/hardware/entry-macro-gic.S
- *
- * Low-level IRQ helper macros for GIC
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/gic.h>
-
-#ifndef HAVE_GET_IRQNR_PREAMBLE
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =gic_cpu_base_addr
- ldr \base, [\base]
- .endm
-#endif
-
-/*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * A simple read from the controller will tell us the number of the highest
- * priority enabled interrupt. We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- ldr \irqstat, [\base, #GIC_CPU_INTACK]
- /* bits 12-10 = src CPU, 9-0 = int # */
-
- ldr \tmp, =1021
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #15
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
- .endm
-
-/* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- cmpcs \irqnr, \irqnr
- .endm
diff -PurN linux-stable-23d8c3f/arch/arm/include/asm/hardware/gic.h kernel_3.2.14_patched/arch/arm/include/asm/hardware/gic.h
--- linux-stable-23d8c3f/arch/arm/include/asm/hardware/gic.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/include/asm/hardware/gic.h 2012-05-16 12:10:46.000000000 +0100
@@ -36,30 +36,22 @@
#include <linux/irqdomain.h>
struct device_node;
-extern void __iomem *gic_cpu_base_addr;
extern struct irq_chip gic_arch_extn;
-void gic_init(unsigned int, int, void __iomem *, void __iomem *);
+void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
+ u32 offset);
int gic_of_init(struct device_node *node, struct device_node *parent);
void gic_secondary_init(unsigned int);
+void gic_handle_irq(struct pt_regs *regs);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
-struct gic_chip_data {
- void __iomem *dist_base;
- void __iomem *cpu_base;
-#ifdef CONFIG_CPU_PM
- u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
- u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
- u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
- u32 __percpu *saved_ppi_enable;
- u32 __percpu *saved_ppi_conf;
-#endif
-#ifdef CONFIG_IRQ_DOMAIN
- struct irq_domain domain;
-#endif
- unsigned int gic_irqs;
-};
+static inline void gic_init(unsigned int nr, int start,
+ void __iomem *dist , void __iomem *cpu)
+{
+ gic_init_bases(nr, start, dist, cpu, 0);
+}
+
#endif
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/include/asm/hardware/vic.h kernel_3.2.14_patched/arch/arm/include/asm/hardware/vic.h
--- linux-stable-23d8c3f/arch/arm/include/asm/hardware/vic.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/include/asm/hardware/vic.h 2012-05-16 12:10:46.000000000 +0100
@@ -41,7 +41,15 @@
#define VIC_PL192_VECT_ADDR 0xF00
#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+struct device_node;
+struct pt_regs;
+
void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
-#endif
+int vic_of_init(struct device_node *node, struct device_node *parent);
+void vic_handle_irq(struct pt_regs *regs);
+#endif /* __ASSEMBLY__ */
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/include/asm/mach/arch.h kernel_3.2.14_patched/arch/arm/include/asm/mach/arch.h
--- linux-stable-23d8c3f/arch/arm/include/asm/mach/arch.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/include/asm/mach/arch.h 2012-05-16 12:10:46.000000000 +0100
@@ -31,10 +31,10 @@
unsigned int video_start; /* start of video RAM */
unsigned int video_end; /* end of video RAM */
- unsigned int reserve_lp0 :1; /* never has lp0 */
- unsigned int reserve_lp1 :1; /* never has lp1 */
- unsigned int reserve_lp2 :1; /* never has lp2 */
- unsigned int soft_reboot :1; /* soft reboot */
+ unsigned char reserve_lp0 :1; /* never has lp0 */
+ unsigned char reserve_lp1 :1; /* never has lp1 */
+ unsigned char reserve_lp2 :1; /* never has lp2 */
+ char restart_mode; /* default restart mode */
void (*fixup)(struct tag *, char **,
struct meminfo *);
void (*reserve)(void);/* reserve mem blocks */
@@ -46,6 +46,7 @@
#ifdef CONFIG_MULTI_IRQ_HANDLER
void (*handle_irq)(struct pt_regs *);
#endif
+ void (*restart)(char, const char *);
};
/*
diff -PurN linux-stable-23d8c3f/arch/arm/include/asm/perf_event.h kernel_3.2.14_patched/arch/arm/include/asm/perf_event.h
--- linux-stable-23d8c3f/arch/arm/include/asm/perf_event.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/include/asm/perf_event.h 2012-05-16 12:10:46.000000000 +0100
@@ -32,7 +32,4 @@
extern enum arm_perf_pmu_ids
armpmu_get_pmu_id(void);
-extern int
-armpmu_get_max_events(void);
-
#endif /* __ARM_PERF_EVENT_H__ */
diff -PurN linux-stable-23d8c3f/arch/arm/include/asm/pgtable.h kernel_3.2.14_patched/arch/arm/include/asm/pgtable.h
--- linux-stable-23d8c3f/arch/arm/include/asm/pgtable.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/include/asm/pgtable.h 2012-05-16 12:10:46.000000000 +0100
@@ -21,7 +21,6 @@
#else
#include <asm/memory.h>
-#include <mach/vmalloc.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable-2level.h>
@@ -33,14 +32,16 @@
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
- *
- * Note that platforms may override VMALLOC_START, but they must provide
- * VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space,
- * which may not overlap IO space.
*/
-#ifndef VMALLOC_START
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END 0xff000000UL
+
+/* This is a temporary hack until shmobile's DMA area size is sorted out */
+#ifdef CONFIG_ARCH_SHMOBILE
+#warning "SH-Mobile's consistent DMA size conflicts with VMALLOC_END by 144MB"
+#undef VMALLOC_END
+#define VMALLOC_END 0xF6000000UL
#endif
#define LIBRARY_TEXT_START 0x0c000000
diff -PurN linux-stable-23d8c3f/arch/arm/include/asm/pmu.h kernel_3.2.14_patched/arch/arm/include/asm/pmu.h
--- linux-stable-23d8c3f/arch/arm/include/asm/pmu.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/include/asm/pmu.h 2012-05-16 12:12:51.000000000 +0100
@@ -27,13 +27,22 @@
/*
* struct arm_pmu_platdata - ARM PMU platform data
*
- * @handle_irq: an optional handler which will be called from the interrupt and
- * passed the address of the low level handler, and can be used to implement
- * any platform specific handling before or after calling it.
+ * @handle_irq: an optional handler which will be called from the
+ * interrupt and passed the address of the low level handler,
+ * and can be used to implement any platform specific handling
+ * before or after calling it.
+ * @enable_irq: an optional handler which will be called after
+ * request_irq and be used to handle some platform specific
+ * irq enablement
+ * @disable_irq: an optional handler which will be called before
+ * free_irq and be used to handle some platform specific
+ * irq disablement
*/
struct arm_pmu_platdata {
irqreturn_t (*handle_irq)(int irq, void *dev,
irq_handler_t pmu_handler);
+ void (*enable_irq)(int irq);
+ void (*disable_irq)(int irq);
};
#ifdef CONFIG_CPU_HAS_PMU
diff -PurN linux-stable-23d8c3f/arch/arm/include/asm/system.h kernel_3.2.14_patched/arch/arm/include/asm/system.h
--- linux-stable-23d8c3f/arch/arm/include/asm/system.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/include/asm/system.h 2012-05-16 12:10:46.000000000 +0100
@@ -101,6 +101,7 @@
extern void cpu_init(void);
void arm_machine_restart(char mode, const char *cmd);
+void soft_restart(unsigned long);
extern void (*arm_pm_restart)(char str, const char *cmd);
#define UDBG_UNDEFINED (1 << 0)
diff -PurN linux-stable-23d8c3f/arch/arm/Kconfig kernel_3.2.14_patched/arch/arm/Kconfig
--- linux-stable-23d8c3f/arch/arm/Kconfig 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/Kconfig 2012-05-16 12:12:51.000000000 +0100
@@ -938,6 +938,7 @@
select ARCH_REQUIRE_GPIOLIB
select ARCH_HAS_CPUFREQ
select CLKSRC_MMIO
+ select GENERIC_ALLOCATOR
select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
select ARCH_HAS_HOLES_MEMORYMODEL
diff -PurN linux-stable-23d8c3f/arch/arm/Kconfig.debug kernel_3.2.14_patched/arch/arm/Kconfig.debug
--- linux-stable-23d8c3f/arch/arm/Kconfig.debug 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/Kconfig.debug 2012-05-16 12:10:46.000000000 +0100
@@ -271,4 +271,10 @@
help
Perform tests of kprobes API and instruction set simulation.
+config DEBUG_JTAG_ENABLE
+ bool "Enable JTAG clock for debugger connectivity"
+ help
+ Say Y here if you want to enable the JTAG clock to enable
+ connectivity to a debugger
+
endmenu
diff -PurN linux-stable-23d8c3f/arch/arm/kernel/entry-armv.S kernel_3.2.14_patched/arch/arm/kernel/entry-armv.S
--- linux-stable-23d8c3f/arch/arm/kernel/entry-armv.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/kernel/entry-armv.S 2012-05-16 12:10:46.000000000 +0100
@@ -36,12 +36,11 @@
#ifdef CONFIG_MULTI_IRQ_HANDLER
ldr r1, =handle_arch_irq
mov r0, sp
- ldr r1, [r1]
adr lr, BSYM(9997f)
- teq r1, #0
- movne pc, r1
-#endif
+ ldr pc, [r1]
+#else
arch_irq_handler_default
+#endif
9997:
.endm
diff -PurN linux-stable-23d8c3f/arch/arm/kernel/machine_kexec.c kernel_3.2.14_patched/arch/arm/kernel/machine_kexec.c
--- linux-stable-23d8c3f/arch/arm/kernel/machine_kexec.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/kernel/machine_kexec.c 2012-05-16 12:10:46.000000000 +0100
@@ -16,7 +16,7 @@
extern const unsigned char relocate_new_kernel[];
extern const unsigned int relocate_new_kernel_size;
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
extern unsigned long kexec_start_address;
extern unsigned long kexec_indirection_page;
@@ -113,7 +113,7 @@
kexec_reinit();
local_irq_disable();
local_fiq_disable();
- setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
+ setup_mm_for_reboot();
flush_cache_all();
outer_flush_all();
outer_disable();
diff -PurN linux-stable-23d8c3f/arch/arm/kernel/perf_event.c kernel_3.2.14_patched/arch/arm/kernel/perf_event.c
--- linux-stable-23d8c3f/arch/arm/kernel/perf_event.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/kernel/perf_event.c 2012-05-16 12:12:51.000000000 +0100
@@ -59,8 +59,7 @@
}
EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
-int
-armpmu_get_max_events(void)
+int perf_num_counters(void)
{
int max_events = 0;
@@ -69,12 +68,6 @@
return max_events;
}
-EXPORT_SYMBOL_GPL(armpmu_get_max_events);
-
-int perf_num_counters(void)
-{
- return armpmu_get_max_events();
-}
EXPORT_SYMBOL_GPL(perf_num_counters);
#define HW_OP_UNSUPPORTED 0xFFFF
@@ -374,6 +367,8 @@
{
int i, irq, irqs;
struct platform_device *pmu_device = armpmu->plat_device;
+ struct arm_pmu_platdata *plat =
+ dev_get_platdata(&pmu_device->dev);
irqs = min(pmu_device->num_resources, num_possible_cpus());
@@ -381,8 +376,11 @@
if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
continue;
irq = platform_get_irq(pmu_device, i);
- if (irq >= 0)
+ if (irq >= 0) {
+ if (plat && plat->disable_irq)
+ plat->disable_irq(irq);
free_irq(irq, armpmu);
+ }
}
release_pmu(armpmu->type);
@@ -442,7 +440,8 @@
irq);
armpmu_release_hardware(armpmu);
return err;
- }
+ } else if (plat && plat->enable_irq)
+ plat->enable_irq(irq);
cpumask_set_cpu(i, &armpmu->active_irqs);
}
diff -PurN linux-stable-23d8c3f/arch/arm/kernel/perf_event_v6.c kernel_3.2.14_patched/arch/arm/kernel/perf_event_v6.c
--- linux-stable-23d8c3f/arch/arm/kernel/perf_event_v6.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/kernel/perf_event_v6.c 2012-05-16 12:12:51.000000000 +0100
@@ -65,13 +65,15 @@
* accesses/misses in hardware.
*/
static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
- [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES,
- [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC,
- [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
- [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
- [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT,
- [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES,
+ [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
+ [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT,
+ [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6_PERFCTR_IBUF_STALL,
+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6_PERFCTR_LSU_FULL_STALL,
};
static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -218,13 +220,15 @@
* accesses/misses in hardware.
*/
static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
- [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
- [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
- [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
- [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
- [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
- [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
+ [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
+ [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
+ [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL,
+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL,
};
static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
diff -PurN linux-stable-23d8c3f/arch/arm/kernel/perf_event_v7.c kernel_3.2.14_patched/arch/arm/kernel/perf_event_v7.c
--- linux-stable-23d8c3f/arch/arm/kernel/perf_event_v7.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/kernel/perf_event_v7.c 2012-05-16 12:12:51.000000000 +0100
@@ -28,165 +28,87 @@
* they are not available.
*/
enum armv7_perf_types {
- ARMV7_PERFCTR_PMNC_SW_INCR = 0x00,
- ARMV7_PERFCTR_IFETCH_MISS = 0x01,
- ARMV7_PERFCTR_ITLB_MISS = 0x02,
- ARMV7_PERFCTR_DCACHE_REFILL = 0x03, /* L1 */
- ARMV7_PERFCTR_DCACHE_ACCESS = 0x04, /* L1 */
- ARMV7_PERFCTR_DTLB_REFILL = 0x05,
- ARMV7_PERFCTR_DREAD = 0x06,
- ARMV7_PERFCTR_DWRITE = 0x07,
- ARMV7_PERFCTR_INSTR_EXECUTED = 0x08,
- ARMV7_PERFCTR_EXC_TAKEN = 0x09,
- ARMV7_PERFCTR_EXC_EXECUTED = 0x0A,
- ARMV7_PERFCTR_CID_WRITE = 0x0B,
- /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
+ ARMV7_PERFCTR_PMNC_SW_INCR = 0x00,
+ ARMV7_PERFCTR_L1_ICACHE_REFILL = 0x01,
+ ARMV7_PERFCTR_ITLB_REFILL = 0x02,
+ ARMV7_PERFCTR_L1_DCACHE_REFILL = 0x03,
+ ARMV7_PERFCTR_L1_DCACHE_ACCESS = 0x04,
+ ARMV7_PERFCTR_DTLB_REFILL = 0x05,
+ ARMV7_PERFCTR_MEM_READ = 0x06,
+ ARMV7_PERFCTR_MEM_WRITE = 0x07,
+ ARMV7_PERFCTR_INSTR_EXECUTED = 0x08,
+ ARMV7_PERFCTR_EXC_TAKEN = 0x09,
+ ARMV7_PERFCTR_EXC_EXECUTED = 0x0A,
+ ARMV7_PERFCTR_CID_WRITE = 0x0B,
+
+ /*
+ * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
* It counts:
- * - all branch instructions,
+ * - all (taken) branch instructions,
* - instructions that explicitly write the PC,
* - exception generating instructions.
*/
- ARMV7_PERFCTR_PC_WRITE = 0x0C,
- ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D,
- ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E,
- ARMV7_PERFCTR_UNALIGNED_ACCESS = 0x0F,
+ ARMV7_PERFCTR_PC_WRITE = 0x0C,
+ ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D,
+ ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E,
+ ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS = 0x0F,
+ ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
+ ARMV7_PERFCTR_CLOCK_CYCLES = 0x11,
+ ARMV7_PERFCTR_PC_BRANCH_PRED = 0x12,
/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
- ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
- ARMV7_PERFCTR_CLOCK_CYCLES = 0x11,
- ARMV7_PERFCTR_PC_BRANCH_PRED = 0x12,
- ARMV7_PERFCTR_MEM_ACCESS = 0x13,
- ARMV7_PERFCTR_L1_ICACHE_ACCESS = 0x14,
- ARMV7_PERFCTR_L1_DCACHE_WB = 0x15,
- ARMV7_PERFCTR_L2_DCACHE_ACCESS = 0x16,
- ARMV7_PERFCTR_L2_DCACHE_REFILL = 0x17,
- ARMV7_PERFCTR_L2_DCACHE_WB = 0x18,
- ARMV7_PERFCTR_BUS_ACCESS = 0x19,
- ARMV7_PERFCTR_MEMORY_ERROR = 0x1A,
- ARMV7_PERFCTR_INSTR_SPEC = 0x1B,
- ARMV7_PERFCTR_TTBR_WRITE = 0x1C,
- ARMV7_PERFCTR_BUS_CYCLES = 0x1D,
+ ARMV7_PERFCTR_MEM_ACCESS = 0x13,
+ ARMV7_PERFCTR_L1_ICACHE_ACCESS = 0x14,
+ ARMV7_PERFCTR_L1_DCACHE_WB = 0x15,
+ ARMV7_PERFCTR_L2_CACHE_ACCESS = 0x16,
+ ARMV7_PERFCTR_L2_CACHE_REFILL = 0x17,
+ ARMV7_PERFCTR_L2_CACHE_WB = 0x18,
+ ARMV7_PERFCTR_BUS_ACCESS = 0x19,
+ ARMV7_PERFCTR_MEM_ERROR = 0x1A,
+ ARMV7_PERFCTR_INSTR_SPEC = 0x1B,
+ ARMV7_PERFCTR_TTBR_WRITE = 0x1C,
+ ARMV7_PERFCTR_BUS_CYCLES = 0x1D,
- ARMV7_PERFCTR_CPU_CYCLES = 0xFF
+ ARMV7_PERFCTR_CPU_CYCLES = 0xFF
};
/* ARMv7 Cortex-A8 specific event types */
enum armv7_a8_perf_types {
- ARMV7_PERFCTR_WRITE_BUFFER_FULL = 0x40,
- ARMV7_PERFCTR_L2_STORE_MERGED = 0x41,
- ARMV7_PERFCTR_L2_STORE_BUFF = 0x42,
- ARMV7_PERFCTR_L2_ACCESS = 0x43,
- ARMV7_PERFCTR_L2_CACH_MISS = 0x44,
- ARMV7_PERFCTR_AXI_READ_CYCLES = 0x45,
- ARMV7_PERFCTR_AXI_WRITE_CYCLES = 0x46,
- ARMV7_PERFCTR_MEMORY_REPLAY = 0x47,
- ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY = 0x48,
- ARMV7_PERFCTR_L1_DATA_MISS = 0x49,
- ARMV7_PERFCTR_L1_INST_MISS = 0x4A,
- ARMV7_PERFCTR_L1_DATA_COLORING = 0x4B,
- ARMV7_PERFCTR_L1_NEON_DATA = 0x4C,
- ARMV7_PERFCTR_L1_NEON_CACH_DATA = 0x4D,
- ARMV7_PERFCTR_L2_NEON = 0x4E,
- ARMV7_PERFCTR_L2_NEON_HIT = 0x4F,
- ARMV7_PERFCTR_L1_INST = 0x50,
- ARMV7_PERFCTR_PC_RETURN_MIS_PRED = 0x51,
- ARMV7_PERFCTR_PC_BRANCH_FAILED = 0x52,
- ARMV7_PERFCTR_PC_BRANCH_TAKEN = 0x53,
- ARMV7_PERFCTR_PC_BRANCH_EXECUTED = 0x54,
- ARMV7_PERFCTR_OP_EXECUTED = 0x55,
- ARMV7_PERFCTR_CYCLES_INST_STALL = 0x56,
- ARMV7_PERFCTR_CYCLES_INST = 0x57,
- ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL = 0x58,
- ARMV7_PERFCTR_CYCLES_NEON_INST_STALL = 0x59,
- ARMV7_PERFCTR_NEON_CYCLES = 0x5A,
-
- ARMV7_PERFCTR_PMU0_EVENTS = 0x70,
- ARMV7_PERFCTR_PMU1_EVENTS = 0x71,
- ARMV7_PERFCTR_PMU_EVENTS = 0x72,
+ ARMV7_A8_PERFCTR_L2_CACHE_ACCESS = 0x43,
+ ARMV7_A8_PERFCTR_L2_CACHE_REFILL = 0x44,
+ ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS = 0x50,
+ ARMV7_A8_PERFCTR_STALL_ISIDE = 0x56,
};
/* ARMv7 Cortex-A9 specific event types */
enum armv7_a9_perf_types {
- ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC = 0x40,
- ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC = 0x41,
- ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC = 0x42,
-
- ARMV7_PERFCTR_COHERENT_LINE_MISS = 0x50,
- ARMV7_PERFCTR_COHERENT_LINE_HIT = 0x51,
-
- ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES = 0x60,
- ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES = 0x61,
- ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
- ARMV7_PERFCTR_STREX_EXECUTED_PASSED = 0x63,
- ARMV7_PERFCTR_STREX_EXECUTED_FAILED = 0x64,
- ARMV7_PERFCTR_DATA_EVICTION = 0x65,
- ARMV7_PERFCTR_ISSUE_STAGE_NO_INST = 0x66,
- ARMV7_PERFCTR_ISSUE_STAGE_EMPTY = 0x67,
- ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE = 0x68,
-
- ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
-
- ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST = 0x70,
- ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
- ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST = 0x72,
- ARMV7_PERFCTR_FP_EXECUTED_INST = 0x73,
- ARMV7_PERFCTR_NEON_EXECUTED_INST = 0x74,
-
- ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
- ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES = 0x81,
- ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES = 0x82,
- ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES = 0x83,
- ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES = 0x84,
- ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES = 0x85,
- ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES = 0x86,
-
- ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES = 0x8A,
- ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
-
- ARMV7_PERFCTR_ISB_INST = 0x90,
- ARMV7_PERFCTR_DSB_INST = 0x91,
- ARMV7_PERFCTR_DMB_INST = 0x92,
- ARMV7_PERFCTR_EXT_INTERRUPTS = 0x93,
-
- ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED = 0xA0,
- ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED = 0xA1,
- ARMV7_PERFCTR_PLE_FIFO_FLUSH = 0xA2,
- ARMV7_PERFCTR_PLE_RQST_COMPLETED = 0xA3,
- ARMV7_PERFCTR_PLE_FIFO_OVERFLOW = 0xA4,
- ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5
+ ARMV7_A9_PERFCTR_INSTR_CORE_RENAME = 0x68,
+ ARMV7_A9_PERFCTR_STALL_ICACHE = 0x60,
+ ARMV7_A9_PERFCTR_STALL_DISPATCH = 0x66,
};
/* ARMv7 Cortex-A5 specific event types */
enum armv7_a5_perf_types {
- ARMV7_PERFCTR_IRQ_TAKEN = 0x86,
- ARMV7_PERFCTR_FIQ_TAKEN = 0x87,
-
- ARMV7_PERFCTR_EXT_MEM_RQST = 0xc0,
- ARMV7_PERFCTR_NC_EXT_MEM_RQST = 0xc1,
- ARMV7_PERFCTR_PREFETCH_LINEFILL = 0xc2,
- ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP = 0xc3,
- ARMV7_PERFCTR_ENTER_READ_ALLOC = 0xc4,
- ARMV7_PERFCTR_READ_ALLOC = 0xc5,
-
- ARMV7_PERFCTR_STALL_SB_FULL = 0xc9,
+ ARMV7_A5_PERFCTR_PREFETCH_LINEFILL = 0xc2,
+ ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP = 0xc3,
};
/* ARMv7 Cortex-A15 specific event types */
enum armv7_a15_perf_types {
- ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS = 0x40,
- ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS = 0x41,
- ARMV7_PERFCTR_L1_DCACHE_READ_REFILL = 0x42,
- ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL = 0x43,
-
- ARMV7_PERFCTR_L1_DTLB_READ_REFILL = 0x4C,
- ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL = 0x4D,
-
- ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS = 0x50,
- ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS = 0x51,
- ARMV7_PERFCTR_L2_DCACHE_READ_REFILL = 0x52,
- ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL = 0x53,
+ ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ = 0x40,
+ ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE = 0x41,
+ ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ = 0x42,
+ ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE = 0x43,
+
+ ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ = 0x4C,
+ ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE = 0x4D,
+
+ ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ = 0x50,
+ ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE = 0x51,
+ ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ = 0x52,
+ ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE = 0x53,
- ARMV7_PERFCTR_SPEC_PC_WRITE = 0x76,
+ ARMV7_A15_PERFCTR_PC_WRITE_SPEC = 0x76,
};
/*
@@ -197,13 +119,15 @@
* accesses/misses in hardware.
*/
static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
- [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
- [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
- [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
- [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
- [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
- [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
+ [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
+ [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+ [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE,
+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
};
static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -217,12 +141,12 @@
* combined.
*/
[C(OP_READ)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
},
[C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -231,12 +155,12 @@
},
[C(L1I)] = {
[C(OP_READ)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS,
+ [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
},
[C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS,
+ [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -245,12 +169,12 @@
},
[C(LL)] = {
[C(OP_READ)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS,
+ [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
+ [C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
},
[C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS,
+ [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
+ [C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -274,11 +198,11 @@
[C(ITLB)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -287,14 +211,12 @@
},
[C(BPU)] = {
[C(OP_READ)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
},
[C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -321,14 +243,15 @@
* Cortex-A9 HW events mapping
*/
static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
- [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
- [PERF_COUNT_HW_INSTRUCTIONS] =
- ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
- [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_DCACHE_ACCESS,
- [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_DCACHE_REFILL,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
- [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
- [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
+ [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
+ [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+ [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE,
+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH,
};
static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -342,12 +265,12 @@
* combined.
*/
[C(OP_READ)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
},
[C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -357,11 +280,11 @@
[C(L1I)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -399,11 +322,11 @@
[C(ITLB)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -412,14 +335,12 @@
},
[C(BPU)] = {
[C(OP_READ)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
},
[C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -446,13 +367,15 @@
* Cortex-A5 HW events mapping
*/
static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
- [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
- [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
- [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
- [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
- [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
- [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
+ [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+ [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
};
static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -460,42 +383,34 @@
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
[C(L1D)] = {
[C(OP_READ)] = {
- [C(RESULT_ACCESS)]
- = ARMV7_PERFCTR_DCACHE_ACCESS,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_DCACHE_REFILL,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)]
- = ARMV7_PERFCTR_DCACHE_ACCESS,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_DCACHE_REFILL,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)]
- = ARMV7_PERFCTR_PREFETCH_LINEFILL,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
+ [C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
},
},
[C(L1I)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
},
/*
* The prefetch counters don't differentiate between the I
* side and the D side.
*/
[C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)]
- = ARMV7_PERFCTR_PREFETCH_LINEFILL,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
+ [C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
+ [C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
},
},
[C(LL)] = {
@@ -529,11 +444,11 @@
[C(ITLB)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -543,13 +458,11 @@
[C(BPU)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -562,13 +475,15 @@
* Cortex-A15 HW events mapping
*/
static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
- [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
- [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
- [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
- [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_SPEC_PC_WRITE,
- [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
- [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
+ [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
+ [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+ [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC,
+ [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
};
static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -576,16 +491,12 @@
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
[C(L1D)] = {
[C(OP_READ)] = {
- [C(RESULT_ACCESS)]
- = ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_L1_DCACHE_READ_REFILL,
+ [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ,
+ [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ,
},
[C(OP_WRITE)] = {
- [C(RESULT_ACCESS)]
- = ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL,
+ [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE,
+ [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -601,11 +512,11 @@
*/
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -614,16 +525,12 @@
},
[C(LL)] = {
[C(OP_READ)] = {
- [C(RESULT_ACCESS)]
- = ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_L2_DCACHE_READ_REFILL,
+ [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
+ [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
},
[C(OP_WRITE)] = {
- [C(RESULT_ACCESS)]
- = ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL,
+ [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
+ [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -633,13 +540,11 @@
[C(DTLB)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_L1_DTLB_READ_REFILL,
+ [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL,
+ [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -649,11 +554,11 @@
[C(ITLB)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -663,13 +568,11 @@
[C(BPU)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
- [C(RESULT_MISS)]
- = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
diff -PurN linux-stable-23d8c3f/arch/arm/kernel/perf_event_xscale.c kernel_3.2.14_patched/arch/arm/kernel/perf_event_xscale.c
--- linux-stable-23d8c3f/arch/arm/kernel/perf_event_xscale.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/kernel/perf_event_xscale.c 2012-05-16 12:12:51.000000000 +0100
@@ -48,13 +48,15 @@
};
static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
- [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT,
- [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION,
- [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
- [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
- [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS,
- [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT,
+ [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
+ [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS,
+ [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XSCALE_PERFCTR_ICACHE_NO_DELIVER,
+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
};
static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
diff -PurN linux-stable-23d8c3f/arch/arm/kernel/process.c kernel_3.2.14_patched/arch/arm/kernel/process.c
--- linux-stable-23d8c3f/arch/arm/kernel/process.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/kernel/process.c 2012-05-16 12:10:46.000000000 +0100
@@ -57,7 +57,7 @@
"ARM" , "Thumb" , "Jazelle", "ThumbEE"
};
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
static volatile int hlt_counter;
@@ -92,7 +92,7 @@
__setup("nohlt", nohlt_setup);
__setup("hlt", hlt_setup);
-void arm_machine_restart(char mode, const char *cmd)
+void soft_restart(unsigned long addr)
{
/* Disable interrupts first */
local_irq_disable();
@@ -103,7 +103,7 @@
* we may need it to insert some 1:1 mappings so that
* soft boot works.
*/
- setup_mm_for_reboot(mode);
+ setup_mm_for_reboot();
/* Clean and invalidate caches */
flush_cache_all();
@@ -114,18 +114,17 @@
/* Push out any further dirty data, and ensure cache is empty */
flush_cache_all();
- /*
- * Now call the architecture specific reboot code.
- */
- arch_reset(mode, cmd);
+ cpu_reset(addr);
+}
- /*
- * Whoops - the architecture was unable to reboot.
- * Tell the user!
- */
- mdelay(1000);
- printk("Reboot failed -- System halted\n");
- while (1);
+void arm_machine_restart(char mode, const char *cmd)
+{
+ /* Disable interrupts first */
+ local_irq_disable();
+ local_fiq_disable();
+
+ /* Call the architecture specific reboot code. */
+ arch_reset(mode, cmd);
}
/*
@@ -253,7 +252,15 @@
void machine_restart(char *cmd)
{
machine_shutdown();
+
arm_pm_restart(reboot_mode, cmd);
+
+ /* Give a grace period for failure to restart of 1s */
+ mdelay(1000);
+
+ /* Whoops - the platform was unable to reboot. Tell the user! */
+ printk("Reboot failed -- System halted\n");
+ while (1);
}
void __show_regs(struct pt_regs *regs)
diff -PurN linux-stable-23d8c3f/arch/arm/kernel/setup.c kernel_3.2.14_patched/arch/arm/kernel/setup.c
--- linux-stable-23d8c3f/arch/arm/kernel/setup.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/kernel/setup.c 2012-05-16 12:10:46.000000000 +0100
@@ -31,6 +31,7 @@
#include <linux/memblock.h>
#include <linux/bug.h>
#include <linux/compiler.h>
+#include <linux/sort.h>
#include <asm/unified.h>
#include <asm/cpu.h>
@@ -890,6 +891,12 @@
return mdesc;
}
+static int __init meminfo_cmp(const void *_a, const void *_b)
+{
+ const struct membank *a = _a, *b = _b;
+ long cmp = bank_pfn_start(a) - bank_pfn_start(b);
+ return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
+}
void __init setup_arch(char **cmdline_p)
{
@@ -902,14 +909,8 @@
machine_desc = mdesc;
machine_name = mdesc->name;
-#ifdef CONFIG_ZONE_DMA
- if (mdesc->dma_zone_size) {
- extern unsigned long arm_dma_zone_size;
- arm_dma_zone_size = mdesc->dma_zone_size;
- }
-#endif
- if (mdesc->soft_reboot)
- reboot_setup("s");
+ if (mdesc->restart_mode)
+ reboot_setup(&mdesc->restart_mode);
init_mm.start_code = (unsigned long) _text;
init_mm.end_code = (unsigned long) _etext;
@@ -922,12 +923,16 @@
parse_early_param();
+ sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
sanity_check_meminfo();
arm_memblock_init(&meminfo, mdesc);
paging_init(mdesc);
request_standard_resources(mdesc);
+ if (mdesc->restart)
+ arm_pm_restart = mdesc->restart;
+
unflatten_device_tree();
#ifdef CONFIG_SMP
diff -PurN linux-stable-23d8c3f/arch/arm/kernel/time.c kernel_3.2.14_patched/arch/arm/kernel/time.c
--- linux-stable-23d8c3f/arch/arm/kernel/time.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/kernel/time.c 2012-05-16 12:10:46.000000000 +0100
@@ -112,7 +112,7 @@
}
#endif
-#if defined(CONFIG_PM) && !defined(CONFIG_GENERIC_CLOCKEVENTS)
+#if defined(CONFIG_PM)
static int timer_suspend(void)
{
if (system_timer->suspend)
diff -PurN linux-stable-23d8c3f/arch/arm/mach-at91/include/mach/io.h kernel_3.2.14_patched/arch/arm/mach-at91/include/mach/io.h
--- linux-stable-23d8c3f/arch/arm/mach-at91/include/mach/io.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-at91/include/mach/io.h 2012-05-16 12:10:46.000000000 +0100
@@ -30,14 +30,6 @@
#ifndef __ASSEMBLY__
-#ifndef CONFIG_ARCH_AT91X40
-#define __arch_ioremap at91_ioremap
-#define __arch_iounmap at91_iounmap
-#endif
-
-void __iomem *at91_ioremap(unsigned long phys, size_t size, unsigned int type);
-void at91_iounmap(volatile void __iomem *addr);
-
static inline unsigned int at91_sys_read(unsigned int reg_offset)
{
void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
diff -PurN linux-stable-23d8c3f/arch/arm/mach-at91/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-at91/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-at91/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-at91/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/vmalloc.h
- *
- * Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-
-#include <mach/hardware.h>
-
-#define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK)
-
-#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-at91/setup.c kernel_3.2.14_patched/arch/arm/mach-at91/setup.c
--- linux-stable-23d8c3f/arch/arm/mach-at91/setup.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-at91/setup.c 2012-05-16 12:12:17.000000000 +0100
@@ -76,24 +76,6 @@
.type = MT_DEVICE,
};
-void __iomem *at91_ioremap(unsigned long p, size_t size, unsigned int type)
-{
- if (p >= AT91_BASE_SYS && p <= (AT91_BASE_SYS + SZ_16K - 1))
- return (void __iomem *)AT91_IO_P2V(p);
-
- return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
-}
-EXPORT_SYMBOL(at91_ioremap);
-
-void at91_iounmap(volatile void __iomem *addr)
-{
- unsigned long virt = (unsigned long)addr;
-
- if (virt >= VMALLOC_START && virt < VMALLOC_END)
- __iounmap(addr);
-}
-EXPORT_SYMBOL(at91_iounmap);
-
#define AT91_DBGU0 0xfffff200
#define AT91_DBGU1 0xffffee00
diff -PurN linux-stable-23d8c3f/arch/arm/mach-bcmring/dma.c kernel_3.2.14_patched/arch/arm/mach-bcmring/dma.c
--- linux-stable-23d8c3f/arch/arm/mach-bcmring/dma.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-bcmring/dma.c 2012-05-16 12:10:46.000000000 +0100
@@ -1615,7 +1615,7 @@
{
unsigned long addrVal = (unsigned long)addr;
- if (addrVal >= VMALLOC_END) {
+ if (addrVal >= CONSISTENT_BASE) {
/* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */
/* dma_alloc_xxx pages are physically and virtually contiguous */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-bcmring/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-bcmring/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-bcmring/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-bcmring/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,25 +0,0 @@
-/*
- *
- * Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-/*
- * Move VMALLOC_END to 0xf0000000 so that the vm space can range from
- * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
- * larger physical memory designs better.
- */
-#define VMALLOC_END 0xf0000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-clps711x/common.c kernel_3.2.14_patched/arch/arm/mach-clps711x/common.c
--- linux-stable-23d8c3f/arch/arm/mach-clps711x/common.c 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-clps711x/common.c 2012-05-16 12:10:46.000000000 +0100
@@ -0,0 +1,222 @@
+/*
+ * linux/arch/arm/mach-clps711x/core.c
+ *
+ * Core support for the CLPS711x-based machines.
+ *
+ * Copyright (C) 2001,2011 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/sched.h>
+#include <linux/timex.h>
+
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/leds.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/clps7111.h>
+
+/*
+ * This maps the generic CLPS711x registers
+ */
+static struct map_desc clps711x_io_desc[] __initdata = {
+ {
+ .virtual = CLPS7111_VIRT_BASE,
+ .pfn = __phys_to_pfn(CLPS7111_PHYS_BASE),
+ .length = SZ_1M,
+ .type = MT_DEVICE
+ }
+};
+
+void __init clps711x_map_io(void)
+{
+ iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
+}
+
+static void int1_mask(struct irq_data *d)
+{
+ u32 intmr1;
+
+ intmr1 = clps_readl(INTMR1);
+ intmr1 &= ~(1 << d->irq);
+ clps_writel(intmr1, INTMR1);
+}
+
+static void int1_ack(struct irq_data *d)
+{
+ u32 intmr1;
+
+ intmr1 = clps_readl(INTMR1);
+ intmr1 &= ~(1 << d->irq);
+ clps_writel(intmr1, INTMR1);
+
+ switch (d->irq) {
+ case IRQ_CSINT: clps_writel(0, COEOI); break;
+ case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
+ case IRQ_TC2OI: clps_writel(0, TC2EOI); break;
+ case IRQ_RTCMI: clps_writel(0, RTCEOI); break;
+ case IRQ_TINT: clps_writel(0, TEOI); break;
+ case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
+ }
+}
+
+static void int1_unmask(struct irq_data *d)
+{
+ u32 intmr1;
+
+ intmr1 = clps_readl(INTMR1);
+ intmr1 |= 1 << d->irq;
+ clps_writel(intmr1, INTMR1);
+}
+
+static struct irq_chip int1_chip = {
+ .irq_ack = int1_ack,
+ .irq_mask = int1_mask,
+ .irq_unmask = int1_unmask,
+};
+
+static void int2_mask(struct irq_data *d)
+{
+ u32 intmr2;
+
+ intmr2 = clps_readl(INTMR2);
+ intmr2 &= ~(1 << (d->irq - 16));
+ clps_writel(intmr2, INTMR2);
+}
+
+static void int2_ack(struct irq_data *d)
+{
+ u32 intmr2;
+
+ intmr2 = clps_readl(INTMR2);
+ intmr2 &= ~(1 << (d->irq - 16));
+ clps_writel(intmr2, INTMR2);
+
+ switch (d->irq) {
+ case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
+ }
+}
+
+static void int2_unmask(struct irq_data *d)
+{
+ u32 intmr2;
+
+ intmr2 = clps_readl(INTMR2);
+ intmr2 |= 1 << (d->irq - 16);
+ clps_writel(intmr2, INTMR2);
+}
+
+static struct irq_chip int2_chip = {
+ .irq_ack = int2_ack,
+ .irq_mask = int2_mask,
+ .irq_unmask = int2_unmask,
+};
+
+void __init clps711x_init_irq(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < NR_IRQS; i++) {
+ if (INT1_IRQS & (1 << i)) {
+ irq_set_chip_and_handler(i, &int1_chip,
+ handle_level_irq);
+ set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+ }
+ if (INT2_IRQS & (1 << i)) {
+ irq_set_chip_and_handler(i, &int2_chip,
+ handle_level_irq);
+ set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+ }
+ }
+
+ /*
+ * Disable interrupts
+ */
+ clps_writel(0, INTMR1);
+ clps_writel(0, INTMR2);
+
+ /*
+ * Clear down any pending interrupts
+ */
+ clps_writel(0, COEOI);
+ clps_writel(0, TC1EOI);
+ clps_writel(0, TC2EOI);
+ clps_writel(0, RTCEOI);
+ clps_writel(0, TEOI);
+ clps_writel(0, UMSEOI);
+ clps_writel(0, SYNCIO);
+ clps_writel(0, KBDEOI);
+}
+
+/*
+ * gettimeoffset() returns time since last timer tick, in usecs.
+ *
+ * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
+ * 'tick' is usecs per jiffy.
+ */
+static unsigned long clps711x_gettimeoffset(void)
+{
+ unsigned long hwticks;
+ hwticks = LATCH - (clps_readl(TC2D) & 0xffff); /* since last underflow */
+ return (hwticks * (tick_nsec / 1000)) / LATCH;
+}
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t p720t_timer_interrupt(int irq, void *dev_id)
+{
+ timer_tick();
+ return IRQ_HANDLED;
+}
+
+static struct irqaction clps711x_timer_irq = {
+ .name = "CLPS711x Timer Tick",
+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+ .handler = p720t_timer_interrupt,
+};
+
+static void __init clps711x_timer_init(void)
+{
+ struct timespec tv;
+ unsigned int syscon;
+
+ syscon = clps_readl(SYSCON1);
+ syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
+ clps_writel(syscon, SYSCON1);
+
+ clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
+
+ setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
+
+ tv.tv_nsec = 0;
+ tv.tv_sec = clps_readl(RTCDR);
+ do_settimeofday(&tv);
+}
+
+struct sys_timer clps711x_timer = {
+ .init = clps711x_timer_init,
+ .offset = clps711x_gettimeoffset,
+};
diff -PurN linux-stable-23d8c3f/arch/arm/mach-clps711x/include/mach/system.h kernel_3.2.14_patched/arch/arm/mach-clps711x/include/mach/system.h
--- linux-stable-23d8c3f/arch/arm/mach-clps711x/include/mach/system.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-clps711x/include/mach/system.h 2012-05-16 12:10:47.000000000 +0100
@@ -34,7 +34,7 @@
static inline void arch_reset(char mode, const char *cmd)
{
- cpu_reset(0);
+ soft_restart(0);
}
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-clps711x/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-clps711x/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-clps711x/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-clps711x/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-clps711x/include/mach/vmalloc.h
- *
- * Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END 0xd0000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-clps711x/irq.c kernel_3.2.14_patched/arch/arm/mach-clps711x/irq.c
--- linux-stable-23d8c3f/arch/arm/mach-clps711x/irq.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-clps711x/irq.c 1970-01-01 01:00:00.000000000 +0100
@@ -1,143 +0,0 @@
-/*
- * linux/arch/arm/mach-clps711x/irq.c
- *
- * Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/io.h>
-
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/hardware/clps7111.h>
-
-static void int1_mask(struct irq_data *d)
-{
- u32 intmr1;
-
- intmr1 = clps_readl(INTMR1);
- intmr1 &= ~(1 << d->irq);
- clps_writel(intmr1, INTMR1);
-}
-
-static void int1_ack(struct irq_data *d)
-{
- u32 intmr1;
-
- intmr1 = clps_readl(INTMR1);
- intmr1 &= ~(1 << d->irq);
- clps_writel(intmr1, INTMR1);
-
- switch (d->irq) {
- case IRQ_CSINT: clps_writel(0, COEOI); break;
- case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
- case IRQ_TC2OI: clps_writel(0, TC2EOI); break;
- case IRQ_RTCMI: clps_writel(0, RTCEOI); break;
- case IRQ_TINT: clps_writel(0, TEOI); break;
- case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
- }
-}
-
-static void int1_unmask(struct irq_data *d)
-{
- u32 intmr1;
-
- intmr1 = clps_readl(INTMR1);
- intmr1 |= 1 << d->irq;
- clps_writel(intmr1, INTMR1);
-}
-
-static struct irq_chip int1_chip = {
- .irq_ack = int1_ack,
- .irq_mask = int1_mask,
- .irq_unmask = int1_unmask,
-};
-
-static void int2_mask(struct irq_data *d)
-{
- u32 intmr2;
-
- intmr2 = clps_readl(INTMR2);
- intmr2 &= ~(1 << (d->irq - 16));
- clps_writel(intmr2, INTMR2);
-}
-
-static void int2_ack(struct irq_data *d)
-{
- u32 intmr2;
-
- intmr2 = clps_readl(INTMR2);
- intmr2 &= ~(1 << (d->irq - 16));
- clps_writel(intmr2, INTMR2);
-
- switch (d->irq) {
- case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
- }
-}
-
-static void int2_unmask(struct irq_data *d)
-{
- u32 intmr2;
-
- intmr2 = clps_readl(INTMR2);
- intmr2 |= 1 << (d->irq - 16);
- clps_writel(intmr2, INTMR2);
-}
-
-static struct irq_chip int2_chip = {
- .irq_ack = int2_ack,
- .irq_mask = int2_mask,
- .irq_unmask = int2_unmask,
-};
-
-void __init clps711x_init_irq(void)
-{
- unsigned int i;
-
- for (i = 0; i < NR_IRQS; i++) {
- if (INT1_IRQS & (1 << i)) {
- irq_set_chip_and_handler(i, &int1_chip,
- handle_level_irq);
- set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
- }
- if (INT2_IRQS & (1 << i)) {
- irq_set_chip_and_handler(i, &int2_chip,
- handle_level_irq);
- set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
- }
- }
-
- /*
- * Disable interrupts
- */
- clps_writel(0, INTMR1);
- clps_writel(0, INTMR2);
-
- /*
- * Clear down any pending interrupts
- */
- clps_writel(0, COEOI);
- clps_writel(0, TC1EOI);
- clps_writel(0, TC2EOI);
- clps_writel(0, RTCEOI);
- clps_writel(0, TEOI);
- clps_writel(0, UMSEOI);
- clps_writel(0, SYNCIO);
- clps_writel(0, KBDEOI);
-}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-clps711x/Makefile kernel_3.2.14_patched/arch/arm/mach-clps711x/Makefile
--- linux-stable-23d8c3f/arch/arm/mach-clps711x/Makefile 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-clps711x/Makefile 2012-05-16 12:10:46.000000000 +0100
@@ -4,7 +4,7 @@
# Object file lists.
-obj-y := irq.o mm.o time.o
+obj-y := common.o
obj-m :=
obj-n :=
obj- :=
diff -PurN linux-stable-23d8c3f/arch/arm/mach-clps711x/mm.c kernel_3.2.14_patched/arch/arm/mach-clps711x/mm.c
--- linux-stable-23d8c3f/arch/arm/mach-clps711x/mm.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-clps711x/mm.c 1970-01-01 01:00:00.000000000 +0100
@@ -1,48 +0,0 @@
-/*
- * linux/arch/arm/mach-clps711x/mm.c
- *
- * Generic MM setup for the CLPS711x-based machines.
- *
- * Copyright (C) 2001 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-
-#include <asm/sizes.h>
-#include <mach/hardware.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-#include <asm/hardware/clps7111.h>
-
-/*
- * This maps the generic CLPS711x registers
- */
-static struct map_desc clps711x_io_desc[] __initdata = {
- {
- .virtual = CLPS7111_VIRT_BASE,
- .pfn = __phys_to_pfn(CLPS7111_PHYS_BASE),
- .length = SZ_1M,
- .type = MT_DEVICE
- }
-};
-
-void __init clps711x_map_io(void)
-{
- iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
-}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-clps711x/time.c kernel_3.2.14_patched/arch/arm/mach-clps711x/time.c
--- linux-stable-23d8c3f/arch/arm/mach-clps711x/time.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-clps711x/time.c 1970-01-01 01:00:00.000000000 +0100
@@ -1,84 +0,0 @@
-/*
- * linux/arch/arm/mach-clps711x/time.c
- *
- * Copyright (C) 2001 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/timex.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/leds.h>
-#include <asm/hardware/clps7111.h>
-
-#include <asm/mach/time.h>
-
-
-/*
- * gettimeoffset() returns time since last timer tick, in usecs.
- *
- * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
- * 'tick' is usecs per jiffy.
- */
-static unsigned long clps711x_gettimeoffset(void)
-{
- unsigned long hwticks;
- hwticks = LATCH - (clps_readl(TC2D) & 0xffff); /* since last underflow */
- return (hwticks * (tick_nsec / 1000)) / LATCH;
-}
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-p720t_timer_interrupt(int irq, void *dev_id)
-{
- timer_tick();
- return IRQ_HANDLED;
-}
-
-static struct irqaction clps711x_timer_irq = {
- .name = "CLPS711x Timer Tick",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = p720t_timer_interrupt,
-};
-
-static void __init clps711x_timer_init(void)
-{
- struct timespec tv;
- unsigned int syscon;
-
- syscon = clps_readl(SYSCON1);
- syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
- clps_writel(syscon, SYSCON1);
-
- clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
-
- setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
-
- tv.tv_nsec = 0;
- tv.tv_sec = clps_readl(RTCDR);
- do_settimeofday(&tv);
-}
-
-struct sys_timer clps711x_timer = {
- .init = clps711x_timer_init,
- .offset = clps711x_gettimeoffset,
-};
diff -PurN linux-stable-23d8c3f/arch/arm/mach-cns3xxx/cns3420vb.c kernel_3.2.14_patched/arch/arm/mach-cns3xxx/cns3420vb.c
--- linux-stable-23d8c3f/arch/arm/mach-cns3xxx/cns3420vb.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-cns3xxx/cns3420vb.c 2012-05-16 12:10:47.000000000 +0100
@@ -26,6 +26,7 @@
#include <linux/mtd/partitions.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
@@ -201,5 +202,6 @@
.map_io = cns3420_map_io,
.init_irq = cns3xxx_init_irq,
.timer = &cns3xxx_timer,
+ .handle_irq = gic_handle_irq,
.init_machine = cns3420_init,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-cns3xxx/include/mach/entry-macro.S kernel_3.2.14_patched/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
--- linux-stable-23d8c3f/arch/arm/mach-cns3xxx/include/mach/entry-macro.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-cns3xxx/include/mach/entry-macro.S 2012-05-16 12:10:47.000000000 +0100
@@ -8,8 +8,6 @@
* published by the Free Software Foundation.
*/
-#include <asm/hardware/entry-macro-gic.S>
-
.macro disable_fiq
.endm
diff -PurN linux-stable-23d8c3f/arch/arm/mach-cns3xxx/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-cns3xxx/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-cns3xxx/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,11 +0,0 @@
-/*
- * Copyright 2000 Russell King.
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#define VMALLOC_END 0xd8000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/board-da850-evm.c kernel_3.2.14_patched/arch/arm/mach-davinci/board-da850-evm.c
--- linux-stable-23d8c3f/arch/arm/mach-davinci/board-da850-evm.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/board-da850-evm.c 2012-05-16 12:10:47.000000000 +0100
@@ -32,7 +32,6 @@
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/delay.h>
-#include <linux/wl12xx.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -794,11 +793,13 @@
static void da850_panel_power_ctrl(int val)
{
- /* lcd backlight */
- gpio_set_value(DA850_LCD_BL_PIN, val);
-
/* lcd power */
gpio_set_value(DA850_LCD_PWR_PIN, val);
+
+ mdelay(200);
+
+ /* lcd backlight */
+ gpio_set_value(DA850_LCD_BL_PIN, val);
}
static int da850_lcd_hw_init(void)
@@ -818,12 +819,6 @@
gpio_direction_output(DA850_LCD_BL_PIN, 0);
gpio_direction_output(DA850_LCD_PWR_PIN, 0);
- /* Switch off panel power and backlight */
- da850_panel_power_ctrl(0);
-
- /* Switch on panel power and backlight */
- da850_panel_power_ctrl(1);
-
return 0;
}
@@ -1254,6 +1249,17 @@
#define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000)
+#ifdef CONFIG_UIO_PRUSS
+struct uio_pruss_pdata da8xx_pruss_uio_pdata = {
+ .pintc_base = 0x4000,
+};
+
+ ret = da8xx_register_pruss_uio(&da8xx_pruss_uio_pdata);
+ if (ret)
+ pr_warning("%s: pruss_uio initialization failed: %d\n",
+ __func__, ret);
+#endif
+
static __init void da850_evm_init(void)
{
int ret;
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/cpuidle.c kernel_3.2.14_patched/arch/arm/mach-davinci/cpuidle.c
--- linux-stable-23d8c3f/arch/arm/mach-davinci/cpuidle.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/cpuidle.c 2012-05-16 12:10:47.000000000 +0100
@@ -174,4 +174,3 @@
davinci_cpuidle_probe);
}
device_initcall(davinci_cpuidle_init);
-
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/da850.c kernel_3.2.14_patched/arch/arm/mach-davinci/da850.c
--- linux-stable-23d8c3f/arch/arm/mach-davinci/da850.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/da850.c 2012-05-16 12:10:47.000000000 +0100
@@ -240,6 +240,12 @@
.flags = ALWAYS_ENABLED,
};
+static struct clk pruss_clk = {
+ .name = "pruss",
+ .parent = &pll0_sysclk2,
+ .lpsc = DA8XX_LPSC0_PRUSS,
+};
+
static struct clk uart0_clk = {
.name = "uart0",
.parent = &pll0_sysclk2,
@@ -411,6 +417,7 @@
CLK(NULL, "tpcc1", &tpcc1_clk),
CLK(NULL, "tptc2", &tptc2_clk),
CLK(NULL, "uart0", &uart0_clk),
+ CLK(NULL, "pruss", &pruss_clk),
CLK(NULL, "uart1", &uart1_clk),
CLK(NULL, "uart2", &uart2_clk),
CLK(NULL, "aintc", &aintc_clk),
@@ -747,7 +754,7 @@
},
{
.virtual = SRAM_VIRT,
- .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
+ .pfn = __phys_to_pfn(DA8XX_SHARED_RAM_BASE),
.length = SZ_8K,
.type = MT_DEVICE
},
@@ -1119,8 +1126,9 @@
.gpio_irq = IRQ_DA8XX_GPIO0,
.serial_dev = &da8xx_serial_device,
.emac_pdata = &da8xx_emac_pdata,
- .sram_dma = DA8XX_ARM_RAM_BASE,
- .sram_len = SZ_8K,
+ .sram_phys = DA8XX_ARM_RAM_BASE,
+ .sram_dma = DA8XX_SHARED_RAM_BASE,
+ .sram_len = SZ_128K,
.reset_device = &da8xx_wdt_device,
};
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/devices-da8xx.c kernel_3.2.14_patched/arch/arm/mach-davinci/devices-da8xx.c
--- linux-stable-23d8c3f/arch/arm/mach-davinci/devices-da8xx.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/devices-da8xx.c 2012-05-16 12:10:47.000000000 +0100
@@ -519,6 +519,71 @@
}
}
+#define DA8XX_PRUSS_MEM_BASE 0x01C30000
+
+static struct resource da8xx_pruss_resources[] = {
+ {
+ .start = DA8XX_PRUSS_MEM_BASE,
+ .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_DA8XX_EVTOUT0,
+ .end = IRQ_DA8XX_EVTOUT0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = IRQ_DA8XX_EVTOUT1,
+ .end = IRQ_DA8XX_EVTOUT1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = IRQ_DA8XX_EVTOUT2,
+ .end = IRQ_DA8XX_EVTOUT2,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = IRQ_DA8XX_EVTOUT3,
+ .end = IRQ_DA8XX_EVTOUT3,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = IRQ_DA8XX_EVTOUT4,
+ .end = IRQ_DA8XX_EVTOUT4,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = IRQ_DA8XX_EVTOUT5,
+ .end = IRQ_DA8XX_EVTOUT5,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = IRQ_DA8XX_EVTOUT6,
+ .end = IRQ_DA8XX_EVTOUT6,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = IRQ_DA8XX_EVTOUT7,
+ .end = IRQ_DA8XX_EVTOUT7,
+ .flags = IORESOURCE_IRQ,
+ },
+;
+
+static struct platform_device da8xx_pruss_uio_dev = {
+ .name = "pruss_uio",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
+ .resource = da8xx_pruss_resources,
+ .dev = {
+ .coherent_dma_mask = 0xffffffff,
+ }
+};
+
+int __init da8xx_register_pruss_uio(struct uio_pruss_pdata *config)
+{
+ da8xx_pruss_uio_dev.dev.platform_data = config;
+ return platform_device_register(&da8xx_pruss_uio_dev);
+
static const struct display_panel disp_panel = {
QVGA,
16,
@@ -541,6 +606,7 @@
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
+ .fifo_th = 6,
};
struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/dm355.c kernel_3.2.14_patched/arch/arm/mach-davinci/dm355.c
--- linux-stable-23d8c3f/arch/arm/mach-davinci/dm355.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/dm355.c 2012-05-16 12:10:47.000000000 +0100
@@ -27,7 +27,7 @@
#include <mach/time.h>
#include <mach/serial.h>
#include <mach/common.h>
-#include <mach/asp.h>
+#include <asm/hardware/asp.h>
#include <mach/spi.h>
#include <mach/gpio-davinci.h>
@@ -851,7 +851,7 @@
.gpio_num = 104,
.gpio_irq = IRQ_DM355_GPIOBNK0,
.serial_dev = &dm355_serial_device,
- .sram_dma = 0x00010000,
+ .sram_phys = 0x00010000,
.sram_len = SZ_32K,
.reset_device = &davinci_wdt_device,
};
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/dm365.c kernel_3.2.14_patched/arch/arm/mach-davinci/dm365.c
--- linux-stable-23d8c3f/arch/arm/mach-davinci/dm365.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/dm365.c 2012-05-16 12:10:47.000000000 +0100
@@ -30,7 +30,7 @@
#include <mach/time.h>
#include <mach/serial.h>
#include <mach/common.h>
-#include <mach/asp.h>
+#include <asm/hardware/asp.h>
#include <mach/keyscan.h>
#include <mach/spi.h>
#include <mach/gpio-davinci.h>
@@ -1081,7 +1081,7 @@
.gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */
.serial_dev = &dm365_serial_device,
.emac_pdata = &dm365_emac_pdata,
- .sram_dma = 0x00010000,
+ .sram_phys = 0x00010000,
.sram_len = SZ_32K,
.reset_device = &davinci_wdt_device,
};
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/dm644x.c kernel_3.2.14_patched/arch/arm/mach-davinci/dm644x.c
--- linux-stable-23d8c3f/arch/arm/mach-davinci/dm644x.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/dm644x.c 2012-05-16 12:10:47.000000000 +0100
@@ -765,7 +765,7 @@
.gpio_irq = IRQ_GPIOBNK0,
.serial_dev = &dm644x_serial_device,
.emac_pdata = &dm644x_emac_pdata,
- .sram_dma = 0x00008000,
+ .sram_phys = 0x00008000,
.sram_len = SZ_16K,
.reset_device = &davinci_wdt_device,
};
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/dm646x.c kernel_3.2.14_patched/arch/arm/mach-davinci/dm646x.c
--- linux-stable-23d8c3f/arch/arm/mach-davinci/dm646x.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/dm646x.c 2012-05-16 12:10:47.000000000 +0100
@@ -852,7 +852,7 @@
.gpio_irq = IRQ_DM646X_GPIOBNK0,
.serial_dev = &dm646x_serial_device,
.emac_pdata = &dm646x_emac_pdata,
- .sram_dma = 0x10010000,
+ .sram_phys = 0x10010000,
.sram_len = SZ_32K,
.reset_device = &davinci_wdt_device,
};
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/asp.h kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/asp.h
--- linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/asp.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/asp.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,137 +0,0 @@
-/*
- * <mach/asp.h> - DaVinci Audio Serial Port support
- */
-#ifndef __ASM_ARCH_DAVINCI_ASP_H
-#define __ASM_ARCH_DAVINCI_ASP_H
-
-#include <mach/irqs.h>
-#include <mach/edma.h>
-
-/* Bases of dm644x and dm355 register banks */
-#define DAVINCI_ASP0_BASE 0x01E02000
-#define DAVINCI_ASP1_BASE 0x01E04000
-
-/* Bases of dm365 register banks */
-#define DAVINCI_DM365_ASP0_BASE 0x01D02000
-
-/* Bases of dm646x register banks */
-#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
-#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
-
-/* Bases of da850/da830 McASP0 register banks */
-#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
-
-/* Bases of da830 McASP1 register banks */
-#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
-
-/* EDMA channels of dm644x and dm355 */
-#define DAVINCI_DMA_ASP0_TX 2
-#define DAVINCI_DMA_ASP0_RX 3
-#define DAVINCI_DMA_ASP1_TX 8
-#define DAVINCI_DMA_ASP1_RX 9
-
-/* EDMA channels of dm646x */
-#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
-#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
-#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
-
-/* EDMA channels of da850/da830 McASP0 */
-#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
-#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
-
-/* EDMA channels of da830 McASP1 */
-#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
-#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
-
-/* Interrupts */
-#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
-#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
-#define DAVINCI_ASP1_RX_INT IRQ_MBRINT
-#define DAVINCI_ASP1_TX_INT IRQ_MBXINT
-
-struct snd_platform_data {
- u32 tx_dma_offset;
- u32 rx_dma_offset;
- enum dma_event_q asp_chan_q; /* event queue number for ASP channel */
- enum dma_event_q ram_chan_q; /* event queue number for RAM channel */
- unsigned int codec_fmt;
- /*
- * Allowing this is more efficient and eliminates left and right swaps
- * caused by underruns, but will swap the left and right channels
- * when compared to previous behavior.
- */
- unsigned enable_channel_combine:1;
- unsigned sram_size_playback;
- unsigned sram_size_capture;
-
- /*
- * If McBSP peripheral gets the clock from an external pin,
- * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
- * and MCBSP_CLKS.
- * Depending on different hardware connections it is possible
- * to use this setting to change the behaviour of McBSP
- * driver. The dm365_clk_input_pin enum is available for dm365
- */
- int clk_input_pin;
-
- /*
- * This flag works when both clock and FS are outputs for the cpu
- * and makes clock more accurate (FS is not symmetrical and the
- * clock is very fast.
- * The clock becoming faster is named
- * i2s continuous serial clock (I2S_SCK) and it is an externally
- * visible bit clock.
- *
- * first line : WordSelect
- * second line : ContinuousSerialClock
- * third line: SerialData
- *
- * SYMMETRICAL APPROACH:
- * _______________________ LEFT
- * _| RIGHT |______________________|
- * _ _ _ _ _ _ _ _
- * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
- * _ _ _ _ _ _ _ _
- * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
- * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
- *
- * ACCURATE CLOCK APPROACH:
- * ______________ LEFT
- * _| RIGHT |_______________________________|
- * _ _ _ _ _ _ _ _ _
- * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
- * _ _ _ _ dummy cycles
- * _/ \_ ... _/ \_/ \_ ... _/ \__________________
- * \_/ \_/ \_/ \_/
- *
- */
- bool i2s_accurate_sck;
-
- /* McASP specific fields */
- int tdm_slots;
- u8 op_mode;
- u8 num_serializer;
- u8 *serial_dir;
- u8 version;
- u8 txnumevt;
- u8 rxnumevt;
-};
-
-enum {
- MCASP_VERSION_1 = 0, /* DM646x */
- MCASP_VERSION_2, /* DA8xx/OMAPL1x */
-};
-
-enum dm365_clk_input_pin {
- MCBSP_CLKR = 0, /* DM365 */
- MCBSP_CLKS,
-};
-
-#define INACTIVE_MODE 0
-#define TX_MODE 1
-#define RX_MODE 2
-
-#define DAVINCI_MCASP_IIS_MODE 0
-#define DAVINCI_MCASP_DIT_MODE 1
-
-#endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/common.h kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/common.h
--- linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/common.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/common.h 2012-05-16 12:10:47.000000000 +0100
@@ -75,7 +75,7 @@
int gpio_ctlrs_num;
struct platform_device *serial_dev;
struct emac_platform_data *emac_pdata;
- dma_addr_t sram_dma;
+ phys_addr_t sram_phys;
unsigned sram_len;
struct platform_device *reset_device;
void (*reset)(struct platform_device *);
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/da8xx.h kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/da8xx.h
--- linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/da8xx.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/da8xx.h 2012-05-16 12:10:47.000000000 +0100
@@ -16,11 +16,12 @@
#include <linux/platform_device.h>
#include <linux/davinci_emac.h>
#include <linux/spi/spi.h>
+#include <linux/platform_data/uio_pruss.h>
#include <mach/serial.h>
#include <mach/edma.h>
#include <mach/i2c.h>
-#include <mach/asp.h>
+#include <asm/hardware/asp.h>
#include <mach/mmc.h>
#include <mach/usb.h>
#include <mach/pm.h>
@@ -69,6 +70,7 @@
#define DA8XX_AEMIF_CS3_BASE 0x62000000
#define DA8XX_AEMIF_CTL_BASE 0x68000000
#define DA8XX_ARM_RAM_BASE 0xffff0000
+#define DA8XX_SHARED_RAM_BASE 0x80000000
void __init da830_init(void);
void __init da850_init(void);
@@ -81,6 +83,7 @@
int da8xx_register_usb20(unsigned mA, unsigned potpgt);
int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
int da8xx_register_emac(void);
+int da8xx_register_pruss_uio(struct uio_pruss_pdata *config);
int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
int da850_register_mmcsd1(struct davinci_mmc_config *config);
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/dm355.h kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/dm355.h
--- linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/dm355.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/dm355.h 2012-05-16 12:10:47.000000000 +0100
@@ -12,7 +12,7 @@
#define __ASM_ARCH_DM355_H
#include <mach/hardware.h>
-#include <mach/asp.h>
+#include <asm/hardware/asp.h>
#include <media/davinci/vpfe_capture.h>
#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01E10000
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/dm365.h kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/dm365.h
--- linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/dm365.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/dm365.h 2012-05-16 12:10:47.000000000 +0100
@@ -16,7 +16,7 @@
#include <linux/platform_device.h>
#include <linux/davinci_emac.h>
#include <mach/hardware.h>
-#include <mach/asp.h>
+#include <asm/hardware/asp.h>
#include <mach/keyscan.h>
#include <media/davinci/vpfe_capture.h>
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/dm644x.h kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/dm644x.h
--- linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/dm644x.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/dm644x.h 2012-05-16 12:10:47.000000000 +0100
@@ -24,7 +24,7 @@
#include <linux/davinci_emac.h>
#include <mach/hardware.h>
-#include <mach/asp.h>
+#include <asm/hardware/asp.h>
#include <media/davinci/vpfe_capture.h>
#define DM644X_EMAC_BASE (0x01C80000)
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/dm646x.h kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/dm646x.h
--- linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/dm646x.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/dm646x.h 2012-05-16 12:10:47.000000000 +0100
@@ -12,7 +12,7 @@
#define __ASM_ARCH_DM646X_H
#include <mach/hardware.h>
-#include <mach/asp.h>
+#include <asm/hardware/asp.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <linux/davinci_emac.h>
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/io.h kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/io.h
--- linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/io.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/io.h 2012-05-16 12:10:47.000000000 +0100
@@ -21,12 +21,4 @@
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
-#ifndef __ASSEMBLER__
-#define __arch_ioremap davinci_ioremap
-#define __arch_iounmap davinci_iounmap
-
-void __iomem *davinci_ioremap(unsigned long phys, size_t size,
- unsigned int type);
-void davinci_iounmap(volatile void __iomem *addr);
-#endif
#endif /* __ASM_ARCH_IO_H */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/sram.h kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/sram.h
--- linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/sram.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/sram.h 2012-05-16 12:10:47.000000000 +0100
@@ -10,18 +10,11 @@
#ifndef __MACH_SRAM_H
#define __MACH_SRAM_H
+#include <linux/genalloc.h>
+
/* ARBITRARY: SRAM allocations are multiples of this 2^N size */
#define SRAM_GRANULARITY 512
-/*
- * SRAM allocations return a CPU virtual address, or NULL on error.
- * If a DMA address is requested and the SRAM supports DMA, its
- * mapped address is also returned.
- *
- * Errors include SRAM memory not being available, and requesting
- * DMA mapped SRAM on systems which don't allow that.
- */
-extern void *sram_alloc(size_t len, dma_addr_t *dma);
-extern void sram_free(void *addr, size_t len);
+extern struct gen_pool *davinci_gen_pool;
#endif /* __MACH_SRAM_H */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-davinci/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,14 +0,0 @@
-/*
- * DaVinci vmalloc definitions
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <mach/hardware.h>
-
-/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */
-#define VMALLOC_END (IO_VIRT - (2<<20))
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/io.c kernel_3.2.14_patched/arch/arm/mach-davinci/io.c
--- linux-stable-23d8c3f/arch/arm/mach-davinci/io.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/io.c 1970-01-01 01:00:00.000000000 +0100
@@ -1,48 +0,0 @@
-/*
- * DaVinci I/O mapping code
- *
- * Copyright (C) 2005-2006 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/io.h>
-
-#include <asm/tlb.h>
-#include <asm/mach/map.h>
-
-#include <mach/common.h>
-
-/*
- * Intercept ioremap() requests for addresses in our fixed mapping regions.
- */
-void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
-{
- struct map_desc *desc = davinci_soc_info.io_desc;
- int desc_num = davinci_soc_info.io_desc_num;
- int i;
-
- for (i = 0; i < desc_num; i++, desc++) {
- unsigned long iophys = __pfn_to_phys(desc->pfn);
- unsigned long iosize = desc->length;
-
- if (p >= iophys && (p + size) <= (iophys + iosize))
- return __io(desc->virtual + p - iophys);
- }
-
- return __arm_ioremap_caller(p, size, type,
- __builtin_return_address(0));
-}
-EXPORT_SYMBOL(davinci_ioremap);
-
-void davinci_iounmap(volatile void __iomem *addr)
-{
- unsigned long virt = (unsigned long)addr;
-
- if (virt >= VMALLOC_START && virt < VMALLOC_END)
- __iounmap(addr);
-}
-EXPORT_SYMBOL(davinci_iounmap);
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/Makefile kernel_3.2.14_patched/arch/arm/mach-davinci/Makefile
--- linux-stable-23d8c3f/arch/arm/mach-davinci/Makefile 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/Makefile 2012-05-16 12:10:47.000000000 +0100
@@ -4,7 +4,7 @@
#
# Common objects
-obj-y := time.o clock.o serial.o io.o psc.o \
+obj-y := time.o clock.o serial.o psc.o \
dma.o usb.o common.o sram.o aemif.o
obj-$(CONFIG_DAVINCI_MUX) += mux.o
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/pm.c kernel_3.2.14_patched/arch/arm/mach-davinci/pm.c
--- linux-stable-23d8c3f/arch/arm/mach-davinci/pm.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/pm.c 2012-05-16 12:10:47.000000000 +0100
@@ -18,6 +18,7 @@
#include <asm/cacheflush.h>
#include <asm/delay.h>
#include <asm/io.h>
+#include <asm/fncpy.h>
#include <mach/da8xx.h>
#include <mach/sram.h>
@@ -28,14 +29,9 @@
#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
static void (*davinci_sram_suspend) (struct davinci_pm_config *);
+static void *davinci_sram_suspend_mem;
static struct davinci_pm_config *pdata;
-static void davinci_sram_push(void *dest, void *src, unsigned int size)
-{
- memcpy(dest, src, size);
- flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
-}
-
static void davinci_pm_suspend(void)
{
unsigned val;
@@ -124,14 +120,14 @@
return -ENOENT;
}
- davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
- if (!davinci_sram_suspend) {
+ davinci_sram_suspend_mem = (void *)gen_pool_alloc(davinci_gen_pool,
+ davinci_cpu_suspend_sz);
+ if (!davinci_sram_suspend_mem) {
dev_err(&pdev->dev, "cannot allocate SRAM memory\n");
return -ENOMEM;
}
-
- davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
- davinci_cpu_suspend_sz);
+ davinci_sram_suspend = fncpy(davinci_sram_suspend_mem,
+ &davinci_cpu_suspend, davinci_cpu_suspend_sz);
suspend_set_ops(&davinci_pm_ops);
@@ -140,7 +136,8 @@
static int __exit davinci_pm_remove(struct platform_device *pdev)
{
- sram_free(davinci_sram_suspend, davinci_cpu_suspend_sz);
+ gen_pool_free(davinci_gen_pool, (unsigned long)davinci_sram_suspend_mem,
+ davinci_cpu_suspend_sz);
return 0;
}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-davinci/sram.c kernel_3.2.14_patched/arch/arm/mach-davinci/sram.c
--- linux-stable-23d8c3f/arch/arm/mach-davinci/sram.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-davinci/sram.c 2012-05-16 12:10:47.000000000 +0100
@@ -10,40 +10,12 @@
*/
#include <linux/module.h>
#include <linux/init.h>
-#include <linux/genalloc.h>
#include <mach/common.h>
#include <mach/sram.h>
-static struct gen_pool *sram_pool;
-
-void *sram_alloc(size_t len, dma_addr_t *dma)
-{
- unsigned long vaddr;
- dma_addr_t dma_base = davinci_soc_info.sram_dma;
-
- if (dma)
- *dma = 0;
- if (!sram_pool || (dma && !dma_base))
- return NULL;
-
- vaddr = gen_pool_alloc(sram_pool, len);
- if (!vaddr)
- return NULL;
-
- if (dma)
- *dma = dma_base + (vaddr - SRAM_VIRT);
- return (void *)vaddr;
-
-}
-EXPORT_SYMBOL(sram_alloc);
-
-void sram_free(void *addr, size_t len)
-{
- gen_pool_free(sram_pool, (unsigned long) addr, len);
-}
-EXPORT_SYMBOL(sram_free);
-
+struct gen_pool *davinci_gen_pool;
+EXPORT_SYMBOL_GPL(davinci_gen_pool);
/*
* REVISIT This supports CPU and DMA access to/from SRAM, but it
@@ -54,18 +26,19 @@
static int __init sram_init(void)
{
unsigned len = davinci_soc_info.sram_len;
- int status = 0;
- if (len) {
- len = min_t(unsigned, len, SRAM_SIZE);
- sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1);
- if (!sram_pool)
- status = -ENOMEM;
- }
- if (sram_pool)
- status = gen_pool_add(sram_pool, SRAM_VIRT, len, -1);
- WARN_ON(status < 0);
- return status;
+ if (!len)
+ return 0;
+
+ len = min_t(unsigned, len, SRAM_SIZE);
+ davinci_gen_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1);
+
+ if (!davinci_gen_pool)
+ return -ENOMEM;
+
+ WARN_ON(gen_pool_add_virt(davinci_gen_pool, SRAM_VIRT,
+ davinci_soc_info.sram_phys, len, -1));
+
+ return 0;
}
core_initcall(sram_init);
-
diff -PurN linux-stable-23d8c3f/arch/arm/mach-dove/include/mach/dove.h kernel_3.2.14_patched/arch/arm/mach-dove/include/mach/dove.h
--- linux-stable-23d8c3f/arch/arm/mach-dove/include/mach/dove.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-dove/include/mach/dove.h 2012-05-16 12:10:47.000000000 +0100
@@ -11,8 +11,6 @@
#ifndef __ASM_ARCH_DOVE_H
#define __ASM_ARCH_DOVE_H
-#include <mach/vmalloc.h>
-
/*
* Marvell Dove address maps.
*
diff -PurN linux-stable-23d8c3f/arch/arm/mach-dove/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-dove/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-dove/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-dove/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/vmalloc.h
- */
-
-#define VMALLOC_END 0xfd800000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ebsa110/core.c kernel_3.2.14_patched/arch/arm/mach-ebsa110/core.c
--- linux-stable-23d8c3f/arch/arm/mach-ebsa110/core.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ebsa110/core.c 2012-05-16 12:10:47.000000000 +0100
@@ -283,7 +283,7 @@
.atag_offset = 0x400,
.reserve_lp0 = 1,
.reserve_lp2 = 1,
- .soft_reboot = 1,
+ .restart_mode = 's',
.map_io = ebsa110_map_io,
.init_irq = ebsa110_init_irq,
.timer = &ebsa110_timer,
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ebsa110/include/mach/system.h kernel_3.2.14_patched/arch/arm/mach-ebsa110/include/mach/system.h
--- linux-stable-23d8c3f/arch/arm/mach-ebsa110/include/mach/system.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ebsa110/include/mach/system.h 2012-05-16 12:10:47.000000000 +0100
@@ -34,6 +34,6 @@
asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
}
-#define arch_reset(mode, cmd) cpu_reset(0x80000000)
+#define arch_reset(mode, cmd) soft_restart(0x80000000)
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ebsa110/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-ebsa110/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-ebsa110/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ebsa110/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,10 +0,0 @@
-/*
- * arch/arm/mach-ebsa110/include/mach/vmalloc.h
- *
- * Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END 0xdf000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ep93xx/adssphere.c kernel_3.2.14_patched/arch/arm/mach-ep93xx/adssphere.c
--- linux-stable-23d8c3f/arch/arm/mach-ep93xx/adssphere.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ep93xx/adssphere.c 2012-05-16 12:10:47.000000000 +0100
@@ -16,6 +16,7 @@
#include <mach/hardware.h>
+#include <asm/hardware/vic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -36,6 +37,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = adssphere_init_machine,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ep93xx/edb93xx.c kernel_3.2.14_patched/arch/arm/mach-ep93xx/edb93xx.c
--- linux-stable-23d8c3f/arch/arm/mach-ep93xx/edb93xx.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ep93xx/edb93xx.c 2012-05-16 12:10:47.000000000 +0100
@@ -39,6 +39,7 @@
#include <mach/ep93xx_spi.h>
#include <mach/gpio-ep93xx.h>
+#include <asm/hardware/vic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -250,6 +251,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine,
MACHINE_END
@@ -261,6 +263,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine,
MACHINE_END
@@ -272,6 +275,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine,
MACHINE_END
@@ -283,6 +287,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine,
MACHINE_END
@@ -294,6 +299,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine,
MACHINE_END
@@ -305,6 +311,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine,
MACHINE_END
@@ -316,6 +323,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine,
MACHINE_END
@@ -327,6 +335,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = edb93xx_init_machine,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ep93xx/gesbc9312.c kernel_3.2.14_patched/arch/arm/mach-ep93xx/gesbc9312.c
--- linux-stable-23d8c3f/arch/arm/mach-ep93xx/gesbc9312.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ep93xx/gesbc9312.c 2012-05-16 12:10:47.000000000 +0100
@@ -16,6 +16,7 @@
#include <mach/hardware.h>
+#include <asm/hardware/vic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -36,6 +37,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = gesbc9312_init_machine,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ep93xx/include/mach/entry-macro.S kernel_3.2.14_patched/arch/arm/mach-ep93xx/include/mach/entry-macro.S
--- linux-stable-23d8c3f/arch/arm/mach-ep93xx/include/mach/entry-macro.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ep93xx/include/mach/entry-macro.S 2012-05-16 12:10:47.000000000 +0100
@@ -9,51 +9,9 @@
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*/
-#include <mach/ep93xx-regs.h>
.macro disable_fiq
.endm
- .macro get_irqnr_preamble, base, tmp
- .endm
-
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \base, =(EP93XX_AHB_VIRT_BASE)
- orr \base, \base, #0x000b0000
- mov \irqnr, #0
- ldr \irqstat, [\base] @ lower 32 interrupts
- cmp \irqstat, #0
- bne 1001f
-
- eor \base, \base, #0x00070000
- ldr \irqstat, [\base] @ upper 32 interrupts
- cmp \irqstat, #0
- beq 1002f
- mov \irqnr, #0x20
-
-1001:
- movs \tmp, \irqstat, lsl #16
- movne \irqstat, \tmp
- addeq \irqnr, \irqnr, #16
-
- movs \tmp, \irqstat, lsl #8
- movne \irqstat, \tmp
- addeq \irqnr, \irqnr, #8
-
- movs \tmp, \irqstat, lsl #4
- movne \irqstat, \tmp
- addeq \irqnr, \irqnr, #4
-
- movs \tmp, \irqstat, lsl #2
- movne \irqstat, \tmp
- addeq \irqnr, \irqnr, #2
-
- movs \tmp, \irqstat, lsl #1
- addeq \irqnr, \irqnr, #1
- orrs \base, \base, #1
-
-1002:
- .endm
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ep93xx/include/mach/system.h kernel_3.2.14_patched/arch/arm/mach-ep93xx/include/mach/system.h
--- linux-stable-23d8c3f/arch/arm/mach-ep93xx/include/mach/system.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ep93xx/include/mach/system.h 2012-05-16 12:10:47.000000000 +0100
@@ -11,8 +11,6 @@
static inline void arch_reset(char mode, const char *cmd)
{
- local_irq_disable();
-
/*
* Set then clear the SWRST bit to initiate a software reset
*/
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ep93xx/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-ep93xx/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-ep93xx/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ep93xx/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/vmalloc.h
- */
-
-#define VMALLOC_END 0xfe800000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ep93xx/micro9.c kernel_3.2.14_patched/arch/arm/mach-ep93xx/micro9.c
--- linux-stable-23d8c3f/arch/arm/mach-ep93xx/micro9.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ep93xx/micro9.c 2012-05-16 12:10:47.000000000 +0100
@@ -18,6 +18,7 @@
#include <mach/hardware.h>
+#include <asm/hardware/vic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -80,6 +81,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = micro9_init_machine,
MACHINE_END
@@ -91,6 +93,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = micro9_init_machine,
MACHINE_END
@@ -102,6 +105,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = micro9_init_machine,
MACHINE_END
@@ -113,6 +117,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = micro9_init_machine,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ep93xx/simone.c kernel_3.2.14_patched/arch/arm/mach-ep93xx/simone.c
--- linux-stable-23d8c3f/arch/arm/mach-ep93xx/simone.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ep93xx/simone.c 2012-05-16 12:10:47.000000000 +0100
@@ -25,6 +25,7 @@
#include <mach/fb.h>
#include <mach/gpio-ep93xx.h>
+#include <asm/hardware/vic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -80,6 +81,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = simone_init_machine,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ep93xx/snappercl15.c kernel_3.2.14_patched/arch/arm/mach-ep93xx/snappercl15.c
--- linux-stable-23d8c3f/arch/arm/mach-ep93xx/snappercl15.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ep93xx/snappercl15.c 2012-05-16 12:10:47.000000000 +0100
@@ -31,6 +31,7 @@
#include <mach/fb.h>
#include <mach/gpio-ep93xx.h>
+#include <asm/hardware/vic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -177,6 +178,7 @@
.atag_offset = 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = snappercl15_init_machine,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ep93xx/ts72xx.c kernel_3.2.14_patched/arch/arm/mach-ep93xx/ts72xx.c
--- linux-stable-23d8c3f/arch/arm/mach-ep93xx/ts72xx.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ep93xx/ts72xx.c 2012-05-16 12:10:47.000000000 +0100
@@ -23,6 +23,7 @@
#include <mach/hardware.h>
#include <mach/ts72xx.h>
+#include <asm/hardware/vic.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
@@ -247,6 +248,7 @@
.atag_offset = 0x100,
.map_io = ts72xx_map_io,
.init_irq = ep93xx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = ts72xx_init_machine,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-exynos/cpu.c kernel_3.2.14_patched/arch/arm/mach-exynos/cpu.c
--- linux-stable-23d8c3f/arch/arm/mach-exynos/cpu.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-exynos/cpu.c 2012-05-16 12:10:47.000000000 +0100
@@ -15,6 +15,7 @@
#include <asm/mach/irq.h>
#include <asm/proc-fns.h>
+#include <asm/exception.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
@@ -33,8 +34,6 @@
#include <mach/regs-irq.h>
#include <mach/regs-pmu.h>
-unsigned int gic_bank_offset __read_mostly;
-
extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
unsigned int irq_start);
extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
@@ -202,27 +201,14 @@
exynos4_setup_clocks();
}
-static void exynos4_gic_irq_fix_base(struct irq_data *d)
-{
- struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-
- gic_data->cpu_base = S5P_VA_GIC_CPU +
- (gic_bank_offset * smp_processor_id());
-
- gic_data->dist_base = S5P_VA_GIC_DIST +
- (gic_bank_offset * smp_processor_id());
-}
-
void __init exynos4_init_irq(void)
{
int irq;
+ unsigned int gic_bank_offset;
gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
- gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
- gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
- gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
- gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
+ gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
diff -PurN linux-stable-23d8c3f/arch/arm/mach-exynos/include/mach/entry-macro.S kernel_3.2.14_patched/arch/arm/mach-exynos/include/mach/entry-macro.S
--- linux-stable-23d8c3f/arch/arm/mach-exynos/include/mach/entry-macro.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-exynos/include/mach/entry-macro.S 2012-05-16 12:10:47.000000000 +0100
@@ -9,83 +9,8 @@
* warranty of any kind, whether express or implied.
*/
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/hardware/gic.h>
-
.macro disable_fiq
.endm
- .macro get_irqnr_preamble, base, tmp
- mov \tmp, #0
-
- mrc p15, 0, \base, c0, c0, 5
- and \base, \base, #3
- cmp \base, #0
- beq 1f
-
- ldr \tmp, =gic_bank_offset
- ldr \tmp, [\tmp]
- cmp \base, #1
- beq 1f
-
- cmp \base, #2
- addeq \tmp, \tmp, \tmp
- addne \tmp, \tmp, \tmp, LSL #1
-
-1: ldr \base, =gic_cpu_base_addr
- ldr \base, [\base]
- add \base, \base, \tmp
- .endm
-
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an interrupt if it's
- * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
- *
- * A simple read from the controller will tell us the number of the highest
- * priority enabled interrupt. We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
- ldr \tmp, =1021
-
- bic \irqnr, \irqstat, #0x1c00
-
- cmp \irqnr, #15
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
- addne \irqnr, \irqnr, #32
-
- .endm
-
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- cmpcs \irqnr, \irqnr
- .endm
diff -PurN linux-stable-23d8c3f/arch/arm/mach-exynos/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-exynos/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-exynos/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-exynos/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * EXYNOS4 vmalloc definition
-*/
-
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H __FILE__
-
-#define VMALLOC_END 0xF6000000UL
-
-#endif /* __ASM_ARCH_VMALLOC_H */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-exynos/mach-armlex4210.c kernel_3.2.14_patched/arch/arm/mach-exynos/mach-armlex4210.c
--- linux-stable-23d8c3f/arch/arm/mach-exynos/mach-armlex4210.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-exynos/mach-armlex4210.c 2012-05-16 12:10:47.000000000 +0100
@@ -16,6 +16,7 @@
#include <linux/smsc911x.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <plat/cpu.h>
@@ -210,6 +211,7 @@
.atag_offset = 0x100,
.init_irq = exynos4_init_irq,
.map_io = armlex4210_map_io,
+ .handle_irq = gic_handle_irq,
.init_machine = armlex4210_machine_init,
.timer = &exynos4_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-exynos/mach-nuri.c kernel_3.2.14_patched/arch/arm/mach-exynos/mach-nuri.c
--- linux-stable-23d8c3f/arch/arm/mach-exynos/mach-nuri.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-exynos/mach-nuri.c 2012-05-16 12:10:47.000000000 +0100
@@ -32,6 +32,7 @@
#include <media/v4l2-mediabus.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <plat/adc.h>
@@ -1333,6 +1334,7 @@
.atag_offset = 0x100,
.init_irq = exynos4_init_irq,
.map_io = nuri_map_io,
+ .handle_irq = gic_handle_irq,
.init_machine = nuri_machine_init,
.timer = &exynos4_timer,
.reserve = &nuri_reserve,
diff -PurN linux-stable-23d8c3f/arch/arm/mach-exynos/mach-origen.c kernel_3.2.14_patched/arch/arm/mach-exynos/mach-origen.c
--- linux-stable-23d8c3f/arch/arm/mach-exynos/mach-origen.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-exynos/mach-origen.c 2012-05-16 12:10:47.000000000 +0100
@@ -22,6 +22,7 @@
#include <linux/lcd.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <video/platform_lcd.h>
@@ -694,6 +695,7 @@
.atag_offset = 0x100,
.init_irq = exynos4_init_irq,
.map_io = origen_map_io,
+ .handle_irq = gic_handle_irq,
.init_machine = origen_machine_init,
.timer = &exynos4_timer,
.reserve = &origen_reserve,
diff -PurN linux-stable-23d8c3f/arch/arm/mach-exynos/mach-smdk4x12.c kernel_3.2.14_patched/arch/arm/mach-exynos/mach-smdk4x12.c
--- linux-stable-23d8c3f/arch/arm/mach-exynos/mach-smdk4x12.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-exynos/mach-smdk4x12.c 2012-05-16 12:10:47.000000000 +0100
@@ -21,6 +21,7 @@
#include <linux/serial_core.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <plat/backlight.h>
@@ -287,6 +288,7 @@
.atag_offset = 0x100,
.init_irq = exynos4_init_irq,
.map_io = smdk4x12_map_io,
+ .handle_irq = gic_handle_irq,
.init_machine = smdk4x12_machine_init,
.timer = &exynos4_timer,
MACHINE_END
@@ -297,6 +299,7 @@
.atag_offset = 0x100,
.init_irq = exynos4_init_irq,
.map_io = smdk4x12_map_io,
+ .handle_irq = gic_handle_irq,
.init_machine = smdk4x12_machine_init,
.timer = &exynos4_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-exynos/mach-smdkv310.c kernel_3.2.14_patched/arch/arm/mach-exynos/mach-smdkv310.c
--- linux-stable-23d8c3f/arch/arm/mach-exynos/mach-smdkv310.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-exynos/mach-smdkv310.c 2012-05-16 12:10:47.000000000 +0100
@@ -21,6 +21,7 @@
#include <linux/pwm_backlight.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <video/platform_lcd.h>
@@ -375,6 +376,7 @@
.atag_offset = 0x100,
.init_irq = exynos4_init_irq,
.map_io = smdkv310_map_io,
+ .handle_irq = gic_handle_irq,
.init_machine = smdkv310_machine_init,
.timer = &exynos4_timer,
.reserve = &smdkv310_reserve,
@@ -385,6 +387,7 @@
.atag_offset = 0x100,
.init_irq = exynos4_init_irq,
.map_io = smdkv310_map_io,
+ .handle_irq = gic_handle_irq,
.init_machine = smdkv310_machine_init,
.timer = &exynos4_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-exynos/mach-universal_c210.c kernel_3.2.14_patched/arch/arm/mach-exynos/mach-universal_c210.c
--- linux-stable-23d8c3f/arch/arm/mach-exynos/mach-universal_c210.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-exynos/mach-universal_c210.c 2012-05-16 12:10:47.000000000 +0100
@@ -24,6 +24,7 @@
#include <linux/i2c/atmel_mxt_ts.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
@@ -1058,6 +1059,7 @@
.atag_offset = 0x100,
.init_irq = exynos4_init_irq,
.map_io = universal_map_io,
+ .handle_irq = gic_handle_irq,
.init_machine = universal_machine_init,
.timer = &exynos4_timer,
.reserve = &universal_reserve,
diff -PurN linux-stable-23d8c3f/arch/arm/mach-exynos/platsmp.c kernel_3.2.14_patched/arch/arm/mach-exynos/platsmp.c
--- linux-stable-23d8c3f/arch/arm/mach-exynos/platsmp.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-exynos/platsmp.c 2012-05-16 12:10:47.000000000 +0100
@@ -32,7 +32,6 @@
#include <plat/cpu.h>
-extern unsigned int gic_bank_offset;
extern void exynos4_secondary_startup(void);
#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
@@ -65,31 +64,6 @@
static DEFINE_SPINLOCK(boot_lock);
-static void __cpuinit exynos4_gic_secondary_init(void)
-{
- void __iomem *dist_base = S5P_VA_GIC_DIST +
- (gic_bank_offset * smp_processor_id());
- void __iomem *cpu_base = S5P_VA_GIC_CPU +
- (gic_bank_offset * smp_processor_id());
- int i;
-
- /*
- * Deal with the banked PPI and SGI interrupts - disable all
- * PPI interrupts, ensure all SGI interrupts are enabled.
- */
- __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
- __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
-
- /*
- * Set priority on PPI and SGI interrupts
- */
- for (i = 0; i < 32; i += 4)
- __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
-
- __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
- __raw_writel(1, cpu_base + GIC_CPU_CTRL);
-}
-
void __cpuinit platform_secondary_init(unsigned int cpu)
{
/*
@@ -97,7 +71,7 @@
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
- exynos4_gic_secondary_init();
+ gic_secondary_init(0);
/*
* let the primary processor know we're out of the
diff -PurN linux-stable-23d8c3f/arch/arm/mach-footbridge/cats-hw.c kernel_3.2.14_patched/arch/arm/mach-footbridge/cats-hw.c
--- linux-stable-23d8c3f/arch/arm/mach-footbridge/cats-hw.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-footbridge/cats-hw.c 2012-05-16 12:10:47.000000000 +0100
@@ -86,7 +86,7 @@
MACHINE_START(CATS, "Chalice-CATS")
/* Maintainer: Philip Blundell */
.atag_offset = 0x100,
- .soft_reboot = 1,
+ .restart_mode = 's',
.fixup = fixup_cats,
.map_io = footbridge_map_io,
.init_irq = footbridge_init_irq,
diff -PurN linux-stable-23d8c3f/arch/arm/mach-footbridge/include/mach/system.h kernel_3.2.14_patched/arch/arm/mach-footbridge/include/mach/system.h
--- linux-stable-23d8c3f/arch/arm/mach-footbridge/include/mach/system.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-footbridge/include/mach/system.h 2012-05-16 12:10:47.000000000 +0100
@@ -24,7 +24,7 @@
/*
* Jump into the ROM
*/
- cpu_reset(0x41000000);
+ soft_restart(0x41000000);
} else {
if (machine_is_netwinder()) {
/* open up the SuperIO chip
diff -PurN linux-stable-23d8c3f/arch/arm/mach-footbridge/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-footbridge/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-footbridge/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-footbridge/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,10 +0,0 @@
-/*
- * arch/arm/mach-footbridge/include/mach/vmalloc.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-
-#define VMALLOC_END 0xf0000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-gemini/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-gemini/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-gemini/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-gemini/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,10 +0,0 @@
-/*
- * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#define VMALLOC_END 0xf0000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-h720x/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-h720x/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-h720x/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-h720x/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,10 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/vmalloc.h
- */
-
-#ifndef __ARCH_ARM_VMALLOC_H
-#define __ARCH_ARM_VMALLOC_H
-
-#define VMALLOC_END 0xd0000000UL
-
-#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-highbank/highbank.c kernel_3.2.14_patched/arch/arm/mach-highbank/highbank.c
--- linux-stable-23d8c3f/arch/arm/mach-highbank/highbank.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-highbank/highbank.c 2012-05-16 12:10:47.000000000 +0100
@@ -144,6 +144,7 @@
.map_io = highbank_map_io,
.init_irq = highbank_init_irq,
.timer = &highbank_timer,
+ .handle_irq = gic_handle_irq,
.init_machine = highbank_init,
.dt_compat = highbank_match,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-highbank/include/mach/entry-macro.S kernel_3.2.14_patched/arch/arm/mach-highbank/include/mach/entry-macro.S
--- linux-stable-23d8c3f/arch/arm/mach-highbank/include/mach/entry-macro.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-highbank/include/mach/entry-macro.S 2012-05-16 12:10:47.000000000 +0100
@@ -1,5 +1,3 @@
-#include <asm/hardware/entry-macro-gic.S>
-
.macro disable_fiq
.endm
diff -PurN linux-stable-23d8c3f/arch/arm/mach-highbank/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-highbank/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-highbank/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-highbank/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1 +0,0 @@
-#define VMALLOC_END 0xFEE00000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-integrator/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-integrator/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-integrator/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-integrator/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-integrator/include/mach/vmalloc.h
- *
- * Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END 0xd0000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-iop13xx/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-iop13xx/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-iop13xx/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-iop13xx/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,4 +0,0 @@
-#ifndef _VMALLOC_H_
-#define _VMALLOC_H_
-#define VMALLOC_END 0xfa000000UL
-#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-iop32x/include/mach/io.h kernel_3.2.14_patched/arch/arm/mach-iop32x/include/mach/io.h
--- linux-stable-23d8c3f/arch/arm/mach-iop32x/include/mach/io.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-iop32x/include/mach/io.h 2012-05-16 12:10:47.000000000 +0100
@@ -13,15 +13,8 @@
#include <asm/hardware/iop3xx.h>
-extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
- unsigned int mtype);
-extern void __iop3xx_iounmap(void __iomem *addr);
-
#define IO_SPACE_LIMIT 0xffffffff
#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
#define __mem_pci(a) (a)
-#define __arch_ioremap __iop3xx_ioremap
-#define __arch_iounmap __iop3xx_iounmap
-
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-iop32x/include/mach/system.h kernel_3.2.14_patched/arch/arm/mach-iop32x/include/mach/system.h
--- linux-stable-23d8c3f/arch/arm/mach-iop32x/include/mach/system.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-iop32x/include/mach/system.h 2012-05-16 12:10:47.000000000 +0100
@@ -18,8 +18,6 @@
static inline void arch_reset(char mode, const char *cmd)
{
- local_irq_disable();
-
if (machine_is_n2100()) {
gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
@@ -30,5 +28,5 @@
*IOP3XX_PCSR = 0x30;
/* Jump into ROM at address 0 */
- cpu_reset(0);
+ soft_restart(0);
}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-iop32x/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-iop32x/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-iop32x/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-iop32x/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-iop32x/include/mach/vmalloc.h
- */
-
-#define VMALLOC_END 0xfe000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-iop33x/include/mach/io.h kernel_3.2.14_patched/arch/arm/mach-iop33x/include/mach/io.h
--- linux-stable-23d8c3f/arch/arm/mach-iop33x/include/mach/io.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-iop33x/include/mach/io.h 2012-05-16 12:10:47.000000000 +0100
@@ -13,15 +13,8 @@
#include <asm/hardware/iop3xx.h>
-extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
- unsigned int mtype);
-extern void __iop3xx_iounmap(void __iomem *addr);
-
#define IO_SPACE_LIMIT 0xffffffff
#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
#define __mem_pci(a) (a)
-#define __arch_ioremap __iop3xx_ioremap
-#define __arch_iounmap __iop3xx_iounmap
-
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-iop33x/include/mach/system.h kernel_3.2.14_patched/arch/arm/mach-iop33x/include/mach/system.h
--- linux-stable-23d8c3f/arch/arm/mach-iop33x/include/mach/system.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-iop33x/include/mach/system.h 2012-05-16 12:10:47.000000000 +0100
@@ -19,5 +19,5 @@
*IOP3XX_PCSR = 0x30;
/* Jump into ROM at address 0 */
- cpu_reset(0);
+ soft_restart(0);
}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-iop33x/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-iop33x/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-iop33x/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-iop33x/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-iop33x/include/mach/vmalloc.h
- */
-
-#define VMALLOC_END 0xfe000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ixp2000/include/mach/system.h kernel_3.2.14_patched/arch/arm/mach-ixp2000/include/mach/system.h
--- linux-stable-23d8c3f/arch/arm/mach-ixp2000/include/mach/system.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ixp2000/include/mach/system.h 2012-05-16 12:10:47.000000000 +0100
@@ -19,8 +19,6 @@
static inline void arch_reset(char mode, const char *cmd)
{
- local_irq_disable();
-
/*
* Reset flash banking register so that we are pointing at
* RedBoot bank.
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ixp2000/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-ixp2000/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-ixp2000/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ixp2000/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/vmalloc.h
- *
- * Author: Naeem Afzal <naeem.m.afzal@intel.com>
- *
- * Copyright 2002 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts. That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-#define VMALLOC_END 0xfb000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ixp23xx/include/mach/io.h kernel_3.2.14_patched/arch/arm/mach-ixp23xx/include/mach/io.h
--- linux-stable-23d8c3f/arch/arm/mach-ixp23xx/include/mach/io.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ixp23xx/include/mach/io.h 2012-05-16 12:10:47.000000000 +0100
@@ -20,33 +20,4 @@
#define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
#define __mem_pci(a) (a)
-static inline void __iomem *
-ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype)
-{
- if (addr >= IXP23XX_PCI_MEM_START &&
- addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) {
- if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE)
- return NULL;
-
- return (void __iomem *)
- ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT);
- }
-
- return __arm_ioremap(addr, size, mtype);
-}
-
-static inline void
-ixp23xx_iounmap(void __iomem *addr)
-{
- if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) &&
- (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE))
- return;
-
- __iounmap(addr);
-}
-
-#define __arch_ioremap ixp23xx_ioremap
-#define __arch_iounmap ixp23xx_iounmap
-
-
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ixp23xx/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-ixp23xx/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ixp23xx/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,10 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/vmalloc.h
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- * NPU mappings end at 0xf0000000 and we allocate 64MB for board
- * specific static I/O.
- */
-
-#define VMALLOC_END (0xec000000UL)
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ixp4xx/include/mach/system.h kernel_3.2.14_patched/arch/arm/mach-ixp4xx/include/mach/system.h
--- linux-stable-23d8c3f/arch/arm/mach-ixp4xx/include/mach/system.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ixp4xx/include/mach/system.h 2012-05-16 12:10:47.000000000 +0100
@@ -26,7 +26,7 @@
{
if ( 1 && mode == 's') {
/* Jump into ROM at address 0 */
- cpu_reset(0);
+ soft_restart(0);
} else {
/* Use on-chip reset capability */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ixp4xx/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-ixp4xx/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ixp4xx/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/vmalloc.h
- */
-#define VMALLOC_END (0xff000000UL)
-
diff -PurN linux-stable-23d8c3f/arch/arm/mach-kirkwood/include/mach/io.h kernel_3.2.14_patched/arch/arm/mach-kirkwood/include/mach/io.h
--- linux-stable-23d8c3f/arch/arm/mach-kirkwood/include/mach/io.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-kirkwood/include/mach/io.h 2012-05-16 12:10:47.000000000 +0100
@@ -19,31 +19,6 @@
+ KIRKWOOD_PCIE_IO_VIRT_BASE);
}
-static inline void __iomem *
-__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
-{
- void __iomem *retval;
- unsigned long offs = paddr - KIRKWOOD_REGS_PHYS_BASE;
- if (mtype == MT_DEVICE && size && offs < KIRKWOOD_REGS_SIZE &&
- size <= KIRKWOOD_REGS_SIZE && offs + size <= KIRKWOOD_REGS_SIZE) {
- retval = (void __iomem *)KIRKWOOD_REGS_VIRT_BASE + offs;
- } else {
- retval = __arm_ioremap(paddr, size, mtype);
- }
-
- return retval;
-}
-
-static inline void
-__arch_iounmap(void __iomem *addr)
-{
- if (addr < (void __iomem *)KIRKWOOD_REGS_VIRT_BASE ||
- addr >= (void __iomem *)(KIRKWOOD_REGS_VIRT_BASE + KIRKWOOD_REGS_SIZE))
- __iounmap(addr);
-}
-
-#define __arch_ioremap __arch_ioremap
-#define __arch_iounmap __arch_iounmap
#define __io(a) __io(a)
#define __mem_pci(a) (a)
diff -PurN linux-stable-23d8c3f/arch/arm/mach-kirkwood/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-kirkwood/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-kirkwood/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-kirkwood/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/vmalloc.h
- */
-
-#define VMALLOC_END 0xfe800000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ks8695/include/mach/system.h kernel_3.2.14_patched/arch/arm/mach-ks8695/include/mach/system.h
--- linux-stable-23d8c3f/arch/arm/mach-ks8695/include/mach/system.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ks8695/include/mach/system.h 2012-05-16 12:10:47.000000000 +0100
@@ -32,7 +32,7 @@
unsigned int reg;
if (mode == 's')
- cpu_reset(0);
+ soft_restart(0);
/* disable timer0 */
reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
diff -PurN linux-stable-23d8c3f/arch/arm/mach-ks8695/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-ks8695/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-ks8695/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-ks8695/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-ks8695/include/mach/vmalloc.h
- *
- * Copyright (C) 2006 Ben Dooks
- * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk>
- *
- * KS8695 vmalloc definition
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-
-#define VMALLOC_END (KS8695_IO_VA & PGDIR_MASK)
-
-#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-lpc32xx/include/mach/system.h kernel_3.2.14_patched/arch/arm/mach-lpc32xx/include/mach/system.h
--- linux-stable-23d8c3f/arch/arm/mach-lpc32xx/include/mach/system.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-lpc32xx/include/mach/system.h 2012-05-16 12:10:47.000000000 +0100
@@ -33,9 +33,6 @@
case 'h':
printk(KERN_CRIT "RESET: Rebooting system\n");
- /* Disable interrupts */
- local_irq_disable();
-
lpc32xx_watchdog_reset();
break;
diff -PurN linux-stable-23d8c3f/arch/arm/mach-lpc32xx/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-lpc32xx/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-lpc32xx/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-lpc32xx/include/mach/vmalloc.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-
-#define VMALLOC_END 0xF0000000UL
-
-#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-mmp/include/mach/system.h kernel_3.2.14_patched/arch/arm/mach-mmp/include/mach/system.h
--- linux-stable-23d8c3f/arch/arm/mach-mmp/include/mach/system.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-mmp/include/mach/system.h 2012-05-16 12:10:47.000000000 +0100
@@ -19,8 +19,8 @@
static inline void arch_reset(char mode, const char *cmd)
{
if (cpu_is_pxa168())
- cpu_reset(0xffff0000);
+ soft_restart(0xffff0000);
else
- cpu_reset(0);
+ soft_restart(0);
}
#endif /* __ASM_MACH_SYSTEM_H */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-mmp/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-mmp/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-mmp/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-mmp/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,5 +0,0 @@
-/*
- * linux/arch/arm/mach-mmp/include/mach/vmalloc.h
- */
-
-#define VMALLOC_END 0xfe000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-msm/board-msm8960.c kernel_3.2.14_patched/arch/arm/mach-msm/board-msm8960.c
--- linux-stable-23d8c3f/arch/arm/mach-msm/board-msm8960.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-msm/board-msm8960.c 2012-05-16 12:10:47.000000000 +0100
@@ -99,6 +99,7 @@
.map_io = msm8960_map_io,
.init_irq = msm8960_init_irq,
.timer = &msm_timer,
+ .handle_irq = gic_handle_irq,
.init_machine = msm8960_sim_init,
MACHINE_END
@@ -108,6 +109,7 @@
.map_io = msm8960_map_io,
.init_irq = msm8960_init_irq,
.timer = &msm_timer,
+ .handle_irq = gic_handle_irq,
.init_machine = msm8960_rumi3_init,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-msm/board-msm8x60.c kernel_3.2.14_patched/arch/arm/mach-msm/board-msm8x60.c
--- linux-stable-23d8c3f/arch/arm/mach-msm/board-msm8x60.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-msm/board-msm8x60.c 2012-05-16 12:10:47.000000000 +0100
@@ -108,6 +108,7 @@
.reserve = msm8x60_reserve,
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
+ .handle_irq = gic_handle_irq,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END
@@ -117,6 +118,7 @@
.reserve = msm8x60_reserve,
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
+ .handle_irq = gic_handle_irq,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END
@@ -126,6 +128,7 @@
.reserve = msm8x60_reserve,
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
+ .handle_irq = gic_handle_irq,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END
@@ -135,6 +138,7 @@
.reserve = msm8x60_reserve,
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
+ .handle_irq = gic_handle_irq,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-msm/include/mach/entry-macro-qgic.S kernel_3.2.14_patched/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
--- linux-stable-23d8c3f/arch/arm/mach-msm/include/mach/entry-macro-qgic.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-msm/include/mach/entry-macro-qgic.S 1970-01-01 01:00:00.000000000 +0100
@@ -1,17 +0,0 @@
-/*
- * Low-level IRQ helper macros
- *
- * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/entry-macro-gic.S>
-
- .macro disable_fiq
- .endm
-
- .macro arch_ret_to_user, tmp1, tmp2
- .endm
diff -PurN linux-stable-23d8c3f/arch/arm/mach-msm/include/mach/entry-macro.S kernel_3.2.14_patched/arch/arm/mach-msm/include/mach/entry-macro.S
--- linux-stable-23d8c3f/arch/arm/mach-msm/include/mach/entry-macro.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-msm/include/mach/entry-macro.S 2012-05-16 12:10:47.000000000 +0100
@@ -16,8 +16,27 @@
*
*/
-#if defined(CONFIG_ARM_GIC)
-#include <mach/entry-macro-qgic.S>
-#else
-#include <mach/entry-macro-vic.S>
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+#if !defined(CONFIG_ARM_GIC)
+#include <mach/msm_iomap.h>
+
+ .macro get_irqnr_preamble, base, tmp
+ @ enable imprecise aborts
+ cpsie a
+ mov \base, #MSM_VIC_BASE
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ @ 0xD0 has irq# or old irq# if the irq has been handled
+ @ 0xD4 has irq# or -1 if none pending *but* if you just
+ @ read 0xD4 you never get the first irq for some reason
+ ldr \irqnr, [\base, #0xD0]
+ ldr \irqnr, [\base, #0xD4]
+ cmp \irqnr, #0xffffffff
+ .endm
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-msm/include/mach/entry-macro-vic.S kernel_3.2.14_patched/arch/arm/mach-msm/include/mach/entry-macro-vic.S
--- linux-stable-23d8c3f/arch/arm/mach-msm/include/mach/entry-macro-vic.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-msm/include/mach/entry-macro-vic.S 1970-01-01 01:00:00.000000000 +0100
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <mach/msm_iomap.h>
-
- .macro disable_fiq
- .endm
-
- .macro get_irqnr_preamble, base, tmp
- @ enable imprecise aborts
- cpsie a
- mov \base, #MSM_VIC_BASE
- .endm
-
- .macro arch_ret_to_user, tmp1, tmp2
- .endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- @ 0xD0 has irq# or old irq# if the irq has been handled
- @ 0xD4 has irq# or -1 if none pending *but* if you just
- @ read 0xD4 you never get the first irq for some reason
- ldr \irqnr, [\base, #0xD0]
- ldr \irqnr, [\base, #0xD4]
- cmp \irqnr, #0xffffffff
- .endm
diff -PurN linux-stable-23d8c3f/arch/arm/mach-msm/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-msm/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-msm/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-msm/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,22 +0,0 @@
-/* arch/arm/mach-msm/include/mach/vmalloc.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_VMALLOC_H
-#define __ASM_ARCH_MSM_VMALLOC_H
-
-#define VMALLOC_END 0xd0000000UL
-
-#endif
-
diff -PurN linux-stable-23d8c3f/arch/arm/mach-mv78xx0/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-mv78xx0/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-mv78xx0/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-mv78xx0/include/mach/vmalloc.h
- */
-
-#define VMALLOC_END 0xfe000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-mxs/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-mxs/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-mxs/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-mxs/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2000 Russell King.
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_MXS_VMALLOC_H__
-#define __MACH_MXS_VMALLOC_H__
-
-/* vmalloc ending address */
-#define VMALLOC_END 0xf4000000UL
-
-#endif /* __MACH_MXS_VMALLOC_H__ */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-mxs/system.c kernel_3.2.14_patched/arch/arm/mach-mxs/system.c
--- linux-stable-23d8c3f/arch/arm/mach-mxs/system.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-mxs/system.c 2012-05-16 12:10:47.000000000 +0100
@@ -53,7 +53,7 @@
mdelay(50);
/* We'll take a jump through zero as a poor second */
- cpu_reset(0);
+ soft_restart(0);
}
static int __init mxs_arch_reset_init(void)
diff -PurN linux-stable-23d8c3f/arch/arm/mach-netx/include/mach/entry-macro.S kernel_3.2.14_patched/arch/arm/mach-netx/include/mach/entry-macro.S
--- linux-stable-23d8c3f/arch/arm/mach-netx/include/mach/entry-macro.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-netx/include/mach/entry-macro.S 2012-05-16 12:10:47.000000000 +0100
@@ -18,22 +18,9 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#include <mach/hardware.h>
.macro disable_fiq
.endm
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =io_p2v(0x001ff000)
- .endm
-
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqstat, [\base, #0]
- clz \irqnr, \irqstat
- rsb \irqnr, \irqnr, #31
- cmp \irqstat, #0
- .endm
-
diff -PurN linux-stable-23d8c3f/arch/arm/mach-netx/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-netx/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-netx/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-netx/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-netx/include/mach/vmalloc.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END 0xd0000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-netx/nxdb500.c kernel_3.2.14_patched/arch/arm/mach-netx/nxdb500.c
--- linux-stable-23d8c3f/arch/arm/mach-netx/nxdb500.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-netx/nxdb500.c 2012-05-16 12:10:47.000000000 +0100
@@ -28,6 +28,7 @@
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/vic.h>
#include <mach/netx-regs.h>
#include <mach/eth.h>
@@ -203,6 +204,7 @@
.atag_offset = 0x100,
.map_io = netx_map_io,
.init_irq = netx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &netx_timer,
.init_machine = nxdb500_init,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-netx/nxdkn.c kernel_3.2.14_patched/arch/arm/mach-netx/nxdkn.c
--- linux-stable-23d8c3f/arch/arm/mach-netx/nxdkn.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-netx/nxdkn.c 2012-05-16 12:10:47.000000000 +0100
@@ -28,6 +28,7 @@
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/vic.h>
#include <mach/netx-regs.h>
#include <mach/eth.h>
@@ -96,6 +97,7 @@
.atag_offset = 0x100,
.map_io = netx_map_io,
.init_irq = netx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &netx_timer,
.init_machine = nxdkn_init,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-netx/nxeb500hmi.c kernel_3.2.14_patched/arch/arm/mach-netx/nxeb500hmi.c
--- linux-stable-23d8c3f/arch/arm/mach-netx/nxeb500hmi.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-netx/nxeb500hmi.c 2012-05-16 12:10:47.000000000 +0100
@@ -28,6 +28,7 @@
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/vic.h>
#include <mach/netx-regs.h>
#include <mach/eth.h>
@@ -180,6 +181,7 @@
.atag_offset = 0x100,
.map_io = netx_map_io,
.init_irq = netx_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &netx_timer,
.init_machine = nxeb500hmi_init,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-nomadik/board-nhk8815.c kernel_3.2.14_patched/arch/arm/mach-nomadik/board-nhk8815.c
--- linux-stable-23d8c3f/arch/arm/mach-nomadik/board-nhk8815.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-nomadik/board-nhk8815.c 2012-05-16 12:10:47.000000000 +0100
@@ -21,6 +21,7 @@
#include <linux/mtd/onenand.h>
#include <linux/mtd/partitions.h>
#include <linux/io.h>
+#include <asm/hardware/vic.h>
#include <asm/sizes.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -280,6 +281,7 @@
.atag_offset = 0x100,
.map_io = cpu8815_map_io,
.init_irq = cpu8815_init_irq,
+ .handle_irq = vic_handle_irq,
.timer = &nomadik_timer,
.init_machine = nhk8815_platform_init,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-nomadik/include/mach/entry-macro.S kernel_3.2.14_patched/arch/arm/mach-nomadik/include/mach/entry-macro.S
--- linux-stable-23d8c3f/arch/arm/mach-nomadik/include/mach/entry-macro.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-nomadik/include/mach/entry-macro.S 2012-05-16 12:10:47.000000000 +0100
@@ -6,38 +6,8 @@
* warranty of any kind, whether express or implied.
*/
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-
.macro disable_fiq
.endm
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =IO_ADDRESS(NOMADIK_IC_BASE)
- .endm
-
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- /* This stanza gets the irq mask from one of two status registers */
- mov \irqnr, #0
- ldr \irqstat, [\base, #VIC_REG_IRQSR0] @ get masked status
- cmp \irqstat, #0
- bne 1001f
- add \irqnr, \irqnr, #32
- ldr \irqstat, [\base, #VIC_REG_IRQSR1] @ get masked status
-
-1001: tst \irqstat, #15
- bne 1002f
- add \irqnr, \irqnr, #4
- movs \irqstat, \irqstat, lsr #4
- bne 1001b
-1002: tst \irqstat, #1
- bne 1003f
- add \irqnr, \irqnr, #1
- movs \irqstat, \irqstat, lsr #1
- bne 1002b
-1003: /* EQ will be set if no irqs pending */
- .endm
diff -PurN linux-stable-23d8c3f/arch/arm/mach-nomadik/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-nomadik/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-nomadik/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-nomadik/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,2 +0,0 @@
-
-#define VMALLOC_END 0xe8000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-ams-delta.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-ams-delta.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-ams-delta.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-ams-delta.c 2012-05-16 12:10:47.000000000 +0100
@@ -35,7 +35,7 @@
#include <plat/mux.h>
#include <plat/usb.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <mach/camera.h>
#include <mach/ams-delta-fiq.h>
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-fsample.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-fsample.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-fsample.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-fsample.c 2012-05-16 12:10:47.000000000 +0100
@@ -32,7 +32,7 @@
#include <plat/flash.h>
#include <plat/fpga.h>
#include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/board.h>
/* fsample is pretty close to p2-sample */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-generic.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-generic.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-generic.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-generic.c 2012-05-16 12:10:47.000000000 +0100
@@ -25,7 +25,7 @@
#include <plat/mux.h>
#include <plat/usb.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
/* assume no Mini-AB port */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-h2.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-h2.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-h2.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-h2.c 2012-05-16 12:10:47.000000000 +0100
@@ -43,7 +43,7 @@
#include <plat/irda.h>
#include <plat/usb.h>
#include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/flash.h>
#include "board-h2.h"
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-h3.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-h3.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-h3.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-h3.c 2012-05-16 12:10:47.000000000 +0100
@@ -45,7 +45,7 @@
#include <plat/usb.h>
#include <plat/keypad.h>
#include <plat/dma.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/flash.h>
#include "board-h3.h"
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-htcherald.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-htcherald.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-htcherald.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-htcherald.c 2012-05-16 12:10:47.000000000 +0100
@@ -41,7 +41,7 @@
#include <asm/mach/arch.h>
#include <plat/omap7xx.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/board.h>
#include <plat/keypad.h>
#include <plat/usb.h>
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-innovator.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-innovator.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-innovator.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-innovator.c 2012-05-16 12:10:47.000000000 +0100
@@ -37,7 +37,7 @@
#include <plat/tc.h>
#include <plat/usb.h>
#include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/mmc.h>
/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-nokia770.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-nokia770.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-nokia770.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-nokia770.c 2012-05-16 12:10:47.000000000 +0100
@@ -12,6 +12,8 @@
#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
+#include <linux/platform_data/cbus.h>
+#include <linux/irq.h>
#include <linux/input.h>
#include <linux/clk.h>
#include <linux/omapfb.h>
@@ -30,7 +32,7 @@
#include <plat/usb.h>
#include <plat/board.h>
#include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/hwa742.h>
#include <plat/lcd_mipid.h>
#include <plat/mmc.h>
@@ -82,6 +84,104 @@
.resource = nokia770_kp_resources,
};
+#if defined(CONFIG_CBUS) || defined(CONFIG_CBUS_MODULE)
+
+static struct cbus_host_platform_data nokia770_cbus_data = {
+ .clk_gpio = OMAP_MPUIO(11),
+ .dat_gpio = OMAP_MPUIO(10),
+ .sel_gpio = OMAP_MPUIO(9),
+};
+
+static struct platform_device nokia770_cbus_device = {
+ .name = "cbus",
+ .id = -1,
+ .dev = {
+ .platform_data = &nokia770_cbus_data,
+ },
+};
+
+static struct resource retu_resource[] = {
+ {
+ .start = -EINVAL, /* set later */
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device retu_device = {
+ .name = "retu",
+ .id = -1,
+ .resource = retu_resource,
+ .num_resources = ARRAY_SIZE(retu_resource),
+ .dev = {
+ .parent = &nokia770_cbus_device.dev,
+ },
+};
+
+static struct resource tahvo_resource[] = {
+ {
+ .start = -EINVAL, /* set later */
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct platform_device tahvo_device = {
+ .name = "tahvo",
+ .id = -1,
+ .resource = tahvo_resource,
+ .num_resources = ARRAY_SIZE(tahvo_resource),
+ .dev = {
+ .parent = &nokia770_cbus_device.dev,
+ },
+};
+
+static void __init nokia770_cbus_init(void)
+{
+ int ret;
+
+ platform_device_register(&nokia770_cbus_device);
+
+ ret = gpio_request(62, "RETU irq");
+ if (ret < 0) {
+ pr_err("retu: Unable to reserve IRQ GPIO\n");
+ return;
+ }
+
+ ret = gpio_direction_input(62);
+ if (ret < 0) {
+ pr_err("retu: Unable to change gpio direction\n");
+ gpio_free(62);
+ return;
+ }
+
+ irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_RISING);
+ retu_resource[0].start = gpio_to_irq(62);
+ platform_device_register(&retu_device);
+
+ ret = gpio_request(40, "TAHVO irq");
+ if (ret) {
+ pr_err("tahvo: Unable to reserve IRQ GPIO\n");
+ gpio_free(62);
+ return;
+ }
+
+ ret = gpio_direction_input(40);
+ if (ret) {
+ pr_err("tahvo: Unable to change direction\n");
+ gpio_free(62);
+ gpio_free(40);
+ return;
+ }
+
+ tahvo_resource[0].start = gpio_to_irq(40);
+ platform_device_register(&tahvo_device);
+}
+
+#else
+static inline void __init nokia770_cbus_init(void)
+{
+}
+#endif
+
static struct platform_device *nokia770_devices[] __initdata = {
&nokia770_kp_device,
};
@@ -239,6 +339,7 @@
/* Unmask SleepX signal */
omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
+ nokia770_cbus_init();
platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
spi_register_board_info(nokia770_spi_board_info,
ARRAY_SIZE(nokia770_spi_board_info));
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-osk.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-osk.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-osk.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-osk.c 2012-05-16 12:10:47.000000000 +0100
@@ -51,7 +51,7 @@
#include <plat/usb.h>
#include <plat/mux.h>
#include <plat/tc.h>
-#include <plat/common.h>
+#include "common.h"
/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
#define OMAP_OSK_ETHR_START 0x04800300
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-palmte.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-palmte.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-palmte.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-palmte.c 2012-05-16 12:10:47.000000000 +0100
@@ -41,7 +41,7 @@
#include <plat/board.h>
#include <plat/irda.h>
#include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
#define PALMTE_USBDETECT_GPIO 0
#define PALMTE_USB_OR_DC_GPIO 1
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-palmtt.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-palmtt.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-palmtt.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-palmtt.c 2012-05-16 12:10:47.000000000 +0100
@@ -39,7 +39,7 @@
#include <plat/board.h>
#include <plat/irda.h>
#include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-palmz71.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-palmz71.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-palmz71.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-palmz71.c 2012-05-16 12:10:47.000000000 +0100
@@ -41,7 +41,7 @@
#include <plat/board.h>
#include <plat/irda.h>
#include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-perseus2.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-perseus2.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-perseus2.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-perseus2.c 2012-05-16 12:10:47.000000000 +0100
@@ -32,7 +32,7 @@
#include <plat/fpga.h>
#include <plat/flash.h>
#include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/board.h>
static const unsigned int p2_keymap[] = {
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-sx1.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-sx1.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-sx1.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-sx1.c 2012-05-16 12:10:47.000000000 +0100
@@ -40,7 +40,7 @@
#include <plat/usb.h>
#include <plat/tc.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/keypad.h>
#include <plat/board-sx1.h>
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/board-voiceblue.c kernel_3.2.14_patched/arch/arm/mach-omap1/board-voiceblue.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/board-voiceblue.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/board-voiceblue.c 2012-05-16 12:10:47.000000000 +0100
@@ -34,7 +34,7 @@
#include <asm/mach/map.h>
#include <plat/board-voiceblue.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/flash.h>
#include <plat/mux.h>
#include <plat/tc.h>
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/clock.c kernel_3.2.14_patched/arch/arm/mach-omap1/clock.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/clock.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/clock.c 2012-05-16 12:10:47.000000000 +0100
@@ -197,11 +197,10 @@
ref_rate = ck_ref_p->rate;
for (ptr = omap1_rate_table; ptr->rate; ptr++) {
- if (ptr->xtal != ref_rate)
+ if (!(ptr->flags & cpu_mask))
continue;
- /* DPLL1 cannot be reprogrammed without risking system crash */
- if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
+ if (ptr->xtal != ref_rate)
continue;
/* Can check only after xtal frequency check */
@@ -215,12 +214,8 @@
/*
* In most cases we should not need to reprogram DPLL.
* Reprogramming the DPLL is tricky, it must be done from SRAM.
- * (on 730, bit 13 must always be 1)
*/
- if (cpu_is_omap7xx())
- omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
- else
- omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
+ omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
/* XXX Do we need to recalculate the tree below DPLL1 at this point? */
ck_dpll1_p->rate = ptr->pll_rate;
@@ -290,6 +285,9 @@
highest_rate = -EINVAL;
for (ptr = omap1_rate_table; ptr->rate; ptr++) {
+ if (!(ptr->flags & cpu_mask))
+ continue;
+
if (ptr->xtal != ref_rate)
continue;
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/clock_data.c kernel_3.2.14_patched/arch/arm/mach-omap1/clock_data.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/clock_data.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/clock_data.c 2012-05-16 12:10:47.000000000 +0100
@@ -25,6 +25,7 @@
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/clkdev_omap.h>
+#include <plat/sram.h> /* for omap_sram_reprogram_clock() */
#include <plat/usb.h> /* for OTG_BASE */
#include "clock.h"
@@ -778,12 +779,14 @@
arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
}
+u32 cpu_mask;
+
int __init omap1_clk_init(void)
{
struct omap_clk *c;
const struct omap_clock_config *info;
int crystal_type = 0; /* Default 12 MHz */
- u32 reg, cpu_mask;
+ u32 reg;
#ifdef CONFIG_DEBUG_LL
/*
@@ -808,6 +811,8 @@
clk_preinit(c->lk.clk);
cpu_mask = 0;
+ if (cpu_is_omap1710())
+ cpu_mask |= CK_1710;
if (cpu_is_omap16xx())
cpu_mask |= CK_16XX;
if (cpu_is_omap1510())
@@ -931,17 +936,13 @@
{
unsigned long rate = ck_dpll1.rate;
- if (rate >= OMAP1_DPLL1_SANE_VALUE)
- return;
-
- /* System booting at unusable rate, force reprogramming of DPLL1 */
- ck_dpll1_p->rate = 0;
-
/* Find the highest supported frequency and enable it */
if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
pr_err("System frequencies not set, using default. Check your config.\n");
- omap_writew(0x2290, DPLL_CTL);
- omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL);
+ /*
+ * Reprogramming the DPLL is tricky, it must be done from SRAM.
+ */
+ omap_sram_reprogram_clock(0x2290, 0x0005);
ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
}
propagate_rate(&ck_dpll1);
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/clock.h kernel_3.2.14_patched/arch/arm/mach-omap1/clock.h
--- linux-stable-23d8c3f/arch/arm/mach-omap1/clock.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/clock.h 2012-05-16 12:10:47.000000000 +0100
@@ -111,4 +111,7 @@
extern const struct clkops clkops_uart_16xx;
extern const struct clkops clkops_generic;
+/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
+extern u32 cpu_mask;
+
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/common.h kernel_3.2.14_patched/arch/arm/mach-omap1/common.h
--- linux-stable-23d8c3f/arch/arm/mach-omap1/common.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/common.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,61 @@
+/*
+ *
+ * Header for code common to all OMAP1 machines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP1_COMMON_H
+#define __ARCH_ARM_MACH_OMAP1_COMMON_H
+
+#include <plat/common.h>
+
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+void omap7xx_map_io(void);
+#else
+static inline void omap7xx_map_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP15XX
+void omap15xx_map_io(void);
+#else
+static inline void omap15xx_map_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP16XX
+void omap16xx_map_io(void);
+#else
+static inline void omap16xx_map_io(void)
+{
+}
+#endif
+
+void omap1_init_early(void);
+void omap1_init_irq(void);
+
+extern struct sys_timer omap1_timer;
+extern bool omap_32k_timer_init(void);
+
+#endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/devices.c kernel_3.2.14_patched/arch/arm/mach-omap1/devices.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/devices.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/devices.c 2012-05-16 12:10:47.000000000 +0100
@@ -22,7 +22,7 @@
#include <mach/hardware.h>
#include <asm/mach/map.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/tc.h>
#include <plat/board.h>
#include <plat/mux.h>
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-omap1/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-omap1/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-omap1/include/mach/vmalloc.h
- *
- * Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END 0xd8000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/io.c kernel_3.2.14_patched/arch/arm/mach-omap1/io.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/io.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/io.c 2012-05-16 12:10:47.000000000 +0100
@@ -121,7 +121,6 @@
void omap1_init_early(void)
{
omap_check_revision();
- omap_ioremap_init();
/* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
* on a Posted Write in the TIPB Bridge".
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/Kconfig kernel_3.2.14_patched/arch/arm/mach-omap1/Kconfig
--- linux-stable-23d8c3f/arch/arm/mach-omap1/Kconfig 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/Kconfig 2012-05-16 12:10:47.000000000 +0100
@@ -168,70 +168,6 @@
custom OMAP boards. Say Y here if you have a custom
board.
-comment "OMAP CPU Speed"
- depends on ARCH_OMAP1
-
-config OMAP_ARM_216MHZ
- bool "OMAP ARM 216 MHz CPU (1710 only)"
- depends on ARCH_OMAP1 && ARCH_OMAP16XX
- help
- Enable 216 MHz clock for OMAP1710 CPU. If unsure, say N.
-
-config OMAP_ARM_195MHZ
- bool "OMAP ARM 195 MHz CPU"
- depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
- help
- Enable 195MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_192MHZ
- bool "OMAP ARM 192 MHz CPU"
- depends on ARCH_OMAP1 && ARCH_OMAP16XX
- help
- Enable 192MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_182MHZ
- bool "OMAP ARM 182 MHz CPU"
- depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
- help
- Enable 182MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_168MHZ
- bool "OMAP ARM 168 MHz CPU"
- depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
- help
- Enable 168MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_150MHZ
- bool "OMAP ARM 150 MHz CPU"
- depends on ARCH_OMAP1 && ARCH_OMAP15XX
- help
- Enable 150MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_120MHZ
- bool "OMAP ARM 120 MHz CPU"
- depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
- help
- Enable 120MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_96MHZ
- bool "OMAP ARM 96 MHz CPU"
- depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
- help
- Enable 96MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_60MHZ
- bool "OMAP ARM 60 MHz CPU"
- depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
- default y
- help
- Enable 60MHz clock for OMAP CPU. If unsure, say Y.
-
-config OMAP_ARM_30MHZ
- bool "OMAP ARM 30 MHz CPU"
- depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
- help
- Enable 30MHz clock for OMAP CPU. If unsure, say N.
-
endmenu
endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/opp_data.c kernel_3.2.14_patched/arch/arm/mach-omap1/opp_data.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/opp_data.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/opp_data.c 2012-05-16 12:10:47.000000000 +0100
@@ -10,6 +10,7 @@
* published by the Free Software Foundation.
*/
+#include <plat/clkdev_omap.h>
#include "opp.h"
/*-------------------------------------------------------------------------
@@ -20,40 +21,34 @@
* NOTE: Comment order here is different from bits in CKCTL value:
* armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
*/
-#if defined(CONFIG_OMAP_ARM_216MHZ)
- { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_195MHZ)
- { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_192MHZ)
- { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
- { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
- { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
- { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
- { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_182MHZ)
- { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_168MHZ)
- { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_150MHZ)
- { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
-#endif
-#if defined(CONFIG_OMAP_ARM_120MHZ)
- { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
-#endif
-#if defined(CONFIG_OMAP_ARM_96MHZ)
- { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_60MHZ)
- { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_30MHZ)
- { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
-#endif
+ { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */
+ CK_1710 },
+ { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */
+ CK_7XX },
+ { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */
+ CK_16XX },
+ { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */
+ CK_16XX },
+ { 96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */
+ CK_16XX },
+ { 48000000, 12000000, 192000000, 0x0baf, 0x2810, /* 4/4/4/8/8/8 */
+ CK_16XX },
+ { 24000000, 12000000, 192000000, 0x0fff, 0x2810, /* 8/8/8/8/8/8 */
+ CK_16XX },
+ { 182000000, 13000000, 182000000, 0x050e, 0x2710, /* 1/1/2/2/4/8 */
+ CK_7XX },
+ { 168000000, 12000000, 168000000, 0x010f, 0x2710, /* 1/1/1/2/8/8 */
+ CK_16XX|CK_7XX },
+ { 150000000, 12000000, 150000000, 0x010a, 0x2cb0, /* 1/1/1/2/4/4 */
+ CK_1510 },
+ { 120000000, 12000000, 120000000, 0x010a, 0x2510, /* 1/1/1/2/4/4 */
+ CK_16XX|CK_1510|CK_310|CK_7XX },
+ { 96000000, 12000000, 96000000, 0x0005, 0x2410, /* 1/1/1/1/2/2 */
+ CK_16XX|CK_1510|CK_310|CK_7XX },
+ { 60000000, 12000000, 60000000, 0x0005, 0x2290, /* 1/1/1/1/2/2 */
+ CK_16XX|CK_1510|CK_310|CK_7XX },
+ { 30000000, 12000000, 60000000, 0x0555, 0x2290, /* 2/2/2/2/2/2 */
+ CK_16XX|CK_1510|CK_310|CK_7XX },
{ 0, 0, 0, 0, 0 },
};
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/opp.h kernel_3.2.14_patched/arch/arm/mach-omap1/opp.h
--- linux-stable-23d8c3f/arch/arm/mach-omap1/opp.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/opp.h 2012-05-16 12:10:47.000000000 +0100
@@ -21,6 +21,7 @@
unsigned long pll_rate;
__u16 ckctl_val;
__u16 dpllctl_val;
+ u32 flags;
};
extern struct mpu_rate omap1_rate_table[];
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/pm.c kernel_3.2.14_patched/arch/arm/mach-omap1/pm.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/pm.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/pm.c 2012-05-16 12:10:47.000000000 +0100
@@ -584,6 +584,9 @@
#endif /* DEBUG && CONFIG_PROC_FS */
static void (*saved_idle)(void) = NULL;
+static void omap1_dummy_idle(void)
+{
+}
/*
* omap_pm_prepare - Do preliminary suspend work.
@@ -593,7 +596,7 @@
{
/* We cannot sleep in idle until we have resumed */
saved_idle = pm_idle;
- pm_idle = NULL;
+ pm_idle = omap1_dummy_idle;
return 0;
}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/time.c kernel_3.2.14_patched/arch/arm/mach-omap1/time.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/time.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/time.c 2012-05-16 12:10:47.000000000 +0100
@@ -54,7 +54,7 @@
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
-#include <plat/common.h>
+#include "common.h"
#ifdef CONFIG_OMAP_MPU_TIMER
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap1/timer32k.c kernel_3.2.14_patched/arch/arm/mach-omap1/timer32k.c
--- linux-stable-23d8c3f/arch/arm/mach-omap1/timer32k.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap1/timer32k.c 2012-05-16 12:10:47.000000000 +0100
@@ -52,7 +52,7 @@
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/dmtimer.h>
/*
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-2430sdp.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-2430sdp.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-2430sdp.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-2430sdp.c 2012-05-16 12:10:47.000000000 +0100
@@ -34,7 +34,7 @@
#include <asm/mach/map.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/gpmc.h>
#include <plat/usb.h>
#include <plat/gpmc-smc91x.h>
@@ -301,6 +301,7 @@
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = omap_2430sdp_init,
.timer = &omap2_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-3430sdp.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-3430sdp.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-3430sdp.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-3430sdp.c 2012-05-16 12:10:47.000000000 +0100
@@ -33,7 +33,7 @@
#include <plat/mcspi.h>
#include <plat/board.h>
#include <plat/usb.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/dma.h>
#include <plat/gpmc.h>
#include <video/omapdss.h>
@@ -475,106 +475,8 @@
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-
-static struct omap_device_pad serial1_pads[] __initdata = {
- /*
- * Note that off output enable is an active low
- * signal. So setting this means pin is a
- * input enabled in off mode
- */
- OMAP_MUX_STATIC("uart1_cts.uart1_cts",
- OMAP_PIN_INPUT |
- OMAP_PIN_OFF_INPUT_PULLDOWN |
- OMAP_OFFOUT_EN |
- OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart1_rts.uart1_rts",
- OMAP_PIN_OUTPUT |
- OMAP_OFF_EN |
- OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart1_rx.uart1_rx",
- OMAP_PIN_INPUT |
- OMAP_PIN_OFF_INPUT_PULLDOWN |
- OMAP_OFFOUT_EN |
- OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart1_tx.uart1_tx",
- OMAP_PIN_OUTPUT |
- OMAP_OFF_EN |
- OMAP_MUX_MODE0),
-};
-
-static struct omap_device_pad serial2_pads[] __initdata = {
- OMAP_MUX_STATIC("uart2_cts.uart2_cts",
- OMAP_PIN_INPUT_PULLUP |
- OMAP_PIN_OFF_INPUT_PULLDOWN |
- OMAP_OFFOUT_EN |
- OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart2_rts.uart2_rts",
- OMAP_PIN_OUTPUT |
- OMAP_OFF_EN |
- OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart2_rx.uart2_rx",
- OMAP_PIN_INPUT |
- OMAP_PIN_OFF_INPUT_PULLDOWN |
- OMAP_OFFOUT_EN |
- OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart2_tx.uart2_tx",
- OMAP_PIN_OUTPUT |
- OMAP_OFF_EN |
- OMAP_MUX_MODE0),
-};
-
-static struct omap_device_pad serial3_pads[] __initdata = {
- OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
- OMAP_PIN_INPUT_PULLDOWN |
- OMAP_PIN_OFF_INPUT_PULLDOWN |
- OMAP_OFFOUT_EN |
- OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
- OMAP_PIN_OUTPUT |
- OMAP_OFF_EN |
- OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
- OMAP_PIN_INPUT |
- OMAP_PIN_OFF_INPUT_PULLDOWN |
- OMAP_OFFOUT_EN |
- OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
- OMAP_PIN_OUTPUT |
- OMAP_OFF_EN |
- OMAP_MUX_MODE0),
-};
-
-static struct omap_board_data serial1_data __initdata = {
- .id = 0,
- .pads = serial1_pads,
- .pads_cnt = ARRAY_SIZE(serial1_pads),
-};
-
-static struct omap_board_data serial2_data __initdata = {
- .id = 1,
- .pads = serial2_pads,
- .pads_cnt = ARRAY_SIZE(serial2_pads),
-};
-
-static struct omap_board_data serial3_data __initdata = {
- .id = 2,
- .pads = serial3_pads,
- .pads_cnt = ARRAY_SIZE(serial3_pads),
-};
-
-static inline void board_serial_init(void)
-{
- omap_serial_init_port(&serial1_data);
- omap_serial_init_port(&serial2_data);
- omap_serial_init_port(&serial3_data);
-}
#else
#define board_mux NULL
-
-static inline void board_serial_init(void)
-{
- omap_serial_init();
-}
#endif
/*
@@ -711,7 +613,7 @@
else
gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
omap_ads7846_init(1, gpio_pendown, 310, NULL);
- board_serial_init();
+ omap_serial_init();
omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
usb_musb_init(NULL);
board_smc91x_init();
@@ -728,6 +630,7 @@
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap_3430sdp_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-3630sdp.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-3630sdp.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-3630sdp.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-3630sdp.c 2012-05-16 12:10:47.000000000 +0100
@@ -16,7 +16,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/board.h>
#include <plat/gpmc-smc91x.h>
#include <plat/usb.h>
@@ -215,6 +215,7 @@
.map_io = omap3_map_io,
.init_early = omap3630_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap_sdp_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-4430sdp.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-4430sdp.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-4430sdp.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-4430sdp.c 2012-05-16 12:12:51.000000000 +0100
@@ -27,13 +27,13 @@
#include <linux/leds_pwm.h>
#include <mach/hardware.h>
-#include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/usb.h>
#include <plat/mmc.h>
#include <plat/omap4-keypad.h>
@@ -373,11 +373,17 @@
},
};
+static struct platform_device sdp4430_dmic_codec = {
+ .name = "dmic-codec",
+ .id = -1,
+};
+
static struct platform_device *sdp4430_devices[] __initdata = {
&sdp4430_gpio_keys_device,
&sdp4430_leds_gpio,
&sdp4430_leds_pwm,
&sdp4430_vbat,
+ &sdp4430_dmic_codec,
};
static struct omap_musb_board_data musb_board_data = {
@@ -405,6 +411,7 @@
{
.mmc = 5,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+ .pm_caps = MMC_PM_KEEP_POWER,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.ocr_mask = MMC_VDD_165_195,
@@ -843,74 +850,8 @@
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-static struct omap_device_pad serial2_pads[] __initdata = {
- OMAP_MUX_STATIC("uart2_cts.uart2_cts",
- OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart2_rts.uart2_rts",
- OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart2_rx.uart2_rx",
- OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart2_tx.uart2_tx",
- OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-
-static struct omap_device_pad serial3_pads[] __initdata = {
- OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
- OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
- OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
- OMAP_PIN_INPUT | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
- OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-
-static struct omap_device_pad serial4_pads[] __initdata = {
- OMAP_MUX_STATIC("uart4_rx.uart4_rx",
- OMAP_PIN_INPUT | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart4_tx.uart4_tx",
- OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-
-static struct omap_board_data serial2_data __initdata = {
- .id = 1,
- .pads = serial2_pads,
- .pads_cnt = ARRAY_SIZE(serial2_pads),
-};
-
-static struct omap_board_data serial3_data __initdata = {
- .id = 2,
- .pads = serial3_pads,
- .pads_cnt = ARRAY_SIZE(serial3_pads),
-};
-
-static struct omap_board_data serial4_data __initdata = {
- .id = 3,
- .pads = serial4_pads,
- .pads_cnt = ARRAY_SIZE(serial4_pads),
-};
-
-static inline void board_serial_init(void)
-{
- struct omap_board_data bdata;
- bdata.flags = 0;
- bdata.pads = NULL;
- bdata.pads_cnt = 0;
- bdata.id = 0;
- /* pass dummy data for UART1 */
- omap_serial_init_port(&bdata);
-
- omap_serial_init_port(&serial2_data);
- omap_serial_init_port(&serial3_data);
- omap_serial_init_port(&serial4_data);
-}
#else
#define board_mux NULL
-
-static inline void board_serial_init(void)
-{
- omap_serial_init();
-}
#endif
static void omap4_sdp4430_wifi_mux_init(void)
@@ -960,7 +901,7 @@
omap4_i2c_init();
omap_sfh7741prox_init();
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
- board_serial_init();
+ omap_serial_init();
omap_sdrc_init(NULL, NULL);
omap4_sdp4430_wifi_init();
omap4_twl6030_hsmmc_init(mmc);
@@ -990,6 +931,7 @@
.map_io = omap4_map_io,
.init_early = omap4430_init_early,
.init_irq = gic_init_irq,
+ .handle_irq = gic_handle_irq,
.init_machine = omap_4430sdp_init,
.timer = &omap4_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-am335xevm.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-am335xevm.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-am335xevm.c 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-am335xevm.c 2012-05-16 12:13:09.000000000 +0100
@@ -0,0 +1,3158 @@
+/*
+ * Code for AM335X EVM.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/i2c/at24.h>
+#include <linux/phy.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/wl12xx.h>
+#include <linux/ethtool.h>
+#include <linux/mfd/tps65910.h>
+#include <linux/mfd/tps65217.h>
+#include <linux/pwm_backlight.h>
+#include <linux/reboot.h>
+#include <linux/pwm/pwm.h>
+#include <linux/w1-gpio.h>
+#include <linux/can/platform/mcp251x.h>
+
+/* LCD controller is similar to DA850 */
+#include <video/da8xx-fb.h>
+
+#include <mach/hardware.h>
+#include <mach/board-am335xevm.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/asp.h>
+
+#include <plat/irqs.h>
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/lcdc.h>
+#include <plat/usb.h>
+#include <plat/mmc.h>
+#include <plat/emif.h>
+#include <plat/nand.h>
+
+#include "board-flash.h"
+#include "cpuidle33xx.h"
+#include "mux.h"
+#include "devices.h"
+#include "hsmmc.h"
+
+/* Convert GPIO signal to GPIO pin number */
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+
+/* TLK PHY IDs */
+#define TLK110_PHY_ID 0x2000A201
+#define TLK110_PHY_MASK 0xfffffff0
+
+/* BBB PHY IDs */
+#define BBB_PHY_ID 0x7c0f1
+#define BBB_PHY_MASK 0xfffffffe
+
+/* TLK110 PHY register offsets */
+#define TLK110_COARSEGAIN_REG 0x00A3
+#define TLK110_LPFHPF_REG 0x00AC
+#define TLK110_SPAREANALOG_REG 0x00B9
+#define TLK110_VRCR_REG 0x00D0
+#define TLK110_SETFFE_REG 0x0107
+#define TLK110_FTSP_REG 0x0154
+#define TLK110_ALFATPIDL_REG 0x002A
+#define TLK110_PSCOEF21_REG 0x0096
+#define TLK110_PSCOEF3_REG 0x0097
+#define TLK110_ALFAFACTOR1_REG 0x002C
+#define TLK110_ALFAFACTOR2_REG 0x0023
+#define TLK110_CFGPS_REG 0x0095
+#define TLK110_FTSPTXGAIN_REG 0x0150
+#define TLK110_SWSCR3_REG 0x000B
+#define TLK110_SCFALLBACK_REG 0x0040
+#define TLK110_PHYRCR_REG 0x001F
+
+/* TLK110 register writes values */
+#define TLK110_COARSEGAIN_VAL 0x0000
+#define TLK110_LPFHPF_VAL 0x8000
+#define TLK110_SPANALOG_VAL 0x0000
+#define TLK110_VRCR_VAL 0x0008
+#define TLK110_SETFFE_VAL 0x0605
+#define TLK110_FTSP_VAL 0x0255
+#define TLK110_ALFATPIDL_VAL 0x7998
+#define TLK110_PSCOEF21_VAL 0x3A20
+#define TLK110_PSCOEF3_VAL 0x003F
+#define TLK110_ALFACTOR1_VAL 0xFF80
+#define TLK110_ALFACTOR2_VAL 0x021C
+#define TLK110_CFGPS_VAL 0x0000
+#define TLK110_FTSPTXGAIN_VAL 0x6A88
+#define TLK110_SWSCR3_VAL 0x0000
+#define TLK110_SCFALLBACK_VAL 0xC11D
+#define TLK110_PHYRCR_VAL 0x4000
+
+#if defined(CONFIG_TLK110_WORKAROUND) || \
+ defined(CONFIG_TLK110_WORKAROUND_MODULE)
+#define am335x_tlk110_phy_init()\
+ do { \
+ phy_register_fixup_for_uid(TLK110_PHY_ID,\
+ TLK110_PHY_MASK,\
+ am335x_tlk110_phy_fixup);\
+ } while (0);
+#else
+#define am335x_tlk110_phy_init() do { } while (0);
+#endif
+
+static const struct display_panel disp_panel = {
+ WVGA,
+ 32,
+ 32,
+ COLOR_ACTIVE,
+};
+
+/* LCD backlight platform Data */
+#define AM335X_BACKLIGHT_MAX_BRIGHTNESS 100
+#define AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS 50
+#define AM335X_PWM_PERIOD_NANO_SECONDS (1000000 * 5)
+
+#define PWM_DEVICE_ID "ecap.0"
+
+static struct platform_pwm_backlight_data am335x_backlight_data = {
+ .pwm_id = PWM_DEVICE_ID,
+ .ch = -1,
+ .lth_brightness = 21,
+ .max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
+ .dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
+ .pwm_period_ns = AM335X_PWM_PERIOD_NANO_SECONDS,
+};
+
+static struct lcd_ctrl_config lcd_cfg = {
+ &disp_panel,
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 32,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+};
+
+struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
+ .manu_name = "ThreeFive",
+ .controller_data = &lcd_cfg,
+ .type = "TFC_S9700RTWV35TR_01B",
+};
+
+#include "common.h"
+
+static const struct display_panel bbtoys7_panel = {
+ WVGA,
+ 16,
+ 16,
+ COLOR_ACTIVE,
+};
+
+#define BBTOYS7LCD_PWM_DEVICE_ID "ehrpwm.1:0"
+
+static struct platform_pwm_backlight_data bbtoys7lcd_backlight_data = {
+ .pwm_id = BBTOYS7LCD_PWM_DEVICE_ID,
+ .ch = -1,
+ .max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
+ .dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
+ .pwm_period_ns = AM335X_PWM_PERIOD_NANO_SECONDS,
+};
+
+static struct lcd_ctrl_config bbtoys7_cfg = {
+ &bbtoys7_panel,
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 16,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+};
+
+struct da8xx_lcdc_platform_data bbtoys7_pdata = {
+ .manu_name = "ThreeFive",
+ .controller_data = &bbtoys7_cfg,
+ .type = "TFC_S9700RTWV35TR_01B",
+};
+
+static struct lcd_ctrl_config bbtoys35_cfg = {
+ &bbtoys7_panel,
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 16,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+};
+
+struct da8xx_lcdc_platform_data bbtoys35_pdata = {
+ .manu_name = "BBToys",
+ .controller_data = &bbtoys35_cfg,
+ .type = "CDTech_S035Q01",
+};
+
+static const struct display_panel dvi_panel = {
+ WVGA,
+ 16,
+ 16,
+ COLOR_ACTIVE,
+};
+
+static struct lcd_ctrl_config dvi_cfg = {
+ &dvi_panel,
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 16,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+};
+
+struct da8xx_lcdc_platform_data dvi_pdata = {
+ .manu_name = "BBToys",
+ .controller_data = &dvi_cfg,
+ .type = "1024x768@60",
+};
+
+/* TSc controller */
+#include <linux/input/ti_tscadc.h>
+#include <linux/lis3lv02d.h>
+
+/* TSc controller */
+static struct tsc_data am335x_touchscreen_data = {
+ .wires = 4,
+ .x_plate_resistance = 200,
+ .mode = TI_TSCADC_TSCMODE,
+};
+
+static struct tsc_data bone_touchscreen_data = {
+ .mode = TI_TSCADC_GENMODE,
+};
+
+static u8 am335x_iis_serializer_direction1[] = {
+ INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
+ INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
+ INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
+ INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
+};
+
+static struct snd_platform_data am335x_evm_snd_data1 = {
+ .tx_dma_offset = 0x46400000, /* McASP1 */
+ .rx_dma_offset = 0x46400000,
+ .op_mode = DAVINCI_MCASP_IIS_MODE,
+ .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
+ .tdm_slots = 2,
+ .serial_dir = am335x_iis_serializer_direction1,
+ .asp_chan_q = EVENTQ_2,
+ .version = MCASP_VERSION_3,
+ .txnumevt = 1,
+ .rxnumevt = 1,
+};
+
+static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
+ {
+ .mmc = 1,
+ .caps = MMC_CAP_4_BIT_DATA,
+ .gpio_cd = GPIO_TO_PIN(0, 6),
+ .gpio_wp = GPIO_TO_PIN(3, 18),
+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
+ },
+ {
+ .mmc = 0, /* will be set at runtime */
+ },
+ {
+ .mmc = 0, /* will be set at runtime */
+ },
+ {} /* Terminator */
+};
+
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+ AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
+ AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
+ AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
+ AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux NULL
+#endif
+
+/* module pin mux structure */
+struct pinmux_config {
+ const char *string_name; /* signal name format */
+ int val; /* Options for the mux register value */
+};
+
+struct evm_dev_cfg {
+ void (*device_init)(int evm_id, int profile);
+
+/*
+* If the device is required on both baseboard & daughter board (ex i2c),
+* specify DEV_ON_BASEBOARD
+*/
+#define DEV_ON_BASEBOARD 0
+#define DEV_ON_DGHTR_BRD 1
+ u32 device_on;
+
+ u32 profile; /* Profiles (0-7) in which the module is present */
+};
+
+/* AM335X - CPLD Register Offsets */
+#define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
+#define CPLD_DEVICE_ID 0x04 /* CPLD identification */
+#define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
+#define CPLD_CFG_REG 0x10 /* Configuration Register */
+
+static struct i2c_client *cpld_client;
+static u32 am335x_evm_id;
+static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
+};
+
+/*
+* EVM Config held in On-Board eeprom device.
+*
+* Header Format
+*
+* Name Size Contents
+* (Bytes)
+*-------------------------------------------------------------
+* Header 4 0xAA, 0x55, 0x33, 0xEE
+*
+* Board Name 8 Name for board in ASCII.
+* example "A33515BB" = "AM335X
+ Low Cost EVM board"
+*
+* Version 4 Hardware version code for board in
+* in ASCII. "1.0A" = rev.01.0A
+*
+* Serial Number 12 Serial number of the board. This is a 12
+* character string which is WWYY4P16nnnn, where
+* WW = 2 digit week of the year of production
+* YY = 2 digit year of production
+* nnnn = incrementing board number
+*
+* Configuration option 32 Codes(TBD) to show the configuration
+* setup on this board.
+*
+* Available 32720 Available space for other non-volatile
+* data.
+*/
+struct am335x_evm_eeprom_config {
+ u32 header;
+ u8 name[8];
+ char version[4];
+ u8 serial[12];
+ u8 opt[32];
+};
+
+/*
+* EVM Config held in daughter board eeprom device.
+*
+* Header Format
+*
+* Name Size Contents
+* (Bytes)
+*-------------------------------------------------------------
+* Header 4 0xAA, 0x55, 0x33, 0xEE
+*
+* Board Name 8 Name for board in ASCII.
+* example "A335GPBD" = "AM335x
+* General Purpose Daughterboard"
+*
+* Version 4 Hardware version code for board in
+* in ASCII. "1.0A" = rev.01.0A
+* Serial Number 12 Serial number of the board. This is a 12
+* character string which is: WWYY4P13nnnn, where
+* WW = 2 digit week of the year of production
+* YY = 2 digit year of production
+* nnnn = incrementing board number
+* Configuration Option 32 Codes to show the configuration
+* setup on this board.
+* CPLD Version 8 CPLD code version for board in ASCII
+* "CPLD1.0A" = rev. 01.0A of the CPLD
+* Available 32700 Available space for other non-volatile
+* codes/data
+*/
+
+struct am335x_eeprom_config1 {
+ u32 header;
+ u8 name[8];
+ char version[4];
+ u8 serial[12];
+ u8 opt[32];
+ u8 cpld_ver[8];
+};
+
+static struct am335x_evm_eeprom_config config;
+static struct am335x_eeprom_config1 config1;
+static bool daughter_brd_detected;
+
+struct beaglebone_cape_eeprom_config {
+ u32 header;
+ char format_revision[2];
+ char name[32];
+ char version[4];
+ char manufacturer[16];
+ char partnumber[16];
+ u16 numpins;
+ char serial[12];
+ u8 muxdata[170];
+ u16 current_3v3;
+ u16 current_vdd5v;
+ u16 current_sys5v;
+ u16 dc;
+};
+
+static struct beaglebone_cape_eeprom_config cape_config;
+static bool beaglebone_cape_detected;
+
+/* keep track of ADC pin usage */
+static int capecount = 0;
+static bool beaglebone_tsadcpins_free = 1;
+
+
+#define GP_EVM_REV_IS_1_0 0x1
+#define GP_EVM_REV_IS_1_0A 0x1
+#define GP_EVM_REV_IS_1_1A 0x2
+#define GP_EVM_REV_IS_UNKNOWN 0xFF
+#define GP_EVM_ACTUALLY_BEAGLEBONE 0xBB
+static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
+
+unsigned int gigabit_enable = 1;
+
+#define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
+#define EEPROM_NO_OF_MAC_ADDR 3
+static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
+
+#define AM335X_EEPROM_HEADER 0xEE3355AA
+
+/* current profile if exists else PROFILE_0 on error */
+static u32 am335x_get_profile_selection(void)
+{
+ int val = 0;
+
+ if (!cpld_client)
+ /* error checking is not done in func's calling this routine.
+ so return profile 0 on error */
+ return 0;
+
+ val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
+ if (val < 0)
+ return 0; /* default to Profile 0 on Error */
+ else
+ return val & 0x7;
+}
+
+static struct pinmux_config haptics_pin_mux[] = {
+ {"gpmc_ad9.ehrpwm2B", OMAP_MUX_MODE4 |
+ AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+/* Module pin mux for LCDC */
+static struct pinmux_config lcdc_pin_mux[] = {
+ {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+/* Module pin mux for Beagleboardtoys DVI cape */
+static struct pinmux_config dvi_pin_mux[] = {
+ {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, // USR0 LED
+ {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, // USR1 LED
+ {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, // DVI PDn
+ {NULL, 0},
+};
+
+/* Module pin mux for Beagleboardtoys 7" LCD cape */
+static struct pinmux_config bbtoys7_pin_mux[] = {
+ {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"ecap0_in_pwm0_out.gpio0_7", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, // AVDD_EN
+ {"gpmc_a2.ehrpwm1A", OMAP_MUX_MODE6 | AM33XX_PIN_OUTPUT}, // Backlight
+ {NULL, 0},
+};
+
+static struct pinmux_config w1_gpio_pin_mux[] = {
+ {"gpmc_ad3.gpio1_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config tsc_pin_mux[] = {
+ {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"ain4.ain4", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"ain5.ain5", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"ain6.ain6", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"ain7.ain7", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {NULL, 0},
+};
+
+/* Pin mux for nand flash module */
+static struct pinmux_config nand_pin_mux[] = {
+ {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ {NULL, 0},
+};
+
+/* Module pin mux for SPI fash */
+static struct pinmux_config spi0_pin_mux[] = {
+ {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
+ | AM33XX_INPUT_EN},
+ {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
+ | AM33XX_INPUT_EN},
+ {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
+ | AM33XX_INPUT_EN},
+ {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
+ | AM33XX_INPUT_EN},
+ {NULL, 0},
+};
+
+/* Module pin mux for SPI flash */
+static struct pinmux_config spi1_pin_mux[] = {
+ {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ | AM33XX_INPUT_EN},
+ {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ | AM33XX_PULL_UP | AM33XX_INPUT_EN},
+ {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ | AM33XX_INPUT_EN},
+ {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ | AM33XX_PULL_UP | AM33XX_INPUT_EN},
+ {NULL, 0},
+};
+
+/* Module pin mux for rgmii1 */
+static struct pinmux_config rgmii1_pin_mux[] = {
+ {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
+ {NULL, 0},
+};
+
+/* Module pin mux for rgmii2 */
+static struct pinmux_config rgmii2_pin_mux[] = {
+ {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
+ {NULL, 0},
+};
+
+/* Module pin mux for mii1 */
+static struct pinmux_config mii1_pin_mux[] = {
+ {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
+ {NULL, 0},
+};
+
+/* Module pin mux for rmii1 */
+static struct pinmux_config rmii1_pin_mux[] = {
+ {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config i2c1_pin_mux[] = {
+ {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
+ AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
+ {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
+ AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
+ {NULL, 0},
+};
+
+static struct pinmux_config i2c2_pin_mux[] = {
+ {"uart1_ctsn.i2c2_sda", OMAP_MUX_MODE3 | AM33XX_SLEWCTRL_SLOW |
+ AM33XX_PIN_INPUT_PULLUP},
+ {"uart1_rtsn.i2c2_scl", OMAP_MUX_MODE3 | AM33XX_SLEWCTRL_SLOW |
+ AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+/* Module pin mux for mcasp1 */
+static struct pinmux_config mcasp1_pin_mux[] = {
+ {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
+ AM33XX_PIN_INPUT_PULLDOWN},
+ {NULL, 0},
+};
+
+
+/* Module pin mux for mmc0 */
+static struct pinmux_config mmc0_pin_mux[] = {
+ {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config mmc0_no_cd_pin_mux[] = {
+ {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+ {NULL, 0},
+};
+
+/* Module pin mux for mmc1 */
+static struct pinmux_config mmc1_pin_mux[] = {
+ {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn0.gpio1_29", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+/* Module pin mux for uart3 */
+static struct pinmux_config uart3_pin_mux[] = {
+ {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
+ {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
+ {NULL, 0},
+};
+
+static struct pinmux_config d_can_gp_pin_mux[] = {
+ {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
+ {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config d_can_ia_pin_mux[] = {
+ {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
+ {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config tt3201_pin_mux[] = {
+ {"uart1_rxd.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT },
+ {"uart1_txd.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP },
+ {"mcasp0_fsr.gpio3_19", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP },
+ {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP },
+ {"ecap0_in_pwm0_out.spi1_cs1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT_PULLUP },
+ {NULL, 0},
+};
+
+/* Module pin mux for uart2 */
+static struct pinmux_config uart2_pin_mux[] = {
+ {"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
+ AM33XX_PIN_INPUT_PULLUP},
+ {"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
+ AM33XX_PULL_DISA |
+ AM33XX_SLEWCTRL_SLOW},
+ {NULL, 0},
+};
+
+
+/*
+* @pin_mux - single module pin-mux structure which defines pin-mux
+* details for all its pins.
+*/
+static void setup_pin_mux(struct pinmux_config *pin_mux)
+{
+ int i;
+
+ for (i = 0; pin_mux->string_name != NULL; pin_mux++)
+ omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
+
+}
+
+/* Matrix GPIO Keypad Support for profile-0 only: TODO */
+
+/* pinmux for keypad device */
+static struct pinmux_config matrix_keypad_pin_mux[] = {
+ {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a6.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {NULL, 0},
+};
+
+/* Keys mapping */
+static const uint32_t am335x_evm_matrix_keys[] = {
+ KEY(0, 0, KEY_MENU),
+ KEY(1, 0, KEY_BACK),
+ KEY(2, 0, KEY_LEFT),
+
+ KEY(0, 1, KEY_RIGHT),
+ KEY(1, 1, KEY_ENTER),
+ KEY(2, 1, KEY_DOWN),
+};
+
+const struct matrix_keymap_data am335x_evm_keymap_data = {
+ .keymap = am335x_evm_matrix_keys,
+ .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
+};
+
+static const unsigned int am335x_evm_keypad_row_gpios[] = {
+ GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
+};
+
+static const unsigned int am335x_evm_keypad_col_gpios[] = {
+ GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
+};
+
+static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
+ .keymap_data = &am335x_evm_keymap_data,
+ .row_gpios = am335x_evm_keypad_row_gpios,
+ .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
+ .col_gpios = am335x_evm_keypad_col_gpios,
+ .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
+ .active_low = false,
+ .debounce_ms = 5,
+ .col_scan_delay_us = 2,
+};
+
+static struct platform_device am335x_evm_keyboard = {
+ .name = "matrix-keypad",
+ .id = -1,
+ .dev = {
+ .platform_data = &am335x_evm_keypad_platform_data,
+ },
+};
+
+static void matrix_keypad_init(int evm_id, int profile)
+{
+ int err;
+
+ setup_pin_mux(matrix_keypad_pin_mux);
+ err = platform_device_register(&am335x_evm_keyboard);
+ if (err) {
+ pr_err("failed to register matrix keypad (2x3) device\n");
+ }
+}
+
+
+/* pinmux for keypad device */
+static struct pinmux_config volume_keys_pin_mux[] = {
+ {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {NULL, 0},
+};
+
+/* Configure GPIOs for Volume Keys */
+static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
+ {
+ .code = KEY_VOLUMEUP,
+ .gpio = GPIO_TO_PIN(0, 2),
+ .active_low = true,
+ .desc = "volume-up",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+ {
+ .code = KEY_VOLUMEDOWN,
+ .gpio = GPIO_TO_PIN(0, 3),
+ .active_low = true,
+ .desc = "volume-down",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+};
+
+static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
+ .buttons = am335x_evm_volume_gpio_buttons,
+ .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
+};
+
+static struct platform_device am335x_evm_volume_keys = {
+ .name = "gpio-keys",
+ .id = -1,
+ .dev = {
+ .platform_data = &am335x_evm_volume_gpio_key_info,
+ },
+};
+
+static void volume_keys_init(int evm_id, int profile)
+{
+ int err;
+
+ setup_pin_mux(volume_keys_pin_mux);
+ err = platform_device_register(&am335x_evm_volume_keys);
+ if (err)
+ pr_err("failed to register matrix keypad (2x3) device\n");
+}
+
+/* pinmux for lcd7 keys */
+static struct pinmux_config lcd7_keys_pin_mux[] = {
+ {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"gpmc_a1.gpio1_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"gpmc_a3.gpio1_19", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"mcasp0_axr0.gpio3_16", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"mcasp0_fsr.gpio3_19", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {NULL, 0},
+};
+
+/* Configure GPIOs for lcd7 keys */
+static struct gpio_keys_button beaglebone_lcd7_gpio_keys[] = {
+ {
+ .code = KEY_LEFT,
+ .gpio = GPIO_TO_PIN(1, 16),
+ .active_low = true,
+ .desc = "left",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+ {
+ .code = KEY_RIGHT,
+ .gpio = GPIO_TO_PIN(1, 17),
+ .active_low = true,
+ .desc = "right",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+ {
+ .code = KEY_UP,
+ .gpio = GPIO_TO_PIN(1, 19),
+ .active_low = true,
+ .desc = "up",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+ {
+ .code = KEY_DOWN,
+ .gpio = GPIO_TO_PIN(3, 16),
+ .active_low = true,
+ .desc = "down",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+ {
+ .code = KEY_ENTER,
+ .gpio = GPIO_TO_PIN(3, 19),
+ .active_low = true,
+ .desc = "enter",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+};
+
+static struct gpio_keys_platform_data beaglebone_lcd7_gpio_key_info = {
+ .buttons = beaglebone_lcd7_gpio_keys,
+ .nbuttons = ARRAY_SIZE(beaglebone_lcd7_gpio_keys),
+};
+
+static struct platform_device beaglebone_lcd7_keys = {
+ .name = "gpio-keys",
+ .id = -1,
+ .dev = {
+ .platform_data = &beaglebone_lcd7_gpio_key_info,
+ },
+};
+
+static void beaglebone_lcd7_keys_init(int evm_id, int profile)
+{
+ int err;
+ setup_pin_mux(lcd7_keys_pin_mux);
+ err = platform_device_register(&beaglebone_lcd7_keys);
+ if (err)
+ pr_err("failed to register gpio keys for LCD7 cape\n");
+}
+
+/* pinmux for lcd3 keys */
+static struct pinmux_config lcd3_keys_pin_mux[] = {
+ {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"gpmc_a1.gpio1_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"mcasp0_fsr.gpio3_19", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"gpmc_ben1.gpio1_28", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"ecap0_in_pwm0_out.gpio0_7", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {NULL, 0},
+};
+
+/* Configure GPIOs for lcd3 keys */
+static struct gpio_keys_button beaglebone_lcd3_gpio_keys[] = {
+ {
+ .code = KEY_LEFT,
+ .gpio = GPIO_TO_PIN(1, 16),
+ .active_low = true,
+ .desc = "left",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+ {
+ .code = KEY_RIGHT,
+ .gpio = GPIO_TO_PIN(1, 17),
+ .active_low = true,
+ .desc = "right",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+ {
+ .code = KEY_UP,
+ .gpio = GPIO_TO_PIN(3, 19),
+ .active_low = true,
+ .desc = "up",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+ {
+ .code = KEY_DOWN,
+ .gpio = GPIO_TO_PIN(1, 28),
+ .active_low = true,
+ .desc = "down",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+ {
+ .code = KEY_ENTER,
+ .gpio = GPIO_TO_PIN(0, 7),
+ .active_low = true,
+ .desc = "down",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+};
+
+static struct gpio_keys_platform_data beaglebone_lcd3_gpio_key_info = {
+ .buttons = beaglebone_lcd3_gpio_keys,
+ .nbuttons = ARRAY_SIZE(beaglebone_lcd3_gpio_keys),
+};
+
+static struct platform_device beaglebone_lcd3_keys = {
+ .name = "gpio-keys",
+ .id = -1,
+ .dev = {
+ .platform_data = &beaglebone_lcd3_gpio_key_info,
+ },
+};
+
+static void beaglebone_lcd3_keys_init(int evm_id, int profile)
+{
+ int err;
+ setup_pin_mux(lcd3_keys_pin_mux);
+ err = platform_device_register(&beaglebone_lcd3_keys);
+ if (err)
+ pr_err("failed to register gpio keys for LCD3 cape\n");
+}
+
+/*
+* @evm_id - evm id which needs to be configured
+* @dev_cfg - single evm structure which includes
+* all module inits, pin-mux defines
+* @profile - if present, else PROFILE_NONE
+* @dghtr_brd_flg - Whether Daughter board is present or not
+*/
+static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
+ int profile)
+{
+ int i;
+
+ /*
+ * Only General Purpose & Industrial Auto Motro Control
+ * EVM has profiles. So check if this evm has profile.
+ * If not, ignore the profile comparison
+ */
+
+ /*
+ * If the device is on baseboard, directly configure it. Else (device on
+ * Daughter board), check if the daughter card is detected.
+ */
+ if (profile == PROFILE_NONE) {
+ for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
+ if (dev_cfg->device_on == DEV_ON_BASEBOARD)
+ dev_cfg->device_init(evm_id, profile);
+ else if (daughter_brd_detected == true)
+ dev_cfg->device_init(evm_id, profile);
+ }
+ } else {
+ for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
+ if (dev_cfg->profile & profile) {
+ if (dev_cfg->device_on == DEV_ON_BASEBOARD)
+ dev_cfg->device_init(evm_id, profile);
+ else if (daughter_brd_detected == true)
+ dev_cfg->device_init(evm_id, profile);
+ }
+ }
+ }
+}
+
+
+/* pinmux for usb0 drvvbus */
+static struct pinmux_config usb0_pin_mux[] = {
+ {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+/* pinmux for usb1 drvvbus */
+static struct pinmux_config usb1_pin_mux[] = {
+ {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+/* pinmux for profibus */
+static struct pinmux_config profibus_pin_mux[] = {
+ {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
+ {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
+ {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+#define BEAGLEBONE_W1_GPIO GPIO_TO_PIN(1, 3)
+
+static struct w1_gpio_platform_data bone_w1_gpio_pdata = {
+ .pin = BEAGLEBONE_W1_GPIO,
+ .is_open_drain = 0,
+};
+
+static struct platform_device bone_w1_device = {
+ .name = "w1-gpio",
+ .id = -1,
+ .dev.platform_data = &bone_w1_gpio_pdata,
+};
+
+/* LEDS - gpio1_21 -> gpio1_24 */
+
+#define BEAGLEBONE_USR1_LED GPIO_TO_PIN(1, 21)
+#define BEAGLEBONE_USR2_LED GPIO_TO_PIN(1, 22)
+#define BEAGLEBONE_USR3_LED GPIO_TO_PIN(1, 23)
+#define BEAGLEBONE_USR4_LED GPIO_TO_PIN(1, 24)
+
+static struct gpio_led bone_gpio_leds[] = {
+ {
+ .name = "beaglebone::usr0",
+ .default_trigger = "heartbeat",
+ .gpio = BEAGLEBONE_USR1_LED,
+ },
+ {
+ .name = "beaglebone::usr1",
+ .default_trigger = "mmc0",
+ .gpio = BEAGLEBONE_USR2_LED,
+ },
+ {
+ .name = "beaglebone::usr2",
+ .gpio = BEAGLEBONE_USR3_LED,
+ },
+ {
+ .name = "beaglebone::usr3",
+ .gpio = BEAGLEBONE_USR4_LED,
+ },
+};
+
+static struct gpio_led_platform_data bone_gpio_led_info = {
+ .leds = bone_gpio_leds,
+ .num_leds = ARRAY_SIZE(bone_gpio_leds),
+};
+
+static struct platform_device bone_leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &bone_gpio_led_info,
+ },
+};
+
+
+#define BEAGLEBONEDVI_USR0_LED GPIO_TO_PIN(1, 18)
+#define BEAGLEBONEDVI_USR1_LED GPIO_TO_PIN(1, 19)
+
+static struct gpio_led dvi_gpio_leds[] = {
+ {
+ .name = "beaglebone::usr0",
+ .default_trigger = "heartbeat",
+ .gpio = BEAGLEBONE_USR1_LED,
+ },
+ {
+ .name = "beaglebone::usr1",
+ .default_trigger = "mmc0",
+ .gpio = BEAGLEBONE_USR2_LED,
+ },
+ {
+ .name = "beaglebone::usr2",
+ .gpio = BEAGLEBONE_USR3_LED,
+ },
+ {
+ .name = "beaglebone::usr3",
+ .gpio = BEAGLEBONE_USR4_LED,
+ },
+ {
+ .name = "dvi::usr0",
+ .default_trigger = "heartbeat",
+ .gpio = BEAGLEBONEDVI_USR0_LED,
+ },
+ {
+ .name = "dvi::usr1",
+ .default_trigger = "mmc0",
+ .gpio = BEAGLEBONEDVI_USR1_LED,
+ },
+};
+
+static struct gpio_led_platform_data dvi_gpio_led_info = {
+ .leds = dvi_gpio_leds,
+ .num_leds = ARRAY_SIZE(dvi_gpio_leds),
+};
+
+static struct platform_device dvi_leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &dvi_gpio_led_info,
+ },
+};
+
+static struct pinmux_config bone_pin_mux[] = {
+ /* User LED gpios (gpio1_21 to gpio1_24) */
+ {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ /* Grounding gpio1_6 (pin 3 Conn A) signals bone tester to start diag tests */
+ {"gpmc_ad6.gpio1_6", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+};
+
+/* Module pin mux for eCAP0 */
+static struct pinmux_config ecap0_pin_mux[] = {
+ {"ecap0_in_pwm0_out.ecap0_in_pwm0_out",
+ OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+static int ehrpwm_backlight_enable;
+static int backlight_enable;
+
+#define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30)
+#define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
+
+struct wl12xx_platform_data am335xevm_wlan_data = {
+ .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
+ .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
+};
+
+/* Module pin mux for wlan and bluetooth */
+static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
+ {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config uart1_wl12xx_pin_mux[] = {
+ {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
+ {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
+ {NULL, 0},
+};
+
+static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
+ {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+ };
+
+static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
+ {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+ };
+
+static void enable_ecap0(int evm_id, int profile)
+{
+ backlight_enable = true;
+ setup_pin_mux(ecap0_pin_mux);
+}
+
+/* Setup pwm-backlight */
+static struct platform_device am335x_backlight = {
+ .name = "pwm-backlight",
+ .id = -1,
+ .dev = {
+ .platform_data = &am335x_backlight_data,
+ }
+};
+
+static struct pwmss_platform_data pwm_pdata[3] = {
+ {
+ .version = PWM_VERSION_1,
+ },
+ {
+ .version = PWM_VERSION_1,
+ },
+ {
+ .version = PWM_VERSION_1,
+ },
+};
+
+static int __init ecap0_init(void)
+{
+ int status = 0;
+
+ if (backlight_enable) {
+ am33xx_register_ecap(0, &pwm_pdata[0]);
+ platform_device_register(&am335x_backlight);
+ }
+ return status;
+}
+late_initcall(ecap0_init);
+
+static void enable_ehrpwm1(int evm_id, int profile)
+{
+ ehrpwm_backlight_enable = true;
+ am33xx_register_ehrpwm(1, &pwm_pdata[1]);
+}
+
+/* Setup pwm-backlight for bbtoys7lcd */
+static struct platform_device bbtoys7lcd_backlight = {
+ .name = "pwm-backlight",
+ .id = -1,
+ .dev = {
+ .platform_data = &bbtoys7lcd_backlight_data,
+ }
+};
+
+static int __init ehrpwm1_init(void)
+{
+ int status = 0;
+ if (ehrpwm_backlight_enable) {
+ platform_device_register(&bbtoys7lcd_backlight);
+ }
+ return status;
+}
+late_initcall(ehrpwm1_init);
+
+static int __init conf_disp_pll(int rate)
+{
+ struct clk *disp_pll;
+ int ret = -EINVAL;
+
+ disp_pll = clk_get(NULL, "dpll_disp_ck");
+ if (IS_ERR(disp_pll)) {
+ pr_err("Cannot clk_get disp_pll\n");
+ goto out;
+ }
+
+ ret = clk_set_rate(disp_pll, rate);
+ clk_put(disp_pll);
+out:
+ return ret;
+}
+
+static void lcdc_init(int evm_id, int profile)
+{
+
+ setup_pin_mux(lcdc_pin_mux);
+
+ if (conf_disp_pll(300000000)) {
+ pr_info("Failed configure display PLL, not attempting to"
+ "register LCDC\n");
+ return;
+ }
+
+ if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
+ pr_info("Failed to register LCDC device\n");
+ return;
+}
+
+#define BEAGLEBONE_LCD_AVDD_EN GPIO_TO_PIN(0, 7)
+
+static void bbtoys7lcd_init(int evm_id, int profile)
+{
+ setup_pin_mux(bbtoys7_pin_mux);
+ gpio_request(BEAGLEBONE_LCD_AVDD_EN, "BONE_LCD_AVDD_EN");
+ gpio_direction_output(BEAGLEBONE_LCD_AVDD_EN, 1);
+
+ // we are being stupid and setting pixclock from here instead of da8xx-fb.c
+ if (conf_disp_pll(300000000)) {
+ pr_info("Failed to set pixclock to 300000000, not attempting to"
+ "register LCD cape\n");
+ return;
+ }
+
+ if (am33xx_register_lcdc(&bbtoys7_pdata))
+ pr_info("Failed to register Beagleboardtoys 7\" LCD cape device\n");
+
+ return;
+}
+
+static void bbtoys35lcd_init(int evm_id, int profile)
+{
+ setup_pin_mux(bbtoys7_pin_mux);
+
+ // we are being stupid and setting pixclock from here instead of da8xx-fb.c
+ if (conf_disp_pll(16000000)) {
+ pr_info("Failed to set pixclock to 16000000, not attempting to"
+ "register LCD cape\n");
+ return;
+ }
+
+ if (am33xx_register_lcdc(&bbtoys35_pdata))
+ pr_info("Failed to register Beagleboardtoys 3.5\" LCD cape device\n");
+
+ return;
+}
+
+#define BEAGLEBONEDVI_PDn GPIO_TO_PIN(1, 7)
+
+static void dvi_init(int evm_id, int profile)
+{
+ setup_pin_mux(dvi_pin_mux);
+ gpio_request(BEAGLEBONEDVI_PDn, "DVI_PDn");
+ gpio_direction_output(BEAGLEBONEDVI_PDn, 1);
+
+ // we are being stupid and setting pixclock from here instead of da8xx-fb.c
+ if (conf_disp_pll(560000000)) {
+ pr_info("Failed to set pixclock to 56000000, not attempting to"
+ "register DVI adapter\n");
+ return;
+ }
+
+ if (am33xx_register_lcdc(&dvi_pdata))
+ pr_info("Failed to register BeagleBoardToys DVI cape\n");
+ return;
+}
+
+static void tsc_init(int evm_id, int profile)
+{
+ int err;
+
+ if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
+ am335x_touchscreen_data.analog_input = 1;
+ pr_info("TSC connected to beta GP EVM\n");
+ }
+ if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
+ am335x_touchscreen_data.analog_input = 0;
+ pr_info("TSC connected to alpha GP EVM\n");
+ }
+ if( gp_evm_revision == GP_EVM_ACTUALLY_BEAGLEBONE) {
+ am335x_touchscreen_data.analog_input = 1;
+ pr_info("TSC connected to BeagleBone\n");;
+ }
+ setup_pin_mux(tsc_pin_mux);
+
+ err = am33xx_register_tsc(&am335x_touchscreen_data);
+ if (err)
+ pr_err("failed to register touchscreen device\n");
+}
+
+static void bone_tsc_init(int evm_id, int profile)
+{
+ int err;
+ setup_pin_mux(tsc_pin_mux);
+ err = am33xx_register_tsc(&bone_touchscreen_data);
+ if (err)
+ pr_err("failed to register touchscreen device\n");
+}
+
+
+static void boneleds_init(int evm_id, int profile )
+{
+ int err;
+ setup_pin_mux(bone_pin_mux);
+ err = platform_device_register(&bone_leds_gpio);
+ if (err)
+ pr_err("failed to register BeagleBone LEDS\n");
+}
+
+static void dvileds_init(int evm_id, int profile )
+{
+ int err;
+ err = platform_device_register(&dvi_leds_gpio);
+ if (err)
+ pr_err("failed to register BeagleBone DVI cape LEDS\n");
+}
+
+static void bonew1_gpio_init(int evm_id, int profile )
+{
+ int err;
+ setup_pin_mux(w1_gpio_pin_mux);
+ err = platform_device_register(&bone_w1_device);
+ if (err)
+ pr_err("failed to register w1-gpio\n");
+ else
+ pr_info("w1-gpio connected to P8_6\n");
+}
+
+static void rgmii1_init(int evm_id, int profile)
+{
+ setup_pin_mux(rgmii1_pin_mux);
+ return;
+}
+
+static void rgmii2_init(int evm_id, int profile)
+{
+ setup_pin_mux(rgmii2_pin_mux);
+ return;
+}
+
+static void mii1_init(int evm_id, int profile)
+{
+ setup_pin_mux(mii1_pin_mux);
+ return;
+}
+
+static void rmii1_init(int evm_id, int profile)
+{
+ setup_pin_mux(rmii1_pin_mux);
+ return;
+}
+
+static void usb0_init(int evm_id, int profile)
+{
+ setup_pin_mux(usb0_pin_mux);
+ return;
+}
+
+static void usb1_init(int evm_id, int profile)
+{
+ setup_pin_mux(usb1_pin_mux);
+ return;
+}
+
+/* setup uart3 */
+static void uart3_init(int evm_id, int profile)
+{
+ setup_pin_mux(uart3_pin_mux);
+ return;
+}
+
+/* setup uart2 */
+static void uart2_init(int evm_id, int profile)
+{
+ setup_pin_mux(uart2_pin_mux);
+ return;
+}
+
+/* setup haptics */
+#define HAPTICS_MAX_FREQ 250
+static void haptics_init(int evm_id, int profile)
+{
+ setup_pin_mux(haptics_pin_mux);
+ pwm_pdata[2].chan_attrib[1].max_freq = HAPTICS_MAX_FREQ;
+ am33xx_register_ehrpwm(2, &pwm_pdata[2]);
+}
+
+/* NAND partition information */
+static struct mtd_partition am335x_nand_partitions[] = {
+/* All the partition sizes are listed in terms of NAND block size */
+ {
+ .name = "SPL",
+ .offset = 0, /* Offset = 0x0 */
+ .size = SZ_128K,
+ },
+ {
+ .name = "SPL.backup1",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
+ .size = SZ_128K,
+ },
+ {
+ .name = "SPL.backup2",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
+ .size = SZ_128K,
+ },
+ {
+ .name = "SPL.backup3",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
+ .size = SZ_128K,
+ },
+ {
+ .name = "U-Boot",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
+ .size = 15 * SZ_128K,
+ },
+ {
+ .name = "U-Boot Env",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
+ .size = 1 * SZ_128K,
+ },
+ {
+ .name = "Kernel",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
+ .size = 40 * SZ_128K,
+ },
+ {
+ .name = "File System",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+/* SPI 0/1 Platform Data */
+/* SPI flash information */
+static struct mtd_partition am335x_spi_partitions[] = {
+ /* All the partition sizes are listed in terms of erase size */
+ {
+ .name = "SPL",
+ .offset = 0, /* Offset = 0x0 */
+ .size = SZ_128K,
+ },
+ {
+ .name = "U-Boot",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
+ .size = 2 * SZ_128K,
+ },
+ {
+ .name = "U-Boot Env",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
+ .size = 2 * SZ_4K,
+ },
+ {
+ .name = "Kernel",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x62000 */
+ .size = 28 * SZ_128K,
+ },
+ {
+ .name = "File System",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x3E2000 */
+ .size = MTDPART_SIZ_FULL, /* size ~= 4.1 MiB */
+ }
+};
+
+static const struct flash_platform_data am335x_spi_flash = {
+ .type = "w25q64",
+ .name = "spi_flash",
+ .parts = am335x_spi_partitions,
+ .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
+};
+
+/*
+ * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
+ * So setup Max speed to be less than that of Controller speed
+ */
+static struct spi_board_info am335x_spi0_slave_info[] = {
+ {
+ .modalias = "m25p80",
+ .platform_data = &am335x_spi_flash,
+ .irq = -1,
+ .max_speed_hz = 24000000,
+ .bus_num = 1,
+ .chip_select = 0,
+ },
+};
+
+static struct spi_board_info am335x_spi1_slave_info[] = {
+ {
+ .modalias = "m25p80",
+ .platform_data = &am335x_spi_flash,
+ .irq = -1,
+ .max_speed_hz = 12000000,
+ .bus_num = 2,
+ .chip_select = 0,
+ },
+};
+
+static struct gpmc_timings am335x_nand_timings = {
+ .sync_clk = 0,
+
+ .cs_on = 0,
+ .cs_rd_off = 44,
+ .cs_wr_off = 44,
+
+ .adv_on = 6,
+ .adv_rd_off = 34,
+ .adv_wr_off = 44,
+ .we_off = 40,
+ .oe_off = 54,
+
+ .access = 64,
+ .rd_cycle = 82,
+ .wr_cycle = 82,
+
+ .wr_access = 40,
+ .wr_data_mux_bus = 0,
+};
+
+static void evm_nand_init(int evm_id, int profile)
+{
+ struct omap_nand_platform_data *pdata;
+ struct gpmc_devices_info gpmc_device[2] = {
+ { NULL, 0 },
+ { NULL, 0 },
+ };
+
+ setup_pin_mux(nand_pin_mux);
+ pdata = omap_nand_init(am335x_nand_partitions,
+ ARRAY_SIZE(am335x_nand_partitions), 0, 0,
+ &am335x_nand_timings);
+ if (!pdata)
+ return;
+ pdata->ecc_opt =OMAP_ECC_BCH8_CODE_HW;
+ pdata->elm_used = true;
+ gpmc_device[0].pdata = pdata;
+ gpmc_device[0].flag = GPMC_DEVICE_NAND;
+
+ omap_init_gpmc(gpmc_device, sizeof(gpmc_device));
+ omap_init_elm();
+}
+
+/* TPS65217 voltage regulator support */
+
+/* 1.8V */
+static struct regulator_consumer_supply tps65217_dcdc1_consumers[] = {
+ {
+ .supply = "vdds_osc",
+ },
+ {
+ .supply = "vdds_pll_ddr",
+ },
+ {
+ .supply = "vdds_pll_mpu",
+ },
+ {
+ .supply = "vdds_pll_core_lcd",
+ },
+ {
+ .supply = "vdds_sram_mpu_bb",
+ },
+ {
+ .supply = "vdds_sram_core_bg",
+ },
+ {
+ .supply = "vdda_usb0_1p8v",
+ },
+ {
+ .supply = "vdds_ddr",
+ },
+ {
+ .supply = "vdds",
+ },
+ {
+ .supply = "vdds_hvx_1p8v",
+ },
+ {
+ .supply = "vdda_adc",
+ },
+ {
+ .supply = "ddr2",
+ },
+};
+
+/* 1.1V */
+static struct regulator_consumer_supply tps65217_dcdc2_consumers[] = {
+ {
+ .supply = "vdd_mpu",
+ },
+};
+
+/* 1.1V */
+static struct regulator_consumer_supply tps65217_dcdc3_consumers[] = {
+ {
+ .supply = "vdd_core",
+ },
+};
+
+/* 1.8V LDO */
+static struct regulator_consumer_supply tps65217_ldo1_consumers[] = {
+ {
+ .supply = "vdds_rtc",
+ },
+};
+
+/* 3.3V LDO */
+static struct regulator_consumer_supply tps65217_ldo2_consumers[] = {
+ {
+ .supply = "vdds_any_pn",
+ },
+};
+
+/* 3.3V LDO */
+static struct regulator_consumer_supply tps65217_ldo3_consumers[] = {
+ {
+ .supply = "vdds_hvx_ldo3_3p3v",
+ },
+ {
+ .supply = "vdda_usb0_3p3v",
+ },
+};
+
+/* 3.3V LDO */
+static struct regulator_consumer_supply tps65217_ldo4_consumers[] = {
+ {
+ .supply = "vdds_hvx_ldo4_3p3v",
+ },
+};
+
+static struct regulator_init_data tps65217_regulator_data[] = {
+ /* dcdc1 */
+ {
+ .constraints = {
+ .min_uV = 900000,
+ .max_uV = 1800000,
+ .boot_on = 1,
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc1_consumers),
+ .consumer_supplies = tps65217_dcdc1_consumers,
+ },
+
+ /* dcdc2 */
+ {
+ .constraints = {
+ .min_uV = 900000,
+ .max_uV = 3300000,
+ .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS),
+ .boot_on = 1,
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc2_consumers),
+ .consumer_supplies = tps65217_dcdc2_consumers,
+ },
+
+ /* dcdc3 */
+ {
+ .constraints = {
+ .min_uV = 900000,
+ .max_uV = 1500000,
+ .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS),
+ .boot_on = 1,
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc3_consumers),
+ .consumer_supplies = tps65217_dcdc3_consumers,
+ },
+
+ /* ldo1 */
+ {
+ .constraints = {
+ .min_uV = 1000000,
+ .max_uV = 3300000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .boot_on = 1,
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo1_consumers),
+ .consumer_supplies = tps65217_ldo1_consumers,
+ },
+
+ /* ldo2 */
+ {
+ .constraints = {
+ .min_uV = 900000,
+ .max_uV = 3300000,
+ .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS),
+ .boot_on = 1,
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo2_consumers),
+ .consumer_supplies = tps65217_ldo2_consumers,
+ },
+
+ /* ldo3 */
+ {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 3300000,
+ .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS),
+ .boot_on = 1,
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo3_consumers),
+ .consumer_supplies = tps65217_ldo3_consumers,
+ },
+
+ /* ldo4 */
+ {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 3300000,
+ .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS),
+ .boot_on = 1,
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(tps65217_ldo4_consumers),
+ .consumer_supplies = tps65217_ldo4_consumers,
+ },
+};
+
+static struct tps65217_board beaglebone_tps65217_info = {
+ .tps65217_init_data = &tps65217_regulator_data[0],
+};
+
+static struct lis3lv02d_platform_data lis331dlh_pdata = {
+ .click_flags = LIS3_CLICK_SINGLE_X |
+ LIS3_CLICK_SINGLE_Y |
+ LIS3_CLICK_SINGLE_Z,
+ .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
+ LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
+ LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
+ .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
+ .wakeup_thresh = 10,
+ .click_thresh_x = 10,
+ .click_thresh_y = 10,
+ .click_thresh_z = 10,
+ .g_range = 2,
+ .st_min_limits[0] = 120,
+ .st_min_limits[1] = 120,
+ .st_min_limits[2] = 140,
+ .st_max_limits[0] = 550,
+ .st_max_limits[1] = 550,
+ .st_max_limits[2] = 750,
+};
+
+static struct i2c_board_info am335x_i2c_boardinfo1[] = {
+ {
+ I2C_BOARD_INFO("tlv320aic3x", 0x1b),
+ },
+ {
+ I2C_BOARD_INFO("lis331dlh", 0x18),
+ .platform_data = &lis331dlh_pdata,
+ },
+ {
+ I2C_BOARD_INFO("tsl2550", 0x39),
+ },
+ {
+ I2C_BOARD_INFO("tmp275", 0x48),
+ },
+};
+
+static void i2c1_init(int evm_id, int profile)
+{
+ setup_pin_mux(i2c1_pin_mux);
+ omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
+ ARRAY_SIZE(am335x_i2c_boardinfo1));
+ return;
+}
+
+static struct mcp251x_platform_data mcp251x_info = {
+ .oscillator_frequency = 16000000,
+};
+
+static struct spi_board_info tt3201_spi_info[] = {
+ {
+ .modalias = "mcp2515",
+ .max_speed_hz = 10000000,
+ .bus_num = 2,
+ .chip_select = 0,
+ .mode = SPI_MODE_0,
+ .platform_data = &mcp251x_info,
+ },
+ {
+ .modalias = "mcp2515",
+ .max_speed_hz = 10000000,
+ .bus_num = 2,
+ .chip_select = 1,
+ .mode = SPI_MODE_0,
+ .platform_data = &mcp251x_info,
+ },
+};
+
+static void tt3201_init(int evm_id, int profile)
+{
+ pr_info("TowerTech TT3201 CAN Cape\n");
+
+ setup_pin_mux(spi1_pin_mux);
+ setup_pin_mux(tt3201_pin_mux);
+
+ tt3201_spi_info[0].irq = gpio_to_irq(GPIO_TO_PIN(3, 19));
+ tt3201_spi_info[1].irq = gpio_to_irq(GPIO_TO_PIN(3, 21));
+
+ spi_register_board_info(tt3201_spi_info,
+ ARRAY_SIZE(tt3201_spi_info));
+
+ am33xx_d_can_init(1);
+}
+static void beaglebone_cape_setup(struct memory_accessor *mem_acc, void *context)
+{
+ capecount++;
+ int ret;
+ char tmp[32];
+ char name[32];
+ char version[4];
+ char manufacturer[32];
+
+ /* get cape specific data */
+ ret = mem_acc->read(mem_acc, (char *)&cape_config, 0, sizeof(cape_config));
+ if (ret != sizeof(cape_config)) {
+ pr_warning("BeagleBone cape EEPROM: could not read eeprom at address 0x%x\n", capecount + 0x53);
+ if ((capecount > 3) && (beaglebone_tsadcpins_free == 1)) {
+ pr_info("BeagleBone cape: exporting ADC pins to sysfs\n");
+ bone_tsc_init(0,0);
+ beaglebone_tsadcpins_free = 0;
+ }
+ return;
+ }
+
+ if (cape_config.header != AM335X_EEPROM_HEADER) {
+ pr_warning("BeagleBone Cape EEPROM: wrong header 0x%x, expected 0x%x\n",
+ cape_config.header, AM335X_EEPROM_HEADER);
+ goto out;
+ }
+
+ pr_info("BeagleBone cape EEPROM: found eeprom at address 0x%x\n", capecount + 0x53);
+ snprintf(name, sizeof(cape_config.name) + 1, "%s", cape_config.name);
+ snprintf(version, sizeof(cape_config.version) + 1, "%s", cape_config.version);
+ snprintf(manufacturer, sizeof(cape_config.manufacturer) + 1, "%s", cape_config.manufacturer);
+ pr_info("BeagleBone cape: %s %s, revision %s\n", manufacturer, name, version);
+ snprintf(tmp, sizeof(cape_config.partnumber) + 1, "%s", cape_config.partnumber);
+ pr_info("BeagleBone cape partnumber: %s\n", tmp);
+
+ if (!strncmp("BB-BONE-DVID-01", cape_config.partnumber, 15)) {
+ pr_info("BeagleBone cape: initializing DVI cape\n");
+ dvi_init(0,0);
+ }
+ if (!strncmp("BB-BONE-LCD7-01", cape_config.partnumber, 15)) {
+ pr_info("BeagleBone cape: initializing LCD cape\n");
+ bbtoys7lcd_init(0,0);
+ pr_info("BeagleBone cape: initializing LCD cape touchscreen\n");
+ tsc_init(0,0);
+ pr_info("BeagleBone cape: Registering PWM backlight for LCD cape\n");
+ enable_ehrpwm1(0,0);
+ beaglebone_tsadcpins_free = 0;
+ pr_info("BeagleBone cape: Registering gpio-keys for LCD cape\n");
+ beaglebone_lcd7_keys_init(0,0);
+ }
+
+ if (!strncmp("BB-BONE-LCD3-01", cape_config.partnumber, 15)) {
+ pr_info("BeagleBone cape: initializing LCD cape\n");
+ bbtoys35lcd_init(0,0);
+ pr_info("BeagleBone cape: initializing LCD cape touchscreen\n");
+ tsc_init(0,0);
+ beaglebone_tsadcpins_free = 0;
+ pr_info("BeagleBone cape: Registering gpio-keys for LCD cape\n");
+ beaglebone_lcd3_keys_init(0,0);
+ }
+
+ if (!strncmp("BB-BONE-VGA-01", cape_config.partnumber, 14)) {
+ pr_info("BeagleBone cape: initializing VGA cape\n");
+ dvi_init(0,0);
+ }
+
+ if (!strncmp("BB-BONE-BATT-01", cape_config.partnumber, 15)) {
+ pr_info("BeagleBone cape: initializing battery cape\n");
+ // gpio1_6, P9_15 lowbat output
+ // AIN4, P9_33 vbat
+ //foo_init(0,0);
+ }
+
+ if (!strncmp("BB-BONE-SERL", cape_config.partnumber, 12)) {
+ pr_info("BeagleBone cape: initializing serial cape\n");
+ // 01 -> CAN
+ // 02 -> Profibus
+ // 03 -> RS232
+ // 04 -> RS485
+ //foo_init(0,0);
+ }
+
+ if (!strncmp("TT3201-001", cape_config.partnumber, 10)) {
+ pr_info("BeagleBone cape: initializing CAN cape\n");
+ tt3201_init(0,0);
+ }
+
+ if ((capecount > 3) && (beaglebone_tsadcpins_free == 1)) {
+ pr_info("BeagleBone cape: exporting ADC pins to sysfs\n");
+ bone_tsc_init(0,0);
+ beaglebone_tsadcpins_free = 0;
+ }
+
+ return;
+out:
+ /*
+ * If the EEPROM hasn't been programed or an incorrect header
+ * or board name are read, assume this is an old beaglebone board
+ * (< Rev A3)
+ */
+ pr_err("Could not detect BeagleBone cape properly\n");
+ beaglebone_cape_detected = false;
+
+}
+
+static struct at24_platform_data cape_eeprom_info = {
+ .byte_len = (256*1024) / 8,
+ .page_size = 64,
+ .flags = AT24_FLAG_ADDR16,
+ .context = (void *)NULL,
+ .setup = beaglebone_cape_setup,
+};
+
+static struct i2c_board_info __initdata cape_i2c_boardinfo[] = {
+ {
+ I2C_BOARD_INFO("24c256", 0x54),
+ .platform_data = &cape_eeprom_info,
+ },
+ {
+ I2C_BOARD_INFO("24c256", 0x55),
+ .platform_data = &cape_eeprom_info,
+ },
+ {
+ I2C_BOARD_INFO("24c256", 0x56),
+ .platform_data = &cape_eeprom_info,
+ },
+ {
+ I2C_BOARD_INFO("24c256", 0x57),
+ .platform_data = &cape_eeprom_info,
+ },
+};
+
+static void i2c2_init(int evm_id, int profile)
+{
+ setup_pin_mux(i2c2_pin_mux);
+ omap_register_i2c_bus(3, 100, cape_i2c_boardinfo,
+ ARRAY_SIZE(cape_i2c_boardinfo));
+ return;
+}
+
+
+/* Setup McASP 1 */
+static void mcasp1_init(int evm_id, int profile)
+{
+ /* Configure McASP */
+ setup_pin_mux(mcasp1_pin_mux);
+ am335x_register_mcasp(&am335x_evm_snd_data1, 1);
+ return;
+}
+
+static void mmc1_init(int evm_id, int profile)
+{
+ setup_pin_mux(mmc1_pin_mux);
+
+ am335x_mmc[1].mmc = 2;
+ am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
+ am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
+ am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
+ am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
+
+ /* mmc will be initialized when mmc0_init is called */
+ return;
+}
+
+static void mmc2_wl12xx_init(int evm_id, int profile)
+{
+ setup_pin_mux(mmc2_wl12xx_pin_mux);
+
+ am335x_mmc[1].mmc = 3;
+ am335x_mmc[1].name = "wl1271";
+ am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
+ | MMC_PM_KEEP_POWER;
+ am335x_mmc[1].nonremovable = true;
+ am335x_mmc[1].gpio_cd = -EINVAL;
+ am335x_mmc[1].gpio_wp = -EINVAL;
+ am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
+
+ /* mmc will be initialized when mmc0_init is called */
+ return;
+}
+
+static void uart1_wl12xx_init(int evm_id, int profile)
+{
+ setup_pin_mux(uart1_wl12xx_pin_mux);
+}
+
+static void wl12xx_bluetooth_enable(void)
+{
+ int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
+ "bt_en\n");
+ if (status < 0)
+ pr_err("Failed to request gpio for bt_enable");
+
+ pr_info("Configure Bluetooth Enable pin...\n");
+ gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
+}
+
+static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
+{
+ if (on) {
+ gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
+ mdelay(70);
+ }
+ else
+ gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
+
+ return 0;
+}
+
+static void wl12xx_init(int evm_id, int profile)
+{
+ struct device *dev;
+ struct omap_mmc_platform_data *pdata;
+ int ret;
+
+ /* Register WLAN and BT enable pins based on the evm board revision */
+ if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
+ am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
+ am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
+ }
+ else {
+ am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
+ am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
+ }
+
+ wl12xx_bluetooth_enable();
+
+ if (wl12xx_set_platform_data(&am335xevm_wlan_data))
+ pr_err("error setting wl12xx data\n");
+
+ dev = am335x_mmc[1].dev;
+ if (!dev) {
+ pr_err("wl12xx mmc device initialization failed\n");
+ goto out;
+ }
+
+ pdata = dev->platform_data;
+ if (!pdata) {
+ pr_err("Platfrom data of wl12xx device not set\n");
+ goto out;
+ }
+
+ ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
+ GPIOF_OUT_INIT_LOW, "wlan_en");
+ if (ret) {
+ pr_err("Error requesting wlan enable gpio: %d\n", ret);
+ goto out;
+ }
+
+ if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
+ setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
+ else
+ setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
+
+ pdata->slots[0].set_power = wl12xx_set_power;
+out:
+ return;
+}
+
+static void d_can_init(int evm_id, int profile)
+{
+ switch (evm_id) {
+ case IND_AUT_MTR_EVM:
+ if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
+ setup_pin_mux(d_can_ia_pin_mux);
+ /* Instance Zero */
+ am33xx_d_can_init(0);
+ }
+ break;
+ case GEN_PURP_EVM:
+ if (profile == PROFILE_1) {
+ setup_pin_mux(d_can_gp_pin_mux);
+ /* Instance One */
+ am33xx_d_can_init(1);
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+static void mmc0_init(int evm_id, int profile)
+{
+ setup_pin_mux(mmc0_pin_mux);
+
+ omap2_hsmmc_init(am335x_mmc);
+ return;
+}
+
+static struct i2c_board_info tps65217_i2c_boardinfo[] = {
+ {
+ I2C_BOARD_INFO("tps65217", TPS65217_I2C_ID),
+ .platform_data = &beaglebone_tps65217_info,
+ },
+};
+
+static void tps65217_init(int evm_id, int profile)
+{
+ struct i2c_adapter *adapter;
+ struct i2c_client *client;
+
+ /* I2C1 adapter request */
+ adapter = i2c_get_adapter(1);
+ if (!adapter) {
+ pr_err("failed to get adapter i2c1\n");
+ return;
+ }
+
+ client = i2c_new_device(adapter, tps65217_i2c_boardinfo);
+ if (!client)
+ pr_err("failed to register tps65217 to i2c1\n");
+
+ i2c_put_adapter(adapter);
+}
+
+static void mmc0_no_cd_init(int evm_id, int profile)
+{
+ setup_pin_mux(mmc0_no_cd_pin_mux);
+
+ omap2_hsmmc_init(am335x_mmc);
+ return;
+}
+
+
+/* setup spi0 */
+static void spi0_init(int evm_id, int profile)
+{
+ setup_pin_mux(spi0_pin_mux);
+ spi_register_board_info(am335x_spi0_slave_info,
+ ARRAY_SIZE(am335x_spi0_slave_info));
+ return;
+}
+
+/* setup spi1 */
+static void spi1_init(int evm_id, int profile)
+{
+ setup_pin_mux(spi1_pin_mux);
+ spi_register_board_info(am335x_spi1_slave_info,
+ ARRAY_SIZE(am335x_spi1_slave_info));
+ return;
+}
+
+
+static int beaglebone_phy_fixup(struct phy_device *phydev)
+{
+ phydev->supported &= ~(SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full);
+
+ return 0;
+}
+
+#if defined(CONFIG_TLK110_WORKAROUND) || \
+ defined(CONFIG_TLK110_WORKAROUND_MODULE)
+static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
+{
+ unsigned int val;
+
+ /* This is done as a workaround to support TLK110 rev1.0 phy */
+ val = phy_read(phydev, TLK110_COARSEGAIN_REG);
+ phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
+
+ val = phy_read(phydev, TLK110_LPFHPF_REG);
+ phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
+
+ val = phy_read(phydev, TLK110_SPAREANALOG_REG);
+ phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
+
+ val = phy_read(phydev, TLK110_VRCR_REG);
+ phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
+
+ val = phy_read(phydev, TLK110_SETFFE_REG);
+ phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
+
+ val = phy_read(phydev, TLK110_FTSP_REG);
+ phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
+
+ val = phy_read(phydev, TLK110_ALFATPIDL_REG);
+ phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
+
+ val = phy_read(phydev, TLK110_PSCOEF21_REG);
+ phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
+
+ val = phy_read(phydev, TLK110_PSCOEF3_REG);
+ phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
+
+ val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
+ phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
+
+ val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
+ phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
+
+ val = phy_read(phydev, TLK110_CFGPS_REG);
+ phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
+
+ val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
+ phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
+
+ val = phy_read(phydev, TLK110_SWSCR3_REG);
+ phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
+
+ val = phy_read(phydev, TLK110_SCFALLBACK_REG);
+ phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
+
+ val = phy_read(phydev, TLK110_PHYRCR_REG);
+ phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
+
+ return 0;
+}
+#endif
+
+static void profibus_init(int evm_id, int profile)
+{
+ setup_pin_mux(profibus_pin_mux);
+ return;
+}
+
+/* Low-Cost EVM */
+static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
+ {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {NULL, 0, 0},
+};
+
+/* General Purpose EVM */
+static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
+ {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
+ PROFILE_2 | PROFILE_7) },
+ {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
+ PROFILE_2 | PROFILE_7) },
+ {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
+ PROFILE_2 | PROFILE_7) },
+ {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
+ PROFILE_4 | PROFILE_6) },
+ {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {evm_nand_init, DEV_ON_DGHTR_BRD,
+ (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
+ {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
+ {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
+ {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
+ {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
+ PROFILE_5)},
+ {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
+ {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
+ {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
+ {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
+ PROFILE_5)},
+ {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
+ {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
+ {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
+ {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
+ {uart2_init, DEV_ON_DGHTR_BRD, PROFILE_3},
+ {haptics_init, DEV_ON_DGHTR_BRD, (PROFILE_4)},
+ {NULL, 0, 0},
+};
+
+/* Industrial Auto Motor Control EVM */
+static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
+ {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
+ {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
+ {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
+ {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
+ {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
+ {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {NULL, 0, 0},
+};
+
+/* IP-Phone EVM */
+static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
+ {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {NULL, 0, 0},
+};
+
+/* Beaglebone < Rev A3 */
+static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
+ {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {i2c2_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {boneleds_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {NULL, 0, 0},
+};
+
+/* Beaglebone Rev A3 and after */
+static struct evm_dev_cfg beaglebone_dev_cfg[] = {
+ {tps65217_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {i2c2_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {boneleds_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {bonew1_gpio_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {NULL, 0, 0},
+};
+
+static void setup_low_cost_evm(void)
+{
+ pr_info("The board is a AM335x Low Cost EVM.\n");
+
+ _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
+}
+
+static void setup_general_purpose_evm(void)
+{
+ u32 prof_sel = am335x_get_profile_selection();
+ pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
+
+ if (!strncmp("1.1A", config.version, 4)) {
+ pr_info("EVM version is %s\n", config.version);
+ gp_evm_revision = GP_EVM_REV_IS_1_1A;
+ } else if (!strncmp("1.0", config.version, 3)) {
+ gp_evm_revision = GP_EVM_REV_IS_1_0;
+ } else {
+ pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
+ gp_evm_revision = GP_EVM_REV_IS_1_1A;
+ }
+
+ if (gp_evm_revision == GP_EVM_REV_IS_1_0)
+ gigabit_enable = 0;
+ else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
+ gigabit_enable = 1;
+
+ _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
+}
+
+static void setup_ind_auto_motor_ctrl_evm(void)
+{
+ u32 prof_sel = am335x_get_profile_selection();
+
+ pr_info("The board is an industrial automation EVM in profile %d\n",
+ prof_sel);
+
+ /* Only Profile 0 is supported */
+ if ((1L << prof_sel) != PROFILE_0) {
+ pr_err("AM335X: Only Profile 0 is supported\n");
+ pr_err("Assuming profile 0 & continuing\n");
+ prof_sel = PROFILE_0;
+ }
+
+ _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
+ PROFILE_0);
+
+ /* Fillup global evmid */
+ am33xx_evmid_fillup(IND_AUT_MTR_EVM);
+
+ /* Initialize TLK110 PHY registers for phy version 1.0 */
+ am335x_tlk110_phy_init();
+
+
+}
+
+static void setup_ip_phone_evm(void)
+{
+ pr_info("The board is an IP phone EVM\n");
+
+ _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
+}
+
+/* BeagleBone < Rev A3 */
+static void setup_beaglebone_old(void)
+{
+ pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
+
+ /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
+ am335x_mmc[0].gpio_wp = -EINVAL;
+
+ _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
+
+ phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
+ beaglebone_phy_fixup);
+
+ /* Fill up global evmid */
+ am33xx_evmid_fillup(BEAGLE_BONE_OLD);
+}
+
+/* BeagleBone after Rev A3 */
+static void setup_beaglebone(void)
+{
+ pr_info("The board is a AM335x Beaglebone.\n");
+ gp_evm_revision = GP_EVM_ACTUALLY_BEAGLEBONE;
+
+ /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
+ am335x_mmc[0].gpio_wp = -EINVAL;
+
+ _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
+
+ /* TPS65217 regulator has full constraints */
+ regulator_has_full_constraints();
+
+ /* Fill up global evmid */
+ am33xx_evmid_fillup(BEAGLE_BONE_A3);
+}
+
+
+static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
+{
+ int ret;
+
+ /*
+ * Read from the EEPROM to see the presence of daughter board.
+ * If present, print the cpld version.
+ */
+
+ ret = m->read(m, (char *)&config1, 0, sizeof(config1));
+ if (ret == sizeof(config1)) {
+ pr_info("Detected a daughter card on AM335x EVM..");
+ daughter_brd_detected = true;
+ }
+ else {
+ pr_info("No daughter card found\n");
+ daughter_brd_detected = false;
+ return;
+ }
+
+ if (!strncmp("CPLD", config1.cpld_ver, 4))
+ pr_info("CPLD version: %s\n", config1.cpld_ver);
+ else
+ pr_err("Unknown CPLD version found\n");
+}
+
+static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
+{
+ int ret;
+ char tmp[10];
+
+ /* 1st get the MAC address from EEPROM */
+ ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
+ EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
+
+ if (ret != sizeof(am335x_mac_addr)) {
+ pr_warning("AM335X: EVM Config read fail: %d\n", ret);
+ return;
+ }
+
+ /* Fillup global mac id */
+ am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
+ &am335x_mac_addr[1][0]);
+
+ /* get board specific data */
+ ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
+ if (ret != sizeof(config)) {
+ pr_err("AM335X EVM config read fail, read %d bytes\n", ret);
+ pr_err("This likely means that there either is no/or a failed EEPROM\n");
+ goto out;
+ }
+
+ if (config.header != AM335X_EEPROM_HEADER) {
+ pr_err("AM335X: wrong header 0x%x, expected 0x%x\n",
+ config.header, AM335X_EEPROM_HEADER);
+ goto out;
+ }
+
+ if (strncmp("A335", config.name, 4)) {
+ pr_err("Board %s\ndoesn't look like an AM335x board\n",
+ config.name);
+ goto out;
+ }
+
+ snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
+ pr_info("Board name: %s\n", tmp);
+ snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
+ pr_info("Board version: %s\n", tmp);
+
+ if (!strncmp("A335BONE", config.name, 8)) {
+ daughter_brd_detected = false;
+ if(!strncmp("00A1", config.version, 4) ||
+ !strncmp("00A2", config.version, 4))
+ setup_beaglebone_old();
+ else
+ setup_beaglebone();
+ } else {
+ /* only 6 characters of options string used for now */
+ snprintf(tmp, 7, "%s", config.opt);
+ pr_info("SKU: %s\n", tmp);
+
+ if (!strncmp("SKU#00", config.opt, 6))
+ setup_low_cost_evm();
+ else if (!strncmp("SKU#01", config.opt, 6))
+ setup_general_purpose_evm();
+ else if (!strncmp("SKU#02", config.opt, 6))
+ setup_ind_auto_motor_ctrl_evm();
+ else if (!strncmp("SKU#03", config.opt, 6))
+ setup_ip_phone_evm();
+ else
+ goto out;
+ }
+ /* Initialize cpsw after board detection is completed as board
+ * information is required for configuring phy address and hence
+ * should be call only after board detection
+ */
+ am33xx_cpsw_init(gigabit_enable);
+
+ return;
+
+out:
+ /*
+ * If the EEPROM hasn't been programed or an incorrect header
+ * or board name are read then the hardware details are unknown.
+ * Notify the user and call machine_halt to stop the boot process.
+ */
+ pr_err("The error message above indicates that there is an issue with\n"
+ "the EEPROM or the EEPROM contents. After verifying the EEPROM\n"
+ "contents, if any, refer to the %s function in the\n"
+ "%s file to modify the board\n"
+ "initialization code to match the hardware configuration\n",
+ __func__ , __FILE__);
+ machine_halt();
+}
+
+static struct at24_platform_data am335x_daughter_board_eeprom_info = {
+ .byte_len = (256*1024) / 8,
+ .page_size = 64,
+ .flags = AT24_FLAG_ADDR16,
+ .setup = am335x_setup_daughter_board,
+ .context = (void *)NULL,
+};
+
+static struct at24_platform_data am335x_baseboard_eeprom_info = {
+ .byte_len = (256*1024) / 8,
+ .page_size = 64,
+ .flags = AT24_FLAG_ADDR16,
+ .setup = am335x_evm_setup,
+ .context = (void *)NULL,
+};
+
+static struct regulator_init_data am335x_dummy = {
+ .constraints.always_on = true,
+};
+
+static struct regulator_consumer_supply am335x_vdd1_supply[] = {
+ REGULATOR_SUPPLY("vdd_mpu", NULL),
+};
+
+static struct regulator_init_data am335x_vdd1 = {
+ .constraints = {
+ .min_uV = 600000,
+ .max_uV = 1500000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply),
+ .consumer_supplies = am335x_vdd1_supply,
+};
+
+static struct regulator_consumer_supply am335x_vdd2_supply[] = {
+ REGULATOR_SUPPLY("vdd_core", NULL),
+};
+
+static struct regulator_init_data am335x_vdd2 = {
+ .constraints = {
+ .min_uV = 600000,
+ .max_uV = 1500000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(am335x_vdd2_supply),
+ .consumer_supplies = am335x_vdd2_supply,
+};
+
+static struct tps65910_board am335x_tps65910_info = {
+ .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy,
+ .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy,
+ .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1,
+ .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_vdd2,
+ .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy,
+ .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy,
+ .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy,
+ .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy,
+ .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy,
+ .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy,
+ .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy,
+ .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy,
+ .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy,
+};
+
+/*
+* Daughter board Detection.
+* Every board has a ID memory (EEPROM) on board. We probe these devices at
+* machine init, starting from daughter board and ending with baseboard.
+* Assumptions :
+* 1. probe for i2c devices are called in the order they are included in
+* the below struct. Daughter boards eeprom are probed 1st. Baseboard
+* eeprom probe is called last.
+*/
+static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
+ {
+ /* Daughter Board EEPROM */
+ I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
+ .platform_data = &am335x_daughter_board_eeprom_info,
+ },
+ {
+ /* Baseboard board EEPROM */
+ I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
+ .platform_data = &am335x_baseboard_eeprom_info,
+ },
+ {
+ I2C_BOARD_INFO("cpld_reg", 0x35),
+ },
+ {
+ I2C_BOARD_INFO("tlc59108", 0x40),
+ },
+ {
+ I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
+ .platform_data = &am335x_tps65910_info,
+ },
+};
+
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ /*
+ * mode[0:3] = USB0PORT's mode
+ * mode[4:7] = USB1PORT's mode
+ * AM335X beta EVM has USB0 in OTG mode and USB1 in host mode.
+ */
+ .mode = (MUSB_HOST << 4) | MUSB_OTG,
+ .power = 500,
+ .instances = 1,
+};
+
+static int cpld_reg_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ cpld_client = client;
+ return 0;
+}
+
+static int __devexit cpld_reg_remove(struct i2c_client *client)
+{
+ cpld_client = NULL;
+ return 0;
+}
+
+static const struct i2c_device_id cpld_reg_id[] = {
+ { "cpld_reg", 0 },
+ { }
+};
+
+static struct i2c_driver cpld_reg_driver = {
+ .driver = {
+ .name = "cpld_reg",
+ },
+ .probe = cpld_reg_probe,
+ .remove = cpld_reg_remove,
+ .id_table = cpld_reg_id,
+};
+
+static void evm_init_cpld(void)
+{
+ i2c_add_driver(&cpld_reg_driver);
+}
+
+static void __init am335x_evm_i2c_init(void)
+{
+ /* Initially assume Low Cost EVM Config */
+ am335x_evm_id = LOW_COST_EVM;
+
+ evm_init_cpld();
+
+ omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
+ ARRAY_SIZE(am335x_i2c_boardinfo));
+}
+
+static struct resource am335x_rtc_resources[] = {
+ {
+ .start = AM33XX_RTC_BASE,
+ .end = AM33XX_RTC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ { /* timer irq */
+ .start = AM33XX_IRQ_RTC_TIMER,
+ .end = AM33XX_IRQ_RTC_TIMER,
+ .flags = IORESOURCE_IRQ,
+ },
+ { /* alarm irq */
+ .start = AM33XX_IRQ_RTC_ALARM,
+ .end = AM33XX_IRQ_RTC_ALARM,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device am335x_rtc_device = {
+ .name = "omap_rtc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(am335x_rtc_resources),
+ .resource = am335x_rtc_resources,
+};
+
+static int am335x_rtc_init(void)
+{
+ void __iomem *base;
+ struct clk *clk;
+
+ clk = clk_get(NULL, "rtc_fck");
+ if (IS_ERR(clk)) {
+ pr_err("rtc : Failed to get RTC clock\n");
+ return -1;
+ }
+
+ if (clk_enable(clk)) {
+ pr_err("rtc: Clock Enable Failed\n");
+ return -1;
+ }
+
+ base = ioremap(AM33XX_RTC_BASE, SZ_4K);
+
+ if (WARN_ON(!base))
+ return -ENOMEM;
+
+ /* Unlock the rtc's registers */
+ writel(0x83e70b13, base + 0x6c);
+ writel(0x95a4f1e0, base + 0x70);
+
+ /*
+ * Enable the 32K OSc
+ * TODO: Need a better way to handle this
+ * Since we want the clock to be running before mmc init
+ * we need to do it before the rtc probe happens
+ */
+ writel(0x48, base + 0x54);
+
+ iounmap(base);
+
+ return platform_device_register(&am335x_rtc_device);
+}
+
+/* Enable clkout2 */
+static struct pinmux_config clkout2_pin_mux[] = {
+ {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+static void __init clkout2_enable(void)
+{
+ struct clk *ck_32;
+
+ ck_32 = clk_get(NULL, "clkout2_ck");
+ if (IS_ERR(ck_32)) {
+ pr_err("Cannot clk_get ck_32\n");
+ return;
+ }
+
+ clk_enable(ck_32);
+
+ setup_pin_mux(clkout2_pin_mux);
+}
+
+void __iomem *am33xx_emif_base;
+
+void __iomem * __init am33xx_get_mem_ctlr(void)
+{
+
+ am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
+
+ if (!am33xx_emif_base)
+ pr_warning("%s: Unable to map DDR2 controller", __func__);
+
+ return am33xx_emif_base;
+}
+
+void __iomem *am33xx_get_ram_base(void)
+{
+ return am33xx_emif_base;
+}
+
+static struct resource am33xx_cpuidle_resources[] = {
+ {
+ .start = AM33XX_EMIF0_BASE,
+ .end = AM33XX_EMIF0_BASE + SZ_32K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+/* AM33XX devices support DDR2 power down */
+static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
+ .ddr2_pdown = 1,
+};
+
+static struct platform_device am33xx_cpuidle_device = {
+ .name = "cpuidle-am33xx",
+ .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources),
+ .resource = am33xx_cpuidle_resources,
+ .dev = {
+ .platform_data = &am33xx_cpuidle_pdata,
+ },
+};
+
+static void __init am33xx_cpuidle_init(void)
+{
+ int ret;
+
+ am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
+
+ ret = platform_device_register(&am33xx_cpuidle_device);
+
+ if (ret)
+ pr_warning("AM33XX cpuidle registration failed\n");
+
+}
+
+static void __init am335x_evm_init(void)
+{
+ am33xx_cpuidle_init();
+ am33xx_mux_init(board_mux);
+ omap_serial_init();
+ am335x_rtc_init();
+ clkout2_enable();
+ am335x_evm_i2c_init();
+ omap_sdrc_init(NULL, NULL);
+ usb_musb_init(&musb_board_data);
+ omap_board_config = am335x_evm_config;
+ omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
+ /* Create an alias for icss clock */
+ if (clk_add_alias("pruss", NULL, "pruss_uart_gclk", NULL))
+ pr_warn("failed to create an alias: icss_uart_gclk --> pruss\n");
+ /* Create an alias for gfx/sgx clock */
+ if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
+ pr_warn("failed to create an alias: gfx_fclk --> sgx_ck\n");
+}
+
+static void __init am335x_evm_map_io(void)
+{
+ omap2_set_globals_am33xx();
+ omapam33xx_map_common_io();
+}
+
+MACHINE_START(AM335XEVM, "am335xevm")
+ /* Maintainer: Texas Instruments */
+ .atag_offset = 0x100,
+ .map_io = am335x_evm_map_io,
+ .init_early = am33xx_init_early,
+ .init_irq = ti81xx_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
+ .timer = &omap3_am33xx_timer,
+ .init_machine = am335x_evm_init,
+MACHINE_END
+
+MACHINE_START(AM335XIAEVM, "am335xiaevm")
+ /* Maintainer: Texas Instruments */
+ .atag_offset = 0x100,
+ .map_io = am335x_evm_map_io,
+ .init_irq = ti81xx_init_irq,
+ .init_early = am33xx_init_early,
+ .timer = &omap3_am33xx_timer,
+ .init_machine = am335x_evm_init,
+MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-am3517crane.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-am3517crane.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-am3517crane.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-am3517crane.c 2012-05-16 12:10:47.000000000 +0100
@@ -27,7 +27,7 @@
#include <asm/mach/map.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/usb.h>
#include "mux.h"
@@ -98,6 +98,7 @@
.map_io = omap3_map_io,
.init_early = am35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = am3517_crane_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-am3517evm.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-am3517evm.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-am3517evm.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-am3517evm.c 2012-05-16 12:10:47.000000000 +0100
@@ -24,6 +24,7 @@
#include <linux/i2c/pca953x.h>
#include <linux/can/platform/ti_hecc.h>
#include <linux/davinci_emac.h>
+#include <linux/mmc/host.h>
#include <mach/hardware.h>
#include <mach/am35xx.h>
@@ -32,7 +33,7 @@
#include <asm/mach/map.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/usb.h>
#include <video/omapdss.h>
#include <video/omap-panel-generic-dpi.h>
@@ -40,6 +41,7 @@
#include "mux.h"
#include "control.h"
+#include "hsmmc.h"
#define AM35XX_EVM_MDIO_FREQUENCY (1000000)
@@ -455,6 +457,23 @@
static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
};
+static struct omap2_hsmmc_info mmc[] = {
+ {
+ .mmc = 1,
+ .caps = MMC_CAP_4_BIT_DATA,
+ .gpio_cd = 127,
+ .gpio_wp = 126,
+ },
+ {
+ .mmc = 2,
+ .caps = MMC_CAP_4_BIT_DATA,
+ .gpio_cd = 128,
+ .gpio_wp = 129,
+ },
+ {} /* Terminator */
+};
+
+
static void __init am3517_evm_init(void)
{
omap_board_config = am3517_evm_config;
@@ -483,6 +502,9 @@
/* MUSB */
am3517_evm_musb_init();
+
+ /* MMC init function */
+ omap2_hsmmc_init(mmc);
}
MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
@@ -491,6 +513,7 @@
.map_io = omap3_map_io,
.init_early = am35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = am3517_evm_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-apollon.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-apollon.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-apollon.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-apollon.c 2012-05-16 12:10:47.000000000 +0100
@@ -37,7 +37,7 @@
#include <plat/led.h>
#include <plat/usb.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/gpmc.h>
#include <video/omapdss.h>
@@ -354,6 +354,7 @@
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = omap_apollon_init,
.timer = &omap2_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-cm-t3517.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-cm-t3517.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-cm-t3517.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-cm-t3517.c 2012-05-16 12:10:47.000000000 +0100
@@ -39,7 +39,7 @@
#include <asm/mach/map.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/usb.h>
#include <plat/nand.h>
#include <plat/gpmc.h>
@@ -299,6 +299,7 @@
.map_io = omap3_map_io,
.init_early = am35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = cm_t3517_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-cm-t35.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-cm-t35.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-cm-t35.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-cm-t35.c 2012-05-16 12:10:47.000000000 +0100
@@ -37,7 +37,7 @@
#include <asm/mach/map.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/nand.h>
#include <plat/gpmc.h>
#include <plat/usb.h>
@@ -53,7 +53,8 @@
#include "hsmmc.h"
#include "common-board-devices.h"
-#define CM_T35_GPIO_PENDOWN 57
+#define CM_T35_GPIO_PENDOWN 57
+#define SB_T35_USB_HUB_RESET_GPIO 167
#define CM_T35_SMSC911X_CS 5
#define CM_T35_SMSC911X_GPIO 163
@@ -279,7 +280,6 @@
static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
.turbo_mode = 0,
- .single_channel = 1, /* 0: slave, 1: master */
};
static struct tdo24m_platform_data tdo24m_config = {
@@ -339,8 +339,10 @@
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
-static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
- REGULATOR_SUPPLY("vdvi", "omapdss"),
+static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
+ REGULATOR_SUPPLY("vcc", "spi1.0"),
+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -373,6 +375,19 @@
.consumer_supplies = cm_t35_vsim_supply,
};
+static struct regulator_init_data cm_t35_vio = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(cm_t35_vio_supplies),
+ .consumer_supplies = cm_t35_vio_supplies,
+};
+
static uint32_t cm_t35_keymap[] = {
KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT),
KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN),
@@ -421,6 +436,23 @@
.reset_gpio_port[2] = -EINVAL
};
+static void cm_t35_init_usbh(void)
+{
+ int err;
+
+ err = gpio_request_one(SB_T35_USB_HUB_RESET_GPIO,
+ GPIOF_OUT_INIT_LOW, "usb hub rst");
+ if (err) {
+ pr_err("SB-T35: usb hub rst gpio request failed: %d\n", err);
+ } else {
+ udelay(10);
+ gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
+ msleep(1);
+ }
+
+ usbhs_init(&usbhs_bdata);
+}
+
static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
unsigned ngpio)
{
@@ -456,17 +488,14 @@
.gpio = &cm_t35_gpio_data,
.vmmc1 = &cm_t35_vmmc1,
.vsim = &cm_t35_vsim,
+ .vio = &cm_t35_vio,
};
static void __init cm_t35_init_i2c(void)
{
omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
- TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
-
- cm_t35_twldata.vpll2->constraints.name = "VDVI";
- cm_t35_twldata.vpll2->num_consumer_supplies =
- ARRAY_SIZE(cm_t35_vdvi_supply);
- cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply;
+ TWL_COMMON_REGULATOR_VDAC |
+ TWL_COMMON_PDATA_AUDIO);
omap3_pmic_init("tps65930", &cm_t35_twldata);
}
@@ -570,24 +599,28 @@
static void __init cm_t35_init_mux(void)
{
- omap_mux_init_signal("gpio_70", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
- omap_mux_init_signal("gpio_71", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
- omap_mux_init_signal("gpio_72", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
- omap_mux_init_signal("gpio_73", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
- omap_mux_init_signal("gpio_74", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
- omap_mux_init_signal("gpio_75", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
- cm_t3x_common_dss_mux_init(OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+ int mux_mode = OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT;
+
+ omap_mux_init_signal("dss_data0.dss_data0", mux_mode);
+ omap_mux_init_signal("dss_data1.dss_data1", mux_mode);
+ omap_mux_init_signal("dss_data2.dss_data2", mux_mode);
+ omap_mux_init_signal("dss_data3.dss_data3", mux_mode);
+ omap_mux_init_signal("dss_data4.dss_data4", mux_mode);
+ omap_mux_init_signal("dss_data5.dss_data5", mux_mode);
+ cm_t3x_common_dss_mux_init(mux_mode);
}
static void __init cm_t3730_init_mux(void)
{
- omap_mux_init_signal("sys_boot0", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
- omap_mux_init_signal("sys_boot1", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
- omap_mux_init_signal("sys_boot3", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
- omap_mux_init_signal("sys_boot4", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
- omap_mux_init_signal("sys_boot5", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
- omap_mux_init_signal("sys_boot6", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
- cm_t3x_common_dss_mux_init(OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+ int mux_mode = OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT;
+
+ omap_mux_init_signal("sys_boot0", mux_mode);
+ omap_mux_init_signal("sys_boot1", mux_mode);
+ omap_mux_init_signal("sys_boot3", mux_mode);
+ omap_mux_init_signal("sys_boot4", mux_mode);
+ omap_mux_init_signal("sys_boot5", mux_mode);
+ omap_mux_init_signal("sys_boot6", mux_mode);
+ cm_t3x_common_dss_mux_init(mux_mode);
}
#else
static inline void cm_t35_init_mux(void) {}
@@ -612,7 +645,7 @@
cm_t35_init_display();
usb_musb_init(NULL);
- usbhs_init(&usbhs_bdata);
+ cm_t35_init_usbh();
}
static void __init cm_t35_init(void)
@@ -634,6 +667,7 @@
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = cm_t35_init,
.timer = &omap3_timer,
MACHINE_END
@@ -644,6 +678,7 @@
.map_io = omap3_map_io,
.init_early = omap3630_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = cm_t3730_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-devkit8000.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-devkit8000.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-devkit8000.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-devkit8000.c 2012-05-16 12:10:47.000000000 +0100
@@ -41,7 +41,7 @@
#include <asm/mach/flash.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/gpmc.h>
#include <plat/nand.h>
#include <plat/usb.h>
@@ -59,6 +59,7 @@
#include "mux.h"
#include "hsmmc.h"
+#include "board-flash.h"
#include "common-board-devices.h"
#define OMAP_DM9000_GPIO_IRQ 25
@@ -646,8 +647,9 @@
usb_musb_init(NULL);
usbhs_init(&usbhs_bdata);
- omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
- ARRAY_SIZE(devkit8000_nand_partitions));
+ omap_nand_init(devkit8000_nand_partitions,
+ ARRAY_SIZE(devkit8000_nand_partitions), GPMC_CS_NUM + 1,
+ NAND_BUSWIDTH_16, NULL);
/* Ensure SDRC pins are mux'd for self-refresh */
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
@@ -660,6 +662,7 @@
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = devkit8000_init,
.timer = &omap3_secure_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-flash.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-flash.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-flash.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-flash.c 2012-05-16 12:10:47.000000000 +0100
@@ -104,11 +104,8 @@
}
#endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */
-#if defined(CONFIG_MTD_NAND_OMAP2) || \
- defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-
/* Note that all values in this struct are in nanoseconds */
-static struct gpmc_timings nand_timings = {
+struct gpmc_timings nand_default_timings = {
.sync_clk = 0,
@@ -131,22 +128,24 @@
.wr_data_mux_bus = 0,
};
-static struct omap_nand_platform_data board_nand_data = {
- .gpmc_t = &nand_timings,
+#if defined(CONFIG_MTD_NAND_OMAP2) || \
+ defined(CONFIG_MTD_NAND_OMAP2_MODULE)
+
+static struct omap_nand_platform_data omap_nand_data = {
+ .gpmc_t = &nand_default_timings,
};
-void
-__init board_nand_init(struct mtd_partition *nand_parts,
- u8 nr_parts, u8 cs, int nand_type)
+struct omap_nand_platform_data *
+__init omap_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
+ int nand_type, struct gpmc_timings *gpmc_t)
{
- board_nand_data.cs = cs;
- board_nand_data.parts = nand_parts;
- board_nand_data.nr_parts = nr_parts;
- board_nand_data.devsize = nand_type;
-
- board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
- board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
- gpmc_nand_init(&board_nand_data);
+ omap_nand_data.cs = cs;
+ omap_nand_data.parts = nand_parts;
+ omap_nand_data.nr_parts = nr_parts;
+ omap_nand_data.devsize = nand_type;
+ omap_nand_data.gpmc_t = gpmc_t;
+
+ return &omap_nand_data;
}
#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
@@ -242,6 +241,7 @@
if (nandcs > GPMC_CS_NUM)
pr_err("NAND: Unable to find configuration in GPMC\n");
else
- board_nand_init(partition_info[2].parts,
- partition_info[2].nr_parts, nandcs, nand_type);
+ omap_nand_init(partition_info[2].parts,
+ partition_info[2].nr_parts, nandcs,
+ nand_type, &nand_default_timings);
}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-flash.h kernel_3.2.14_patched/arch/arm/mach-omap2/board-flash.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-flash.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-flash.h 2012-05-16 12:10:47.000000000 +0100
@@ -39,11 +39,15 @@
#if defined(CONFIG_MTD_NAND_OMAP2) || \
defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-extern void board_nand_init(struct mtd_partition *nand_parts,
- u8 nr_parts, u8 cs, int nand_type);
+extern struct gpmc_timings nand_default_timings;
+extern struct omap_nand_platform_data *
+__init omap_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
+ int nand_type, struct gpmc_timings *gpmc_t);
#else
-static inline void board_nand_init(struct mtd_partition *nand_parts,
- u8 nr_parts, u8 cs, int nand_type)
+static inline struct omap_nand_platform_data *
+omap_nand_init(struct mtd_partition *nand_parts,
+ u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t)
{
+ return NULL;
}
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-generic.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-generic.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-generic.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-generic.c 2012-05-16 12:10:47.000000000 +0100
@@ -17,11 +17,11 @@
#include <linux/i2c/twl.h>
#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
#include <plat/board.h>
-#include <plat/common.h>
-#include <mach/omap4-common.h>
+#include "common.h"
#include "common-board-devices.h"
/*
@@ -70,7 +70,6 @@
if (node)
irq_domain_add_simple(node, 0);
- omap_serial_init();
omap_sdrc_init(NULL, NULL);
of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
@@ -104,6 +103,7 @@
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap2_timer,
.dt_compat = omap242x_boards_compat,
@@ -122,6 +122,7 @@
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap2_timer,
.dt_compat = omap243x_boards_compat,
@@ -140,6 +141,7 @@
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_init,
.timer = &omap3_timer,
.dt_compat = omap3_boards_compat,
@@ -158,6 +160,7 @@
.map_io = omap4_map_io,
.init_early = omap4430_init_early,
.init_irq = gic_init_irq,
+ .handle_irq = gic_handle_irq,
.init_machine = omap4_init,
.timer = &omap4_timer,
.dt_compat = omap4_boards_compat,
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-h4.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-h4.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-h4.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-h4.c 2012-05-16 12:10:47.000000000 +0100
@@ -34,7 +34,7 @@
#include <plat/usb.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/menelaus.h>
#include <plat/dma.h>
#include <plat/gpmc.h>
@@ -396,6 +396,7 @@
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = omap_h4_init,
.timer = &omap2_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-igep0020.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-igep0020.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-igep0020.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-igep0020.c 2012-05-16 12:10:47.000000000 +0100
@@ -28,7 +28,7 @@
#include <asm/mach/arch.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/gpmc.h>
#include <plat/usb.h>
#include <video/omapdss.h>
@@ -672,6 +672,7 @@
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = igep_init,
.timer = &omap3_timer,
MACHINE_END
@@ -682,6 +683,7 @@
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = igep_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-ldp.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-ldp.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-ldp.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-ldp.c 2012-05-16 12:10:47.000000000 +0100
@@ -36,7 +36,7 @@
#include <plat/mcspi.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/gpmc.h>
#include <mach/board-zoom.h>
@@ -421,8 +421,8 @@
omap_serial_init();
omap_sdrc_init(NULL, NULL);
usb_musb_init(NULL);
- board_nand_init(ldp_nand_partitions,
- ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
+ omap_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
+ ZOOM_NAND_CS, 0, &nand_default_timings);
omap2_hsmmc_init(mmc);
ldp_display_init();
@@ -434,6 +434,7 @@
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap_ldp_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-n8x0.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-n8x0.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-n8x0.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-n8x0.c 2012-05-16 12:10:47.000000000 +0100
@@ -15,8 +15,11 @@
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/init.h>
+#include <linux/irq.h>
#include <linux/io.h>
#include <linux/stddef.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/cbus.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/usb/musb.h>
@@ -26,7 +29,7 @@
#include <asm/mach-types.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/menelaus.h>
#include <mach/irqs.h>
#include <plat/mcspi.h>
@@ -46,7 +49,7 @@
#define TUSB6010_GPIO_ENABLE 0
#define TUSB6010_DMACHAN 0x3f
-#ifdef CONFIG_USB_MUSB_TUSB6010
+#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
/*
* Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and
* 1.5 V voltage regulators of PM companion chip. Companion chip will then
@@ -137,7 +140,6 @@
static struct omap2_mcspi_device_config p54spi_mcspi_config = {
.turbo_mode = 0,
- .single_channel = 1,
};
static struct spi_board_info n800_spi_board_info[] __initdata = {
@@ -193,6 +195,105 @@
};
#endif
+#if defined(CONFIG_CBUS) || defined(CONFIG_CBUS_MODULE)
+
+static struct cbus_host_platform_data n8x0_cbus_data = {
+ .clk_gpio = 66,
+ .dat_gpio = 65,
+ .sel_gpio = 64,
+};
+
+static struct platform_device n8x0_cbus_device = {
+ .name = "cbus",
+ .id = -1,
+ .dev = {
+ .platform_data = &n8x0_cbus_data,
+ },
+};
+
+static struct resource retu_resource[] = {
+ {
+ .start = -EINVAL, /* set later */
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device retu_device = {
+ .name = "retu",
+ .id = -1,
+ .resource = retu_resource,
+ .num_resources = ARRAY_SIZE(retu_resource),
+ .dev = {
+ .parent = &n8x0_cbus_device.dev,
+ },
+};
+
+static struct resource tahvo_resource[] = {
+ {
+ .start = -EINVAL, /* set later */
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct platform_device tahvo_device = {
+ .name = "tahvo",
+ .id = -1,
+ .resource = tahvo_resource,
+ .num_resources = ARRAY_SIZE(tahvo_resource),
+ .dev = {
+ .parent = &n8x0_cbus_device.dev,
+ },
+};
+
+static void __init n8x0_cbus_init(void)
+{
+ int ret;
+
+ platform_device_register(&n8x0_cbus_device);
+
+ ret = gpio_request(108, "RETU irq");
+ if (ret < 0) {
+ pr_err("retu: Unable to reserve IRQ GPIO\n");
+ return;
+ }
+
+ ret = gpio_direction_input(108);
+ if (ret < 0) {
+ pr_err("retu: Unable to change gpio direction\n");
+ gpio_free(108);
+ return;
+ }
+
+ irq_set_irq_type(gpio_to_irq(108), IRQ_TYPE_EDGE_RISING);
+ retu_resource[0].start = gpio_to_irq(108);
+ platform_device_register(&retu_device);
+
+ ret = gpio_request(111, "TAHVO irq");
+ if (ret) {
+ pr_err("tahvo: Unable to reserve IRQ GPIO\n");
+ gpio_free(108);
+ return;
+ }
+
+ /* Set the pin as input */
+ ret = gpio_direction_input(111);
+ if (ret) {
+ pr_err("tahvo: Unable to change direction\n");
+ gpio_free(108);
+ gpio_free(111);
+ return;
+ }
+
+ tahvo_resource[0].start = gpio_to_irq(111);
+ platform_device_register(&tahvo_device);
+}
+
+#else
+static inline void __init n8x0_cbus_init(void)
+{
+}
+#endif
+
#if defined(CONFIG_MENELAUS) && \
(defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE))
@@ -644,15 +745,15 @@
bdata.pads_cnt = 0;
bdata.id = 0;
- omap_serial_init_port(&bdata);
+ omap_serial_init_port(&bdata, NULL);
bdata.id = 1;
- omap_serial_init_port(&bdata);
+ omap_serial_init_port(&bdata, NULL);
bdata.id = 2;
bdata.pads = serial2_pads;
bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
- omap_serial_init_port(&bdata);
+ omap_serial_init_port(&bdata, NULL);
}
#else
@@ -667,6 +768,8 @@
static void __init n8x0_init_machine(void)
{
omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
+ n8x0_cbus_init();
+
/* FIXME: add n810 spi devices */
spi_register_board_info(n800_spi_board_info,
ARRAY_SIZE(n800_spi_board_info));
@@ -689,6 +792,7 @@
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.timer = &omap2_timer,
MACHINE_END
@@ -699,6 +803,7 @@
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.timer = &omap2_timer,
MACHINE_END
@@ -709,6 +814,7 @@
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.timer = &omap2_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3beagle.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3beagle.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3beagle.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3beagle.c 2012-05-16 12:10:47.000000000 +0100
@@ -40,7 +40,7 @@
#include <asm/mach/flash.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <video/omapdss.h>
#include <video/omap-panel-dvi.h>
#include <plat/gpmc.h>
@@ -51,6 +51,7 @@
#include "mux.h"
#include "hsmmc.h"
#include "pm.h"
+#include "board-flash.h"
#include "common-board-devices.h"
/*
@@ -538,8 +539,9 @@
usb_musb_init(NULL);
usbhs_init(&usbhs_bdata);
- omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
- ARRAY_SIZE(omap3beagle_nand_partitions));
+ omap_nand_init(omap3beagle_nand_partitions,
+ ARRAY_SIZE(omap3beagle_nand_partitions), GPMC_CS_NUM + 1,
+ NAND_BUSWIDTH_16, NULL);
/* Ensure msecure is mux'd to be able to set the RTC. */
omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
@@ -559,6 +561,7 @@
.map_io = omap3_map_io,
.init_early = omap3_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_beagle_init,
.timer = &omap3_secure_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3encore.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3encore.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3encore.c 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3encore.c 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,344 @@
+/*
+ * Support for Barns&Noble Nook Color
+ *
+ * Loosely based on mach-omap2/board-zoom.c
+ * Copyright (C) 2008-2010 Texas Instruments Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * June 2011 Oleg Drokin <green@linuxhacker.ru> - Port to mainline
+ *
+ */
+
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c/twl.h>
+#include <linux/regulator/machine.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <plat/usb.h>
+#include <plat/mux.h>
+#include <plat/mmc.h>
+
+#include "common.h"
+#include "mux.h"
+#include "hsmmc.h"
+#include "sdram-hynix-h8mbx00u0mer-0em.h"
+
+/* Encore-specific device-info and i2c addresses. */
+/* Battery, bus 1 */
+#define MAX17042_I2C_SLAVE_ADDRESS 0x36
+#define MAX17042_GPIO_FOR_IRQ 100
+
+/*addition of MAXIM8903/TI GPIO mapping WRT schematics */
+#define MAX8903_UOK_GPIO_FOR_IRQ 115
+#define MAX8903_DOK_GPIO_FOR_IRQ 114
+#define MAX8903_GPIO_CHG_EN 110
+#define MAX8903_GPIO_CHG_STATUS 111
+#define MAX8903_GPIO_CHG_FLT 101
+#define MAX8903_GPIO_CHG_IUSB 102
+#define MAX8903_GPIO_CHG_USUS 104
+#define MAX8903_GPIO_CHG_ILM 61
+
+/* TI WLAN */
+#define ENCORE_WIFI_PMENA_GPIO 22
+#define ENCORE_WIFI_IRQ_GPIO 15
+#define ENCORE_WIFI_EN_POW 16
+
+/* Accelerometer i2c bus 1*/
+#define KXTF9_I2C_SLAVE_ADDRESS 0x0F
+#define KXTF9_GPIO_FOR_PWR 34
+#define KXTF9_GPIO_FOR_IRQ 113
+
+/* Touch screen i2c bus 2*/
+#define CYTTSP_I2C_SLAVEADDRESS 34
+#define ENCORE_CYTTSP_GPIO 99
+#define ENCORE_CYTTSP_RESET_GPIO 46
+
+/* Audio codec, i2c bus 2 */
+#define AUDIO_CODEC_POWER_ENABLE_GPIO 103
+#define AUDIO_CODEC_RESET_GPIO 37
+#define AUDIO_CODEC_IRQ_GPIO 59
+#define AIC3100_I2CSLAVEADDRESS 0x18
+
+
+/* Different HW revisions */
+#define BOARD_ENCORE_REV_EVT1A 0x1
+#define BOARD_ENCORE_REV_EVT1B 0x2
+#define BOARD_ENCORE_REV_EVT2 0x3
+#define BOARD_ENCORE_REV_DVT 0x4
+#define BOARD_ENCORE_REV_PVT 0x5
+#define BOARD_ENCORE_REV_UNKNOWN 0x6
+
+static inline int is_encore_board_evt2(void)
+{
+ return system_rev >= BOARD_ENCORE_REV_EVT2;
+}
+
+static inline int is_encore_board_evt1b(void)
+{
+ return system_rev == BOARD_ENCORE_REV_EVT1B;
+}
+
+static int encore_twl4030_keymap[] = {
+ KEY(1, 0, KEY_VOLUMEUP),
+ KEY(2, 0, KEY_VOLUMEDOWN),
+};
+
+static struct matrix_keymap_data encore_twl4030_keymap_data = {
+ .keymap = encore_twl4030_keymap,
+ .keymap_size = ARRAY_SIZE(encore_twl4030_keymap),
+};
+
+static struct twl4030_keypad_data encore_kp_twl4030_data = {
+ .rows = 8,
+ .cols = 8,
+ .keymap_data = &encore_twl4030_keymap_data,
+ .rep = 1,
+};
+
+/* HOME key code for HW > EVT2A */
+static struct gpio_keys_button encore_gpio_buttons[] = {
+ {
+ .code = KEY_POWER,
+ .gpio = 14,
+ .desc = "POWER",
+ .active_low = 0,
+ .wakeup = 1,
+ },
+ {
+ .code = KEY_HOME,
+ .gpio = 48,
+ .desc = "HOME",
+ .active_low = 1,
+ .wakeup = 1,
+ },
+};
+
+static struct gpio_keys_platform_data encore_gpio_key_info = {
+ .buttons = encore_gpio_buttons,
+ .nbuttons = ARRAY_SIZE(encore_gpio_buttons),
+};
+
+static struct platform_device encore_keys_gpio = {
+ .name = "gpio-keys",
+ .id = -1,
+ .dev = {
+ .platform_data = &encore_gpio_key_info,
+ },
+};
+
+static struct platform_device *encore_devices[] __initdata = {
+ &encore_keys_gpio,
+};
+
+static struct twl4030_usb_data encore_usb_data = {
+ .usb_mode = T2_USB_MODE_ULPI,
+};
+
+static struct regulator_consumer_supply encore_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
+
+static struct regulator_consumer_supply encore_vdda_dac_supply[] = {
+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+};
+
+/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+static struct regulator_init_data encore_vmmc1 = {
+ .constraints = {
+ .min_uV = 1850000,
+ .max_uV = 3150000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(encore_vmmc1_supply),
+ .consumer_supplies = encore_vmmc1_supply,
+};
+
+static struct regulator_init_data encore_vdac = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(encore_vdda_dac_supply),
+ .consumer_supplies = encore_vdda_dac_supply,
+};
+
+/*
+ * The order is reverted in this table so that internal eMMC is presented
+ * as first mmc card for compatibility with existing installations and
+ * for common sense reasons
+ */
+static struct omap2_hsmmc_info mmc[] __initdata = {
+ {
+ .name = "internal",
+ .mmc = 2,
+ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+ .gpio_cd = -EINVAL,
+ .gpio_wp = -EINVAL,
+ .nonremovable = true,
+ .power_saving = true,
+ .ocr_mask = MMC_VDD_165_195, /* 1.85V */
+ },
+ {
+ .name = "external",
+ .mmc = 1,
+ .caps = MMC_CAP_4_BIT_DATA,
+ .gpio_cd = -EINVAL,
+ .gpio_wp = -EINVAL,
+ .power_saving = true,
+ },
+ {
+ .name = "internal",
+ .mmc = 3,
+ .caps = MMC_CAP_4_BIT_DATA,
+ .gpio_cd = -EINVAL,
+ .gpio_wp = -EINVAL,
+ .nonremovable = true,
+ .power_saving = true,
+ },
+ {} /* Terminator */
+};
+
+static int encore_hsmmc_card_detect(struct device *dev, int slot)
+{
+ struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+ /* Encore board EVT2 and later has pin high when card is present */
+ return gpio_get_value_cansleep(mmc->slots[0].switch_pin);
+}
+
+static int encore_twl4030_hsmmc_late_init(struct device *dev)
+{
+ int ret = 0;
+ struct platform_device *pdev = container_of(dev,
+ struct platform_device, dev);
+ struct omap_mmc_platform_data *pdata = dev->platform_data;
+
+ if (is_encore_board_evt2()) {
+ /* Setting MMC1 (external) Card detect */
+ if (pdev->id == 0)
+ pdata->slots[0].card_detect = encore_hsmmc_card_detect;
+ }
+
+ return ret;
+}
+
+static __init void encore_hsmmc_set_late_init(struct device *dev)
+{
+ struct omap_mmc_platform_data *pdata;
+
+ /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
+ if (!dev)
+ return;
+
+ pdata = dev->platform_data;
+ pdata->init = encore_twl4030_hsmmc_late_init;
+}
+
+static int __ref encore_twl_gpio_setup(struct device *dev,
+ unsigned gpio, unsigned ngpio)
+{
+ struct omap2_hsmmc_info *c;
+ /*
+ * gpio + 0 is "mmc0_cd" (input/IRQ),
+ * gpio + 1 is "mmc1_cd" (input/IRQ)
+ */
+ mmc[1].gpio_cd = gpio + 0;
+ mmc[0].gpio_cd = gpio + 1;
+ omap2_hsmmc_init(mmc);
+ for (c = mmc; c->mmc; c++)
+ encore_hsmmc_set_late_init(c->dev);
+
+ return 0;
+}
+
+static struct twl4030_gpio_platform_data encore_gpio_data = {
+ .gpio_base = OMAP_MAX_GPIO_LINES,
+ .irq_base = TWL4030_GPIO_IRQ_BASE,
+ .irq_end = TWL4030_GPIO_IRQ_END,
+ .setup = encore_twl_gpio_setup,
+};
+
+static struct twl4030_madc_platform_data encore_madc_data = {
+ .irq_line = 1,
+};
+
+static struct twl4030_platform_data __refdata encore_twldata = {
+ .irq_base = TWL4030_IRQ_BASE,
+ .irq_end = TWL4030_IRQ_END,
+
+ .madc = &encore_madc_data,
+ .usb = &encore_usb_data,
+ .gpio = &encore_gpio_data,
+ .keypad = &encore_kp_twl4030_data,
+ .vmmc1 = &encore_vmmc1,
+ .vdac = &encore_vdac,
+};
+
+static struct i2c_board_info __initdata encore_i2c_bus1_info[] = {
+ {
+ I2C_BOARD_INFO("tps65921", 0x48),
+ .flags = I2C_CLIENT_WAKE,
+ .irq = INT_34XX_SYS_NIRQ,
+ .platform_data = &encore_twldata,
+ },
+};
+
+static struct i2c_board_info __initdata encore_i2c_bus2_info[] = {
+};
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#endif
+
+static struct omap_board_config_kernel encore_config[] __initdata = {
+};
+
+static void __init omap_i2c_init(void)
+{
+ omap_register_i2c_bus(1, 100, encore_i2c_bus1_info,
+ ARRAY_SIZE(encore_i2c_bus1_info));
+ omap_register_i2c_bus(2, 400, encore_i2c_bus2_info,
+ ARRAY_SIZE(encore_i2c_bus2_info));
+}
+
+static void __init omap_encore_init(void)
+{
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
+ omap_i2c_init();
+ omap_serial_init();
+ omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
+ h8mbx00u0mer0em_sdrc_params);
+ usb_musb_init(NULL);
+
+ omap_board_config = encore_config;
+ omap_board_config_size = ARRAY_SIZE(encore_config);
+
+ platform_add_devices(encore_devices, ARRAY_SIZE(encore_devices));
+}
+
+MACHINE_START(ENCORE, "encore")
+ .atag_offset = 0x100,
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = omap3630_init_early,
+ .init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
+ .init_machine = omap_encore_init,
+ .timer = &omap3_timer,
+MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3evm.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3evm.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3evm.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3evm.c 2012-05-16 12:10:47.000000000 +0100
@@ -43,7 +43,7 @@
#include <plat/board.h>
#include <plat/usb.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/mcspi.h>
#include <video/omapdss.h>
#include <video/omap-panel-dvi.h>
@@ -637,7 +637,7 @@
omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
/* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
- usb_nop_xceiv_register();
+ usb_nop_xceiv_register(0);
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
/* enable EHCI VBUS using GPIO22 */
@@ -672,6 +672,12 @@
pr_err("error setting wl12xx data\n");
platform_device_register(&omap3evm_wlan_regulator);
#endif
+ /* NAND */
+ omap_nand_init(omap3_evm_nand_partitions,
+ ARRAY_SIZE(omap3_evm_nand_partitions),
+ 0, NAND_BUSWIDTH_16, &nand_default_timings);
+ board_onenand_init(omap3_evm_onenand_partitions,
+ ARRAY_SIZE(omap3_evm_onenand_partitions), 0);
}
MACHINE_START(OMAP3EVM, "OMAP3 EVM")
@@ -681,6 +687,7 @@
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_evm_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3logic.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3logic.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3logic.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3logic.c 2012-05-16 12:10:47.000000000 +0100
@@ -40,7 +40,7 @@
#include <plat/mux.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/gpmc-smsc911x.h>
#include <plat/gpmc.h>
#include <plat/sdrc.h>
@@ -208,6 +208,7 @@
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3logic_init,
.timer = &omap3_timer,
MACHINE_END
@@ -217,6 +218,7 @@
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3logic_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3pandora.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3pandora.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3pandora.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3pandora.c 2012-05-16 12:10:47.000000000 +0100
@@ -41,7 +41,7 @@
#include <asm/mach/map.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <mach/hardware.h>
#include <plat/mcspi.h>
#include <plat/usb.h>
@@ -606,6 +606,7 @@
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3pandora_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3stalker.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3stalker.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3stalker.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3stalker.c 2012-05-16 12:10:47.000000000 +0100
@@ -35,7 +35,7 @@
#include <asm/mach/flash.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/gpmc.h>
#include <plat/nand.h>
#include <plat/usb.h>
@@ -454,6 +454,7 @@
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_stalker_init,
.timer = &omap3_secure_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3touchbook.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3touchbook.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap3touchbook.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap3touchbook.c 2012-05-16 12:10:47.000000000 +0100
@@ -44,13 +44,14 @@
#include <asm/mach/flash.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/gpmc.h>
#include <plat/nand.h>
#include <plat/usb.h>
#include "mux.h"
#include "hsmmc.h"
+#include "board-flash.h"
#include "common-board-devices.h"
#include <asm/setup.h>
@@ -366,8 +367,9 @@
omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
usb_musb_init(NULL);
usbhs_init(&usbhs_bdata);
- omap_nand_flash_init(NAND_BUSWIDTH_16, omap3touchbook_nand_partitions,
- ARRAY_SIZE(omap3touchbook_nand_partitions));
+ omap_nand_init(omap3touchbook_nand_partitions,
+ ARRAY_SIZE(omap3touchbook_nand_partitions), GPMC_CS_NUM + 1,
+ NAND_BUSWIDTH_16, NULL);
/* Ensure SDRC pins are mux'd for self-refresh */
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
@@ -381,6 +383,7 @@
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_touchbook_init,
.timer = &omap3_secure_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap4panda.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap4panda.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap4panda.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap4panda.c 2012-05-16 12:12:51.000000000 +0100
@@ -30,14 +30,14 @@
#include <linux/wl12xx.h>
#include <mach/hardware.h>
-#include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <video/omapdss.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/usb.h>
#include <plat/mmc.h>
#include <video/omap-panel-dvi.h>
@@ -365,74 +365,8 @@
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
-static struct omap_device_pad serial2_pads[] __initdata = {
- OMAP_MUX_STATIC("uart2_cts.uart2_cts",
- OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart2_rts.uart2_rts",
- OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart2_rx.uart2_rx",
- OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart2_tx.uart2_tx",
- OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-
-static struct omap_device_pad serial3_pads[] __initdata = {
- OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
- OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
- OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
- OMAP_PIN_INPUT | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
- OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-
-static struct omap_device_pad serial4_pads[] __initdata = {
- OMAP_MUX_STATIC("uart4_rx.uart4_rx",
- OMAP_PIN_INPUT | OMAP_MUX_MODE0),
- OMAP_MUX_STATIC("uart4_tx.uart4_tx",
- OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-
-static struct omap_board_data serial2_data __initdata = {
- .id = 1,
- .pads = serial2_pads,
- .pads_cnt = ARRAY_SIZE(serial2_pads),
-};
-
-static struct omap_board_data serial3_data __initdata = {
- .id = 2,
- .pads = serial3_pads,
- .pads_cnt = ARRAY_SIZE(serial3_pads),
-};
-
-static struct omap_board_data serial4_data __initdata = {
- .id = 3,
- .pads = serial4_pads,
- .pads_cnt = ARRAY_SIZE(serial4_pads),
-};
-
-static inline void board_serial_init(void)
-{
- struct omap_board_data bdata;
- bdata.flags = 0;
- bdata.pads = NULL;
- bdata.pads_cnt = 0;
- bdata.id = 0;
- /* pass dummy data for UART1 */
- omap_serial_init_port(&bdata);
-
- omap_serial_init_port(&serial2_data);
- omap_serial_init_port(&serial3_data);
- omap_serial_init_port(&serial4_data);
-}
#else
#define board_mux NULL
-
-static inline void board_serial_init(void)
-{
- omap_serial_init();
-}
#endif
/* Display DVI */
@@ -568,7 +502,7 @@
omap4_panda_i2c_init();
platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
platform_device_register(&omap_vwlan_device);
- board_serial_init();
+ omap_serial_init();
omap_sdrc_init(NULL, NULL);
omap4_twl6030_hsmmc_init(mmc);
omap4_ehci_init();
@@ -583,6 +517,7 @@
.map_io = omap4_map_io,
.init_early = omap4430_init_early,
.init_irq = gic_init_irq,
+ .handle_irq = gic_handle_irq,
.init_machine = omap4_panda_init,
.timer = &omap4_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap4pcm049.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap4pcm049.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-omap4pcm049.c 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-omap4pcm049.c 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,584 @@
+/*
+ * Board support file for Phytec phyCORE-OMAP4 Board.
+ *
+ * Copyright (C) 2011 Phytec Messtechnik GmbH
+ *
+ * Author: Jan Weitzel <armlinux@phytec.de>
+ *
+ * Based on mach-omap2/board-omap4panda.c
+ *
+ * Author: David Anders <x0132446@ti.com>
+ *
+ * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/usb/otg.h>
+#include <linux/i2c/twl.h>
+#include <linux/i2c/at24.h>
+#include <linux/mfd/stmpe.h>
+#include <linux/leds-pca9532.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/smsc911x.h>
+
+#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <video/omapdss.h>
+
+#include <plat/board.h>
+#include <plat/usb.h>
+#include <plat/gpmc.h>
+#include <plat/gpmc-smsc911x.h>
+#include <plat/mmc.h>
+#include <video/omap-panel-generic-dpi.h>
+
+#include "common.h"
+#include "hsmmc.h"
+#include "control.h"
+#include "mux.h"
+#include "common-board-devices.h"
+
+#define OMAP4_PCM049_ETH_GPIO_IRQ 121
+#define OMAP4_PCM049_ETH_CS 5
+#define OMAP4_PCM049_STMPE811_GPIO_IRQ 117
+#define OMAP4_PCM049_LCD_ENABLE 118
+
+static struct gpio_led gpio_leds[] = {
+ {
+ .name = "modul:red:status1",
+ .default_trigger = "heartbeat",
+ .gpio = 152,
+ },
+ {
+ .name = "modul:green:status2",
+ .default_trigger = "mmc0",
+ .gpio = 153,
+ },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+ .leds = gpio_leds,
+ .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &gpio_led_info,
+ },
+};
+
+static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .phy_reset = false,
+ .reset_gpio_port[0] = -EINVAL,
+ .reset_gpio_port[1] = -EINVAL,
+ .reset_gpio_port[2] = -EINVAL
+};
+
+static void __init omap4_ehci_init(void)
+{
+ struct clk *phy_ref_clk;
+ /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
+ phy_ref_clk = clk_get(NULL, "auxclk3_ck");
+ if (IS_ERR(phy_ref_clk)) {
+ pr_err("Cannot request auxclk3\n");
+ return;
+ }
+ clk_set_rate(phy_ref_clk, 19200000);
+ clk_enable(phy_ref_clk);
+
+ usbhs_init(&usbhs_bdata);
+ return;
+}
+
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_UTMI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
+
+static struct omap2_hsmmc_info mmc[] = {
+ {
+ .mmc = 1,
+ .caps = MMC_CAP_4_BIT_DATA,
+ .gpio_wp = -EINVAL,
+ .gpio_cd = -EINVAL,
+ }, {
+ .mmc = 5,
+ .caps = MMC_CAP_4_BIT_DATA,
+ .gpio_wp = -EINVAL,
+ .gpio_cd = 30, /* wk30 */
+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
+ }, {} /* Terminator */
+};
+
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
+ .cs = OMAP4_PCM049_ETH_CS,
+ .gpio_irq = OMAP4_PCM049_ETH_GPIO_IRQ,
+ .gpio_reset = -EINVAL,
+ .flags = SMSC911X_USE_16BIT,
+};
+
+static inline void __init pcm049_init_smsc911x(void)
+{
+ omap_mux_init_gpio(OMAP4_PCM049_ETH_GPIO_IRQ, OMAP_PIN_INPUT);
+ gpmc_smsc911x_init(&board_smsc911x_data);
+}
+#else
+static inline void __init pcm049_init_smsc911x(void) { return; }
+#endif
+
+static int omap4_twl6030_hsmmc_late_init(struct device *dev)
+{
+ int ret = 0;
+ struct platform_device *pdev = container_of(dev,
+ struct platform_device, dev);
+ struct omap_mmc_platform_data *pdata = dev->platform_data;
+
+ /* Setting MMC1 Card detect Irq */
+ if (pdev->id == 0) {
+ ret = twl6030_mmc_card_detect_config();
+ if (ret)
+ dev_err(dev, "%s: Error card detect config(%d)\n",
+ __func__, ret);
+ pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE +
+ MMCDETECT_INTR_OFFSET;
+ pdata->slots[0].card_detect = twl6030_mmc_card_detect;
+ }
+ return ret;
+}
+
+static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
+{
+ struct omap_mmc_platform_data *pdata;
+
+ /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
+ if (!dev) {
+ pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n");
+ return;
+ }
+ pdata = dev->platform_data;
+
+ pdata->init = omap4_twl6030_hsmmc_late_init;
+}
+
+static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
+{
+ struct omap2_hsmmc_info *c;
+
+ omap2_hsmmc_init(controllers);
+ for (c = controllers; c->mmc; c++)
+ omap4_twl6030_hsmmc_set_late_init(c->dev);
+
+ return 0;
+}
+
+/* Fixed regulator for max1027 */
+static struct regulator_consumer_supply pcm049_vcc_3v3_consumer_supply[] = {
+ REGULATOR_SUPPLY("vcc", "4-0064"),
+};
+
+struct regulator_init_data pcm049_vcc_3v3_initdata = {
+ .consumer_supplies = pcm049_vcc_3v3_consumer_supply,
+ .num_consumer_supplies = ARRAY_SIZE(pcm049_vcc_3v3_consumer_supply),
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+};
+
+static struct fixed_voltage_config pcm049_vcc_3v3_config = {
+ .supply_name = "pcm049_vcc_3v3",
+ .microvolts = 3300000,
+ .gpio = -EINVAL,
+ .enabled_at_boot = 1,
+ .init_data = &pcm049_vcc_3v3_initdata,
+};
+
+static struct platform_device pcm049_vcc_3v3_device = {
+ .name = "reg-fixed-voltage",
+ .id = 0,
+ .dev = {
+ .platform_data = &pcm049_vcc_3v3_config,
+ },
+};
+
+static struct at24_platform_data board_eeprom = {
+ .byte_len = 4096,
+ .page_size = 32,
+ .flags = AT24_FLAG_ADDR16,
+};
+
+static struct stmpe_gpio_platform_data pba_gpio_stm_data = {
+ .gpio_base = -1,
+ .norequest_mask = STMPE_GPIO_NOREQ_811_TOUCH,
+};
+
+static struct stmpe_ts_platform_data pba_ts_stm_pdata = {
+ .sample_time = 4,
+ .mod_12b = 1,
+ .ref_sel = 0,
+ .adc_freq = 1,
+ .ave_ctrl = 3,
+ .touch_det_delay = 3,
+ .settling = 3,
+ .fraction_z = 7,
+ .i_drive = 0,
+};
+
+static struct stmpe_platform_data pba_stm_pdata = {
+ .blocks = STMPE_BLOCK_GPIO | STMPE_BLOCK_TOUCHSCREEN,
+ .irq_base = TWL6030_IRQ_END,
+ .irq_trigger = IRQF_TRIGGER_RISING,
+ .irq_invert_polarity = true,
+ .gpio = &pba_gpio_stm_data,
+ .ts = &pba_ts_stm_pdata,
+};
+
+static struct pca9532_platform_data pba_pca9532 = {
+ .leds = {
+ {
+ .name = "board:red:free_use1",
+ .state = PCA9532_OFF,
+ .type = PCA9532_TYPE_LED,
+ }, {
+ .name = "board:yellow:free_use2",
+ .state = PCA9532_OFF,
+ .type = PCA9532_TYPE_LED,
+ }, {
+ .name = "board:yellow:free_use3",
+ .state = PCA9532_OFF,
+ .type = PCA9532_TYPE_LED,
+ }, {
+ .name = "board:green:free_use4",
+ .state = PCA9532_OFF,
+ .type = PCA9532_TYPE_LED,
+ },
+ },
+ .psc = { 1, 1 },
+ .pwm = { 1, 1 },
+};
+
+static struct i2c_board_info __initdata pcm049_i2c_1_boardinfo[] = {
+ {
+ I2C_BOARD_INFO("at24", 0x57), /* E0=1, E1=1, E2=1 */
+ .platform_data = &board_eeprom,
+ },
+};
+
+static struct i2c_board_info __initdata pcm049_i2c_3_boardinfo[] = {
+};
+
+static struct i2c_board_info __initdata pcm049_i2c_4_boardinfo[] = {
+ {
+ I2C_BOARD_INFO("stmpe811", 0x41), /* Touch controller */
+ .irq = OMAP_GPIO_IRQ(OMAP4_PCM049_STMPE811_GPIO_IRQ),
+ .platform_data = &pba_stm_pdata,
+ }, {
+ I2C_BOARD_INFO("max1037", 0x64), /* A/D converter */
+ }, {
+ I2C_BOARD_INFO("pca9533", 0x62), /* Leds pca9533 */
+ .platform_data = &pba_pca9532,
+ }
+};
+
+static struct twl4030_platform_data pcm049_twldata;
+
+static int __init pcm049_i2c_init(void)
+{
+ /* I2C1 */
+ omap4_pmic_get_config(&pcm049_twldata, TWL_COMMON_PDATA_USB,
+ TWL_COMMON_REGULATOR_VDAC |
+ TWL_COMMON_REGULATOR_VAUX2 |
+ TWL_COMMON_REGULATOR_VAUX3 |
+ TWL_COMMON_REGULATOR_VMMC |
+ TWL_COMMON_REGULATOR_VPP |
+ TWL_COMMON_REGULATOR_VANA |
+ TWL_COMMON_REGULATOR_VCXIO |
+ TWL_COMMON_REGULATOR_VUSB |
+ TWL_COMMON_REGULATOR_CLK32KG);
+ omap4_pmic_init("twl6030", &pcm049_twldata);
+ i2c_register_board_info(1, pcm049_i2c_1_boardinfo,
+ ARRAY_SIZE(pcm049_i2c_1_boardinfo));
+
+ /* I2C3 */
+ omap_register_i2c_bus(3, 400, pcm049_i2c_3_boardinfo,
+ ARRAY_SIZE(pcm049_i2c_3_boardinfo));
+
+ /* I2C4 */
+ if (omap_mux_init_gpio(OMAP4_PCM049_STMPE811_GPIO_IRQ, OMAP_PIN_INPUT))
+ printk(KERN_ERR "Failed to mux GPIO%d for STMPE811 IRQ\n",
+ OMAP4_PCM049_STMPE811_GPIO_IRQ);
+ else if (gpio_request(OMAP4_PCM049_STMPE811_GPIO_IRQ, "STMPE811 irq"))
+ printk(KERN_ERR "Failed to request GPIO%d for STMPE811 IRQ\n",
+ OMAP4_PCM049_STMPE811_GPIO_IRQ);
+ else
+ gpio_direction_input(OMAP4_PCM049_STMPE811_GPIO_IRQ);
+
+ omap_register_i2c_bus(4, 400, pcm049_i2c_4_boardinfo,
+ ARRAY_SIZE(pcm049_i2c_4_boardinfo));
+ return 0;
+}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+ OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+ OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+ OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+ OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+
+ /* dispc2_data23 */
+ OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data22 */
+ OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data21 */
+ OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data20 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data19 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data18 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data15 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data14 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data13 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data12 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data11 */
+ OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data10 */
+ OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data9 */
+ OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data16 */
+ OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data17 */
+ OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_hsync */
+ OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_pclk */
+ OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_vsync */
+ OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_de */
+ OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data8 */
+ OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data7 */
+ OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data6 */
+ OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data5 */
+ OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data4 */
+ OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data3 */
+ OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data2 */
+ OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data1 */
+ OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+ /* dispc2_data0 */
+ OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+static struct omap_device_pad serial2_pads[] __initdata = {
+ OMAP_MUX_STATIC("uart2_cts.uart2_cts",
+ OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+ OMAP_MUX_STATIC("uart2_rts.uart2_rts",
+ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+ OMAP_MUX_STATIC("uart2_rx.uart2_rx",
+ OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+ OMAP_MUX_STATIC("uart2_tx.uart2_tx",
+ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+};
+
+static struct omap_device_pad serial3_pads[] __initdata = {
+ OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
+ OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+ OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
+ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+ OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
+ OMAP_PIN_INPUT | OMAP_MUX_MODE0),
+ OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
+ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
+};
+
+static struct omap_board_data serial2_data __initdata = {
+ .id = 1,
+ .pads = serial2_pads,
+ .pads_cnt = ARRAY_SIZE(serial2_pads),
+};
+
+static struct omap_board_data serial3_data __initdata = {
+ .id = 2,
+ .pads = serial3_pads,
+ .pads_cnt = ARRAY_SIZE(serial3_pads),
+};
+
+static inline void board_serial_init(void)
+{
+ omap_serial_init_port(&serial2_data, NULL);
+ omap_serial_init_port(&serial3_data, NULL);
+}
+#else
+#define board_mux NULL
+
+static inline void board_serial_init(void)
+{
+ omap_serial_init();
+}
+#endif
+
+/* Display */
+static int pcm049_panel_enable_lcd(struct omap_dss_device *dssdev)
+{
+ return gpio_direction_output(OMAP4_PCM049_LCD_ENABLE, 1);
+}
+
+static void pcm049_panel_disable_lcd(struct omap_dss_device *dssdev)
+{
+ gpio_direction_output(OMAP4_PCM049_LCD_ENABLE, 0);
+ return;
+}
+
+/* Using generic display panel */
+static struct panel_generic_dpi_data omap4_dpi_panel = {
+ .name = "pd050vl1",
+ .platform_enable = pcm049_panel_enable_lcd,
+ .platform_disable = pcm049_panel_disable_lcd,
+};
+
+struct omap_dss_device pcm049_dpi_device = {
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .name = "dpi",
+ .driver_name = "generic_dpi_panel",
+ .data = &omap4_dpi_panel,
+ .phy.dpi.data_lines = 24,
+ .channel = OMAP_DSS_CHANNEL_LCD2,
+};
+
+static void pcm049_dvi_mux_init(void)
+{
+ /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
+ omap_mux_init_signal("hdmi_hpd",
+ OMAP_PIN_INPUT_PULLUP);
+ omap_mux_init_signal("hdmi_cec",
+ OMAP_PIN_INPUT_PULLUP);
+ /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
+ omap_mux_init_signal("hdmi_ddc_scl",
+ OMAP_PIN_INPUT_PULLUP);
+ omap_mux_init_signal("hdmi_ddc_sda",
+ OMAP_PIN_INPUT_PULLUP);
+}
+
+static struct omap_dss_device pcm049_dvi_device = {
+ .name = "dvi",
+ .driver_name = "hdmi_panel",
+ .type = OMAP_DISPLAY_TYPE_HDMI,
+ .clocks = {
+ .dispc = {
+ .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
+ },
+ .hdmi = {
+ .regn = 15,
+ .regm2 = 1,
+ },
+ },
+ .channel = OMAP_DSS_CHANNEL_DIGIT,
+};
+
+static struct omap_dss_device *pcm049_dss_devices[] = {
+ &pcm049_dpi_device,
+ &pcm049_dvi_device,
+};
+
+static struct omap_dss_board_info pcm049_dss_data = {
+ .num_devices = ARRAY_SIZE(pcm049_dss_devices),
+ .devices = pcm049_dss_devices,
+ .default_device = &pcm049_dpi_device,
+};
+
+void pcm049_display_init(void)
+{
+ omap_mux_init_gpio(OMAP4_PCM049_LCD_ENABLE, OMAP_PIN_OUTPUT);
+
+ if ((gpio_request(OMAP4_PCM049_LCD_ENABLE, "DISP_ENA") == 0) &&
+ (gpio_direction_output(OMAP4_PCM049_LCD_ENABLE, 1) == 0)) {
+ gpio_export(OMAP4_PCM049_LCD_ENABLE, 0);
+ gpio_set_value(OMAP4_PCM049_LCD_ENABLE, 0);
+ } else
+ printk(KERN_ERR "could not obtain gpio for DISP_ENA");
+ pcm049_dvi_mux_init();
+ omap_display_init(&pcm049_dss_data);
+}
+
+static struct platform_device *pcm049_devices[] __initdata = {
+ &pcm049_vcc_3v3_device,
+ &leds_gpio,
+};
+
+#define TWL_PHOENIX_DEV_ON 0x25
+
+static void pcm049_power_off(void)
+{
+ printk(KERN_INFO "Goodbye phyCORE OMAP4!\n");
+ twl_i2c_write_u8(TWL6030_MODULE_ID0, 0x7, TWL_PHOENIX_DEV_ON);
+}
+
+
+static void __init pcm049_init(void)
+{
+ pm_power_off = pcm049_power_off;
+ omap4_mux_init(board_mux, NULL, OMAP_PACKAGE_CBS);
+ pcm049_init_smsc911x();
+ pcm049_i2c_init();
+ platform_add_devices(pcm049_devices, ARRAY_SIZE(pcm049_devices));
+ board_serial_init();
+ omap_sdrc_init(NULL, NULL);
+ omap4_twl6030_hsmmc_init(mmc);
+ omap4_ehci_init();
+ usb_musb_init(&musb_board_data);
+ pcm049_display_init();
+}
+
+static void __init pcm049_map_io(void)
+{
+ omap2_set_globals_443x();
+ omap44xx_map_common_io();
+}
+
+MACHINE_START(PCM049, "phyCORE OMAP4")
+ /* Maintainer: Jan Weitzel - Phytec Messtechnik GmbH */
+ .atag_offset = 0x100,
+ .reserve = omap_reserve,
+ .map_io = pcm049_map_io,
+ .init_early = omap4430_init_early,
+ .init_irq = gic_init_irq,
+ .handle_irq = gic_handle_irq,
+ .init_machine = pcm049_init,
+ .timer = &omap4_timer,
+MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-overo.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-overo.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-overo.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-overo.c 2012-05-16 12:10:47.000000000 +0100
@@ -43,7 +43,7 @@
#include <asm/mach/map.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <video/omapdss.h>
#include <video/omap-panel-generic-dpi.h>
#include <video/omap-panel-dvi.h>
@@ -57,6 +57,7 @@
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
#include "hsmmc.h"
+#include "board-flash.h"
#include "common-board-devices.h"
#define OVERO_GPIO_BT_XGATE 15
@@ -510,8 +511,8 @@
omap_serial_init();
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
- omap_nand_flash_init(0, overo_nand_partitions,
- ARRAY_SIZE(overo_nand_partitions));
+ omap_nand_init(overo_nand_partitions,
+ ARRAY_SIZE(overo_nand_partitions), GPMC_CS_NUM + 1, 0, NULL);
usb_musb_init(NULL);
usbhs_init(&usbhs_bdata);
overo_spi_init();
@@ -562,6 +563,7 @@
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = overo_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-rm680.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-rm680.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-rm680.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-rm680.c 2012-05-16 12:10:47.000000000 +0100
@@ -25,7 +25,7 @@
#include <plat/mmc.h>
#include <plat/usb.h>
#include <plat/gpmc.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/onenand.h>
#include "mux.h"
@@ -149,6 +149,7 @@
.map_io = omap3_map_io,
.init_early = omap3630_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = rm680_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-rx51.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-rx51.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-rx51.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-rx51.c 2012-05-16 12:10:47.000000000 +0100
@@ -25,7 +25,7 @@
#include <plat/mcspi.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/dma.h>
#include <plat/gpmc.h>
#include <plat/usb.h>
@@ -127,6 +127,7 @@
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = rx51_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-rx51-peripherals.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-rx51-peripherals.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-rx51-peripherals.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-rx51-peripherals.c 2012-05-16 12:10:47.000000000 +0100
@@ -15,6 +15,7 @@
#include <linux/input/matrix_keypad.h>
#include <linux/spi/spi.h>
#include <linux/wl12xx.h>
+#include <linux/spi/tsc2005.h>
#include <linux/i2c.h>
#include <linux/i2c/twl.h>
#include <linux/clk.h>
@@ -27,7 +28,7 @@
#include <plat/mcspi.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/dma.h>
#include <plat/gpmc.h>
#include <plat/onenand.h>
@@ -58,6 +59,9 @@
#define RX51_USB_TRANSCEIVER_RST_GPIO 67
+#define RX51_TSC2005_RESET_GPIO 104
+#define RX51_TSC2005_IRQ_GPIO 100
+
/* list all spi devices here */
enum {
RX51_SPI_WL1251,
@@ -66,6 +70,7 @@
};
static struct wl12xx_platform_data wl1251_pdata;
+static struct tsc2005_platform_data tsc2005_pdata;
#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
@@ -133,17 +138,14 @@
static struct omap2_mcspi_device_config wl1251_mcspi_config = {
.turbo_mode = 0,
- .single_channel = 1,
};
static struct omap2_mcspi_device_config mipid_mcspi_config = {
.turbo_mode = 0,
- .single_channel = 1,
};
static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
.turbo_mode = 0,
- .single_channel = 1,
};
static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
@@ -167,10 +169,10 @@
.modalias = "tsc2005",
.bus_num = 1,
.chip_select = 0,
- /* .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),*/
+ .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
.max_speed_hz = 6000000,
.controller_data = &tsc2005_mcspi_config,
- /* .platform_data = &tsc2005_config,*/
+ .platform_data = &tsc2005_pdata,
},
};
@@ -1086,6 +1088,42 @@
*/
}
+static struct tsc2005_platform_data tsc2005_pdata = {
+ .ts_pressure_max = 2048,
+ .ts_pressure_fudge = 2,
+ .ts_x_max = 4096,
+ .ts_x_fudge = 4,
+ .ts_y_max = 4096,
+ .ts_y_fudge = 7,
+ .ts_x_plate_ohm = 280,
+ .esd_timeout_ms = 8000,
+};
+
+static void rx51_tsc2005_set_reset(bool enable)
+{
+ gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
+}
+
+static void __init rx51_init_tsc2005(void)
+{
+ int r;
+
+ r = gpio_request_one(RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ");
+ if (r < 0) {
+ printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 IRQ");
+ rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq = 0;
+ }
+
+ r = gpio_request_one(RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
+ "tsc2005 reset");
+ if (r >= 0) {
+ tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
+ } else {
+ printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
+ tsc2005_pdata.esd_timeout_ms = 0;
+ }
+}
+
void __init rx51_peripherals_init(void)
{
rx51_i2c_init();
@@ -1094,6 +1132,7 @@
board_smc91x_init();
rx51_add_gpio_keys();
rx51_init_wl1251();
+ rx51_init_tsc2005();
rx51_init_si4713();
spi_register_board_info(rx51_peripherals_spi_board_info,
ARRAY_SIZE(rx51_peripherals_spi_board_info));
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-ti8168evm.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-ti8168evm.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-ti8168evm.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-ti8168evm.c 2012-05-16 12:10:47.000000000 +0100
@@ -1,5 +1,5 @@
/*
- * Code for TI8168 EVM.
+ * Code for TI8168/TI8148 EVM.
*
* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
*
@@ -22,30 +22,44 @@
#include <plat/irqs.h>
#include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
+#include <plat/usb.h>
-static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
+static struct omap_musb_board_data musb_board_data = {
+ .set_phy_power = ti81xx_musb_phy_power,
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 500,
};
-static void __init ti8168_evm_init(void)
+static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = {
+};
+
+static void __init ti81xx_evm_init(void)
{
omap_serial_init();
omap_sdrc_init(NULL, NULL);
- omap_board_config = ti8168_evm_config;
- omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
-}
-
-static void __init ti8168_evm_map_io(void)
-{
- omapti816x_map_common_io();
+ omap_board_config = ti81xx_evm_config;
+ omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config);
+ usb_musb_init(&musb_board_data);
}
MACHINE_START(TI8168EVM, "ti8168evm")
/* Maintainer: Texas Instruments */
.atag_offset = 0x100,
- .map_io = ti8168_evm_map_io,
- .init_early = ti816x_init_early,
- .init_irq = ti816x_init_irq,
+ .map_io = ti81xx_map_io,
+ .init_early = ti81xx_init_early,
+ .init_irq = ti81xx_init_irq,
+ .timer = &omap3_timer,
+ .init_machine = ti81xx_evm_init,
+MACHINE_END
+
+MACHINE_START(TI8148EVM, "ti8148evm")
+ /* Maintainer: Texas Instruments */
+ .atag_offset = 0x100,
+ .map_io = ti81xx_map_io,
+ .init_early = ti81xx_init_early,
+ .init_irq = ti81xx_init_irq,
.timer = &omap3_timer,
- .init_machine = ti8168_evm_init,
+ .init_machine = ti81xx_evm_init,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-zoom.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-zoom.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-zoom.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-zoom.c 2012-05-16 12:10:47.000000000 +0100
@@ -21,7 +21,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/board.h>
#include <plat/usb.h>
@@ -114,8 +114,9 @@
usbhs_init(&usbhs_bdata);
}
- board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
- ZOOM_NAND_CS, NAND_BUSWIDTH_16);
+ omap_nand_init(zoom_nand_partitions,
+ ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS,
+ NAND_BUSWIDTH_16, &nand_default_timings);
zoom_debugboard_init();
zoom_peripherals_init();
@@ -135,6 +136,7 @@
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap_zoom_init,
.timer = &omap3_timer,
MACHINE_END
@@ -145,6 +147,7 @@
.map_io = omap3_map_io,
.init_early = omap3630_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap_zoom_init,
.timer = &omap3_timer,
MACHINE_END
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-zoom-display.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-zoom-display.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-zoom-display.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-zoom-display.c 2012-05-16 12:10:47.000000000 +0100
@@ -117,7 +117,6 @@
static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
.turbo_mode = 1,
- .single_channel = 1, /* 0: slave, 1: master */
};
static struct spi_board_info nec_8048_spi_board_info[] __initdata = {
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/board-zoom-peripherals.c kernel_3.2.14_patched/arch/arm/mach-omap2/board-zoom-peripherals.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/board-zoom-peripherals.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/board-zoom-peripherals.c 2012-05-16 12:10:47.000000000 +0100
@@ -24,7 +24,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/usb.h>
#include <mach/board-zoom.h>
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/clkt_dpll.c kernel_3.2.14_patched/arch/arm/mach-omap2/clkt_dpll.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/clkt_dpll.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/clkt_dpll.c 2012-05-16 12:10:47.000000000 +0100
@@ -206,13 +206,9 @@
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
clk_reparent(clk, dd->clk_bypass);
- } else if (cpu_is_omap34xx()) {
+ } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
- v == OMAP3XXX_EN_DPLL_FRBYPASS)
- clk_reparent(clk, dd->clk_bypass);
- } else if (cpu_is_omap44xx()) {
- if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
- v == OMAP4XXX_EN_DPLL_FRBYPASS ||
+ v == OMAP3XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
clk_reparent(clk, dd->clk_bypass);
}
@@ -252,13 +248,9 @@
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
return dd->clk_bypass->rate;
- } else if (cpu_is_omap34xx()) {
+ } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
- v == OMAP3XXX_EN_DPLL_FRBYPASS)
- return dd->clk_bypass->rate;
- } else if (cpu_is_omap44xx()) {
- if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
- v == OMAP4XXX_EN_DPLL_FRBYPASS ||
+ v == OMAP3XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
return dd->clk_bypass->rate;
}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/clock33xx_data.c kernel_3.2.14_patched/arch/arm/mach-omap2/clock33xx_data.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/clock33xx_data.c 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/clock33xx_data.c 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,2233 @@
+/*
+ * AM33XX Clock data
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <plat/clkdev_omap.h>
+
+#include "control.h"
+#include "clock.h"
+#include "clock33xx.h"
+#include "cm.h"
+#include "cm33xx.h"
+#include "cm-regbits-33xx.h"
+#include "prm.h"
+
+/* Modulemode control */
+#define AM33XX_MODULEMODE_HWCTRL 0
+#define AM33XX_MODULEMODE_SWCTRL 1
+
+/* Root clocks */
+static struct clk clk_32768_ck = {
+ .name = "clk_32768_ck",
+ .rate = 32768,
+ .ops = &clkops_null,
+};
+
+/* On-Chip 32KHz RC OSC */
+static struct clk clk_rc32k_ck = {
+ .name = "clk_rc32k_ck",
+ .rate = 32000,
+ .ops = &clkops_null,
+};
+
+/* Crystal input clks */
+static struct clk virt_19_2m_ck = {
+ .name = "virt_19_2m_ck",
+ .rate = 19200000,
+ .ops = &clkops_null,
+};
+
+static struct clk virt_24m_ck = {
+ .name = "virt_24m_ck",
+ .rate = 24000000,
+ .ops = &clkops_null,
+};
+
+static struct clk virt_25m_ck = {
+ .name = "virt_25m_ck",
+ .rate = 25000000,
+ .ops = &clkops_null,
+};
+
+static struct clk virt_26m_ck = {
+ .name = "virt_26m_ck",
+ .rate = 26000000,
+ .ops = &clkops_null,
+};
+
+static struct clk tclkin_ck = {
+ .name = "tclkin_ck",
+ .rate = 12000000,
+ .ops = &clkops_null,
+};
+
+static const struct clksel_rate div_1_0_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
+ { .div = 0 },
+};
+
+static const struct clksel_rate div_1_1_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
+ { .div = 0 },
+};
+
+static const struct clksel_rate div_1_2_rates[] = {
+ { .div = 1, .val = 2, .flags = RATE_IN_AM33XX },
+ { .div = 0 },
+};
+
+static const struct clksel_rate div_1_3_rates[] = {
+ { .div = 1, .val = 3, .flags = RATE_IN_AM33XX },
+ { .div = 0 },
+};
+
+static const struct clksel_rate div_1_4_rates[] = {
+ { .div = 1, .val = 4, .flags = RATE_IN_AM33XX },
+ { .div = 0 },
+};
+
+static const struct clksel_rate div31_1to31_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_AM33XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_AM33XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_AM33XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_AM33XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_AM33XX },
+ { .div = 7, .val = 7, .flags = RATE_IN_AM33XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_AM33XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_AM33XX },
+ { .div = 10, .val = 10, .flags = RATE_IN_AM33XX },
+ { .div = 11, .val = 11, .flags = RATE_IN_AM33XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_AM33XX },
+ { .div = 13, .val = 13, .flags = RATE_IN_AM33XX },
+ { .div = 14, .val = 14, .flags = RATE_IN_AM33XX },
+ { .div = 15, .val = 15, .flags = RATE_IN_AM33XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_AM33XX },
+ { .div = 17, .val = 17, .flags = RATE_IN_AM33XX },
+ { .div = 18, .val = 18, .flags = RATE_IN_AM33XX },
+ { .div = 19, .val = 19, .flags = RATE_IN_AM33XX },
+ { .div = 20, .val = 20, .flags = RATE_IN_AM33XX },
+ { .div = 21, .val = 21, .flags = RATE_IN_AM33XX },
+ { .div = 22, .val = 22, .flags = RATE_IN_AM33XX },
+ { .div = 23, .val = 23, .flags = RATE_IN_AM33XX },
+ { .div = 24, .val = 24, .flags = RATE_IN_AM33XX },
+ { .div = 25, .val = 25, .flags = RATE_IN_AM33XX },
+ { .div = 26, .val = 26, .flags = RATE_IN_AM33XX },
+ { .div = 27, .val = 27, .flags = RATE_IN_AM33XX },
+ { .div = 28, .val = 28, .flags = RATE_IN_AM33XX },
+ { .div = 29, .val = 29, .flags = RATE_IN_AM33XX },
+ { .div = 30, .val = 30, .flags = RATE_IN_AM33XX },
+ { .div = 31, .val = 31, .flags = RATE_IN_AM33XX },
+ { .div = 0 },
+};
+
+/* Oscillator clock */
+/* 19.2, 24, 25 or 26 MHz */
+static const struct clksel sys_clkin_sel[] = {
+ { .parent = &virt_19_2m_ck, .rates = div_1_0_rates },
+ { .parent = &virt_24m_ck, .rates = div_1_1_rates },
+ { .parent = &virt_25m_ck, .rates = div_1_2_rates },
+ { .parent = &virt_26m_ck, .rates = div_1_3_rates },
+ { .parent = NULL },
+};
+
+/* sys_clk_in */
+static struct clk sys_clkin_ck = {
+ .name = "sys_clkin_ck",
+ .parent = &virt_24m_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = AM33XX_CTRL_REGADDR(0x40), /* CONTROL_STATUS */
+ .clksel_mask = (0x3 << 22),
+ .clksel = sys_clkin_sel,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* DPLL_CORE */
+static struct dpll_data dpll_core_dd = {
+ .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
+ .clk_bypass = &sys_clkin_ck,
+ .clk_ref = &sys_clkin_ck,
+ .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
+ .mult_mask = AM33XX_DPLL_MULT_MASK,
+ .div1_mask = AM33XX_DPLL_DIV_MASK,
+ .enable_mask = AM33XX_DPLL_EN_MASK,
+ .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = AM33XX_MAX_DPLL_MULT,
+ .max_divider = AM33XX_MAX_DPLL_DIV,
+ .min_divider = 1,
+};
+
+/* CLKDCOLDO output */
+static struct clk dpll_core_ck = {
+ .name = "dpll_core_ck",
+ .parent = &sys_clkin_ck,
+ .dpll_data = &dpll_core_dd,
+ .init = &omap2_init_dpll_parent,
+ .ops = &clkops_omap3_core_dpll_ops,
+ .recalc = &omap3_dpll_recalc,
+};
+
+static struct clk dpll_core_x2_ck = {
+ .name = "dpll_core_x2_ck",
+ .parent = &dpll_core_ck,
+ .flags = CLOCK_CLKOUTX2,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+
+static const struct clksel dpll_core_m4_div[] = {
+ { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
+static struct clk dpll_core_m4_ck = {
+ .name = "dpll_core_m4_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m4_div,
+ .clksel_reg = AM33XX_CM_DIV_M4_DPLL_CORE,
+ .clksel_mask = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static const struct clksel dpll_core_m5_div[] = {
+ { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
+static struct clk dpll_core_m5_ck = {
+ .name = "dpll_core_m5_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m5_div,
+ .clksel_reg = AM33XX_CM_DIV_M5_DPLL_CORE,
+ .clksel_mask = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static const struct clksel dpll_core_m6_div[] = {
+ { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
+static struct clk dpll_core_m6_ck = {
+ .name = "dpll_core_m6_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m6_div,
+ .clksel_reg = AM33XX_CM_DIV_M6_DPLL_CORE,
+ .clksel_mask = AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static struct clk sysclk1_ck = {
+ .name = "sysclk1_ck",
+ .parent = &dpll_core_m4_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sysclk2_ck = {
+ .name = "sysclk2_ck",
+ .parent = &dpll_core_m5_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk core_clk_out = {
+ .name = "core_clk_out",
+ .parent = &dpll_core_m4_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+/* DPLL_MPU */
+static struct dpll_data dpll_mpu_dd = {
+ .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
+ .clk_bypass = &sys_clkin_ck,
+ .clk_ref = &sys_clkin_ck,
+ .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
+ .mult_mask = AM33XX_DPLL_MULT_MASK,
+ .div1_mask = AM33XX_DPLL_DIV_MASK,
+ .enable_mask = AM33XX_DPLL_EN_MASK,
+ .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = AM33XX_MAX_DPLL_MULT,
+ .max_divider = AM33XX_MAX_DPLL_DIV,
+ .min_divider = 1,
+};
+
+/* CLKOUT: fdpll/M2 */
+static struct clk dpll_mpu_ck = {
+ .name = "dpll_mpu_ck",
+ .parent = &sys_clkin_ck,
+ .dpll_data = &dpll_mpu_dd,
+ .init = &omap2_init_dpll_parent,
+ .ops = &clkops_omap3_noncore_dpll_ops,
+ .recalc = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+};
+
+/*
+ * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
+ * and ALT_CLK1/2)
+ */
+static const struct clksel dpll_mpu_m2_div[] = {
+ { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
+static struct clk dpll_mpu_m2_ck = {
+ .name = "dpll_mpu_m2_ck",
+ .parent = &dpll_mpu_ck,
+ .clksel = dpll_mpu_m2_div,
+ .clksel_reg = AM33XX_CM_DIV_M2_DPLL_MPU,
+ .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static struct clk mpu_fck = {
+ .name = "mpu_fck",
+ .clkdm_name = "mpu_clkdm",
+ .parent = &dpll_mpu_m2_ck,
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = AM33XX_CM_MPU_MPU_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .recalc = &followparent_recalc,
+ .flags = ENABLE_ON_INIT,
+};
+
+/* DPLL_DDR */
+static struct dpll_data dpll_ddr_dd = {
+ .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
+ .clk_bypass = &sys_clkin_ck,
+ .clk_ref = &sys_clkin_ck,
+ .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
+ .mult_mask = AM33XX_DPLL_MULT_MASK,
+ .div1_mask = AM33XX_DPLL_DIV_MASK,
+ .enable_mask = AM33XX_DPLL_EN_MASK,
+ .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = AM33XX_MAX_DPLL_MULT,
+ .max_divider = AM33XX_MAX_DPLL_DIV,
+ .min_divider = 1,
+};
+
+/* CLKOUT: fdpll/M2 */
+static struct clk dpll_ddr_ck = {
+ .name = "dpll_ddr_ck",
+ .parent = &sys_clkin_ck,
+ .dpll_data = &dpll_ddr_dd,
+ .init = &omap2_init_dpll_parent,
+ .ops = &clkops_null,
+ .recalc = &omap3_dpll_recalc,
+};
+
+/*
+ * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
+ * and ALT_CLK1/2)
+ */
+static const struct clksel dpll_ddr_m2_div[] = {
+ { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
+static struct clk dpll_ddr_m2_ck = {
+ .name = "dpll_ddr_m2_ck",
+ .parent = &dpll_ddr_ck,
+ .clksel = dpll_ddr_m2_div,
+ .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DDR,
+ .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static struct clk ddr_pll_clk = {
+ .name = "ddr_pll_clk",
+ .parent = &dpll_ddr_m2_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk emif_fck = {
+ .name = "emif_fck",
+ .clkdm_name = "l3_clkdm",
+ .parent = &ddr_pll_clk,
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = AM33XX_CM_PER_EMIF_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
+ .flags = ENABLE_ON_INIT,
+};
+
+/* DPLL_DISP */
+static struct dpll_data dpll_disp_dd = {
+ .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
+ .clk_bypass = &sys_clkin_ck,
+ .clk_ref = &sys_clkin_ck,
+ .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
+ .mult_mask = AM33XX_DPLL_MULT_MASK,
+ .div1_mask = AM33XX_DPLL_DIV_MASK,
+ .enable_mask = AM33XX_DPLL_EN_MASK,
+ .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = AM33XX_MAX_DPLL_MULT,
+ .max_divider = AM33XX_MAX_DPLL_DIV,
+ .min_divider = 1,
+};
+
+/* CLKOUT: fdpll/M2 */
+static struct clk dpll_disp_ck = {
+ .name = "dpll_disp_ck",
+ .parent = &sys_clkin_ck,
+ .dpll_data = &dpll_disp_dd,
+ .init = &omap2_init_dpll_parent,
+ .ops = &clkops_null,
+ .recalc = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+};
+
+/*
+ * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
+ * and ALT_CLK1/2)
+ */
+static const struct clksel dpll_disp_m2_div[] = {
+ { .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
+static struct clk dpll_disp_m2_ck = {
+ .name = "dpll_disp_m2_ck",
+ .parent = &dpll_disp_ck,
+ .clksel = dpll_disp_m2_div,
+ .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DISP,
+ .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static struct clk disp_pll_clk = {
+ .name = "disp_pll_clk",
+ .parent = &dpll_disp_m2_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+/* DPLL_PER */
+static struct dpll_data dpll_per_dd = {
+ .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
+ .clk_bypass = &sys_clkin_ck,
+ .clk_ref = &sys_clkin_ck,
+ .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
+ .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
+ .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
+ .enable_mask = AM33XX_DPLL_EN_MASK,
+ .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = AM33XX_MAX_DPLL_MULT,
+ .max_divider = AM33XX_MAX_DPLL_DIV,
+ .min_divider = 1,
+ .flags = DPLL_J_TYPE,
+};
+
+/* CLKDCOLDO */
+static struct clk dpll_per_ck = {
+ .name = "dpll_per_ck",
+ .parent = &sys_clkin_ck,
+ .dpll_data = &dpll_per_dd,
+ .init = &omap2_init_dpll_parent,
+ .ops = &clkops_null,
+ .recalc = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+};
+
+/* CLKOUT: fdpll/M2 */
+static const struct clksel dpll_per_m2_div[] = {
+ { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
+static struct clk dpll_per_m2_ck = {
+ .name = "dpll_per_m2_ck",
+ .parent = &dpll_per_ck,
+ .clksel = dpll_per_m2_div,
+ .clksel_reg = AM33XX_CM_DIV_M2_DPLL_PER,
+ .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static struct clk per_192mhz_clk = {
+ .name = "per_192mhz_clk",
+ .parent = &dpll_per_m2_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usb_pll_clk = {
+ .name = "usb_pll_clk",
+ .parent = &dpll_per_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk core_100mhz_ck = {
+ .name = "core_100mhz_ck",
+ .parent = &sysclk1_ck,
+ .ops = &clkops_null,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk l3_aon_gclk = {
+ .name = "l3_aon_gclk",
+ .parent = &sysclk1_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l4_wkup_aon_gclk = {
+ .name = "l4_wkup_aon_gclk",
+ .clkdm_name = "l4_wkup_aon_clkdm",
+ .parent = &sysclk1_ck,
+ .enable_reg = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_null,
+ .fixed_div = 2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l3_gclk = {
+ .name = "l3_gclk",
+ .parent = &sysclk1_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l3_ick = {
+ .name = "l3_ick",
+ .clkdm_name = "l3_clkdm",
+ .parent = &l3_gclk,
+ .enable_reg = AM33XX_CM_PER_L3_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .flags = ENABLE_ON_INIT,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l3_instr_ick = {
+ .name = "l3_instr_ick",
+ .clkdm_name = "l3_clkdm",
+ .parent = &l3_gclk,
+ .enable_reg = AM33XX_CM_PER_L3_INSTR_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .flags = ENABLE_ON_INIT,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l4_wkup_gclk = {
+ .name = "l4_wkup_gclk",
+ .parent = &sysclk1_ck,
+ .ops = &clkops_null,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk l4hs_gclk = {
+ .name = "l4hs_gclk",
+ .parent = &sysclk1_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gfx_l3_gclk = {
+ .name = "gfx_l3_gclk",
+ .clkdm_name = "gfx_l3_clkdm",
+ .parent = &sysclk1_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk debug_clka_gclk = {
+ .name = "debug_clka_gclk",
+ .parent = &sysclk1_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l4_rtc_gclk = {
+ .name = "l4_rtc_gclk",
+ .parent = &sysclk1_ck,
+ .ops = &clkops_null,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk rtc_ick = {
+ .name = "rtc_ick",
+ .parent = &l4_rtc_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l3s_gclk = {
+ .name = "l3s_gclk",
+ .parent = &core_100mhz_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l4fw_gclk = {
+ .name = "l4fw_gclk",
+ .parent = &core_100mhz_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l4ls_gclk = {
+ .name = "l4ls_gclk",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &core_100mhz_ck,
+ .enable_reg = AM33XX_CM_PER_L4LS_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk clk_24mhz = {
+ .name = "clk_24mhz",
+ .parent = &per_192mhz_clk,
+ .fixed_div = 8,
+ .ops = &clkops_null,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk l4_cefuse_gclk = {
+ .name = "l4_cefsue_gclk",
+ .parent = &core_100mhz_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk cefuse_iclk = {
+ .name = "cefuse_iclk",
+ .clkdm_name = "l4_cefuse_clkdm",
+ .parent = &l4_cefuse_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk cefuse_fck = {
+ .name = "cefuse_fck",
+ .clkdm_name = "l4_cefuse_clkdm",
+ .parent = &sys_clkin_ck,
+ .enable_reg = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sysclk_div_ck = {
+ .name = "sysclk_div_ck",
+ .parent = &dpll_core_m4_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk adc_tsc_fck = {
+ .name = "adc_tsc_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &sys_clkin_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk adc_tsc_ick = {
+ .name = "adc_tsc_ick",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &l4_wkup_gclk,
+ .enable_reg = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk aes0_fck = {
+ .name = "aes0_fck",
+ .clkdm_name = "l3_clkdm",
+ .parent = &l3_gclk,
+ .enable_reg = AM33XX_CM_PER_AES0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * clkdiv32 is generated from fixed division of 732.4219
+ */
+static struct clk clkdiv32k_ick = {
+ .name = "clkdiv32k_ick",
+ .clkdm_name = "clk_24mhz_clkdm",
+ .rate = 32768,
+ .parent = &clk_24mhz,
+ .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+};
+
+static struct clk clk_32khz_ck = {
+ .name = "clk_32khz_ck",
+ .clkdm_name = "clk_24mhz_clkdm",
+ .parent = &clkdiv32k_ick,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk control_fck = {
+ .name = "control_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &l4_wkup_gclk,
+ .enable_reg = AM33XX_CM_WKUP_CONTROL_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dcan0_ick = {
+ .name = "dcan0_ick",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dcan0_fck = {
+ .name = "dcan0_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &sys_clkin_ck,
+ .enable_reg = AM33XX_CM_PER_DCAN0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dcan1_ick = {
+ .name = "dcan1_ick",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dcan1_fck = {
+ .name = "dcan1_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &sys_clkin_ck,
+ .enable_reg = AM33XX_CM_PER_DCAN1_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk debugss_ick = {
+ .name = "debugss_ick",
+ .clkdm_name = "l3_aon_clkdm",
+ .parent = &l3_aon_gclk,
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk elm_fck = {
+ .name = "elm_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_ELM_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk emif_fw_fck = {
+ .name = "emif_fw_fck",
+ .clkdm_name = "l4fw_clkdm",
+ .parent = &l4fw_gclk,
+ .enable_reg = AM33XX_CM_PER_EMIF_FW_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk epwmss0_fck = {
+ .name = "epwmss0_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_EPWMSS0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk epwmss1_fck = {
+ .name = "epwmss1_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_EPWMSS1_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk epwmss2_fck = {
+ .name = "epwmss2_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_EPWMSS2_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpmc_fck = {
+ .name = "gpmc_fck",
+ .clkdm_name = "l3s_clkdm",
+ .parent = &l3s_gclk,
+ .enable_reg = AM33XX_CM_PER_GPMC_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+ .name = "i2c1_ick",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &l4_wkup_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+ .name = "i2c1_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &per_192mhz_clk,
+ .enable_reg = AM33XX_CM_WKUP_I2C0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .fixed_div = 4,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk i2c2_ick = {
+ .name = "i2c2_ick",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+ .name = "i2c2_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &per_192mhz_clk,
+ .enable_reg = AM33XX_CM_PER_I2C1_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .fixed_div = 4,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk i2c3_ick = {
+ .name = "i2c3_ick",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c3_fck = {
+ .name = "i2c3_fck",
+ .parent = &per_192mhz_clk,
+ .enable_reg = AM33XX_CM_PER_I2C2_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .clkdm_name = "l4ls_clkdm",
+ .fixed_div = 4,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk ieee5000_fck = {
+ .name = "ieee5000_fck",
+ .clkdm_name = "l3s_clkdm",
+ .parent = &l3s_gclk,
+ .enable_reg = AM33XX_CM_PER_IEEE5000_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l4hs_ick = {
+ .name = "l4hs_ick",
+ .clkdm_name = "l4hs_clkdm",
+ .parent = &l4hs_gclk,
+ .enable_reg = AM33XX_CM_PER_L4HS_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .flags = ENABLE_ON_INIT,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l4wkup_ick = {
+ .name = "l4wkup_ick",
+ .clkdm_name = "l4_wkup_aon_clkdm",
+ .parent = &l4_wkup_aon_gclk,
+ .enable_reg = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .flags = ENABLE_ON_INIT,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l4fw_ick = {
+ .name = "l4fw_ick",
+ .clkdm_name = "l4fw_clkdm",
+ .parent = &core_100mhz_ck,
+ .enable_reg = AM33XX_CM_PER_L4FW_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .flags = ENABLE_ON_INIT,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk l4ls_ick = {
+ .name = "l4ls_ick",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_L4LS_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .flags = ENABLE_ON_INIT,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mailbox0_fck = {
+ .name = "mailbox0_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_MAILBOX0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcasp0_ick = {
+ .name = "mcasp0_ick",
+ .parent = &l3s_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcasp0_fck = {
+ .name = "mcasp0_fck",
+ .clkdm_name = "l3s_clkdm",
+ .parent = &sys_clkin_ck,
+ .enable_reg = AM33XX_CM_PER_MCASP0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcasp1_ick = {
+ .name = "mcasp1_ick",
+ .parent = &l3s_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcasp1_fck = {
+ .name = "mcasp1_fck",
+ .clkdm_name = "l3s_clkdm",
+ .parent = &sys_clkin_ck,
+ .enable_reg = AM33XX_CM_PER_MCASP1_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mlb_fck = {
+ .name = "mlb_fck",
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = AM33XX_CM_PER_MLB_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .clkdm_name = "l3_clkdm",
+ .parent = &sysclk_div_ck,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmu_fck = {
+ .name = "mmu_fck",
+ .clkdm_name = "gfx_l3_clkdm",
+ .parent = &gfx_l3_gclk,
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = AM33XX_CM_GFX_MMUDATA_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk ocmcram_ick = {
+ .name = "ocmcram_ick",
+ .clkdm_name = "l3_clkdm",
+ .parent = &l3_gclk,
+ .enable_reg = AM33XX_CM_PER_OCMCRAM_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk ocpwp_fck = {
+ .name = "ocpwp_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_OCPWP_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk pka_fck = {
+ .name = "pka_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_PKA_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk rng_fck = {
+ .name = "rng_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_RNG_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk rtc_fck = {
+ .name = "rtc_fck",
+ .clkdm_name = "l4_rtc_clkdm",
+ .parent = &clk_32768_ck,
+ .enable_reg = AM33XX_CM_RTC_RTC_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sha0_fck = {
+ .name = "sha0_fck",
+ .clkdm_name = "l3_clkdm",
+ .parent = &l3_gclk,
+ .enable_reg = AM33XX_CM_PER_SHA0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk smartreflex0_ick = {
+ .name = "smartreflex0_ick",
+ .parent = &l4_wkup_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk smartreflex0_fck = {
+ .name = "smartreflex0_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &sys_clkin_ck,
+ .enable_reg = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk smartreflex1_ick = {
+ .name = "smartreflex1_ick",
+ .parent = &l4_wkup_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk smartreflex1_fck = {
+ .name = "smartreflex1_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &sys_clkin_ck,
+ .enable_reg = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk spi0_ick = {
+ .name = "spi0_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk spi0_fck = {
+ .name = "spi0_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &per_192mhz_clk,
+ .enable_reg = AM33XX_CM_PER_SPI0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .fixed_div = 4,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk spi1_ick = {
+ .name = "spi1_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk spi1_fck = {
+ .name = "spi1_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &per_192mhz_clk,
+ .enable_reg = AM33XX_CM_PER_SPI1_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .fixed_div = 4,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk spinlock_fck = {
+ .name = "spinlock_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_SPINLOCK_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk clk_32khz_timer = {
+ .name = "clk_32khz_timer",
+ .parent = &clk_32khz_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+/* Timers */
+
+/* Secure Timer: Used only to disable the clocks and for completeness */
+static const struct clksel timer0_clkmux_sel[] = {
+ { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
+ { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
+ { .parent = &sys_clkin_ck, .rates = div_1_2_rates },
+ { .parent = &tclkin_ck, .rates = div_1_3_rates },
+ { .parent = NULL },
+};
+
+static struct clk timer0_ick = {
+ .name = "timer0_ick",
+ .parent = &l4_wkup_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk timer0_fck = {
+ .name = "timer0_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &clk_rc32k_ck,
+ .clksel = timer0_clkmux_sel,
+ .enable_reg = AM33XX_CM_WKUP_TIMER0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .clksel_reg = AM33XX_CTRL_REGADDR(0x01BC),
+ .clksel_mask = (0x3 << 4),
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static const struct clksel timer1_clkmux_sel[] = {
+ { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+ { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
+ { .parent = &tclkin_ck, .rates = div_1_2_rates },
+ { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
+ { .parent = &clk_32768_ck, .rates = div_1_4_rates },
+ { .parent = NULL },
+};
+
+static struct clk timer1_ick = {
+ .name = "timer1_ick",
+ .parent = &l4_wkup_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk timer1_fck = {
+ .name = "timer1_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel = timer1_clkmux_sel,
+ .enable_reg = AM33XX_CM_WKUP_TIMER1_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
+ .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel timer2_to_7_clk_sel[] = {
+ { .parent = &tclkin_ck, .rates = div_1_0_rates },
+ { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
+ { .parent = &clk_32khz_timer, .rates = div_1_2_rates },
+ { .parent = NULL },
+};
+
+static struct clk timer2_ick = {
+ .name = "timer2_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk timer2_fck = {
+ .name = "timer2_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel = timer2_to_7_clk_sel,
+ .enable_reg = AM33XX_CM_PER_TIMER2_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
+ .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk timer3_ick = {
+ .name = "timer3_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk timer3_fck = {
+ .name = "timer3_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &sys_clkin_ck,
+ .init = &am33xx_init_timer_parent,
+ .clksel = timer2_to_7_clk_sel,
+ .enable_reg = AM33XX_CM_PER_TIMER3_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
+ .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk timer4_ick = {
+ .name = "timer4_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk timer4_fck = {
+ .name = "timer4_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel = timer2_to_7_clk_sel,
+ .enable_reg = AM33XX_CM_PER_TIMER4_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
+ .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk timer5_ick = {
+ .name = "timer5_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk timer5_fck = {
+ .name = "timer5_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel = timer2_to_7_clk_sel,
+ .enable_reg = AM33XX_CM_PER_TIMER5_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
+ .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk timer6_ick = {
+ .name = "timer6_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk timer6_fck = {
+ .name = "timer6_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &sys_clkin_ck,
+ .init = &am33xx_init_timer_parent,
+ .clksel = timer2_to_7_clk_sel,
+ .enable_reg = AM33XX_CM_PER_TIMER6_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
+ .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk timer7_ick = {
+ .name = "timer7_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk timer7_fck = {
+ .name = "timer7_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel = timer2_to_7_clk_sel,
+ .enable_reg = AM33XX_CM_PER_TIMER7_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
+ .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk tpcc_ick = {
+ .name = "tpcc_ick",
+ .clkdm_name = "l3_clkdm",
+ .parent = &l3_gclk,
+ .enable_reg = AM33XX_CM_PER_TPCC_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk tptc0_ick = {
+ .name = "tptc0_ick",
+ .parent = &l3_gclk,
+ .clkdm_name = "l3_clkdm",
+ .enable_reg = AM33XX_CM_PER_TPTC0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk tptc1_ick = {
+ .name = "tptc1_ick",
+ .clkdm_name = "l3_clkdm",
+ .parent = &l3_gclk,
+ .enable_reg = AM33XX_CM_PER_TPTC1_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk tptc2_ick = {
+ .name = "tptc2_ick",
+ .clkdm_name = "l3_clkdm",
+ .parent = &l3_gclk,
+ .enable_reg = AM33XX_CM_PER_TPTC2_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+ .name = "uart1_ick",
+ .parent = &l4_wkup_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+ .name = "uart1_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &per_192mhz_clk,
+ .enable_reg = AM33XX_CM_WKUP_UART0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .fixed_div = 4,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk uart2_ick = {
+ .name = "uart2_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+ .name = "uart2_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &per_192mhz_clk,
+ .enable_reg = AM33XX_CM_PER_UART1_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .fixed_div = 4,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk uart3_ick = {
+ .name = "uart3_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+ .name = "uart3_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &per_192mhz_clk,
+ .enable_reg = AM33XX_CM_PER_UART2_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .fixed_div = 4,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk uart4_ick = {
+ .name = "uart4_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart4_fck = {
+ .name = "uart4_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &per_192mhz_clk,
+ .enable_reg = AM33XX_CM_PER_UART3_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .fixed_div = 4,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk uart5_ick = {
+ .name = "uart5_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart5_fck = {
+ .name = "uart5_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &per_192mhz_clk,
+ .enable_reg = AM33XX_CM_PER_UART4_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .fixed_div = 4,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk uart6_ick = {
+ .name = "uart6_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart6_fck = {
+ .name = "uart6_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &per_192mhz_clk,
+ .enable_reg = AM33XX_CM_PER_UART5_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .fixed_div = 4,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk wkup_m3_fck = {
+ .name = "wkup_m3_fck",
+ .clkdm_name = "l4_wkup_aon_clkdm",
+ .parent = &l4_wkup_aon_gclk,
+ .enable_reg = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk cpsw_250mhz_clk = {
+ .name = "cpsw_250mhz_clk",
+ .clkdm_name = "l4hs_clkdm",
+ .parent = &sysclk2_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk cpsw_125mhz_gclk = {
+ .name = "cpsw_125mhz_gclk",
+ .clkdm_name = "cpsw_125mhz_clkdm",
+ .parent = &sysclk2_ck,
+ .ops = &clkops_null,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+/*
+ * TODO: As per clock tree @OPP50 /2 is used, but there is not register
+ * to configure this. @ normal OPP, /5 is used - 250MHz/5 = 50MHz
+ */
+static struct clk cpsw_50mhz_clk = {
+ .name = "cpsw_50mhz_clk",
+ .clkdm_name = "l4hs_clkdm",
+ .parent = &sysclk2_ck,
+ .ops = &clkops_null,
+ .fixed_div = 5,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk cpsw_5mhz_clk = {
+ .name = "cpsw_5mhz_clk",
+ .clkdm_name = "l4hs_clkdm",
+ .parent = &cpsw_50mhz_clk,
+ .ops = &clkops_null,
+ .fixed_div = 10,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk cpgmac0_ick = {
+ .name = "cpgmac0_ick",
+ .clkdm_name = "cpsw_125mhz_clkdm",
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = AM33XX_CM_PER_CPGMAC0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .parent = &cpsw_125mhz_gclk,
+ .recalc = &followparent_recalc,
+};
+
+static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
+ { .parent = &sysclk2_ck, .rates = div_1_0_rates },
+ { .parent = &sysclk1_ck, .rates = div_1_1_rates },
+ { .parent = NULL },
+};
+
+static struct clk cpsw_cpts_rft_clk = {
+ .name = "cpsw_cpts_rft_clk",
+ .clkdm_name = "l3_clkdm",
+ .parent = &dpll_core_m5_ck,
+ .clksel = cpsw_cpts_rft_clkmux_sel,
+ .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
+ .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbotg_ick = {
+ .name = "usbotg_ick",
+ .clkdm_name = "l3s_clkdm",
+ .parent = &l3s_gclk,
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = AM33XX_CM_PER_USB0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbotg_fck = {
+ .name = "usbotg_fck",
+ .clkdm_name = "l3s_clkdm",
+ .parent = &usb_pll_clk,
+ .enable_reg = AM33XX_CM_CLKDCOLDO_DPLL_PER,
+ .enable_bit = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+/* gpio */
+static const struct clksel gpio0_dbclk_mux_sel[] = {
+ { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
+ { .parent = &clk_32768_ck, .rates = div_1_1_rates },
+ { .parent = &clk_32khz_timer, .rates = div_1_2_rates },
+ { .parent = NULL },
+};
+
+static struct clk gpio0_dbclk_mux_ck = {
+ .name = "gpio0_dbclk_mux_ck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &clk_rc32k_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel = gpio0_dbclk_mux_sel,
+ .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
+ .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpio0_dbclk = {
+ .name = "gpio0_dbclk",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &gpio0_dbclk_mux_ck,
+ .enable_reg = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
+ .enable_bit = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio0_ick = {
+ .name = "gpio0_ick",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &l4_wkup_gclk,
+ .enable_reg = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio1_dbclk = {
+ .name = "gpio1_dbclk",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &clkdiv32k_ick,
+ .enable_reg = AM33XX_CM_PER_GPIO1_CLKCTRL,
+ .enable_bit = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio1_ick = {
+ .name = "gpio1_ick",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_GPIO1_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio2_dbclk = {
+ .name = "gpio2_dbclk",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &clkdiv32k_ick,
+ .enable_reg = AM33XX_CM_PER_GPIO2_CLKCTRL,
+ .enable_bit = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio2_ick = {
+ .name = "gpio2_ick",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_GPIO2_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio3_dbclk = {
+ .name = "gpio3_dbclk",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &clkdiv32k_ick,
+ .enable_reg = AM33XX_CM_PER_GPIO3_CLKCTRL,
+ .enable_bit = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio3_ick = {
+ .name = "gpio3_ick",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &l4ls_gclk,
+ .enable_reg = AM33XX_CM_PER_GPIO3_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static const struct clksel pruss_ocp_clk_mux_sel[] = {
+ { .parent = &l3_gclk, .rates = div_1_0_rates },
+ { .parent = &disp_pll_clk, .rates = div_1_1_rates },
+ { .parent = NULL },
+};
+
+static struct clk pruss_ocp_gclk = {
+ .name = "pruss_ocp_gclk",
+ .parent = &l3_gclk,
+ .init = &omap2_init_clksel_parent,
+ .clksel = pruss_ocp_clk_mux_sel,
+ .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
+ .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk pruss_iep_gclk = {
+ .name = "pruss_iep_gclk",
+ .clkdm_name = "pruss_ocp_clkdm",
+ .parent = &l3_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk pruss_uart_gclk = {
+ .name = "pruss_uart_gclk",
+ .clkdm_name = "pruss_ocp_clkdm",
+ .parent = &per_192mhz_clk,
+ .enable_reg = AM33XX_CM_PER_PRUSS_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk lcdc_ick = {
+ .name = "lcdc_ick",
+ .clkdm_name = "l3_clkdm",
+ .parent = &sysclk1_ck,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static const struct clksel lcd_clk_mux_sel[] = {
+ { .parent = &disp_pll_clk, .rates = div_1_0_rates },
+ { .parent = &sysclk2_ck, .rates = div_1_1_rates },
+ { .parent = &per_192mhz_clk, .rates = div_1_2_rates },
+ { .parent = NULL },
+};
+
+static struct clk lcd_gclk = {
+ .name = "lcd_gclk",
+ .parent = &disp_pll_clk,
+ .init = &omap2_init_clksel_parent,
+ .clksel = lcd_clk_mux_sel,
+ .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
+ .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk lcdc_fck = {
+ .name = "lcdc_fck",
+ .clkdm_name = "lcdc_clkdm",
+ .parent = &lcd_gclk,
+ .enable_reg = AM33XX_CM_PER_LCDC_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmc_clk = {
+ .name = "mmc_clk",
+ .parent = &per_192mhz_clk,
+ .ops = &clkops_null,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static struct clk mmc0_ick = {
+ .name = "mmc0_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmc0_fck = {
+ .name = "mmc0_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &mmc_clk,
+ .enable_reg = AM33XX_CM_PER_MMC0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmc1_ick = {
+ .name = "mmc1_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmc1_fck = {
+ .name = "mmc1_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .parent = &mmc_clk,
+ .enable_reg = AM33XX_CM_PER_MMC1_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmc2_ick = {
+ .name = "mmc2_ick",
+ .parent = &l4ls_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmc2_fck = {
+ .name = "mmc2_fck",
+ .clkdm_name = "l3s_clkdm",
+ .parent = &mmc_clk,
+ .enable_reg = AM33XX_CM_PER_MMC2_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static const struct clksel gfx_clksel_sel[] = {
+ { .parent = &sysclk1_ck, .rates = div_1_0_rates },
+ { .parent = &per_192mhz_clk, .rates = div_1_1_rates },
+ { .parent = NULL },
+};
+
+static struct clk gfx_fclk_clksel_ck = {
+ .name = "gfx_fclk_clksel_ck",
+ .parent = &sysclk1_ck,
+ .clksel = gfx_clksel_sel,
+ .ops = &clkops_null,
+ .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
+ .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate div_1_0_2_1_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
+ { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
+ { .div = 0 },
+};
+
+static const struct clksel gfx_div_sel[] = {
+ { .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates },
+ { .parent = NULL },
+};
+
+static struct clk gfx_ick = {
+ .name = "gfx_ick",
+ .clkdm_name = "gfx_l3_clkdm",
+ .parent = &gfx_l3_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gfx_fclk = {
+ .name = "gfx_fclk",
+ .clkdm_name = "gfx_l3_clkdm",
+ .parent = &gfx_fclk_clksel_ck,
+ .clksel = gfx_div_sel,
+ .enable_reg = AM33XX_CM_GFX_GFX_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
+ .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+ .ops = &clkops_omap2_dflt,
+};
+
+static const struct clksel sysclkout_pre_sel[] = {
+ { .parent = &clk_32768_ck, .rates = div_1_0_rates },
+ { .parent = &l3_gclk, .rates = div_1_1_rates },
+ { .parent = &ddr_pll_clk, .rates = div_1_2_rates },
+ { .parent = &per_192mhz_clk, .rates = div_1_3_rates },
+ { .parent = &lcd_gclk, .rates = div_1_4_rates },
+ { .parent = NULL },
+};
+
+static struct clk sysclkout_pre_ck = {
+ .name = "sysclkout_pre_ck",
+ .parent = &clk_32768_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel = sysclkout_pre_sel,
+ .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
+ .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* Divide by 8 clock rates with default clock is 1/1*/
+static const struct clksel_rate div8_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
+ { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
+ { .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
+ { .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
+ { .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
+ { .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
+ { .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
+ { .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
+ { .div = 0 },
+};
+
+static const struct clksel clkout2_div[] = {
+ { .parent = &sysclkout_pre_ck, .rates = div8_rates },
+ { .parent = NULL },
+};
+
+static struct clk clkout2_ck = {
+ .name = "clkout2_ck",
+ .parent = &sysclkout_pre_ck,
+ .ops = &clkops_omap2_dflt,
+ .clksel = clkout2_div,
+ .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
+ .clksel_mask = AM33XX_CLKOUT2DIV_MASK,
+ .enable_reg = AM33XX_CM_CLKOUT_CTRL,
+ .enable_bit = AM33XX_CLKOUT2EN_SHIFT,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static struct clk vtp_clk = {
+ .name = "vtp_clk",
+ .parent = &sys_clkin_ck,
+ .ops = &clkops_null,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+static const struct clksel wdt_clkmux_sel[] = {
+ { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
+ { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
+ { .parent = NULL },
+};
+
+static struct clk wdt0_ick = {
+ .name = "wdt0_ick",
+ .parent = &l4_wkup_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt0_fck = {
+ .name = "wdt0_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &clk_rc32k_ck,
+ .clksel = wdt_clkmux_sel,
+ .enable_reg = AM33XX_CM_WKUP_WDT0_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt1_ick = {
+ .name = "wdt1_ick",
+ .parent = &l4_wkup_gclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt1_fck = {
+ .name = "wdt1_fck",
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &clk_rc32k_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel = wdt_clkmux_sel,
+ .enable_reg = AM33XX_CM_WKUP_WDT1_CLKCTRL,
+ .enable_bit = AM33XX_MODULEMODE_SWCTRL,
+ .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
+ .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
+ .ops = &clkops_omap2_dflt,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/*
+ * Provides clock definitions for enabling bits for Time base module in
+ * PWMSS ctrl register.
+ */
+
+static struct clk ehrpwm0_tbclk = {
+ .name = "ehrpwm0_tbclk",
+ .enable_reg = AM33XX_CONTROL_PWMSS_CTRL,
+ .enable_bit = AM33XX_PWMSS0_TBCLKEN,
+ .ops = &clkops_omap2_dflt,
+ .flags = ENABLE_ON_INIT,
+};
+
+static struct clk ehrpwm1_tbclk = {
+ .name = "ehrpwm1_tbclk",
+ .enable_reg = AM33XX_CONTROL_PWMSS_CTRL,
+ .enable_bit = AM33XX_PWMSS1_TBCLKEN,
+ .ops = &clkops_omap2_dflt,
+ .flags = ENABLE_ON_INIT,
+};
+
+static struct clk ehrpwm2_tbclk = {
+ .name = "ehrpwm2_tbclk",
+ .enable_reg = AM33XX_CONTROL_PWMSS_CTRL,
+ .enable_bit = AM33XX_PWMSS2_TBCLKEN,
+ .ops = &clkops_omap2_dflt,
+ .flags = ENABLE_ON_INIT,
+};
+
+
+/*
+ * clkdev
+ */
+static struct omap_clk am33xx_clks[] = {
+ CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX),
+ CLK(NULL, "clk_32khz_ck", &clk_32khz_ck, CK_AM33XX),
+ CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX),
+ CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_AM33XX),
+ CLK(NULL, "virt_24m_ck", &virt_24m_ck, CK_AM33XX),
+ CLK(NULL, "virt_25m_ck", &virt_25m_ck, CK_AM33XX),
+ CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_AM33XX),
+ CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX),
+ CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX),
+ CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX),
+ CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX),
+ CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX),
+ CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
+ CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
+ CLK(NULL, "sysclk1_ck", &sysclk1_ck, CK_AM33XX),
+ CLK(NULL, "sysclk2_ck", &sysclk2_ck, CK_AM33XX),
+ CLK(NULL, "core_clk_out", &core_clk_out, CK_AM33XX),
+ CLK(NULL, "clk_32khz_timer", &clk_32khz_timer, CK_AM33XX),
+ CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
+ CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
+ CLK(NULL, "mpu_ck", &mpu_fck, CK_AM33XX),
+ CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
+ CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),
+ CLK(NULL, "ddr_pll_clk", &ddr_pll_clk, CK_AM33XX),
+ CLK(NULL, "emif_fck", &emif_fck, CK_AM33XX),
+ CLK(NULL, "emif_fw_fck", &emif_fw_fck, CK_AM33XX),
+ CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX),
+ CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX),
+ CLK(NULL, "disp_pll_clk", &disp_pll_clk, CK_AM33XX),
+ CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX),
+ CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX),
+ CLK(NULL, "per_192mhz_clk", &per_192mhz_clk, CK_AM33XX),
+ CLK(NULL, "usb_pll_clk", &usb_pll_clk, CK_AM33XX),
+ CLK(NULL, "core_100mhz_ck", &core_100mhz_ck, CK_AM33XX),
+ CLK(NULL, "l3_ick", &l3_ick, CK_AM33XX),
+ CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_AM33XX),
+ CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX),
+ CLK(NULL, "adc_tsc_ick", &adc_tsc_ick, CK_AM33XX),
+ CLK(NULL, "aes0_fck", &aes0_fck, CK_AM33XX),
+ CLK(NULL, "l4_cefuse_gclk", &l4_cefuse_gclk, CK_AM33XX),
+ CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX),
+ CLK(NULL, "cefuse_iclk", &cefuse_iclk, CK_AM33XX),
+ CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX),
+ CLK(NULL, "control_fck", &control_fck, CK_AM33XX),
+ CLK("cpsw.0", NULL, &cpgmac0_ick, CK_AM33XX),
+ CLK("d_can.0", "fck", &dcan0_fck, CK_AM33XX),
+ CLK("d_can.1", "fck", &dcan1_fck, CK_AM33XX),
+ CLK("d_can.0", "ick", &dcan0_ick, CK_AM33XX),
+ CLK("d_can.1", "ick", &dcan1_ick, CK_AM33XX),
+ CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX),
+ CLK(NULL, "elm_fck", &elm_fck, CK_AM33XX),
+ CLK(NULL, "epwmss0_fck", &epwmss0_fck, CK_AM33XX),
+ CLK(NULL, "epwmss1_fck", &epwmss1_fck, CK_AM33XX),
+ CLK(NULL, "epwmss2_fck", &epwmss2_fck, CK_AM33XX),
+ CLK(NULL, "gpio0_ick", &gpio0_ick, CK_AM33XX),
+ CLK(NULL, "gpio1_ick", &gpio1_ick, CK_AM33XX),
+ CLK(NULL, "gpio2_ick", &gpio2_ick, CK_AM33XX),
+ CLK(NULL, "gpio3_ick", &gpio3_ick, CK_AM33XX),
+ CLK(NULL, "gpmc_fck", &gpmc_fck, CK_AM33XX),
+ CLK("omap_i2c.1", "fck", &i2c1_fck, CK_AM33XX),
+ CLK("omap_i2c.1", "ick", &i2c1_ick, CK_AM33XX),
+ CLK("omap_i2c.2", "fck", &i2c2_fck, CK_AM33XX),
+ CLK("omap_i2c.2", "ick", &i2c2_ick, CK_AM33XX),
+ CLK("omap_i2c.3", "fck", &i2c3_fck, CK_AM33XX),
+ CLK("omap_i2c.3", "ick", &i2c3_ick, CK_AM33XX),
+ CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX),
+ CLK(NULL, "pruss_uart_gclk", &pruss_uart_gclk, CK_AM33XX),
+ CLK(NULL, "pruss_iep_gclk", &pruss_iep_gclk, CK_AM33XX),
+ CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
+ CLK(NULL, "l4hs_ick", &l4hs_ick, CK_AM33XX),
+ CLK(NULL, "l4wkup_ick", &l4wkup_ick, CK_AM33XX),
+ CLK(NULL, "l4fw_ick", &l4fw_ick, CK_AM33XX),
+ CLK(NULL, "l4ls_ick", &l4ls_ick, CK_AM33XX),
+ CLK("da8xx_lcdc.0", NULL, &lcdc_fck, CK_AM33XX),
+ CLK(NULL, "mailbox0_fck", &mailbox0_fck, CK_AM33XX),
+ CLK(NULL, "mcasp1_ick", &mcasp0_ick, CK_AM33XX),
+ CLK("davinci-mcasp.0", NULL, &mcasp0_fck, CK_AM33XX),
+ CLK(NULL, "mcasp2_ick", &mcasp1_ick, CK_AM33XX),
+ CLK("davinci-mcasp.1", NULL, &mcasp1_fck, CK_AM33XX),
+ CLK(NULL, "mlb_fck", &mlb_fck, CK_AM33XX),
+ CLK("omap_hsmmc.0", "ick", &mmc0_ick, CK_AM33XX),
+ CLK("omap_hsmmc.1", "ick", &mmc1_ick, CK_AM33XX),
+ CLK("omap_hsmmc.2", "ick", &mmc2_ick, CK_AM33XX),
+ CLK("omap_hsmmc.0", "fck", &mmc0_fck, CK_AM33XX),
+ CLK("omap_hsmmc.1", "fck", &mmc1_fck, CK_AM33XX),
+ CLK("omap_hsmmc.2", "fck", &mmc2_fck, CK_AM33XX),
+ CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
+ CLK(NULL, "ocmcram_ick", &ocmcram_ick, CK_AM33XX),
+ CLK(NULL, "ocpwp_fck", &ocpwp_fck, CK_AM33XX),
+ CLK(NULL, "pka_fck", &pka_fck, CK_AM33XX),
+ CLK(NULL, "rng_fck", &rng_fck, CK_AM33XX),
+ CLK(NULL, "rtc_fck", &rtc_fck, CK_AM33XX),
+ CLK(NULL, "rtc_ick", &rtc_ick, CK_AM33XX),
+ CLK(NULL, "sha0_fck", &sha0_fck, CK_AM33XX),
+ CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
+ CLK(NULL, "smartreflex0_ick", &smartreflex0_ick, CK_AM33XX),
+ CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
+ CLK(NULL, "smartreflex1_ick", &smartreflex1_ick, CK_AM33XX),
+ CLK("omap2_mcspi.1", "fck", &spi0_fck, CK_AM33XX),
+ CLK("omap2_mcspi.2", "fck", &spi1_fck, CK_AM33XX),
+ CLK("omap2_mcspi.1", "ick", &spi0_ick, CK_AM33XX),
+ CLK("omap2_mcspi.2", "ick", &spi1_ick, CK_AM33XX),
+ CLK(NULL, "spinlock_fck", &spinlock_fck, CK_AM33XX),
+ CLK(NULL, "gpt0_fck", &timer0_fck, CK_AM33XX),
+ CLK(NULL, "gpt1_fck", &timer1_fck, CK_AM33XX),
+ CLK(NULL, "gpt2_fck", &timer2_fck, CK_AM33XX),
+ CLK(NULL, "gpt3_fck", &timer3_fck, CK_AM33XX),
+ CLK(NULL, "gpt4_fck", &timer4_fck, CK_AM33XX),
+ CLK(NULL, "gpt5_fck", &timer5_fck, CK_AM33XX),
+ CLK(NULL, "gpt6_fck", &timer6_fck, CK_AM33XX),
+ CLK(NULL, "gpt7_fck", &timer7_fck, CK_AM33XX),
+ CLK("da8xx_lcdc.0", "lcdc_ick", &lcdc_ick, CK_AM33XX),
+ CLK(NULL, "tpcc_ick", &tpcc_ick, CK_AM33XX),
+ CLK(NULL, "tptc0_ick", &tptc0_ick, CK_AM33XX),
+ CLK(NULL, "tptc1_ick", &tptc1_ick, CK_AM33XX),
+ CLK(NULL, "tptc2_ick", &tptc2_ick, CK_AM33XX),
+ CLK(NULL, "uart1_fck", &uart1_fck, CK_AM33XX),
+ CLK(NULL, "uart2_fck", &uart2_fck, CK_AM33XX),
+ CLK(NULL, "uart3_fck", &uart3_fck, CK_AM33XX),
+ CLK(NULL, "uart4_fck", &uart4_fck, CK_AM33XX),
+ CLK(NULL, "uart5_fck", &uart5_fck, CK_AM33XX),
+ CLK(NULL, "uart6_fck", &uart6_fck, CK_AM33XX),
+ CLK(NULL, "uart1_ick", &uart1_ick, CK_AM33XX),
+ CLK(NULL, "uart2_ick", &uart2_ick, CK_AM33XX),
+ CLK(NULL, "uart3_ick", &uart3_ick, CK_AM33XX),
+ CLK(NULL, "uart4_ick", &uart4_ick, CK_AM33XX),
+ CLK(NULL, "uart5_ick", &uart5_ick, CK_AM33XX),
+ CLK(NULL, "uart6_ick", &uart6_ick, CK_AM33XX),
+ CLK(NULL, "usbotg_ick", &usbotg_ick, CK_AM33XX),
+ CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
+ CLK(NULL, "wdt0_ick", &wdt0_ick, CK_AM33XX),
+ CLK(NULL, "wdt0_fck", &wdt0_fck, CK_AM33XX),
+ CLK(NULL, "wdt1_ick", &wdt1_ick, CK_AM33XX),
+ CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
+ CLK(NULL, "wkup_m3_fck", &wkup_m3_fck, CK_AM33XX),
+ CLK(NULL, "l3_aon_gclk", &l3_aon_gclk, CK_AM33XX),
+ CLK(NULL, "l4_wkup_aon_gclk", &l4_wkup_aon_gclk, CK_AM33XX),
+ CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX),
+ CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX),
+ CLK(NULL, "gfx_l3_gclk", &gfx_l3_gclk, CK_AM33XX),
+ CLK(NULL, "l4_wkup_gclk", &l4_wkup_gclk, CK_AM33XX),
+ CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX),
+ CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX),
+ CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX),
+ CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX),
+ CLK(NULL, "debug_clka_gclk", &debug_clka_gclk, CK_AM33XX),
+ CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX),
+ CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX),
+ CLK(NULL, "cpsw_250mhz_clk", &cpsw_250mhz_clk, CK_AM33XX),
+ CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX),
+ CLK(NULL, "cpsw_50mhz_clk", &cpsw_50mhz_clk, CK_AM33XX),
+ CLK(NULL, "cpsw_5mhz_clk", &cpsw_5mhz_clk, CK_AM33XX),
+ CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX),
+ CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX),
+ CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX),
+ CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX),
+ CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX),
+ CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX),
+ CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX),
+ CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX),
+ CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX),
+ CLK(NULL, "gfx_fclk", &gfx_fclk, CK_AM33XX),
+ CLK(NULL, "gfx_ick", &gfx_ick, CK_AM33XX),
+ CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
+ CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX),
+ CLK(NULL, "gpt0_ick", &timer0_ick, CK_AM33XX),
+ CLK(NULL, "gpt1_ick", &timer1_ick, CK_AM33XX),
+ CLK(NULL, "gpt2_ick", &timer2_ick, CK_AM33XX),
+ CLK(NULL, "gpt3_ick", &timer3_ick, CK_AM33XX),
+ CLK(NULL, "gpt4_ick", &timer4_ick, CK_AM33XX),
+ CLK(NULL, "gpt5_ick", &timer5_ick, CK_AM33XX),
+ CLK(NULL, "gpt6_ick", &timer6_ick, CK_AM33XX),
+ CLK(NULL, "gpt7_ick", &timer7_ick, CK_AM33XX),
+ CLK(NULL, "vtp_clk", &vtp_clk, CK_AM33XX),
+ CLK(NULL, "ehrpwm0_tbclk", &ehrpwm0_tbclk, CK_AM33XX),
+ CLK(NULL, "ehrpwm1_tbclk", &ehrpwm1_tbclk, CK_AM33XX),
+ CLK(NULL, "ehrpwm2_tbclk", &ehrpwm2_tbclk, CK_AM33XX),
+};
+
+int __init am33xx_clk_init(void)
+{
+ struct omap_clk *c;
+ u32 cpu_clkflg;
+
+ if (cpu_is_am33xx()) {
+ cpu_mask = RATE_IN_AM33XX;
+ cpu_clkflg = CK_AM33XX;
+ }
+
+ clk_init(&omap2_clk_functions);
+
+ for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
+ clk_preinit(c->lk.clk);
+
+ for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
+ if (c->cpu & cpu_clkflg) {
+ clkdev_add(&c->lk);
+ clk_register(c->lk.clk);
+ omap2_init_clk_clkdm(c->lk.clk);
+ }
+
+ recalculate_root_clocks();
+
+ /*
+ * Only enable those clocks we will need, let the drivers
+ * enable other clocks as necessary
+ */
+ clk_enable_init_clocks();
+
+ return 0;
+}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/clock33xx.h kernel_3.2.14_patched/arch/arm/mach-omap2/clock33xx.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/clock33xx.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/clock33xx.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,37 @@
+/*
+ * AM33XX clock function prototypes and macros.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK33XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK33XX_H
+
+#define AM33XX_MAX_DPLL_MULT 2047
+#define AM33XX_MAX_DPLL_DIV 128
+
+
+int am33xx_clk_init(void);
+
+/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
+ physically present, in such a case HWMOD enabling of
+ clock would be failure with default parent. And timer
+ probe thinks clock is already enabled, this leads to
+ crash upon accessing timer 3 & 6 registers in probe.
+ Fix by setting parent of both these timers to master
+ oscillator clock.
+ */
+static inline void am33xx_init_timer_parent(struct clk *clk)
+{
+ omap2_clksel_set_parent(clk, clk->parent);
+}
+#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/clock3xxx_data.c kernel_3.2.14_patched/arch/arm/mach-omap2/clock3xxx_data.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/clock3xxx_data.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/clock3xxx_data.c 2012-05-16 12:10:47.000000000 +0100
@@ -27,6 +27,7 @@
#include "clock34xx.h"
#include "clock36xx.h"
#include "clock3517.h"
+#include "clock33xx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
@@ -2480,6 +2481,16 @@
.recalc = &followparent_recalc,
};
+static struct clk uart4_fck_am35xx = {
+ .name = "uart4_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &per_48m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_UART4_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+ .recalc = &followparent_recalc,
+};
+
static struct clk gpt2_fck = {
.name = "gpt2_fck",
.ops = &clkops_omap2_dflt_wait,
@@ -3287,7 +3298,7 @@
CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- CLK("usbhs-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
@@ -3323,7 +3334,7 @@
CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- CLK("usbhs-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
@@ -3369,20 +3380,18 @@
CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- CLK("usbhs-omap.0", "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- CLK("usbhs-omap.0", "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- CLK("usbhs-omap.0", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- CLK("usbhs-omap.0", "utmi_p1_gfclk", &dummy_ck, CK_3XXX),
- CLK("usbhs-omap.0", "utmi_p2_gfclk", &dummy_ck, CK_3XXX),
- CLK("usbhs-omap.0", "xclk60mhsp1_ck", &dummy_ck, CK_3XXX),
- CLK("usbhs-omap.0", "xclk60mhsp2_ck", &dummy_ck, CK_3XXX),
- CLK("usbhs-omap.0", "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX),
- CLK("usbhs-omap.0", "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
- CLK("usbhs-omap.0", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
- CLK("usbhs-omap.0", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
- CLK("usbhs-omap.0", "init_60m_fclk", &dummy_ck, CK_3XXX),
+ CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK("usbhs_omap", "utmi_p1_gfclk", &dummy_ck, CK_3XXX),
+ CLK("usbhs_omap", "utmi_p2_gfclk", &dummy_ck, CK_3XXX),
+ CLK("usbhs_omap", "xclk60mhsp1_ck", &dummy_ck, CK_3XXX),
+ CLK("usbhs_omap", "xclk60mhsp2_ck", &dummy_ck, CK_3XXX),
+ CLK("usbhs_omap", "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX),
+ CLK("usbhs_omap", "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
+ CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
+ CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
+ CLK("usbhs_omap", "init_60m_fclk", &dummy_ck, CK_3XXX),
CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
@@ -3403,6 +3412,7 @@
CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
+ CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_3505 | CK_3517),
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
@@ -3517,6 +3527,11 @@
} else if (cpu_is_ti816x()) {
cpu_mask = RATE_IN_TI816X;
cpu_clkflg = CK_TI816X;
+ } else if (cpu_is_am33xx()) {
+ am33xx_clk_init();
+ return 0;
+ } else if (cpu_is_ti814x()) {
+ cpu_mask = RATE_IN_TI814X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
@@ -3600,7 +3615,7 @@
* Lock DPLL5 -- here only until other device init code can
* handle this
*/
- if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+ if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
omap3_clk_lock_dpll5();
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/clock44xx_data.c kernel_3.2.14_patched/arch/arm/mach-omap2/clock44xx_data.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/clock44xx_data.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/clock44xx_data.c 2012-05-16 12:10:47.000000000 +0100
@@ -1206,6 +1206,14 @@
{ .parent = NULL },
};
+static struct clk mpu_periphclk = {
+ .name = "mpu_periphclk",
+ .parent = &dpll_mpu_ck,
+ .ops = &clkops_null,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
static struct clk ocp_abe_iclk = {
.name = "ocp_abe_iclk",
.parent = &aess_fclk,
@@ -3189,6 +3197,7 @@
CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
+ CLK("smp_twd", NULL, &mpu_periphclk, CK_443X),
CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
@@ -3295,7 +3304,7 @@
CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
- CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
+ CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
@@ -3306,7 +3315,7 @@
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
- CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
+ CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
@@ -3314,7 +3323,7 @@
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
- CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
+ CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
CLK(NULL, "usim_fck", &usim_fck, CK_443X),
@@ -3374,8 +3383,8 @@
CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
- CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
- CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
+ CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
+ CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X),
CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X),
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/clock.c kernel_3.2.14_patched/arch/arm/mach-omap2/clock.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/clock.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/clock.c 2012-05-16 12:10:47.000000000 +0100
@@ -35,7 +35,7 @@
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
-u8 cpu_mask;
+u16 cpu_mask;
/*
* clkdm_control: if true, then when a clock is enabled in the
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c kernel_3.2.14_patched/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c 2012-05-16 12:10:47.000000000 +0100
@@ -147,6 +147,9 @@
if (cpu_is_omap24xx())
omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
+ else if (cpu_is_am33xx())
+ am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs,
+ clkdm->clktrctrl_mask);
else if (cpu_is_omap34xx())
omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
@@ -157,6 +160,9 @@
if (cpu_is_omap24xx())
omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
+ else if (cpu_is_am33xx())
+ am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs,
+ clkdm->clktrctrl_mask);
else if (cpu_is_omap34xx())
omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
@@ -211,14 +217,22 @@
static int omap3_clkdm_sleep(struct clockdomain *clkdm)
{
- omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+ if (cpu_is_am33xx())
+ am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs,
+ clkdm->clktrctrl_mask);
+ else
+ omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
return 0;
}
static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
{
- omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
+ if (cpu_is_am33xx())
+ am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs,
+ clkdm->clktrctrl_mask);
+ else
+ omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
return 0;
}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/clockdomain44xx.c kernel_3.2.14_patched/arch/arm/mach-omap2/clockdomain44xx.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/clockdomain44xx.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/clockdomain44xx.c 2012-05-16 12:10:47.000000000 +0100
@@ -128,3 +128,10 @@
.clkdm_clk_enable = omap4_clkdm_clk_enable,
.clkdm_clk_disable = omap4_clkdm_clk_disable,
};
+
+struct clkdm_ops am33xx_clkdm_operations = {
+ .clkdm_sleep = omap4_clkdm_sleep,
+ .clkdm_wakeup = omap4_clkdm_wakeup,
+ .clkdm_clk_enable = omap4_clkdm_clk_enable,
+ .clkdm_clk_disable = omap4_clkdm_clk_disable,
+};
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/clockdomain.h kernel_3.2.14_patched/arch/arm/mach-omap2/clockdomain.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/clockdomain.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/clockdomain.h 2012-05-16 12:10:47.000000000 +0100
@@ -195,6 +195,7 @@
extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
+extern void __init am33xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
@@ -202,6 +203,7 @@
extern struct clkdm_ops omap2_clkdm_operations;
extern struct clkdm_ops omap3_clkdm_operations;
extern struct clkdm_ops omap4_clkdm_operations;
+extern struct clkdm_ops am33xx_clkdm_operations;
extern struct clkdm_dep gfx_24xx_wkdeps[];
extern struct clkdm_dep dsp_24xx_wkdeps[];
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/clockdomains33xx_data.c kernel_3.2.14_patched/arch/arm/mach-omap2/clockdomains33xx_data.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/clockdomains33xx_data.c 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/clockdomains33xx_data.c 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,232 @@
+/*
+ * AM33XX Clock Domain data.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "prcm44xx.h"
+#include "clockdomain.h"
+#include "cm.h"
+#include "cm33xx.h"
+#include "cm-regbits-33xx.h"
+
+static struct clockdomain l4ls_am33xx_clkdm = {
+ .name = "l4ls_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .cm_inst = AM33XX_CM_PER_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain l3s_am33xx_clkdm = {
+ .name = "l3s_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .cm_inst = AM33XX_CM_PER_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain l4fw_am33xx_clkdm = {
+ .name = "l4fw_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .cm_inst = AM33XX_CM_PER_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain l3_am33xx_clkdm = {
+ .name = "l3_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .cm_inst = AM33XX_CM_PER_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain l4hs_am33xx_clkdm = {
+ .name = "l4hs_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .cm_inst = AM33XX_CM_PER_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain ocpwp_l3_am33xx_clkdm = {
+ .name = "ocpwp_l3_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .cm_inst = AM33XX_CM_PER_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain pruss_ocp_am33xx_clkdm = {
+ .name = "pruss_ocp_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .cm_inst = AM33XX_CM_PER_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
+ .name = "cpsw_125mhz_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .cm_inst = AM33XX_CM_PER_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain lcdc_am33xx_clkdm = {
+ .name = "lcdc_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .cm_inst = AM33XX_CM_PER_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain clk_24mhz_am33xx_clkdm = {
+ .name = "clk_24mhz_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .cm_inst = AM33XX_CM_PER_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain l4_wkup_am33xx_clkdm = {
+ .name = "l4_wkup_clkdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
+ .cm_inst = AM33XX_CM_WKUP_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain l3_aon_am33xx_clkdm = {
+ .name = "l3_aon_clkdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
+ .cm_inst = AM33XX_CM_WKUP_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
+ .name = "l4_wkup_aon_clkdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
+ .cm_inst = AM33XX_CM_WKUP_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain mpu_am33xx_clkdm = {
+ .name = "mpu_clkdm",
+ .pwrdm = { .name = "mpu_pwrdm" },
+ .cm_inst = AM33XX_CM_MPU_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain l4_rtc_am33xx_clkdm = {
+ .name = "l4_rtc_clkdm",
+ .pwrdm = { .name = "rtc_pwrdm" },
+ .cm_inst = AM33XX_CM_RTC_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain gfx_l3_am33xx_clkdm = {
+ .name = "gfx_l3_clkdm",
+ .pwrdm = { .name = "gfx_pwrdm" },
+ .cm_inst = AM33XX_CM_GFX_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
+ .name = "gfx_l4ls_gfx_clkdm",
+ .pwrdm = { .name = "gfx_pwrdm" },
+ .cm_inst = AM33XX_CM_GFX_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain l4_cefuse_am33xx_clkdm = {
+ .name = "l4_cefuse_clkdm",
+ .pwrdm = { .name = "cefuse_pwrdm" },
+ .cm_inst = AM33XX_CM_CEFUSE_MOD,
+ .prcm_partition = AM33XX_PRM_PARTITION,
+ .clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
+ .clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
+};
+
+static struct clockdomain *clockdomains_am33xx[] __initdata = {
+ &l4ls_am33xx_clkdm,
+ &l3s_am33xx_clkdm,
+ &l4fw_am33xx_clkdm,
+ &l3_am33xx_clkdm,
+ &l4hs_am33xx_clkdm,
+ &ocpwp_l3_am33xx_clkdm,
+ &pruss_ocp_am33xx_clkdm,
+ &cpsw_125mhz_am33xx_clkdm,
+ &lcdc_am33xx_clkdm,
+ &clk_24mhz_am33xx_clkdm,
+ &l4_wkup_am33xx_clkdm,
+ &l3_aon_am33xx_clkdm,
+ &l4_wkup_aon_am33xx_clkdm,
+ &mpu_am33xx_clkdm,
+ &l4_rtc_am33xx_clkdm,
+ &gfx_l3_am33xx_clkdm,
+ &gfx_l4ls_gfx_am33xx_clkdm,
+ &l4_cefuse_am33xx_clkdm,
+ NULL,
+};
+
+void __init am33xx_clockdomains_init(void)
+{
+ clkdm_register_platform_funcs(&am33xx_clkdm_operations);
+ clkdm_register_clkdms(clockdomains_am33xx);
+ clkdm_complete_init();
+}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/clock.h kernel_3.2.14_patched/arch/arm/mach-omap2/clock.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/clock.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/clock.h 2012-05-16 12:10:47.000000000 +0100
@@ -37,9 +37,6 @@
/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
-#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
-#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
-#define OMAP4XXX_EN_DPLL_LOCKED 0x7
/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
#define DPLL_LOW_POWER_STOP 0x1
@@ -132,7 +129,7 @@
const char *core_ck_name,
const char *mpu_ck_name);
-extern u8 cpu_mask;
+extern u16 cpu_mask;
extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_dummy;
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/cm2xxx_3xxx.c kernel_3.2.14_patched/arch/arm/mach-omap2/cm2xxx_3xxx.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/cm2xxx_3xxx.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/cm2xxx_3xxx.c 2012-05-16 12:10:47.000000000 +0100
@@ -18,7 +18,7 @@
#include <linux/err.h>
#include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
@@ -84,6 +84,16 @@
omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
}
+static void _am33xx_write_clktrctrl(u8 c, s16 module, u16 idx, u32 mask)
+{
+ u32 v;
+
+ v = omap2_cm_read_mod_reg(module, idx);
+ v &= ~mask;
+ v |= c << __ffs(mask);
+ omap2_cm_write_mod_reg(v, module, idx);
+}
+
bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
{
u32 v;
@@ -195,6 +205,30 @@
OMAP24XX_AUTO_96M_MASK);
}
+void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 clkdm, u32 mask)
+{
+ _am33xx_write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst,
+ clkdm, mask);
+}
+
+void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 clkdm, u32 mask)
+{
+ _am33xx_write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst,
+ clkdm, mask);
+}
+
+void am33xx_cm_clkdm_force_sleep(s16 inst, u16 clkdm, u32 mask)
+{
+ _am33xx_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst,
+ clkdm, mask);
+}
+
+void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 clkdm, u32 mask)
+{
+ _am33xx_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst,
+ clkdm, mask);
+}
+
/*
*
*/
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/cm2xxx_3xxx.h kernel_3.2.14_patched/arch/arm/mach-omap2/cm2xxx_3xxx.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/cm2xxx_3xxx.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/cm2xxx_3xxx.h 2012-05-16 12:10:47.000000000 +0100
@@ -122,6 +122,12 @@
extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
+extern int am33xx_cm_wait_module_ready(u16 inst, u16 clkctrl_reg);
+extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 clkdm, u32 mask);
+extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 clkdm, u32 mask);
+extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 clkdm, u32 mask);
+extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 clkdm, u32 mask);
+
extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/cm33xx.h kernel_3.2.14_patched/arch/arm/mach-omap2/cm33xx.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/cm33xx.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/cm33xx.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,377 @@
+/*
+ * AM33XX CM instance offset macros
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
+
+#include "common.h"
+
+#include "cm.h"
+#include "cm-regbits-33xx.h"
+#include "cm33xx.h"
+
+/* CM base address */
+#define AM33XX_CM_BASE 0x44e00000
+
+#define AM33XX_CM_REGADDR(inst, reg) \
+ AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
+
+/* CM instances */
+#define AM33XX_CM_PER_MOD 0x0000
+#define AM33XX_CM_WKUP_MOD 0x0400
+#define AM33XX_CM_DPLL_MOD 0x0500
+#define AM33XX_CM_MPU_MOD 0x0600
+#define AM33XX_CM_DEVICE_MOD 0x0700
+#define AM33XX_CM_RTC_MOD 0x0800
+#define AM33XX_CM_GFX_MOD 0x0900
+#define AM33XX_CM_CEFUSE_MOD 0x0A00
+
+/* CM */
+
+/* CM.PER_CM register offsets */
+#define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
+#define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
+#define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004
+#define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
+#define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008
+#define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
+#define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c
+#define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
+#define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014
+#define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
+#define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018
+#define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
+#define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c
+#define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
+#define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020
+#define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
+#define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024
+#define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
+#define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028
+#define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
+#define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c
+#define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
+#define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030
+#define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
+#define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034
+#define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
+#define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038
+#define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
+#define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c
+#define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
+#define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040
+#define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
+#define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044
+#define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
+#define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048
+#define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
+#define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c
+#define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
+#define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050
+#define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
+#define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054
+#define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
+#define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058
+#define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
+#define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060
+#define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
+#define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064
+#define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
+#define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068
+#define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
+#define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c
+#define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
+#define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070
+#define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
+#define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074
+#define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
+#define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078
+#define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
+#define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c
+#define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
+#define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080
+#define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
+#define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084
+#define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
+#define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088
+#define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
+#define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c
+#define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
+#define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090
+#define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
+#define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094
+#define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
+#define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098
+#define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
+#define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c
+#define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
+#define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0
+#define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
+#define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4
+#define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
+#define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8
+#define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
+#define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac
+#define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
+#define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0
+#define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
+#define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4
+#define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
+#define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8
+#define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
+#define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc
+#define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
+#define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0
+#define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
+#define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4
+#define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
+#define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc
+#define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
+#define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0
+#define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
+#define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4
+#define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
+#define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8
+#define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
+#define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc
+#define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
+#define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0
+#define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
+#define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4
+#define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
+#define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8
+#define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
+#define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec
+#define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
+#define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0
+#define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
+#define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4
+#define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
+#define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8
+#define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
+#define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc
+#define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
+#define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100
+#define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
+#define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104
+#define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
+#define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c
+#define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
+#define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110
+#define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
+#define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c
+#define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
+#define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120
+#define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
+#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124
+#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
+#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128
+#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
+#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c
+#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
+#define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130
+#define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
+#define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134
+#define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
+#define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140
+#define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
+#define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144
+#define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
+#define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148
+#define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
+#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c
+#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
+#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150
+#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
+
+/* CM.WKUP_CM register offsets */
+#define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000
+#define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
+#define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004
+#define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
+#define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008
+#define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
+#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c
+#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
+#define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010
+#define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
+#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014
+#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
+#define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018
+#define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
+#define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c
+#define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
+#define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020
+#define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
+#define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c
+#define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
+#define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030
+#define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
+#define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034
+#define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
+#define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040
+#define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
+#define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044
+#define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
+#define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048
+#define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
+#define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054
+#define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
+#define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058
+#define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
+#define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c
+#define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
+#define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068
+#define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
+#define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c
+#define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
+#define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070
+#define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
+#define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c
+#define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
+#define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080
+#define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
+#define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084
+#define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
+#define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088
+#define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
+#define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c
+#define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
+#define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090
+#define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
+#define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094
+#define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
+#define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098
+#define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
+#define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c
+#define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
+#define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0
+#define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
+#define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4
+#define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
+#define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8
+#define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
+#define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac
+#define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
+#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0
+#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
+#define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4
+#define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
+#define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8
+#define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
+#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc
+#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
+#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0
+#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
+#define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4
+#define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
+#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8
+#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
+#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc
+#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
+#define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0
+#define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
+#define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4
+#define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
+#define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8
+#define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
+
+/* CM.DPLL_CM register offsets */
+#define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004
+#define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
+#define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008
+#define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
+#define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c
+#define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
+#define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010
+#define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
+#define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014
+#define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
+#define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018
+#define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
+#define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c
+#define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
+#define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020
+#define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
+#define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028
+#define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
+#define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c
+#define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
+#define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030
+#define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
+#define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034
+#define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
+#define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038
+#define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
+#define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c
+#define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
+
+/* CM.MPU_CM register offsets */
+#define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
+#define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
+#define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004
+#define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
+
+/* CM.DEVICE_CM register offsets */
+#define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000
+#define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
+
+/* CM.RTC_CM register offsets */
+#define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000
+#define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
+#define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004
+#define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
+
+/* CM.GFX_CM register offsets */
+#define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000
+#define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
+#define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004
+#define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
+#define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008
+#define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
+#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c
+#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
+#define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010
+#define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
+#define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014
+#define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
+
+/* CM.CEFUSE_CM register offsets */
+#define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
+#define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
+#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
+#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
+
+#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/cm44xx.c kernel_3.2.14_patched/arch/arm/mach-omap2/cm44xx.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/cm44xx.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/cm44xx.c 2012-05-16 12:10:47.000000000 +0100
@@ -18,7 +18,7 @@
#include <linux/err.h>
#include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
#include "cm.h"
#include "cm1_44xx.h"
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/cminst33xx.h kernel_3.2.14_patched/arch/arm/mach-omap2/cminst33xx.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/cminst33xx.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/cminst33xx.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,63 @@
+/*
+ * am33xx Clock Management (CM) function prototypes
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ASM_MACH_OMAP2_CMINST33XX_H
+#define __ARCH_ASM_MACH_OMAP2_CMINST33XX_H
+
+extern bool am33xx_cminst_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
+extern void am33xx_cminst_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
+extern void am33xx_cminst_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
+extern void am33xx_cminst_clkdm_force_sleep(s16 inst, u16 cdoffs);
+extern void am33xx_cminst_clkdm_force_wakeup(s16 inst, u16 cdoffs);
+
+extern int am33xx_cminst_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs);
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+extern int am33xx_cminst_wait_module_idle(u16 inst, s16 cdoffs,
+ u16 clkctrl_offs);
+
+extern void am33xx_cminst_module_enable(u8 mode, u16 inst, s16 cdoffs,
+ u16 clkctrl_offs);
+extern void am33xx_cminst_module_disable(u16 inst, s16 cdoffs,
+ u16 clkctrl_offs);
+
+#else
+
+static inline int am33xx_cminst_wait_module_idle(u16 inst, s16 cdoffs,
+ u16 clkctrl_offs)
+{
+ return 0;
+}
+
+static inline void am33xx_cminst_module_enable(u8 mode, u16 inst,
+ s16 cdoffs, u16 clkctrl_offs)
+{
+}
+
+static inline void am33xx_cminst_module_disable(u16 inst, s16 cdoffs,
+ u16 clkctrl_offs)
+{
+}
+
+#endif
+
+/*
+ * In an ideal world, we would not export these low-level functions,
+ * but this will probably take some time to fix properly
+ */
+extern u32 am33xx_cminst_read_inst_reg(s16 inst, u16 idx);
+extern void am33xx_cminst_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 am33xx_cminst_rmw_inst_reg_bits(u32 mask, u32 bits,
+ s16 inst, s16 idx);
+extern u32 am33xx_cminst_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+extern u32 am33xx_cminst_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+extern u32 am33xx_cminst_read_inst_reg_bits(u16 inst, s16 idx, u32 mask);
+
+#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/cminst44xx.c kernel_3.2.14_patched/arch/arm/mach-omap2/cminst44xx.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/cminst44xx.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/cminst44xx.c 2012-05-16 12:10:47.000000000 +0100
@@ -20,7 +20,7 @@
#include <linux/err.h>
#include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
#include "cm.h"
#include "cm1_44xx.h"
@@ -31,6 +31,7 @@
#include "cm-regbits-44xx.h"
#include "prcm44xx.h"
#include "prm44xx.h"
+#include "prm33xx.h"
#include "prcm_mpu44xx.h"
/*
@@ -49,13 +50,21 @@
#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
#define CLKCTRL_IDLEST_DISABLED 0x3
-static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
+static u32 **_cm_bases;
+static u32 max_cm_partitions;
+
+static u32 *omap44xx_cm_bases[] = {
[OMAP4430_INVALID_PRCM_PARTITION] = 0,
- [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE,
- [OMAP4430_CM1_PARTITION] = OMAP4430_CM1_BASE,
- [OMAP4430_CM2_PARTITION] = OMAP4430_CM2_BASE,
+ [OMAP4430_PRM_PARTITION] = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
+ [OMAP4430_CM1_PARTITION] = OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE),
+ [OMAP4430_CM2_PARTITION] = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
[OMAP4430_SCRM_PARTITION] = 0,
- [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE,
+ [OMAP4430_PRCM_MPU_PARTITION] = OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE),
+};
+
+static u32 *am33xx_cm_bases[] = {
+ [OMAP4430_INVALID_PRCM_PARTITION] = 0,
+ [AM33XX_PRM_PARTITION] = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE),
};
/* Private functions */
@@ -103,19 +112,19 @@
/* Read a register in a CM instance */
u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
{
- BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
+ BUG_ON(part >= max_cm_partitions ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_cm_bases[part]);
- return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+ return __raw_readl(_cm_bases[part] + ((inst + idx)/sizeof(u32)));
}
/* Write into a register in a CM instance */
void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
{
- BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
+ BUG_ON(part >= max_cm_partitions ||
part == OMAP4430_INVALID_PRCM_PARTITION ||
!_cm_bases[part]);
- __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+ __raw_writel(val, _cm_bases[part] + ((inst + idx)/sizeof(u32)));
}
/* Read-modify-write a register in CM1. Caller must lock */
@@ -349,3 +358,14 @@
v &= ~OMAP4430_MODULEMODE_MASK;
omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
}
+
+void __init omap44xx_cminst_init(void)
+{
+ if (cpu_is_omap44xx()) {
+ _cm_bases = omap44xx_cm_bases;
+ max_cm_partitions = ARRAY_SIZE(omap44xx_cm_bases);
+ } else if (cpu_is_am33xx()) {
+ _cm_bases = am33xx_cm_bases;
+ max_cm_partitions = ARRAY_SIZE(am33xx_cm_bases);
+ }
+}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/cminst44xx.h kernel_3.2.14_patched/arch/arm/mach-omap2/cminst44xx.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/cminst44xx.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/cminst44xx.h 2012-05-16 12:10:47.000000000 +0100
@@ -19,7 +19,7 @@
extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
-# ifdef CONFIG_ARCH_OMAP4
+# if defined (CONFIG_ARCH_OMAP4) || defined (CONFIG_SOC_OMAPAM33XX)
extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
u16 clkctrl_offs);
@@ -63,4 +63,5 @@
extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
u32 mask);
+extern void __init omap44xx_cminst_init(void);
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/cm-regbits-33xx.h kernel_3.2.14_patched/arch/arm/mach-omap2/cm-regbits-33xx.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/cm-regbits-33xx.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/cm-regbits-33xx.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,683 @@
+/*
+ * AM33XX Power Management register bits
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
+
+/*
+ * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
+ * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
+ */
+#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
+#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
+#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
+#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
+
+/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
+#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
+
+/* Used by CM_PER_CPSW_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
+#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
+
+/* Used by CM_PER_L4HS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
+#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
+
+/* Used by CM_PER_L4HS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
+#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
+
+/* Used by CM_PER_L4HS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
+#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
+#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
+
+/* Used by CM_CEFUSE_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
+#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
+
+/* Used by CM_L3_AON_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
+#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
+
+/* Used by CM_L3_AON_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
+#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
+#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
+
+/* Used by CM_GFX_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
+#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
+
+/* Used by CM_GFX_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
+#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
+#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
+#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
+#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
+#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
+#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
+#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
+#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
+#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
+#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
+
+/* Used by CM_PER_PRUSS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
+#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
+
+/* Used by CM_PER_PRUSS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
+#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
+
+/* Used by CM_PER_PRUSS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
+#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
+
+/* Used by CM_PER_L3S_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
+#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
+
+/* Used by CM_L3_AON_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
+#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
+#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
+
+/* Used by CM_PER_L4FW_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
+#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
+
+/* Used by CM_PER_L4HS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
+#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
+#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
+
+/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
+#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
+#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
+
+/* Used by CM_CEFUSE_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
+#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
+
+/* Used by CM_RTC_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
+#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
+
+/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
+#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
+#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
+#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
+
+/* Used by CM_PER_LCDC_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
+#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
+
+/* Used by CM_PER_LCDC_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
+#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
+#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
+#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
+
+/* Used by CM_MPU_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
+#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
+
+/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
+#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
+
+/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
+#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
+
+/* Used by CM_RTC_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
+#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
+#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
+#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
+#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
+#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
+#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
+#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
+#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
+#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
+#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
+#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
+#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
+#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
+#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
+#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
+
+/* Used by CLKSEL_GFX_FCLK */
+#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
+#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
+
+/* Used by CM_CLKOUT_CTRL */
+#define AM33XX_CLKOUT2DIV_SHIFT 3
+#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3)
+
+/* Used by CM_CLKOUT_CTRL */
+#define AM33XX_CLKOUT2EN_SHIFT 7
+#define AM33XX_CLKOUT2EN_MASK (1 << 7)
+
+/* Used by CM_CLKOUT_CTRL */
+#define AM33XX_CLKOUT2SOURCE_SHIFT 0
+#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0)
+
+/*
+ * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
+ * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
+ * CLKSEL_TIMER7_CLK
+ */
+#define AM33XX_CLKSEL_SHIFT 0
+#define AM33XX_CLKSEL_MASK (0x01 << 0)
+
+/*
+ * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
+ * CM_CPTS_RFT_CLKSEL
+ */
+#define AM33XX_CLKSEL_0_0_SHIFT 0
+#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
+
+#define AM33XX_CLKSEL_0_1_SHIFT 0
+#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
+
+/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
+#define AM33XX_CLKSEL_0_2_SHIFT 0
+#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
+
+/* Used by CLKSEL_GFX_FCLK */
+#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
+#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
+
+/*
+ * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
+ * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
+ * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
+ * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
+ * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
+ * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
+ */
+#define AM33XX_CLKTRCTRL_SHIFT 0
+#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
+
+/*
+ * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
+ * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
+ * CM_SSC_DELTAMSTEP_DPLL_PER
+ */
+#define AM33XX_DELTAMSTEP_SHIFT 0
+#define AM33XX_DELTAMSTEP_MASK (0x19 << 0)
+
+/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
+#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
+#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
+
+/* Used by CM_CLKDCOLDO_DPLL_PER */
+#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
+#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
+
+/* Used by CM_CLKDCOLDO_DPLL_PER */
+#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
+#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
+
+/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
+#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
+#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
+
+/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0)
+
+/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
+
+/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
+
+/*
+ * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER
+ */
+#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
+#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
+
+/*
+ * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
+ * CM_CLKSEL_DPLL_MPU
+ */
+#define AM33XX_DPLL_DIV_SHIFT 0
+#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
+
+#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
+
+/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
+#define AM33XX_DPLL_DIV_0_7_SHIFT 0
+#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU
+ */
+#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
+#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define AM33XX_DPLL_EN_SHIFT 0
+#define AM33XX_DPLL_EN_MASK (0x7 << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU
+ */
+#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
+#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
+
+/*
+ * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
+ * CM_CLKSEL_DPLL_MPU
+ */
+#define AM33XX_DPLL_MULT_SHIFT 8
+#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
+
+/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
+#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
+#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU
+ */
+#define AM33XX_DPLL_REGM4XEN_SHIFT 11
+#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
+
+/* Used by CM_CLKSEL_DPLL_PERIPH */
+#define AM33XX_DPLL_SD_DIV_SHIFT 24
+#define AM33XX_DPLL_SD_DIV_MASK (24, 31)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define AM33XX_DPLL_SSC_ACK_SHIFT 13
+#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
+#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define AM33XX_DPLL_SSC_EN_SHIFT 12
+#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
+#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
+#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
+#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
+#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
+#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
+#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
+#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
+#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
+#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
+#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
+#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
+
+/*
+ * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
+ * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
+ * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
+ * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
+ * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
+ * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
+ * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
+ * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
+ * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
+ * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
+ * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
+ * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
+ * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
+ * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
+ * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
+ * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
+ * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
+ * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
+ * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
+ * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
+ * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
+ * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
+ * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
+ * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
+ * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
+ * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
+ * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
+ * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
+ * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
+ */
+#define AM33XX_IDLEST_SHIFT 16
+#define AM33XX_IDLEST_MASK (0x3 << 16)
+#define AM33XX_IDLEST_VAL 0x3
+
+/* Used by CM_MAC_CLKSEL */
+#define AM33XX_MII_CLK_SEL_SHIFT 2
+#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
+ * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER
+ */
+#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
+#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
+ * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER
+ */
+#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
+#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0)
+
+/*
+ * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
+ * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
+ * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
+ * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
+ * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
+ * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
+ * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
+ * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
+ * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
+ * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
+ * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
+ * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
+ * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
+ * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
+ * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
+ * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
+ * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
+ * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
+ * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
+ * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
+ * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
+ * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
+ * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
+ * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
+ * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
+ * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
+ * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
+ * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
+ * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
+ * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
+ * CM_CEFUSE_CEFUSE_CLKCTRL
+ */
+#define AM33XX_MODULEMODE_SHIFT 0
+#define AM33XX_MODULEMODE_MASK (0x3 << 0)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
+#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
+#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
+
+/* Used by CM_WKUP_GPIO0_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
+#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
+
+/* Used by CM_PER_GPIO1_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
+#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
+
+/* Used by CM_PER_GPIO2_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
+#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
+
+/* Used by CM_PER_GPIO3_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
+#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
+
+/* Used by CM_PER_GPIO4_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
+#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
+
+/* Used by CM_PER_GPIO5_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
+#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
+
+/* Used by CM_PER_GPIO6_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
+#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
+
+/*
+ * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
+ * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
+ * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
+ * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
+ * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
+ * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
+ */
+#define AM33XX_STBYST_SHIFT 18
+#define AM33XX_STBYST_MASK (1 << 18)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
+#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
+#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22)
+
+/*
+ * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
+ */
+#define AM33XX_ST_DPLL_CLK_SHIFT 0
+#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
+
+/* Used by CM_CLKDCOLDO_DPLL_PER */
+#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
+#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
+
+/*
+ * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER
+ */
+#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
+#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
+#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
+#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
+#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
+
+/*
+ * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
+ */
+#define AM33XX_ST_MN_BYPASS_SHIFT 8
+#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
+#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
+#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20)
+#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/common-board-devices.c kernel_3.2.14_patched/arch/arm/mach-omap2/common-board-devices.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/common-board-devices.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/common-board-devices.c 2012-05-16 12:10:47.000000000 +0100
@@ -33,7 +33,6 @@
defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
static struct omap2_mcspi_device_config ads7846_mcspi_config = {
.turbo_mode = 0,
- .single_channel = 1, /* 0: slave, 1: master */
};
static struct ads7846_platform_data ads7846_config = {
@@ -92,49 +91,3 @@
{
}
#endif
-
-#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-static struct omap_nand_platform_data nand_data;
-
-void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
- int nr_parts)
-{
- u8 cs = 0;
- u8 nandcs = GPMC_CS_NUM + 1;
-
- /* find out the chip-select on which NAND exists */
- while (cs < GPMC_CS_NUM) {
- u32 ret = 0;
- ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
- if ((ret & 0xC00) == 0x800) {
- printk(KERN_INFO "Found NAND on CS%d\n", cs);
- if (nandcs > GPMC_CS_NUM)
- nandcs = cs;
- }
- cs++;
- }
-
- if (nandcs > GPMC_CS_NUM) {
- printk(KERN_INFO "NAND: Unable to find configuration "
- "in GPMC\n ");
- return;
- }
-
- if (nandcs < GPMC_CS_NUM) {
- nand_data.cs = nandcs;
- nand_data.parts = parts;
- nand_data.nr_parts = nr_parts;
- nand_data.devsize = options;
-
- printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
- if (gpmc_nand_init(&nand_data) < 0)
- printk(KERN_ERR "Unable to register NAND device\n");
- }
-}
-#else
-void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
- int nr_parts)
-{
-}
-#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/common-board-devices.h kernel_3.2.14_patched/arch/arm/mach-omap2/common-board-devices.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/common-board-devices.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/common-board-devices.h 2012-05-16 12:10:47.000000000 +0100
@@ -10,6 +10,5 @@
void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
struct ads7846_platform_data *board_pdata);
-void omap_nand_flash_init(int opts, struct mtd_partition *parts, int n_parts);
#endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/common.c kernel_3.2.14_patched/arch/arm/mach-omap2/common.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/common.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/common.c 2012-05-16 12:10:47.000000000 +0100
@@ -17,7 +17,7 @@
#include <linux/clk.h>
#include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/board.h>
#include <plat/mux.h>
@@ -110,23 +110,49 @@
/*
* Adjust TAP register base such that omap3_check_revision accesses the correct
- * TI816X register for checking device ID (it adds 0x204 to tap base while
- * TI816X DEVICE ID register is at offset 0x600 from control base).
+ * TI81XX register for checking device ID (it adds 0x204 to tap base while
+ * TI81XX DEVICE ID register is at offset 0x600 from control base).
*/
-#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \
- TI816X_CONTROL_DEVICE_ID - 0x204)
+#define TI81XX_TAP_BASE (TI81XX_CTRL_BASE + \
+ TI81XX_CONTROL_DEVICE_ID - 0x204)
-static struct omap_globals ti816x_globals = {
+static struct omap_globals ti81xx_globals = {
.class = OMAP343X_CLASS,
- .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
- .ctrl = OMAP2_L4_IO_ADDRESS(TI816X_CTRL_BASE),
- .prm = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
- .cm = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
+ .tap = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE),
+ .ctrl = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
+ .prm = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
+ .cm = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
};
-void __init omap2_set_globals_ti816x(void)
+void __init omap2_set_globals_ti81xx(void)
{
- __omap2_set_globals(&ti816x_globals);
+ __omap2_set_globals(&ti81xx_globals);
+}
+
+void __init ti81xx_map_io(void)
+{
+ omapti81xx_map_common_io();
+}
+
+#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + \
+ TI81XX_CONTROL_DEVICE_ID - 0x204)
+
+static struct omap_globals am33xx_globals = {
+ .class = AM335X_CLASS,
+ .tap = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
+ .ctrl = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+ .prm = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+ .cm = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+};
+
+void __init omap2_set_globals_am33xx(void)
+{
+ __omap2_set_globals(&am33xx_globals);
+}
+
+void __init am33xx_map_io(void)
+{
+ omapam33xx_map_common_io();
}
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/common.h kernel_3.2.14_patched/arch/arm/mach-omap2/common.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/common.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/common.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,240 @@
+/*
+ * Header for code common to all OMAP2+ machines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
+#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
+#ifndef __ASSEMBLER__
+
+#include <linux/delay.h>
+#include <plat/common.h>
+#include <asm/proc-fns.h>
+
+#ifdef CONFIG_SOC_OMAP2420
+extern void omap242x_map_common_io(void);
+#else
+static inline void omap242x_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_SOC_OMAP2430
+extern void omap243x_map_common_io(void);
+#else
+static inline void omap243x_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+extern void omap34xx_map_common_io(void);
+#else
+static inline void omap34xx_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_SOC_OMAPTI81XX
+extern void omapti81xx_map_common_io(void);
+#else
+static inline void omapti81xx_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+extern void omapam33xx_map_common_io(void);
+#else
+static inline void omapam33xx_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP4
+extern void omap44xx_map_common_io(void);
+#else
+static inline void omap44xx_map_common_io(void)
+{
+}
+#endif
+
+extern void omap2_init_common_infrastructure(void);
+
+extern struct sys_timer omap2_timer;
+extern struct sys_timer omap3_timer;
+extern struct sys_timer omap3_secure_timer;
+extern struct sys_timer omap3_am33xx_timer;
+extern struct sys_timer omap4_timer;
+
+void omap2420_init_early(void);
+void omap2430_init_early(void);
+void omap3430_init_early(void);
+void omap35xx_init_early(void);
+void omap3630_init_early(void);
+void omap3_init_early(void); /* Do not use this one */
+void am35xx_init_early(void);
+void ti81xx_init_early(void);
+void am33xx_init_early(void);
+void omap4430_init_early(void);
+
+/*
+ * IO bases for various OMAP processors
+ * Except the tap base, rest all the io bases
+ * listed are physical addresses.
+ */
+struct omap_globals {
+ u32 class; /* OMAP class to detect */
+ void __iomem *tap; /* Control module ID code */
+ void __iomem *sdrc; /* SDRAM Controller */
+ void __iomem *sms; /* SDRAM Memory Scheduler */
+ void __iomem *ctrl; /* System Control Module */
+ void __iomem *ctrl_pad; /* PAD Control Module */
+ void __iomem *prm; /* Power and Reset Management */
+ void __iomem *cm; /* Clock Management */
+ void __iomem *cm2;
+};
+
+void omap2_set_globals_242x(void);
+void omap2_set_globals_243x(void);
+void omap2_set_globals_3xxx(void);
+void omap2_set_globals_443x(void);
+void omap2_set_globals_ti81xx(void);
+void omap2_set_globals_am33xx(void);
+
+/* These get called from omap2_set_globals_xxxx(), do not call these */
+void omap2_set_globals_tap(struct omap_globals *);
+void omap2_set_globals_sdrc(struct omap_globals *);
+void omap2_set_globals_control(struct omap_globals *);
+void omap2_set_globals_prcm(struct omap_globals *);
+
+void omap242x_map_io(void);
+void omap243x_map_io(void);
+void omap3_map_io(void);
+void am33xx_map_io(void);
+void omap4_map_io(void);
+void ti81xx_map_io(void);
+
+/**
+ * omap_test_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed. To use, define some integer @index in the
+ * calling code. After running, if @index == @timeout, then the loop has
+ * timed out.
+ */
+#define omap_test_timeout(cond, timeout, index) \
+({ \
+ for (index = 0; index < timeout; index++) { \
+ if (cond) \
+ break; \
+ udelay(1); \
+ } \
+})
+
+extern struct device *omap2_get_mpuss_device(void);
+extern struct device *omap2_get_iva_device(void);
+extern struct device *omap2_get_l3_device(void);
+extern struct device *omap4_get_dsp_device(void);
+
+void omap2_init_irq(void);
+void omap3_init_irq(void);
+void ti81xx_init_irq(void);
+extern int omap_irq_pending(void);
+void omap_intc_save_context(void);
+void omap_intc_restore_context(void);
+void omap3_intc_suspend(void);
+void omap3_intc_prepare_idle(void);
+void omap3_intc_resume_idle(void);
+void omap2_intc_handle_irq(struct pt_regs *regs);
+void omap3_intc_handle_irq(struct pt_regs *regs);
+
+#ifdef CONFIG_CACHE_L2X0
+extern void __iomem *omap4_get_l2cache_base(void);
+#endif
+
+#ifdef CONFIG_SMP
+extern void __iomem *omap4_get_scu_base(void);
+#else
+static inline void __iomem *omap4_get_scu_base(void)
+{
+ return NULL;
+}
+#endif
+
+extern void __init gic_init_irq(void);
+extern void omap_smc1(u32 fn, u32 arg);
+extern void __iomem *omap4_get_sar_ram_base(void);
+extern void omap_do_wfi(void);
+
+#ifdef CONFIG_SMP
+/* Needed for secondary core boot */
+extern void omap_secondary_startup(void);
+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
+extern void omap_auxcoreboot_addr(u32 cpu_addr);
+extern u32 omap_read_auxcoreboot0(void);
+#endif
+
+#if defined(CONFIG_SMP) && defined(CONFIG_PM)
+extern int omap4_mpuss_init(void);
+extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
+extern int omap4_finish_suspend(unsigned long cpu_state);
+extern void omap4_cpu_resume(void);
+extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
+extern u32 omap4_mpuss_read_prev_context_state(void);
+#else
+static inline int omap4_enter_lowpower(unsigned int cpu,
+ unsigned int power_state)
+{
+ cpu_do_idle();
+ return 0;
+}
+
+static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
+{
+ cpu_do_idle();
+ return 0;
+}
+
+static inline int omap4_mpuss_init(void)
+{
+ return 0;
+}
+
+static inline int omap4_finish_suspend(unsigned long cpu_state)
+{
+ return 0;
+}
+
+static inline void omap4_cpu_resume(void)
+{}
+
+static inline u32 omap4_mpuss_read_prev_context_state(void)
+{
+ return 0;
+}
+#endif
+#endif /* __ASSEMBLER__ */
+#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/control.c kernel_3.2.14_patched/arch/arm/mach-omap2/control.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/control.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/control.c 2012-05-16 12:10:47.000000000 +0100
@@ -13,9 +13,10 @@
#undef DEBUG
#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/sdrc.h>
#include "cm-regbits-34xx.h"
@@ -190,6 +191,7 @@
{
__raw_writel(val, OMAP_CTRL_REGADDR(offset));
}
+EXPORT_SYMBOL_GPL(omap_ctrl_writel);
/*
* On OMAP4 control pad are not addressable from control
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/control.h kernel_3.2.14_patched/arch/arm/mach-omap2/control.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/control.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/control.h 2012-05-16 12:10:47.000000000 +0100
@@ -29,6 +29,8 @@
OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
#define OMAP343X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define AM33XX_CTRL_REGADDR(reg) \
+ AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
#else
#define OMAP242X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -36,6 +38,8 @@
OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
#define OMAP343X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define AM33XX_CTRL_REGADDR(reg) \
+ AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
#endif /* __ASSEMBLY__ */
/*
@@ -52,8 +56,14 @@
#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
-/* TI816X spefic control submodules */
-#define TI816X_CONTROL_DEVCONF 0x600
+/* TI81XX spefic control submodules */
+#define TI81XX_CONTROL_DEVCONF 0x600
+
+/* TI81XX CONTROL_DEVCONF register offsets */
+#define TI81XX_CONTROL_MAC_ID0_LO (TI81XX_CONTROL_DEVCONF + 0x030)
+#define TI81XX_CONTROL_MAC_ID0_HI (TI81XX_CONTROL_DEVCONF + 0x034)
+#define TI81XX_CONTROL_MAC_ID1_LO (TI81XX_CONTROL_DEVCONF + 0x038)
+#define TI81XX_CONTROL_MAC_ID1_HI (TI81XX_CONTROL_DEVCONF + 0x03c)
/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
@@ -244,8 +254,8 @@
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
-/* TI816X CONTROL_DEVCONF register offsets */
-#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000)
+/* TI81XX CONTROL_DEVCONF register offsets */
+#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
/*
* REVISIT: This list of registers is not comprehensive - there are more
@@ -338,6 +348,35 @@
#define AM35XX_HECC_SW_RST BIT(3)
#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
+/* AM33XX CONTROL_STATUS bits */
+#define AM33XX_SYSBOOT0 (0xff << 0)
+#define AM33XX_DEVTYPE (1 << 8)
+#define AM33XX_GPMC_CS0_BW (1 << 16)
+#define AM33XX_GPMC_CS0_WAITEN (1 << 17)
+#define AM33XX_GPMC_CS0_ADMUX (0x3 << 18)
+#define AM33XX_SYSBOOT1 (0x3 << 22)
+
+/*
+ * CONTROL AM33XX STATUS register to identify boot-time configurations
+ */
+#define AM33XX_CONTROL_STATUS_OFF 0x040
+#define AM33XX_CONTROL_STATUS AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE + \
+ AM33XX_CONTROL_STATUS_OFF)
+#define AM33XX_DEV_FEATURE 0x604
+#define AM33XX_SGX_SHIFT 29
+#define AM33XX_SGX_MASK (1 << AM33XX_SGX_SHIFT)
+
+/*
+ * CONTROL AM33XX PWMSS_CTRL register to enable time base clock Enable
+ */
+
+#define AM33XX_CONTROL_PWMSS_CTRL_OFS 0x664
+#define AM33XX_PWMSS0_TBCLKEN 0x0
+#define AM33XX_PWMSS1_TBCLKEN 0x1
+#define AM33XX_PWMSS2_TBCLKEN 0x2
+#define AM33XX_CONTROL_PWMSS_CTRL AM33XX_L4_WK_IO_ADDRESS( \
+ AM33XX_CTRL_BASE + AM33XX_CONTROL_PWMSS_CTRL_OFS)
+
/*
* CONTROL OMAP STATUS register to identify OMAP3 features
*/
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/cpuidle33xx.c kernel_3.2.14_patched/arch/arm/mach-omap2/cpuidle33xx.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/cpuidle33xx.c 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/cpuidle33xx.c 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,179 @@
+/*
+ * CPU idle for AM33XX SoCs
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated. http://www.ti.com/
+ *
+ * Derived from Davinci CPU idle code
+ * (arch/arm/mach-davinci/cpuidle.c)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/cpuidle.h>
+#include <linux/sched.h>
+#include <asm/proc-fns.h>
+
+#include <plat/emif.h>
+
+#include "cpuidle33xx.h"
+
+#define AM33XX_CPUIDLE_MAX_STATES 2
+
+struct am33xx_ops {
+ void (*enter) (u32 flags);
+ void (*exit) (u32 flags);
+ u32 flags;
+};
+
+/* fields in am33xx_ops.flags */
+#define AM33XX_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
+
+static struct cpuidle_driver am33xx_idle_driver = {
+ .name = "cpuidle-am33xx",
+ .owner = THIS_MODULE,
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, am33xx_cpuidle_device);
+static void __iomem *emif_base;
+
+static void am33xx_save_ddr_power(int enter, bool pdown)
+{
+ u32 val;
+
+ val = __raw_readl(emif_base + EMIF4_0_SDRAM_MGMT_CTRL);
+
+ /* TODO: Choose the mode based on memory type */
+ if (enter)
+ val = SELF_REFRESH_ENABLE(64);
+ else
+ val = SELF_REFRESH_DISABLE;
+
+ __raw_writel(val, emif_base + EMIF4_0_SDRAM_MGMT_CTRL);
+}
+
+static void am33xx_c2state_enter(u32 flags)
+{
+ am33xx_save_ddr_power(1, !!(flags & AM33XX_CPUIDLE_FLAGS_DDR2_PWDN));
+}
+
+static void am33xx_c2state_exit(u32 flags)
+{
+ am33xx_save_ddr_power(0, !!(flags & AM33XX_CPUIDLE_FLAGS_DDR2_PWDN));
+}
+
+static struct am33xx_ops am33xx_states[AM33XX_CPUIDLE_MAX_STATES] = {
+ [1] = {
+ .enter = am33xx_c2state_enter,
+ .exit = am33xx_c2state_exit,
+ },
+};
+
+/* Actual code that puts the SoC in different idle states */
+static int am33xx_enter_idle(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
+{
+ struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
+ struct am33xx_ops *ops = cpuidle_get_statedata(state_usage);
+ struct timeval before, after;
+ int idle_time;
+
+ local_irq_disable();
+ do_gettimeofday(&before);
+
+ if (ops && ops->enter)
+ ops->enter(ops->flags);
+
+ /* Wait for interrupt state */
+ cpu_do_idle();
+ if (ops && ops->exit)
+ ops->exit(ops->flags);
+
+ do_gettimeofday(&after);
+ local_irq_enable();
+ idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+ (after.tv_usec - before.tv_usec);
+
+ dev->last_residency = idle_time;
+
+ return index;
+}
+
+static int __init am33xx_cpuidle_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct cpuidle_device *device;
+ struct cpuidle_driver *driver = &am33xx_idle_driver;
+ struct am33xx_cpuidle_config *pdata = pdev->dev.platform_data;
+
+ device = &per_cpu(am33xx_cpuidle_device, smp_processor_id());
+
+ if (!pdata) {
+ dev_err(&pdev->dev, "cannot get platform data\n");
+ return -ENOENT;
+ }
+
+ emif_base = pdata->emif_base;
+
+ /* Wait for interrupt state */
+ driver->states[0].enter = am33xx_enter_idle;
+ driver->states[0].exit_latency = 1;
+ driver->states[0].target_residency = 10000;
+ driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
+ strcpy(driver->states[0].name, "WFI");
+ strcpy(driver->states[0].desc, "Wait for interrupt");
+
+ /* Wait for interrupt and DDR self refresh state */
+ driver->states[1].enter = am33xx_enter_idle;
+ driver->states[1].exit_latency = 100;
+ driver->states[1].target_residency = 10000;
+ driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
+ strcpy(driver->states[1].name, "DDR SR");
+ strcpy(driver->states[1].desc, "WFI and DDR Self Refresh");
+ if (pdata->ddr2_pdown)
+ am33xx_states[1].flags |= AM33XX_CPUIDLE_FLAGS_DDR2_PWDN;
+ cpuidle_set_statedata(&device->states_usage[1], &am33xx_states[1]);
+
+ device->state_count = AM33XX_CPUIDLE_MAX_STATES;
+ driver->state_count = AM33XX_CPUIDLE_MAX_STATES;
+
+ ret = cpuidle_register_driver(&am33xx_idle_driver);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register driver\n");
+ return ret;
+ }
+
+ ret = cpuidle_register_device(device);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register device\n");
+ cpuidle_unregister_driver(&am33xx_idle_driver);
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct platform_driver am33xx_cpuidle_driver = {
+ .driver = {
+ .name = "cpuidle-am33xx",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init am33xx_cpuidle_init(void)
+{
+ return platform_driver_probe(&am33xx_cpuidle_driver,
+ am33xx_cpuidle_probe);
+}
+device_initcall(am33xx_cpuidle_init);
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/cpuidle33xx.h kernel_3.2.14_patched/arch/arm/mach-omap2/cpuidle33xx.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/cpuidle33xx.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/cpuidle33xx.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,24 @@
+/*
+ * TI AM33XX cpuidle platform support
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _AM33XX_CPUIDLE_H
+#define _AM33XX_CPUIDLE_H
+
+struct am33xx_cpuidle_config {
+ u32 ddr2_pdown;
+ void __iomem *emif_base;
+};
+
+#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/cpuidle34xx.c kernel_3.2.14_patched/arch/arm/mach-omap2/cpuidle34xx.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/cpuidle34xx.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/cpuidle34xx.c 2012-05-16 12:10:47.000000000 +0100
@@ -25,15 +25,16 @@
#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/export.h>
+#include <linux/cpu_pm.h>
#include <plat/prcm.h>
#include <plat/irqs.h>
#include "powerdomain.h"
#include "clockdomain.h"
-#include <plat/serial.h>
#include "pm.h"
#include "control.h"
+#include "common.h"
#ifdef CONFIG_CPU_IDLE
@@ -123,9 +124,23 @@
pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
}
+ /*
+ * Call idle CPU PM enter notifier chain so that
+ * VFP context is saved.
+ */
+ if (mpu_state == PWRDM_POWER_OFF)
+ cpu_pm_enter();
+
/* Execute ARM wfi */
omap_sram_idle();
+ /*
+ * Call idle CPU PM enter notifier chain to restore
+ * VFP context.
+ */
+ if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
+ cpu_pm_exit();
+
/* Re-allow idle for C1 */
if (index == 0) {
pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
@@ -244,11 +259,6 @@
struct omap3_idle_statedata *cx;
int ret;
- if (!omap3_can_sleep()) {
- new_state_idx = drv->safe_state_index;
- goto select_state;
- }
-
/*
* Prevent idle completely if CAM is active.
* CAM does not have wakeup capability in OMAP3.
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/cpuidle44xx.c kernel_3.2.14_patched/arch/arm/mach-omap2/cpuidle44xx.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/cpuidle44xx.c 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/cpuidle44xx.c 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,245 @@
+/*
+ * OMAP4 CPU idle Routines
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/sched.h>
+#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/export.h>
+#include <linux/clockchips.h>
+
+#include <asm/proc-fns.h>
+
+#include "common.h"
+#include "pm.h"
+#include "prm.h"
+
+#ifdef CONFIG_CPU_IDLE
+
+/* Machine specific information to be recorded in the C-state driver_data */
+struct omap4_idle_statedata {
+ u32 cpu_state;
+ u32 mpu_logic_state;
+ u32 mpu_state;
+ u8 valid;
+};
+
+static struct cpuidle_params cpuidle_params_table[] = {
+ /* C1 - CPU0 ON + CPU1 ON + MPU ON */
+ {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
+ /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
+ {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
+ /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+ {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
+};
+
+#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
+
+struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
+static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
+
+/**
+ * omap4_enter_idle - Programs OMAP4 to enter the specified state
+ * @dev: cpuidle device
+ * @drv: cpuidle driver
+ * @index: the index of state to be entered
+ *
+ * Called from the CPUidle framework to program the device to the
+ * specified low power state selected by the governor.
+ * Returns the amount of time spent in the low power state.
+ */
+static int omap4_enter_idle(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ struct omap4_idle_statedata *cx =
+ cpuidle_get_statedata(&dev->states_usage[index]);
+ struct timespec ts_preidle, ts_postidle, ts_idle;
+ u32 cpu1_state;
+ int idle_time;
+ int new_state_idx;
+ int cpu_id = smp_processor_id();
+
+ /* Used to keep track of the total time in idle */
+ getnstimeofday(&ts_preidle);
+
+ local_irq_disable();
+ local_fiq_disable();
+
+ /*
+ * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
+ * This is necessary to honour hardware recommondation
+ * of triggeing all the possible low power modes once CPU1 is
+ * out of coherency and in OFF mode.
+ * Update dev->last_state so that governor stats reflects right
+ * data.
+ */
+ cpu1_state = pwrdm_read_pwrst(cpu1_pd);
+ if (cpu1_state != PWRDM_POWER_OFF) {
+ new_state_idx = drv->safe_state_index;
+ cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]);
+ }
+
+ if (index > 0)
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
+
+ /*
+ * Call idle CPU PM enter notifier chain so that
+ * VFP and per CPU interrupt context is saved.
+ */
+ if (cx->cpu_state == PWRDM_POWER_OFF)
+ cpu_pm_enter();
+
+ pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
+ omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
+
+ /*
+ * Call idle CPU cluster PM enter notifier chain
+ * to save GIC and wakeupgen context.
+ */
+ if ((cx->mpu_state == PWRDM_POWER_RET) &&
+ (cx->mpu_logic_state == PWRDM_POWER_OFF))
+ cpu_cluster_pm_enter();
+
+ omap4_enter_lowpower(dev->cpu, cx->cpu_state);
+
+ /*
+ * Call idle CPU PM exit notifier chain to restore
+ * VFP and per CPU IRQ context. Only CPU0 state is
+ * considered since CPU1 is managed by CPU hotplug.
+ */
+ if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
+ cpu_pm_exit();
+
+ /*
+ * Call idle CPU cluster PM exit notifier chain
+ * to restore GIC and wakeupgen context.
+ */
+ if (omap4_mpuss_read_prev_context_state())
+ cpu_cluster_pm_exit();
+
+ if (index > 0)
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
+
+ getnstimeofday(&ts_postidle);
+ ts_idle = timespec_sub(ts_postidle, ts_preidle);
+
+ local_irq_enable();
+ local_fiq_enable();
+
+ idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
+ USEC_PER_SEC;
+
+ /* Update cpuidle counters */
+ dev->last_residency = idle_time;
+
+ return index;
+}
+
+DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
+
+struct cpuidle_driver omap4_idle_driver = {
+ .name = "omap4_idle",
+ .owner = THIS_MODULE,
+};
+
+static inline void _fill_cstate(struct cpuidle_driver *drv,
+ int idx, const char *descr)
+{
+ struct cpuidle_state *state = &drv->states[idx];
+
+ state->exit_latency = cpuidle_params_table[idx].exit_latency;
+ state->target_residency = cpuidle_params_table[idx].target_residency;
+ state->flags = CPUIDLE_FLAG_TIME_VALID;
+ state->enter = omap4_enter_idle;
+ sprintf(state->name, "C%d", idx + 1);
+ strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
+}
+
+static inline struct omap4_idle_statedata *_fill_cstate_usage(
+ struct cpuidle_device *dev,
+ int idx)
+{
+ struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
+ struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
+
+ cx->valid = cpuidle_params_table[idx].valid;
+ cpuidle_set_statedata(state_usage, cx);
+
+ return cx;
+}
+
+
+
+/**
+ * omap4_idle_init - Init routine for OMAP4 idle
+ *
+ * Registers the OMAP4 specific cpuidle driver to the cpuidle
+ * framework with the valid set of states.
+ */
+int __init omap4_idle_init(void)
+{
+ struct omap4_idle_statedata *cx;
+ struct cpuidle_device *dev;
+ struct cpuidle_driver *drv = &omap4_idle_driver;
+ unsigned int cpu_id = 0;
+
+ mpu_pd = pwrdm_lookup("mpu_pwrdm");
+ cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
+ cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
+ if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
+ return -ENODEV;
+
+
+ drv->safe_state_index = -1;
+ dev = &per_cpu(omap4_idle_dev, cpu_id);
+ dev->cpu = cpu_id;
+
+ /* C1 - CPU0 ON + CPU1 ON + MPU ON */
+ _fill_cstate(drv, 0, "MPUSS ON");
+ drv->safe_state_index = 0;
+ cx = _fill_cstate_usage(dev, 0);
+ cx->valid = 1; /* C1 is always valid */
+ cx->cpu_state = PWRDM_POWER_ON;
+ cx->mpu_state = PWRDM_POWER_ON;
+ cx->mpu_logic_state = PWRDM_POWER_RET;
+
+ /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
+ _fill_cstate(drv, 1, "MPUSS CSWR");
+ cx = _fill_cstate_usage(dev, 1);
+ cx->cpu_state = PWRDM_POWER_OFF;
+ cx->mpu_state = PWRDM_POWER_RET;
+ cx->mpu_logic_state = PWRDM_POWER_RET;
+
+ /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+ _fill_cstate(drv, 2, "MPUSS OSWR");
+ cx = _fill_cstate_usage(dev, 2);
+ cx->cpu_state = PWRDM_POWER_OFF;
+ cx->mpu_state = PWRDM_POWER_RET;
+ cx->mpu_logic_state = PWRDM_POWER_OFF;
+
+ drv->state_count = OMAP4_NUM_STATES;
+ cpuidle_register_driver(&omap4_idle_driver);
+
+ dev->state_count = OMAP4_NUM_STATES;
+ if (cpuidle_register_device(dev)) {
+ pr_err("%s: CPUidle register device failed\n", __func__);
+ return -EIO;
+ }
+
+ return 0;
+}
+#else
+int __init omap4_idle_init(void)
+{
+ return 0;
+}
+#endif /* CONFIG_CPU_IDLE */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/devices.c kernel_3.2.14_patched/arch/arm/mach-omap2/devices.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/devices.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/devices.c 2012-05-16 12:10:47.000000000 +0100
@@ -17,13 +17,28 @@
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/of.h>
+#include <linux/davinci_emac.h>
+#include <linux/cpsw.h>
+#include <linux/etherdevice.h>
+#include <linux/dma-mapping.h>
+#include <linux/can/platform/d_can.h>
+#include <linux/platform_data/uio_pruss.h>
+#include <linux/pwm/pwm.h>
+#include <linux/input/ti_tscadc.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
+#include <mach/board-am335xevm.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/pmu.h>
+#ifdef CONFIG_OMAP3_EDMA
+#include <mach/edma.h>
+#endif
+
+#include <asm/hardware/asp.h>
+
#include <plat/tc.h>
#include <plat/board.h>
#include <plat/mcbsp.h>
@@ -32,6 +47,12 @@
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
#include <plat/omap4-keypad.h>
+#include <plat/config_pwm.h>
+#include <plat/cpu.h>
+#include <plat/gpmc.h>
+
+/* LCD controller similar DA8xx */
+#include <video/da8xx-fb.h>
#include "mux.h"
#include "control.h"
@@ -51,7 +72,7 @@
* To avoid code running on other OMAPs in
* multi-omap builds
*/
- if (!(cpu_is_omap34xx()))
+ if (!(cpu_is_omap34xx()) || (cpu_is_am33xx()))
return -ENODEV;
l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
@@ -127,6 +148,99 @@
};
#endif
+int __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
+{
+ int id = 0;
+ struct platform_device *pdev;
+ struct omap_hwmod *oh;
+ char *oh_name = "lcdc";
+ char *dev_name = "da8xx_lcdc";
+
+ oh = omap_hwmod_lookup(oh_name);
+ if (!oh) {
+ pr_err("Could not look up LCD%d hwmod\n", id);
+ return -ENODEV;
+ }
+
+ pdev = omap_device_build(dev_name, id, oh, pdata,
+ sizeof(struct da8xx_lcdc_platform_data), NULL, 0, 0);
+ if (IS_ERR(pdev)) {
+ WARN(1, "Can't build omap_device for %s:%s.\n",
+ dev_name, oh->name);
+ return PTR_ERR(pdev);
+ }
+ return 0;
+}
+
+int __init am33xx_register_tsc(struct tsc_data *pdata)
+{
+ int id = -1;
+ struct platform_device *pdev;
+ struct omap_hwmod *oh;
+ char *oh_name = "adc_tsc";
+ char *dev_name = "tsc";
+
+ oh = omap_hwmod_lookup(oh_name);
+ if (!oh) {
+ pr_err("Could not look up TSC%d hwmod\n", id);
+ return -ENODEV;
+ }
+
+ pdev = omap_device_build(dev_name, id, oh, pdata,
+ sizeof(struct tsc_data), NULL, 0, 0);
+
+ WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
+ dev_name, oh->name);
+ return 0;
+}
+
+#if defined(CONFIG_SND_AM335X_SOC_EVM) || \
+ defined(CONFIG_SND_AM335X_SOC_EVM_MODULE)
+int __init am335x_register_mcasp(struct snd_platform_data *pdata, int ctrl_nr)
+{
+ int l;
+ struct omap_hwmod *oh;
+ struct platform_device *pdev;
+ char oh_name[12];
+ char *dev_name = "davinci-mcasp";
+
+ l = snprintf(oh_name, 12, "mcasp%d", ctrl_nr);
+
+ oh = omap_hwmod_lookup(oh_name);
+ if (!oh) {
+ pr_err("could not look up %s\n", oh_name);
+ return -ENODEV;
+ }
+
+ pdev = omap_device_build(dev_name, ctrl_nr, oh, pdata,
+ sizeof(struct snd_platform_data), NULL, 0, 0);
+ WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
+ dev_name, oh->name);
+ return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+}
+
+#else
+int __init am335x_register_mcasp(struct snd_platform_data *pdata, int ctrl_nr)
+{
+ return 0;
+}
+#endif
+
+#if (defined(CONFIG_SND_AM33XX_SOC) || (defined(CONFIG_SND_AM33XX_SOC_MODULE)))
+struct platform_device am33xx_pcm_device = {
+ .name = "davinci-pcm-audio",
+ .id = -1,
+};
+
+static void am33xx_init_pcm(void)
+{
+ platform_device_register(&am33xx_pcm_device);
+}
+
+#else
+static inline void am33xx_init_pcm(void) {}
+#endif
+
static struct resource omap3isp_resources[] = {
{
.start = OMAP3430_ISP_BASE,
@@ -299,6 +413,9 @@
static void omap_init_audio(void)
{
+ if (cpu_is_am33xx())
+ return;
+
platform_device_register(&omap_mcbsp1);
platform_device_register(&omap_mcbsp2);
if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
@@ -336,6 +453,27 @@
static inline void omap_init_mcpdm(void) {}
#endif
+#if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
+ defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
+
+static void omap_init_dmic(void)
+{
+ struct omap_hwmod *oh;
+ struct platform_device *pdev;
+
+ oh = omap_hwmod_lookup("dmic");
+ if (!oh) {
+ printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
+ return;
+ }
+
+ pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
+ WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
+}
+#else
+static inline void omap_init_dmic(void) {}
+#endif
+
#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
#include <plat/mcspi.h>
@@ -386,6 +524,92 @@
static inline void omap_init_mcspi(void) {}
#endif
+int __init omap_init_elm(void)
+{
+ int id = -1;
+ struct platform_device *pdev;
+ struct omap_hwmod *oh;
+ char *oh_name = "elm";
+ char *name = "omap2_elm";
+
+ oh = omap_hwmod_lookup(oh_name);
+ if (!oh) {
+ pr_err("Could not look up %s\n", oh_name);
+ return -ENODEV;
+ }
+
+ pdev = omap_device_build(name, id, oh, NULL, 0, NULL, 0, 0);
+
+ if (IS_ERR(pdev)) {
+ WARN(1, "Can't build omap_device for %s:%s.\n",
+ name, oh->name);
+ return PTR_ERR(pdev);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+#define PWM_STR_LEN 10
+int __init am33xx_register_ecap(int id, struct pwmss_platform_data *pdata)
+{
+ struct platform_device *pdev;
+ struct omap_hwmod *oh;
+ char *oh_name = "ecap";
+ char dev_name[PWM_STR_LEN];
+
+ sprintf(dev_name, "ecap.%d", id);
+
+ oh = omap_hwmod_lookup(dev_name);
+ if (!oh) {
+ pr_err("Could not look up %s hwmod\n", dev_name);
+ return -ENODEV;
+ }
+
+ pdev = omap_device_build(oh_name, id, oh, pdata,
+ sizeof(*pdata), NULL, 0, 0);
+
+ if (IS_ERR(pdev)) {
+ WARN(1, "Can't build omap_device for %s:%s.\n",
+ dev_name, oh->name);
+ return PTR_ERR(pdev);
+ }
+ return 0;
+}
+
+int __init am33xx_register_ehrpwm(int id, struct pwmss_platform_data *pdata)
+{
+ struct platform_device *pdev;
+ struct omap_hwmod *oh;
+ char *oh_name = "ehrpwm";
+ char dev_name[PWM_STR_LEN];
+
+ sprintf(dev_name, "ehrpwm.%d", id);
+
+ oh = omap_hwmod_lookup(dev_name);
+ if (!oh) {
+ pr_err("Could not look up %s hwmod\n", dev_name);
+ return -ENODEV;
+ }
+
+ pdev = omap_device_build(oh_name, id, oh, pdata,
+ sizeof(*pdata), NULL, 0, 0);
+
+ if (IS_ERR(pdev)) {
+ WARN(1, "Can't build omap_device for %s:%s.\n",
+ dev_name, oh->name);
+ return PTR_ERR(pdev);
+ }
+ return 0;
+}
+
+#else
+static int __init am335x_register_ehrpwm(int id,
+ struct pwmss_platform_data *pdata) { }
+static int __init am335x_register_ecap(int id,
+ struct pwmss_platform_data *pdata) { }
+#endif
+
static struct resource omap2_pmu_resource = {
.start = 3,
.end = 3,
@@ -408,7 +632,7 @@
{
if (cpu_is_omap24xx())
omap_pmu_device.resource = &omap2_pmu_resource;
- else if (cpu_is_omap34xx())
+ else if (cpu_is_omap34xx() && !cpu_is_am33xx())
omap_pmu_device.resource = &omap3_pmu_resource;
else
return;
@@ -469,7 +693,7 @@
if (cpu_is_omap24xx()) {
sham_device.resource = omap2_sham_resources;
sham_device.num_resources = omap2_sham_resources_sz;
- } else if (cpu_is_omap34xx()) {
+ } else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
sham_device.resource = omap3_sham_resources;
sham_device.num_resources = omap3_sham_resources_sz;
} else {
@@ -538,7 +762,7 @@
if (cpu_is_omap24xx()) {
aes_device.resource = omap2_aes_resources;
aes_device.num_resources = omap2_aes_resources_sz;
- } else if (cpu_is_omap34xx()) {
+ } else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
aes_device.resource = omap3_aes_resources;
aes_device.num_resources = omap3_aes_resources_sz;
} else {
@@ -671,6 +895,268 @@
static inline void omap_init_vout(void) {}
#endif
+#if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
+
+#define AM33XX_SCM_BASE_EDMA 0x00000f90
+
+static const s16 am33xx_dma_rsv_chans[][2] = {
+ /* (offset, number) */
+ {0, 2},
+ {14, 2},
+ {26, 6},
+ {48, 4},
+ {56, 8},
+ {-1, -1}
+};
+
+static const s16 am33xx_dma_rsv_slots[][2] = {
+ /* (offset, number) */
+ {0, 2},
+ {14, 2},
+ {26, 6},
+ {48, 4},
+ {56, 8},
+ {64, 127},
+ {-1, -1}
+};
+
+/* Three Transfer Controllers on AM33XX */
+static const s8 am33xx_queue_tc_mapping[][2] = {
+ /* {event queue no, TC no} */
+ {0, 0},
+ {1, 1},
+ {2, 2},
+ {-1, -1}
+};
+
+static const s8 am33xx_queue_priority_mapping[][2] = {
+ /* {event queue no, Priority} */
+ {0, 0},
+ {1, 1},
+ {2, 2},
+ {-1, -1}
+};
+
+static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
+ /* {xbar event no, Channel} */
+ {1, 12}, /* SDTXEVT1 -> MMCHS2 */
+ {2, 13}, /* SDRXEVT1 -> MMCHS2 */
+ {3, -1},
+ {4, -1},
+ {5, -1},
+ {6, -1},
+ {7, -1},
+ {8, -1},
+ {9, -1},
+ {10, -1},
+ {11, -1},
+ {12, -1},
+ {13, -1},
+ {14, -1},
+ {15, -1},
+ {16, -1},
+ {17, -1},
+ {18, -1},
+ {19, -1},
+ {20, -1},
+ {21, -1},
+ {22, -1},
+ {23, -1},
+ {24, -1},
+ {25, -1},
+ {26, -1},
+ {27, -1},
+ {28, -1},
+ {29, -1},
+ {30, -1},
+ {31, -1},
+ {-1, -1}
+};
+
+/**
+ * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
+ * according to the configuration provided
+ * @event: the event number for which mapping is required
+ * @channel: channel being activated
+ * @xbar_event_mapping: array that has the event to channel map
+ *
+ * Events that are routed by default are not mapped. Only events that
+ * are crossbar mapped are routed to available channels according to
+ * the configuration provided
+ *
+ * Returns zero on success, else negative errno.
+ */
+int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
+ struct event_to_channel_map *xbar_event_mapping)
+{
+ unsigned int ctrl = 0;
+ unsigned int xbar_evt_no = 0;
+ unsigned int val = 0;
+ unsigned int offset = 0;
+ unsigned int mask = 0;
+
+ ctrl = EDMA_CTLR(event);
+ xbar_evt_no = event - (edma_cc[ctrl]->num_channels);
+
+ if (event < edma_cc[ctrl]->num_channels) {
+ *channel = event;
+ } else if (event < edma_cc[ctrl]->num_events) {
+ *channel = xbar_event_mapping[xbar_evt_no].channel_no;
+ /* confirm the range */
+ if (*channel < EDMA_MAX_DMACH)
+ clear_bit(*channel, edma_cc[ctrl]->edma_unused);
+ mask = (*channel)%4;
+ offset = (*channel)/4;
+ offset *= 4;
+ offset += mask;
+ val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
+ AM33XX_SCM_BASE_EDMA + offset));
+ val = val & (~(0xFF));
+ val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
+ __raw_writel(val,
+ AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
+ return 0;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct edma_soc_info am33xx_edma_info[] = {
+ {
+ .n_channel = 64,
+ .n_region = 4,
+ .n_slot = 256,
+ .n_tc = 3,
+ .n_cc = 1,
+ .rsv_chans = am33xx_dma_rsv_chans,
+ .rsv_slots = am33xx_dma_rsv_slots,
+ .queue_tc_mapping = am33xx_queue_tc_mapping,
+ .queue_priority_mapping = am33xx_queue_priority_mapping,
+ .is_xbar = 1,
+ .n_events = 95,
+ .xbar_event_mapping = am33xx_xbar_event_mapping,
+ .map_xbar_channel = map_xbar_event_to_channel,
+ },
+};
+
+static int __init am33xx_register_edma(void)
+{
+ int i, l;
+ struct omap_hwmod *oh[4];
+ struct platform_device *pdev;
+ struct edma_soc_info *pdata = am33xx_edma_info;
+ char oh_name[8];
+
+ if (!cpu_is_am33xx())
+ return -ENODEV;
+
+ oh[0] = omap_hwmod_lookup("tpcc");
+ if (!oh[0]) {
+ pr_err("could not look up %s\n", "tpcc");
+ return -ENODEV;
+ }
+
+ for (i = 0; i < 3; i++) {
+ l = snprintf(oh_name, 8, "tptc%d", i);
+
+ oh[i+1] = omap_hwmod_lookup(oh_name);
+ if (!oh[i+1]) {
+ pr_err("could not look up %s\n", oh_name);
+ return -ENODEV;
+ }
+ }
+
+ pdev = omap_device_build_ss("edma", 0, oh, 4, pdata, sizeof(*pdata),
+ NULL, 0, 0);
+
+ WARN(IS_ERR(pdev), "could not build omap_device for edma\n");
+
+ return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+
+}
+
+#else
+static inline void am33xx_register_edma(void) {}
+#endif
+
+#if defined (CONFIG_SOC_OMAPAM33XX)
+struct uio_pruss_pdata am335x_pruss_uio_pdata = {
+ .pintc_base = 0x20000,
+};
+
+static struct resource am335x_pruss_resources[] = {
+ {
+ .start = AM33XX_ICSS_BASE,
+ .end = AM33XX_ICSS_BASE + AM33XX_ICSS_LEN,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_0,
+ .end = AM33XX_IRQ_ICSS0_0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_1,
+ .end = AM33XX_IRQ_ICSS0_1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_2,
+ .end = AM33XX_IRQ_ICSS0_2,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_3,
+ .end = AM33XX_IRQ_ICSS0_3,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_4,
+ .end = AM33XX_IRQ_ICSS0_4,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_5,
+ .end = AM33XX_IRQ_ICSS0_5,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_6,
+ .end = AM33XX_IRQ_ICSS0_6,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_7,
+ .end = AM33XX_IRQ_ICSS0_7,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device am335x_pruss_uio_dev = {
+ .name = "pruss_uio",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(am335x_pruss_resources),
+ .resource = am335x_pruss_resources,
+ .dev = {
+ .coherent_dma_mask = 0xffffffff,
+ }
+};
+
+int __init am335x_register_pruss_uio(struct uio_pruss_pdata *config)
+{
+ am335x_pruss_uio_dev.dev.platform_data = config;
+ return platform_device_register(&am335x_pruss_uio_dev);
+}
+
+static struct platform_device am335x_sgx = {
+ .name = "sgx",
+ .id = -1,
+};
+
+#endif
+
/*-------------------------------------------------------------------------*/
static int __init omap2_init_devices(void)
@@ -681,6 +1167,7 @@
*/
omap_init_audio();
omap_init_mcpdm();
+ omap_init_dmic();
omap_init_camera();
omap_init_mbox();
omap_init_mcspi();
@@ -690,11 +1177,276 @@
omap_init_sham();
omap_init_aes();
omap_init_vout();
-
+ am33xx_register_edma();
+ am33xx_init_pcm();
+#if defined (CONFIG_SOC_OMAPAM33XX)
+ am335x_register_pruss_uio(&am335x_pruss_uio_pdata);
+ if (omap3_has_sgx())
+ platform_device_register(&am335x_sgx);
+#endif
return 0;
}
arch_initcall(omap2_init_devices);
+#define AM33XX_EMAC_MDIO_FREQ (1000000)
+
+static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
+/* TODO : Verify the offsets */
+static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = "0:00",
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_id = "0:01",
+ },
+};
+
+static struct cpsw_platform_data am33xx_cpsw_pdata = {
+ .ss_reg_ofs = 0x1200,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 2,
+ .slave_data = am33xx_cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .bd_ram_size = SZ_8K,
+ .rx_descs = 64,
+ .mac_control = BIT(5), /* MIIEN */
+ .gigabit_en = 1,
+ .host_port_num = 0,
+ .no_bd_ram = false,
+ .version = CPSW_VERSION_2,
+};
+
+static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
+ .bus_freq = AM33XX_EMAC_MDIO_FREQ,
+};
+
+static struct resource am33xx_cpsw_mdioresources[] = {
+ {
+ .start = AM33XX_CPSW_MDIO_BASE,
+ .end = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device am33xx_cpsw_mdiodevice = {
+ .name = "davinci_mdio",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(am33xx_cpsw_mdioresources),
+ .resource = am33xx_cpsw_mdioresources,
+ .dev.platform_data = &am33xx_cpsw_mdiopdata,
+};
+
+static struct resource am33xx_cpsw_resources[] = {
+ {
+ .start = AM33XX_CPSW_BASE,
+ .end = AM33XX_CPSW_BASE + SZ_2K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = AM33XX_CPSW_SS_BASE,
+ .end = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = AM33XX_IRQ_CPSW_C0_RX,
+ .end = AM33XX_IRQ_CPSW_C0_RX,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_DMTIMER5,
+ .end = AM33XX_IRQ_DMTIMER5,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_DMTIMER6,
+ .end = AM33XX_IRQ_DMTIMER6,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_CPSW_C0,
+ .end = AM33XX_IRQ_CPSW_C0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device am33xx_cpsw_device = {
+ .name = "cpsw",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(am33xx_cpsw_resources),
+ .resource = am33xx_cpsw_resources,
+ .dev = {
+ .platform_data = &am33xx_cpsw_pdata,
+ .dma_mask = &am33xx_cpsw_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+static unsigned char am33xx_macid0[ETH_ALEN];
+static unsigned char am33xx_macid1[ETH_ALEN];
+static unsigned int am33xx_evmid;
+
+/*
+* am33xx_evmid_fillup - set up board evmid
+* @evmid - evm id which needs to be configured
+*
+* This function is called to configure board evm id.
+* IA Motor Control EVM needs special setting of MAC PHY Id.
+* This function is called when IA Motor Control EVM is detected
+* during boot-up.
+*/
+void am33xx_evmid_fillup(unsigned int evmid)
+{
+ am33xx_evmid = evmid;
+ return;
+}
+
+/*
+* am33xx_cpsw_macidfillup - setup mac adrresses
+* @eeprommacid0 - mac id 0 which needs to be configured
+* @eeprommacid1 - mac id 1 which needs to be configured
+*
+* This function is called to configure mac addresses.
+* Mac addresses are read from eeprom and this function is called
+* to store those mac adresses in am33xx_macid0 and am33xx_macid1.
+* In case, mac address read from eFuse are invalid, mac addresses
+* stored in these variable are used.
+*/
+void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
+{
+ u32 i;
+
+ /* Fillup these mac addresses with the mac adresses from eeprom */
+ for (i = 0; i < ETH_ALEN; i++) {
+ am33xx_macid0[i] = eeprommacid0[i];
+ am33xx_macid1[i] = eeprommacid1[i];
+ }
+
+ return;
+}
+
+#define MII_MODE_ENABLE 0x0
+#define RMII_MODE_ENABLE 0x5
+#define RGMII_MODE_ENABLE 0xA
+#define MAC_MII_SEL 0x650
+
+void am33xx_cpsw_init(unsigned int gigen)
+{
+ u32 mac_lo, mac_hi;
+ u32 i;
+
+ mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
+ mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
+ am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
+ am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
+ am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ /* Read MACID0 from eeprom if eFuse MACID is invalid */
+ if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
+ for (i = 0; i < ETH_ALEN; i++)
+ am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
+ }
+
+ mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
+ mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
+ am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
+ am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
+ am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ /* Read MACID1 from eeprom if eFuse MACID is invalid */
+ if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
+ for (i = 0; i < ETH_ALEN; i++)
+ am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
+ }
+
+ if (am33xx_evmid == BEAGLE_BONE_OLD) {
+ __raw_writel(RMII_MODE_ENABLE,
+ AM33XX_CTRL_REGADDR(MAC_MII_SEL));
+ } else if (am33xx_evmid == BEAGLE_BONE_A3) {
+ __raw_writel(MII_MODE_ENABLE,
+ AM33XX_CTRL_REGADDR(MAC_MII_SEL));
+ } else if (am33xx_evmid == IND_AUT_MTR_EVM) {
+ am33xx_cpsw_slaves[0].phy_id = "0:1e";
+ am33xx_cpsw_slaves[1].phy_id = "0:00";
+ } else {
+ __raw_writel(RGMII_MODE_ENABLE,
+ AM33XX_CTRL_REGADDR(MAC_MII_SEL));
+ }
+
+ am33xx_cpsw_pdata.gigabit_en = gigen;
+
+ memcpy(am33xx_cpsw_pdata.mac_addr,
+ am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
+ platform_device_register(&am33xx_cpsw_mdiodevice);
+ platform_device_register(&am33xx_cpsw_device);
+ clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
+ NULL, &am33xx_cpsw_device.dev);
+}
+
+#define AM33XX_DCAN_NUM_MSG_OBJS 64
+#define AM33XX_DCAN_RAMINIT_OFFSET 0x644
+#define AM33XX_DCAN_RAMINIT_START(n) (0x1 << n)
+
+static void d_can_hw_raminit(unsigned int instance, unsigned int enable)
+{
+ u32 val;
+
+ /* Read the value */
+ val = readl(AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
+ if (enable) {
+ /* Set to "1" */
+ val &= ~AM33XX_DCAN_RAMINIT_START(instance);
+ val |= AM33XX_DCAN_RAMINIT_START(instance);
+ writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
+ } else {
+ /* Set to "0" */
+ val &= ~AM33XX_DCAN_RAMINIT_START(instance);
+ writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
+ }
+}
+
+/* dcan dev_attr */
+static struct d_can_platform_data am33xx_dcan_info = {
+ .num_of_msg_objs = AM33XX_DCAN_NUM_MSG_OBJS,
+ .ram_init = d_can_hw_raminit,
+ .dma_support = false,
+};
+
+void am33xx_d_can_init(unsigned int instance)
+{
+ struct omap_hwmod *oh;
+ struct platform_device *pdev;
+ char oh_name[L3_MODULES_MAX_LEN];
+
+ /* Copy string name to oh_name buffer */
+ snprintf(oh_name, L3_MODULES_MAX_LEN, "d_can%d", instance);
+
+ oh = omap_hwmod_lookup(oh_name);
+ if (!oh) {
+ pr_err("could not find %s hwmod data\n", oh_name);
+ return;
+ }
+
+ pdev = omap_device_build("d_can", instance, oh, &am33xx_dcan_info,
+ sizeof(am33xx_dcan_info), NULL, 0, 0);
+ if (IS_ERR(pdev))
+ pr_err("could not build omap_device for %s\n", oh_name);
+}
+
#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
static int __init omap_init_wdt(void)
{
@@ -720,3 +1472,27 @@
}
subsys_initcall(omap_init_wdt);
#endif
+
+int __init omap_init_gpmc(struct gpmc_devices_info *pdata, int pdata_len)
+{
+ struct omap_hwmod *oh;
+ struct platform_device *pdev;
+ char *name = "omap-gpmc";
+ char *oh_name = "gpmc";
+
+ oh = omap_hwmod_lookup(oh_name);
+ if (!oh) {
+ pr_err("Could not look up %s\n", oh_name);
+ return -ENODEV;
+ }
+
+ pdev = omap_device_build(name, -1, oh, pdata,
+ pdata_len, NULL, 0, 0);
+ if (IS_ERR(pdev)) {
+ WARN(1, "Can't build omap_device for %s:%s.\n",
+ name, oh->name);
+ return PTR_ERR(pdev);
+ }
+
+ return 0;
+}
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/devices.h kernel_3.2.14_patched/arch/arm/mach-omap2/devices.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/devices.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/devices.h 2012-05-16 12:10:47.000000000 +0100
@@ -16,4 +16,12 @@
int omap3_init_camera(struct isp_platform_data *pdata);
+int __init am335x_register_mcasp(struct snd_platform_data *pdata, int ctrl_nr);
+extern int __init am33xx_register_tsc(struct tsc_data *pdata);
+extern int __init am33xx_register_ecap(int id,
+ struct pwmss_platform_data *pdata);
+extern int __init am33xx_register_ehrpwm(int id,
+ struct pwmss_platform_data *pdata);
+extern int __init omap_init_elm(void);
+
#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/display.c kernel_3.2.14_patched/arch/arm/mach-omap2/display.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/display.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/display.c 2012-05-16 12:10:47.000000000 +0100
@@ -22,12 +22,13 @@
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
+#include <linux/delay.h>
#include <video/omapdss.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
#include <plat/omap-pm.h>
-#include <plat/common.h>
+#include "common.h"
#include "control.h"
#include "display.h"
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/dpll3xxx.c kernel_3.2.14_patched/arch/arm/mach-omap2/dpll3xxx.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/dpll3xxx.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/dpll3xxx.c 2012-05-16 12:10:47.000000000 +0100
@@ -142,7 +142,8 @@
ai = omap3_dpll_autoidle_read(clk);
- omap3_dpll_deny_idle(clk);
+ if (ai)
+ omap3_dpll_deny_idle(clk);
_omap3_dpll_write_clken(clk, DPLL_LOCKED);
@@ -186,8 +187,6 @@
if (ai)
omap3_dpll_allow_idle(clk);
- else
- omap3_dpll_deny_idle(clk);
return r;
}
@@ -216,8 +215,6 @@
if (ai)
omap3_dpll_allow_idle(clk);
- else
- omap3_dpll_deny_idle(clk);
return 0;
}
@@ -301,10 +298,10 @@
_omap3_noncore_dpll_bypass(clk);
/*
- * Set jitter correction. No jitter correction for OMAP4 and 3630
- * since freqsel field is no longer present
+ * Set jitter correction. No jitter correction for OMAP4, 3630
+ * and AM33XX since freqsel field is no longer present
*/
- if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+ if (!cpu_is_omap44xx() && !cpu_is_omap3630() && !cpu_is_am33xx()) {
v = __raw_readl(dd->control_reg);
v &= ~dd->freqsel_mask;
v |= freqsel << __ffs(dd->freqsel_mask);
@@ -463,8 +460,9 @@
if (dd->last_rounded_rate == 0)
return -EINVAL;
- /* No freqsel on OMAP4 and OMAP3630 */
- if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+ /* No freqsel on OMAP4, OMAP3630 and AM33XX */
+ if (!cpu_is_omap44xx() && !cpu_is_omap3630() &&
+ !cpu_is_am33xx()) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n);
if (!freqsel)
@@ -519,6 +517,9 @@
dd = clk->dpll_data;
+ if (!dd->autoidle_reg)
+ return -EINVAL;
+
v = __raw_readl(dd->autoidle_reg);
v &= dd->autoidle_mask;
v >>= __ffs(dd->autoidle_mask);
@@ -545,6 +546,12 @@
dd = clk->dpll_data;
+ if (!dd->autoidle_reg) {
+ pr_debug("clock: DPLL %s: autoidle not supported\n",
+ clk->name);
+ return;
+ }
+
/*
* REVISIT: CORE DPLL can optionally enter low-power bypass
* by writing 0x5 instead of 0x1. Add some mechanism to
@@ -554,6 +561,7 @@
v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
__raw_writel(v, dd->autoidle_reg);
+
}
/**
@@ -572,6 +580,12 @@
dd = clk->dpll_data;
+ if (!dd->autoidle_reg) {
+ pr_debug("clock: DPLL %s: autoidle not supported\n",
+ clk->name);
+ return;
+ }
+
v = __raw_readl(dd->autoidle_reg);
v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/gpmc.c kernel_3.2.14_patched/arch/arm/mach-omap2/gpmc.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/gpmc.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/gpmc.c 2012-05-16 12:12:23.000000000 +0100
@@ -14,6 +14,8 @@
*/
#undef DEBUG
+#include <linux/platform_device.h>
+
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
@@ -24,9 +26,11 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/interrupt.h>
+#include <linux/pm_runtime.h>
#include <asm/mach-types.h>
#include <plat/gpmc.h>
+#include <plat/nand.h>
#include <plat/sdrc.h>
@@ -49,6 +53,7 @@
#define GPMC_ECC_CONTROL 0x1f8
#define GPMC_ECC_SIZE_CONFIG 0x1fc
#define GPMC_ECC1_RESULT 0x200
+#define GPMC_ECC_BCH_RESULT_0 0x240
#define GPMC_CS0_OFFSET 0x60
#define GPMC_CS_SIZE 0x30
@@ -91,58 +96,99 @@
struct gpmc_cs_config cs_context[GPMC_CS_NUM];
};
-static struct resource gpmc_mem_root;
-static struct resource gpmc_cs_mem[GPMC_CS_NUM];
-static DEFINE_SPINLOCK(gpmc_mem_lock);
-static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
-static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */
-static void __iomem *gpmc_base;
+#define DRIVER_NAME "omap-gpmc"
-static struct clk *gpmc_l3_clk;
+struct gpmc {
+ struct device *dev;
+ void __iomem *io_base;
+ unsigned long phys_base;
+ u32 memsize;
+ unsigned int cs_map;
+ int ecc_used;
+ spinlock_t mem_lock;
+ struct resource mem_root;
+ struct resource cs_mem[GPMC_CS_NUM];
+};
-static irqreturn_t gpmc_handle_irq(int irq, void *dev);
+static struct gpmc *gpmc;
static void gpmc_write_reg(int idx, u32 val)
{
- __raw_writel(val, gpmc_base + idx);
+ writel(val, gpmc->io_base + idx);
}
static u32 gpmc_read_reg(int idx)
{
- return __raw_readl(gpmc_base + idx);
+ return readl(gpmc->io_base + idx);
}
static void gpmc_cs_write_byte(int cs, int idx, u8 val)
{
void __iomem *reg_addr;
- reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
- __raw_writeb(val, reg_addr);
+ reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+ writeb(val, reg_addr);
}
static u8 gpmc_cs_read_byte(int cs, int idx)
{
void __iomem *reg_addr;
- reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
- return __raw_readb(reg_addr);
+ reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+ return readb(reg_addr);
}
void gpmc_cs_write_reg(int cs, int idx, u32 val)
{
void __iomem *reg_addr;
- reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
- __raw_writel(val, reg_addr);
+ if (!gpmc) {
+ pr_err("%s invoked without initializing GPMC\n", __func__);
+ return;
+ }
+
+ reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+ writel(val, reg_addr);
}
u32 gpmc_cs_read_reg(int cs, int idx)
{
void __iomem *reg_addr;
- reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
- return __raw_readl(reg_addr);
+ if (!gpmc) {
+ pr_err("%s invoked without initializing GPMC\n", __func__);
+ return 0;
+ }
+
+ reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+ return readl(reg_addr);
+}
+
+static struct clk *gpmc_l3_clk;
+
+static void __devinit gpmc_clk_init(struct device *dev)
+{
+ char *ck = NULL;
+
+ if (cpu_is_omap24xx())
+ ck = "core_l3_ck";
+ else if (cpu_is_omap34xx())
+ ck = "gpmc_fck";
+ else if (cpu_is_omap44xx())
+ ck = "gpmc_ck";
+
+ if (WARN_ON(!ck))
+ return;
+
+ gpmc_l3_clk = clk_get(NULL, ck);
+ if (IS_ERR(gpmc_l3_clk)) {
+ printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
+ BUG();
+ }
+
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
}
/* TODO: Add support for gpmc_fck to clock framework and use it */
@@ -341,6 +387,11 @@
*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
mask = (l >> 8) & 0x0f;
*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
+
+ if (cpu_is_am33xx()) {
+ *base = 0x8000000;
+ *size = 0x10000000;
+ }
}
static int gpmc_cs_mem_enabled(int cs)
@@ -356,8 +407,8 @@
if (cs > GPMC_CS_NUM)
return -ENODEV;
- gpmc_cs_map &= ~(1 << cs);
- gpmc_cs_map |= (reserved ? 1 : 0) << cs;
+ gpmc->cs_map &= ~(1 << cs);
+ gpmc->cs_map |= (reserved ? 1 : 0) << cs;
return 0;
}
@@ -367,7 +418,7 @@
if (cs > GPMC_CS_NUM)
return -ENODEV;
- return gpmc_cs_map & (1 << cs);
+ return gpmc->cs_map & (1 << cs);
}
static unsigned long gpmc_mem_align(unsigned long size)
@@ -386,22 +437,22 @@
static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
{
- struct resource *res = &gpmc_cs_mem[cs];
+ struct resource *res = &gpmc->cs_mem[cs];
int r;
size = gpmc_mem_align(size);
- spin_lock(&gpmc_mem_lock);
+ spin_lock(&gpmc->mem_lock);
res->start = base;
res->end = base + size - 1;
- r = request_resource(&gpmc_mem_root, res);
- spin_unlock(&gpmc_mem_lock);
+ r = request_resource(&gpmc->mem_root, res);
+ spin_unlock(&gpmc->mem_lock);
return r;
}
int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
{
- struct resource *res = &gpmc_cs_mem[cs];
+ struct resource *res = &gpmc->cs_mem[cs];
int r = -1;
if (cs > GPMC_CS_NUM)
@@ -411,7 +462,7 @@
if (size > (1 << GPMC_SECTION_SHIFT))
return -ENOMEM;
- spin_lock(&gpmc_mem_lock);
+ spin_lock(&gpmc->mem_lock);
if (gpmc_cs_reserved(cs)) {
r = -EBUSY;
goto out;
@@ -419,7 +470,7 @@
if (gpmc_cs_mem_enabled(cs))
r = adjust_resource(res, res->start & ~(size - 1), size);
if (r < 0)
- r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
+ r = allocate_resource(&gpmc->mem_root, res, size, 0, ~0,
size, NULL, NULL);
if (r < 0)
goto out;
@@ -428,24 +479,24 @@
*base = res->start;
gpmc_cs_set_reserved(cs, 1);
out:
- spin_unlock(&gpmc_mem_lock);
+ spin_unlock(&gpmc->mem_lock);
return r;
}
EXPORT_SYMBOL(gpmc_cs_request);
void gpmc_cs_free(int cs)
{
- spin_lock(&gpmc_mem_lock);
+ spin_lock(&gpmc->mem_lock);
if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
BUG();
- spin_unlock(&gpmc_mem_lock);
+ spin_unlock(&gpmc->mem_lock);
return;
}
gpmc_cs_disable_mem(cs);
- release_resource(&gpmc_cs_mem[cs]);
+ release_resource(&gpmc->cs_mem[cs]);
gpmc_cs_set_reserved(cs, 0);
- spin_unlock(&gpmc_mem_lock);
+ spin_unlock(&gpmc->mem_lock);
}
EXPORT_SYMBOL(gpmc_cs_free);
@@ -668,7 +719,7 @@
}
EXPORT_SYMBOL(gpmc_prefetch_reset);
-static void __init gpmc_mem_init(void)
+static void __devinit gpmc_mem_init(void)
{
int cs;
unsigned long boot_rom_space = 0;
@@ -680,8 +731,8 @@
/* In apollon the CS0 is mapped as 0x0000 0000 */
if (machine_is_omap_apollon())
boot_rom_space = 0;
- gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
- gpmc_mem_root.end = GPMC_MEM_END;
+ gpmc->mem_root.start = GPMC_MEM_START + boot_rom_space;
+ gpmc->mem_root.end = GPMC_MEM_END;
/* Reserve all regions that has been set up by bootloader */
for (cs = 0; cs < GPMC_CS_NUM; cs++) {
@@ -695,85 +746,107 @@
}
}
-static int __init gpmc_init(void)
+struct device *gpmc_dev;
+
+static int __devinit gpmc_probe(struct platform_device *pdev)
{
- u32 l, irq;
- int cs, ret = -EINVAL;
- int gpmc_irq;
- char *ck = NULL;
+ u32 l;
+ int ret = -EINVAL;
+ struct resource *res = NULL;
+ struct gpmc_devices_info *gpmc_device = pdev->dev.platform_data;
+ void *p;
- if (cpu_is_omap24xx()) {
- ck = "core_l3_ck";
- if (cpu_is_omap2420())
- l = OMAP2420_GPMC_BASE;
- else
- l = OMAP34XX_GPMC_BASE;
- gpmc_irq = INT_34XX_GPMC_IRQ;
- } else if (cpu_is_omap34xx()) {
- ck = "gpmc_fck";
- l = OMAP34XX_GPMC_BASE;
- gpmc_irq = INT_34XX_GPMC_IRQ;
- } else if (cpu_is_omap44xx()) {
- ck = "gpmc_ck";
- l = OMAP44XX_GPMC_BASE;
- gpmc_irq = OMAP44XX_IRQ_GPMC;
- }
+ /* XXX: This should go away with HWMOD & runtime PM adaptation */
+ gpmc_clk_init(&pdev->dev);
- if (WARN_ON(!ck))
- return ret;
+ gpmc_dev = &pdev->dev;
- gpmc_l3_clk = clk_get(NULL, ck);
- if (IS_ERR(gpmc_l3_clk)) {
- printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
- BUG();
+ gpmc = devm_kzalloc(&pdev->dev, sizeof(struct gpmc), GFP_KERNEL);
+ if (!gpmc)
+ return -ENOMEM;
+
+ gpmc->dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ ret = -ENOENT;
+ dev_err(gpmc->dev, "Failed to get resource: memory\n");
+ goto err_res;
}
+ gpmc->phys_base = res->start;
+ gpmc->memsize = resource_size(res);
- gpmc_base = ioremap(l, SZ_4K);
- if (!gpmc_base) {
- clk_put(gpmc_l3_clk);
- printk(KERN_ERR "Could not get GPMC register memory\n");
- BUG();
+ if (request_mem_region(gpmc->phys_base,
+ gpmc->memsize, DRIVER_NAME) == NULL) {
+ ret = -ENOMEM;
+ dev_err(gpmc->dev, "Failed to request memory region\n");
+ goto err_mem;
}
- clk_enable(gpmc_l3_clk);
+ gpmc->io_base = ioremap(gpmc->phys_base, gpmc->memsize);
+ if (!gpmc->io_base) {
+ ret = -ENOMEM;
+ dev_err(gpmc->dev, "Failed to ioremap memory\n");
+ goto err_remap;
+ }
+
+ gpmc->ecc_used = -EINVAL;
+ spin_lock_init(&gpmc->mem_lock);
+ platform_set_drvdata(pdev, gpmc);
l = gpmc_read_reg(GPMC_REVISION);
- printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
- /* Set smart idle mode and automatic L3 clock gating */
- l = gpmc_read_reg(GPMC_SYSCONFIG);
- l &= 0x03 << 3;
- l |= (0x02 << 3) | (1 << 0);
- gpmc_write_reg(GPMC_SYSCONFIG, l);
+ dev_info(gpmc->dev, "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
+
gpmc_mem_init();
- /* initalize the irq_chained */
- irq = OMAP_GPMC_IRQ_BASE;
- for (cs = 0; cs < GPMC_CS_NUM; cs++) {
- irq_set_chip_and_handler(irq, &dummy_irq_chip,
- handle_simple_irq);
- set_irq_flags(irq, IRQF_VALID);
- irq++;
- }
+ for (p = gpmc_device->pdata; p; gpmc_device++, p = gpmc_device->pdata)
+ if (gpmc_device->flag & GPMC_DEVICE_NAND)
+ gpmc_nand_init((struct omap_nand_platform_data *) p);
+ return 0;
- ret = request_irq(gpmc_irq,
- gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
- if (ret)
- pr_err("gpmc: irq-%d could not claim: err %d\n",
- gpmc_irq, ret);
+err_remap:
+ release_mem_region(gpmc->phys_base, gpmc->memsize);
+err_mem:
+err_res:
+ devm_kfree(&pdev->dev, gpmc);
return ret;
}
-postcore_initcall(gpmc_init);
-static irqreturn_t gpmc_handle_irq(int irq, void *dev)
+static int __devexit gpmc_remove(struct platform_device *pdev)
{
- u8 cs;
+ struct gpmc *gpmc = platform_get_drvdata(pdev);
+
+ platform_set_drvdata(pdev, NULL);
+ iounmap(gpmc->io_base);
+ release_mem_region(gpmc->phys_base, gpmc->memsize);
+ devm_kfree(&pdev->dev, gpmc);
+
+ return 0;
+}
- /* check cs to invoke the irq */
- cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
- if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
- generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
+static struct platform_driver gpmc_driver = {
+ .probe = gpmc_probe,
+ .remove = __devexit_p(gpmc_remove),
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+module_platform_driver(gpmc_driver);
- return IRQ_HANDLED;
+int gpmc_suspend(void)
+{
+ omap3_gpmc_save_context();
+ pm_runtime_put_sync(gpmc_dev);
+ return 0;
+}
+
+int gpmc_resume(void)
+{
+ pm_runtime_get_sync(gpmc_dev);
+ omap3_gpmc_restore_context();
+ return 0;
}
#ifdef CONFIG_ARCH_OMAP3
@@ -845,52 +918,74 @@
/**
* gpmc_enable_hwecc - enable hardware ecc functionality
+ * @ecc_type: ecc type e.g. Hamming, BCH
* @cs: chip select number
* @mode: read/write mode
* @dev_width: device bus width(1 for x16, 0 for x8)
* @ecc_size: bytes for which ECC will be generated
*/
-int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
+int gpmc_enable_hwecc(int ecc_type, int cs, int mode,
+ int dev_width, int ecc_size)
{
- unsigned int val;
-
- /* check if ecc module is in used */
- if (gpmc_ecc_used != -EINVAL)
- return -EINVAL;
-
- gpmc_ecc_used = cs;
-
- /* clear ecc and enable bits */
- val = ((0x00000001<<8) | 0x00000001);
- gpmc_write_reg(GPMC_ECC_CONTROL, val);
-
- /* program ecc and result sizes */
- val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
- gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
+ unsigned int bch_mod = 0, bch_wrapmode = 0, eccsize1 = 0, eccsize0 = 0;
+ unsigned int ecc_conf_val = 0, ecc_size_conf_val = 0;
switch (mode) {
case GPMC_ECC_READ:
- gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
+ if (ecc_type == OMAP_ECC_BCH4_CODE_HW) {
+ eccsize1 = 0xD; eccsize0 = 0x48;
+ bch_mod = 0;
+ bch_wrapmode = 0x09;
+ } else if (ecc_type == OMAP_ECC_BCH8_CODE_HW) {
+ eccsize1 = 0x2; eccsize0 = 0x1A;
+ bch_mod = 1;
+ bch_wrapmode = 0x01;
+ } else
+ eccsize1 = ((ecc_size >> 1) - 1);
break;
case GPMC_ECC_READSYN:
- gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
break;
case GPMC_ECC_WRITE:
- gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
+ if (ecc_type == OMAP_ECC_BCH4_CODE_HW) {
+ eccsize1 = 0x20; eccsize0 = 0x00;
+ bch_mod = 0;
+ bch_wrapmode = 0x06;
+ } else if (ecc_type == OMAP_ECC_BCH8_CODE_HW) {
+ eccsize1 = 0x1c; eccsize0 = 0x00;
+ bch_mod = 1;
+ bch_wrapmode = 0x01;
+ } else
+ eccsize1 = ((ecc_size >> 1) - 1);
break;
default:
printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
break;
}
- /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
- val = (dev_width << 7) | (cs << 1) | (0x1);
- gpmc_write_reg(GPMC_ECC_CONFIG, val);
+ /* clear ecc and enable bits */
+ if ((ecc_type == OMAP_ECC_BCH4_CODE_HW) ||
+ (ecc_type == OMAP_ECC_BCH8_CODE_HW)) {
+ gpmc_write_reg(GPMC_ECC_CONTROL, 0x00000001);
+ ecc_size_conf_val = (eccsize1 << 22) | (eccsize0 << 12);
+ ecc_conf_val = ((0x01 << 16) | (bch_mod << 12)
+ | (bch_wrapmode << 8) | (dev_width << 7)
+ | (0x00 << 4) | (cs << 1) | (0x1));
+ } else {
+ gpmc_write_reg(GPMC_ECC_CONTROL, 0x00000101);
+ ecc_size_conf_val = (eccsize1 << 22) | 0x0000000F;
+ ecc_conf_val = (dev_width << 7) | (cs << 1) | (0x1);
+ }
+
+ gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, ecc_size_conf_val);
+ gpmc_write_reg(GPMC_ECC_CONFIG, ecc_conf_val);
+ gpmc_write_reg(GPMC_ECC_CONTROL, 0x00000101);
return 0;
}
+EXPORT_SYMBOL(gpmc_enable_hwecc);
/**
* gpmc_calculate_ecc - generate non-inverted ecc bytes
+ * @ecc_type: ecc type e.g. Hamming, BCH
* @cs: chip select number
* @dat: data pointer over which ecc is computed
* @ecc_code: ecc code buffer
@@ -901,20 +996,51 @@
* an erased page will produce an ECC mismatch between generated and read
* ECC bytes that has to be dealt with separately.
*/
-int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
+int gpmc_calculate_ecc(int ecc_type, int cs,
+ const u_char *dat, u_char *ecc_code)
{
- unsigned int val = 0x0;
-
- if (gpmc_ecc_used != cs)
- return -EINVAL;
-
- /* read ecc result */
- val = gpmc_read_reg(GPMC_ECC1_RESULT);
- *ecc_code++ = val; /* P128e, ..., P1e */
- *ecc_code++ = val >> 16; /* P128o, ..., P1o */
- /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
- *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
+ unsigned int reg;
+ unsigned int val1 = 0x0, val2 = 0x0;
+ unsigned int val3 = 0x0, val4 = 0x0;
+ int i;
- gpmc_ecc_used = -EINVAL;
+ if ((ecc_type == OMAP_ECC_BCH4_CODE_HW) ||
+ (ecc_type == OMAP_ECC_BCH8_CODE_HW)) {
+ for (i = 0; i < 1; i++) {
+ /*
+ * Reading HW ECC_BCH_Results
+ * 0x240-0x24C, 0x250-0x25C, 0x260-0x26C, 0x270-0x27C
+ */
+ reg = GPMC_ECC_BCH_RESULT_0 + (0x10 * i);
+ val1 = gpmc_read_reg(reg);
+ val2 = gpmc_read_reg(reg + 4);
+ if (ecc_type == OMAP_ECC_BCH8_CODE_HW) {
+ val3 = gpmc_read_reg(reg + 8);
+ val4 = gpmc_read_reg(reg + 12);
+
+ *ecc_code++ = (val4 & 0xFF);
+ *ecc_code++ = ((val3 >> 24) & 0xFF);
+ *ecc_code++ = ((val3 >> 16) & 0xFF);
+ *ecc_code++ = ((val3 >> 8) & 0xFF);
+ *ecc_code++ = (val3 & 0xFF);
+ *ecc_code++ = ((val2 >> 24) & 0xFF);
+ }
+ *ecc_code++ = ((val2 >> 16) & 0xFF);
+ *ecc_code++ = ((val2 >> 8) & 0xFF);
+ *ecc_code++ = (val2 & 0xFF);
+ *ecc_code++ = ((val1 >> 24) & 0xFF);
+ *ecc_code++ = ((val1 >> 16) & 0xFF);
+ *ecc_code++ = ((val1 >> 8) & 0xFF);
+ *ecc_code++ = (val1 & 0xFF);
+ }
+ } else {
+ /* read ecc result */
+ val1 = gpmc_read_reg(GPMC_ECC1_RESULT);
+ *ecc_code++ = val1; /* P128e, ..., P1e */
+ *ecc_code++ = val1 >> 16; /* P128o, ..., P1o */
+ /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
+ *ecc_code++ = ((val1 >> 8) & 0x0f) | ((val1 >> 20) & 0xf0);
+ }
return 0;
}
+EXPORT_SYMBOL(gpmc_calculate_ecc);
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/gpmc-nand.c kernel_3.2.14_patched/arch/arm/mach-omap2/gpmc-nand.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/gpmc-nand.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/gpmc-nand.c 2012-05-16 12:10:47.000000000 +0100
@@ -81,12 +81,37 @@
return 0;
}
-int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
+int __devinit gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
{
int err = 0;
+ u8 cs = 0;
struct device *dev = &gpmc_nand_device.dev;
+ /* if cs not provided, find out the chip-select on which NAND exist */
+ if (gpmc_nand_data->cs > GPMC_CS_NUM)
+ while (cs < GPMC_CS_NUM) {
+ u32 ret = 0;
+ ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+
+ if ((ret & 0xC00) == 0x800) {
+ printk(KERN_INFO "Found NAND on CS%d\n", cs);
+ gpmc_nand_data->cs = cs;
+ break;
+ }
+ cs++;
+ }
+
+ if (gpmc_nand_data->cs > GPMC_CS_NUM) {
+ printk(KERN_INFO "NAND: Unable to find configuration "
+ "in GPMC\n ");
+ return -ENODEV;
+ }
+
gpmc_nand_device.dev.platform_data = gpmc_nand_data;
+ gpmc_nand_data->ctrlr_suspend = gpmc_suspend;
+ gpmc_nand_data->ctrlr_resume = gpmc_resume;
+
+ printk(KERN_INFO "Registering NAND on CS%d\n", gpmc_nand_data->cs);
err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
&gpmc_nand_data->phys_base);
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/hsmmc.c kernel_3.2.14_patched/arch/arm/mach-omap2/hsmmc.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/hsmmc.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/hsmmc.c 2012-05-16 12:10:47.000000000 +0100
@@ -171,6 +171,17 @@
}
}
+static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
+{
+ u32 reg;
+
+ if (mmc->slots[0].internal_clock) {
+ reg = omap_ctrl_readl(control_devconf1_offset);
+ reg |= OMAP2_MMCSDIO2ADPCLKISEL;
+ omap_ctrl_writel(reg, control_devconf1_offset);
+ }
+}
+
static void hsmmc23_before_set_reg(struct device *dev, int slot,
int power_on, int vdd)
{
@@ -179,16 +190,19 @@
if (mmc->slots[0].remux)
mmc->slots[0].remux(dev, slot, power_on);
- if (power_on) {
- /* Only MMC2 supports a CLKIN */
- if (mmc->slots[0].internal_clock) {
- u32 reg;
-
- reg = omap_ctrl_readl(control_devconf1_offset);
- reg |= OMAP2_MMCSDIO2ADPCLKISEL;
- omap_ctrl_writel(reg, control_devconf1_offset);
- }
- }
+ if (power_on)
+ hsmmc2_select_input_clk_src(mmc);
+}
+
+static int am35x_hsmmc2_set_power(struct device *dev, int slot,
+ int power_on, int vdd)
+{
+ struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+ if (power_on)
+ hsmmc2_select_input_clk_src(mmc);
+
+ return 0;
}
static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
@@ -200,10 +214,12 @@
static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
int controller_nr)
{
- if (gpio_is_valid(mmc_controller->slots[0].switch_pin))
+ if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
+ (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
OMAP_PIN_INPUT_PULLUP);
- if (gpio_is_valid(mmc_controller->slots[0].gpio_wp))
+ if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
+ (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
OMAP_PIN_INPUT_PULLUP);
if (cpu_is_omap34xx()) {
@@ -288,6 +304,9 @@
return -ENOMEM;
}
+ if (cpu_is_am33xx())
+ mmc->version = MMC_CTRL_VERSION_2;
+
if (c->name)
strncpy(hc_name, c->name, HSMMC_NAME_LEN);
else
@@ -296,6 +315,7 @@
mmc->slots[0].name = hc_name;
mmc->nr_slots = 1;
mmc->slots[0].caps = c->caps;
+ mmc->slots[0].pm_caps = c->pm_caps;
mmc->slots[0].internal_clock = !c->ext_clock;
mmc->dma_mask = 0xffffffff;
if (cpu_is_omap44xx())
@@ -336,14 +356,21 @@
*
* temporary HACK: ocr_mask instead of fixed supply
*/
- mmc->slots[0].ocr_mask = c->ocr_mask;
-
- if (cpu_is_omap3517() || cpu_is_omap3505())
- mmc->slots[0].set_power = nop_mmc_set_power;
+ if (cpu_is_omap3505() || cpu_is_omap3517())
+ mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
+ MMC_VDD_26_27 |
+ MMC_VDD_27_28 |
+ MMC_VDD_29_30 |
+ MMC_VDD_30_31 |
+ MMC_VDD_31_32;
else
+ mmc->slots[0].ocr_mask = c->ocr_mask;
+
+ if (!cpu_is_omap3517() && !cpu_is_omap3505() && !cpu_is_am33xx())
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
- if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
+ if ((cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) ||
+ cpu_is_am33xx())
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
switch (c->mmc) {
@@ -363,6 +390,9 @@
}
}
+ if (cpu_is_omap3517() || cpu_is_omap3505() || cpu_is_am33xx())
+ mmc->slots[0].set_power = nop_mmc_set_power;
+
/* OMAP3630 HSMMC1 supports only 4-bit */
if (cpu_is_omap3630() &&
(c->caps & MMC_CAP_8_BIT_DATA)) {
@@ -372,6 +402,12 @@
}
break;
case 2:
+ if (cpu_is_omap3517() || cpu_is_omap3505())
+ mmc->slots[0].set_power = am35x_hsmmc2_set_power;
+
+ if (cpu_is_am33xx())
+ mmc->slots[0].set_power = nop_mmc_set_power;
+
if (c->ext_clock)
c->transceiver = 1;
if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
@@ -421,7 +457,9 @@
pr_err("%s fails!\n", __func__);
goto done;
}
- omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
+
+ if (!cpu_is_am33xx())
+ omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
name = "omap_hsmmc";
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/hsmmc.h kernel_3.2.14_patched/arch/arm/mach-omap2/hsmmc.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/hsmmc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/hsmmc.h 2012-05-16 12:10:47.000000000 +0100
@@ -12,6 +12,7 @@
u8 mmc; /* controller 1/2/3 */
u32 caps; /* 4/8 wires and any additional host
* capabilities OR'd (ref. linux/mmc/host.h) */
+ u32 pm_caps; /* PM capabilities */
bool transceiver; /* MMC-2 option */
bool ext_clock; /* use external pin for input clock */
bool cover_only; /* No card detect - just cover switch */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/i2c.c kernel_3.2.14_patched/arch/arm/mach-omap2/i2c.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/i2c.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/i2c.c 2012-05-16 12:10:47.000000000 +0100
@@ -21,7 +21,7 @@
#include <plat/cpu.h>
#include <plat/i2c.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/omap_hwmod.h>
#include "mux.h"
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/id.c kernel_3.2.14_patched/arch/arm/mach-omap2/id.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/id.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/id.c 2012-05-16 12:10:47.000000000 +0100
@@ -21,7 +21,7 @@
#include <asm/cputype.h>
-#include <plat/common.h>
+#include "common.h"
#include <plat/cpu.h>
#include <mach/id.h>
@@ -29,7 +29,7 @@
#include "control.h"
static unsigned int omap_revision;
-
+static const char *cpu_rev;
u32 omap_features;
unsigned int omap_rev(void)
@@ -44,6 +44,8 @@
if (cpu_is_omap24xx()) {
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
+ } else if (cpu_is_am33xx()) {
+ val = omap_ctrl_readl(AM33XX_CONTROL_STATUS_OFF);
} else if (cpu_is_omap34xx()) {
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
@@ -112,7 +114,7 @@
odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
}
-static void __init omap24xx_check_revision(void)
+void __init omap2xxx_check_revision(void)
{
int i, j;
u32 idcode, prod_id;
@@ -166,13 +168,63 @@
pr_info("\n");
}
+#define OMAP3_SHOW_FEATURE(feat) \
+ if (omap3_has_ ##feat()) \
+ printk(#feat" ");
+
+static void __init omap3_cpuinfo(void)
+{
+ const char *cpu_name;
+
+ /*
+ * OMAP3430 and OMAP3530 are assumed to be same.
+ *
+ * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
+ * on available features. Upon detection, update the CPU id
+ * and CPU class bits.
+ */
+ if (cpu_is_omap3630()) {
+ cpu_name = "OMAP3630";
+ } else if (cpu_is_omap3517()) {
+ /* AM35xx devices */
+ cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
+ } else if (cpu_is_ti816x()) {
+ cpu_name = "TI816X";
+ } else if (cpu_is_am335x()) {
+ cpu_name = "AM335X";
+ } else if (cpu_is_ti814x()) {
+ cpu_name = "TI814X";
+ } else if (omap3_has_iva() && omap3_has_sgx()) {
+ /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
+ cpu_name = "OMAP3430/3530";
+ } else if (omap3_has_iva()) {
+ cpu_name = "OMAP3525";
+ } else if (omap3_has_sgx()) {
+ cpu_name = "OMAP3515";
+ } else {
+ cpu_name = "OMAP3503";
+ }
+
+ /* Print verbose information */
+ pr_info("%s ES%s (", cpu_name, cpu_rev);
+
+ OMAP3_SHOW_FEATURE(l2cache);
+ OMAP3_SHOW_FEATURE(iva);
+ OMAP3_SHOW_FEATURE(sgx);
+ OMAP3_SHOW_FEATURE(neon);
+ OMAP3_SHOW_FEATURE(isp);
+ OMAP3_SHOW_FEATURE(192mhz_clk);
+
+ printk(")\n");
+}
+
#define OMAP3_CHECK_FEATURE(status,feat) \
if (((status & OMAP3_ ##feat## _MASK) \
>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
omap_features |= OMAP3_HAS_ ##feat; \
}
-static void __init omap3_check_features(void)
+void __init omap3xxx_check_features(void)
{
u32 status;
@@ -199,9 +251,11 @@
* TODO: Get additional info (where applicable)
* e.g. Size of L2 cache.
*/
+
+ omap3_cpuinfo();
}
-static void __init omap4_check_features(void)
+void __init omap4xxx_check_features(void)
{
u32 si_type;
@@ -226,12 +280,26 @@
}
}
-static void __init ti816x_check_features(void)
+void __init ti81xx_check_features(void)
{
omap_features = OMAP3_HAS_NEON;
+ omap3_cpuinfo();
}
-static void __init omap3_check_revision(const char **cpu_rev)
+void __init am33xx_check_features(void)
+{
+ u32 status;
+
+ omap_features = OMAP3_HAS_NEON;
+
+ status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
+ if (status & AM33XX_SGX_MASK)
+ omap_features |= OMAP3_HAS_SGX;
+
+ omap3_cpuinfo();
+}
+
+void __init omap3xxx_check_revision(void)
{
u32 cpuid, idcode;
u16 hawkeye;
@@ -245,7 +313,7 @@
cpuid = read_cpuid(CPUID_ID);
if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
omap_revision = OMAP3430_REV_ES1_0;
- *cpu_rev = "1.0";
+ cpu_rev = "1.0";
return;
}
@@ -266,26 +334,26 @@
case 0: /* Take care of early samples */
case 1:
omap_revision = OMAP3430_REV_ES2_0;
- *cpu_rev = "2.0";
+ cpu_rev = "2.0";
break;
case 2:
omap_revision = OMAP3430_REV_ES2_1;
- *cpu_rev = "2.1";
+ cpu_rev = "2.1";
break;
case 3:
omap_revision = OMAP3430_REV_ES3_0;
- *cpu_rev = "3.0";
+ cpu_rev = "3.0";
break;
case 4:
omap_revision = OMAP3430_REV_ES3_1;
- *cpu_rev = "3.1";
+ cpu_rev = "3.1";
break;
case 7:
/* FALLTHROUGH */
default:
/* Use the latest known revision as default */
omap_revision = OMAP3430_REV_ES3_1_2;
- *cpu_rev = "3.1.2";
+ cpu_rev = "3.1.2";
}
break;
case 0xb868:
@@ -298,13 +366,13 @@
switch (rev) {
case 0:
omap_revision = OMAP3517_REV_ES1_0;
- *cpu_rev = "1.0";
+ cpu_rev = "1.0";
break;
case 1:
/* FALLTHROUGH */
default:
omap_revision = OMAP3517_REV_ES1_1;
- *cpu_rev = "1.1";
+ cpu_rev = "1.1";
}
break;
case 0xb891:
@@ -313,42 +381,66 @@
switch(rev) {
case 0: /* Take care of early samples */
omap_revision = OMAP3630_REV_ES1_0;
- *cpu_rev = "1.0";
+ cpu_rev = "1.0";
break;
case 1:
omap_revision = OMAP3630_REV_ES1_1;
- *cpu_rev = "1.1";
+ cpu_rev = "1.1";
break;
case 2:
/* FALLTHROUGH */
default:
omap_revision = OMAP3630_REV_ES1_2;
- *cpu_rev = "1.2";
+ cpu_rev = "1.2";
}
break;
case 0xb81e:
switch (rev) {
case 0:
omap_revision = TI8168_REV_ES1_0;
- *cpu_rev = "1.0";
+ cpu_rev = "1.0";
break;
case 1:
/* FALLTHROUGH */
default:
omap_revision = TI8168_REV_ES1_1;
- *cpu_rev = "1.1";
+ cpu_rev = "1.1";
+ break;
+ }
+ break;
+ case 0xb944:
+ omap_revision = AM335X_REV_ES1_0;
+ cpu_rev = "1.0";
+ break;
+ case 0xb8f2:
+ switch (rev) {
+ case 0:
+ /* FALLTHROUGH */
+ case 1:
+ omap_revision = TI8148_REV_ES1_0;
+ cpu_rev = "1.0";
+ break;
+ case 2:
+ omap_revision = TI8148_REV_ES2_0;
+ cpu_rev = "2.0";
+ break;
+ case 3:
+ /* FALLTHROUGH */
+ default:
+ omap_revision = TI8148_REV_ES2_1;
+ cpu_rev = "2.1";
break;
}
break;
default:
/* Unknown default to latest silicon rev as default */
omap_revision = OMAP3630_REV_ES1_2;
- *cpu_rev = "1.2";
+ cpu_rev = "1.2";
pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
}
}
-static void __init omap4_check_revision(void)
+void __init omap4xxx_check_revision(void)
{
u32 idcode;
u16 hawkeye;
@@ -367,7 +459,7 @@
* Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
* Use ARM register to detect the correct ES version
*/
- if (!rev && (hawkeye != 0xb94e)) {
+ if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
idcode = read_cpuid(CPUID_ID);
rev = (idcode & 0xf) - 1;
}
@@ -389,8 +481,11 @@
omap_revision = OMAP4430_REV_ES2_1;
break;
case 4:
- default:
omap_revision = OMAP4430_REV_ES2_2;
+ break;
+ case 6:
+ default:
+ omap_revision = OMAP4430_REV_ES2_3;
}
break;
case 0xb94e:
@@ -401,94 +496,23 @@
break;
}
break;
+ case 0xb975:
+ switch (rev) {
+ case 0:
+ default:
+ omap_revision = OMAP4470_REV_ES1_0;
+ break;
+ }
+ break;
default:
/* Unknown default to latest silicon rev as default */
- omap_revision = OMAP4430_REV_ES2_2;
+ omap_revision = OMAP4430_REV_ES2_3;
}
pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
}
-#define OMAP3_SHOW_FEATURE(feat) \
- if (omap3_has_ ##feat()) \
- printk(#feat" ");
-
-static void __init omap3_cpuinfo(const char *cpu_rev)
-{
- const char *cpu_name;
-
- /*
- * OMAP3430 and OMAP3530 are assumed to be same.
- *
- * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
- * on available features. Upon detection, update the CPU id
- * and CPU class bits.
- */
- if (cpu_is_omap3630()) {
- cpu_name = "OMAP3630";
- } else if (cpu_is_omap3517()) {
- /* AM35xx devices */
- cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
- } else if (cpu_is_ti816x()) {
- cpu_name = "TI816X";
- } else if (omap3_has_iva() && omap3_has_sgx()) {
- /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
- cpu_name = "OMAP3430/3530";
- } else if (omap3_has_iva()) {
- cpu_name = "OMAP3525";
- } else if (omap3_has_sgx()) {
- cpu_name = "OMAP3515";
- } else {
- cpu_name = "OMAP3503";
- }
-
- /* Print verbose information */
- pr_info("%s ES%s (", cpu_name, cpu_rev);
-
- OMAP3_SHOW_FEATURE(l2cache);
- OMAP3_SHOW_FEATURE(iva);
- OMAP3_SHOW_FEATURE(sgx);
- OMAP3_SHOW_FEATURE(neon);
- OMAP3_SHOW_FEATURE(isp);
- OMAP3_SHOW_FEATURE(192mhz_clk);
-
- printk(")\n");
-}
-
-/*
- * Try to detect the exact revision of the omap we're running on
- */
-void __init omap2_check_revision(void)
-{
- const char *cpu_rev;
-
- /*
- * At this point we have an idea about the processor revision set
- * earlier with omap2_set_globals_tap().
- */
- if (cpu_is_omap24xx()) {
- omap24xx_check_revision();
- } else if (cpu_is_omap34xx()) {
- omap3_check_revision(&cpu_rev);
-
- /* TI816X doesn't have feature register */
- if (!cpu_is_ti816x())
- omap3_check_features();
- else
- ti816x_check_features();
-
- omap3_cpuinfo(cpu_rev);
- return;
- } else if (cpu_is_omap44xx()) {
- omap4_check_revision();
- omap4_check_features();
- return;
- } else {
- pr_err("OMAP revision unknown, please fix!\n");
- }
-}
-
/*
* Set up things for map_io and processor detection later on. Gets called
* pretty much first thing from board init. For multi-omap, this gets
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/barriers.h kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/barriers.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/barriers.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/barriers.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,31 @@
+/*
+ * OMAP memory barrier header.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __MACH_BARRIERS_H
+#define __MACH_BARRIERS_H
+
+extern void omap_bus_sync(void);
+
+#define rmb() dsb()
+#define wmb() do { dsb(); outer_sync(); omap_bus_sync(); } while (0)
+#define mb() wmb()
+
+#endif /* __MACH_BARRIERS_H */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/board-am335xevm.h kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/board-am335xevm.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/board-am335xevm.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/board-am335xevm.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,47 @@
+/*
+ * Code for supporting AM335X EVM.
+ *
+ * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BOARD_AM335X_H
+#define _BOARD_AM335X_H
+
+#define BASEBOARD_I2C_ADDR 0x50
+#define DAUG_BOARD_I2C_ADDR 0x51
+#define LCD_BOARD_I2C_ADDR 0x52
+
+#define LOW_COST_EVM 0
+#define GEN_PURP_EVM 1
+#define IND_AUT_MTR_EVM 2
+#define IP_PHN_EVM 3
+#define BEAGLE_BONE_OLD 4
+#define BEAGLE_BONE_A3 5
+
+/* REVIST : check posibility of PROFILE_(x) syntax usage */
+#define PROFILE_NONE -1 /* Few EVM doesn't have profiles */
+#define PROFILE_0 (0x1 << 0)
+#define PROFILE_1 (0x1 << 1)
+#define PROFILE_2 (0x1 << 2)
+#define PROFILE_3 (0x1 << 3)
+#define PROFILE_4 (0x1 << 4)
+#define PROFILE_5 (0x1 << 5)
+#define PROFILE_6 (0x1 << 6)
+#define PROFILE_7 (0x1 << 7)
+#define PROFILE_ALL 0xFF
+
+void am33xx_evmid_fillup(unsigned int evmid);
+void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1);
+void am33xx_cpsw_init(unsigned int gigen);
+void am33xx_d_can_init(unsigned int instance);
+
+#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/debug-macro.S kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/debug-macro.S
--- linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/debug-macro.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/debug-macro.S 2012-05-16 12:10:47.000000000 +0100
@@ -66,12 +66,16 @@
beq 34f @ configure OMAP3UART4
cmp \rp, #OMAP4UART4 @ only on 44xx
beq 44f @ configure OMAP4UART4
- cmp \rp, #TI816XUART1 @ ti816x UART offsets different
+ cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different
beq 81f @ configure UART1
- cmp \rp, #TI816XUART2 @ ti816x UART offsets different
+ cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different
beq 82f @ configure UART2
- cmp \rp, #TI816XUART3 @ ti816x UART offsets different
+ cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different
beq 83f @ configure UART3
+ cmp \rp, #AM33XXUART1 @ AM33XX UART offsets different
+ beq 84f @ configure UART1
+ cmp \rp, #AM33XXUART4 @ AM33XX UART offsets different
+ beq 85f @ configure UART1
cmp \rp, #ZOOM_UART @ only on zoom2/3
beq 95f @ configure ZOOM_UART
@@ -94,13 +98,17 @@
b 98f
44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
b 98f
-81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE)
+81: mov \rp, #UART_OFFSET(TI81XX_UART1_BASE)
b 98f
-82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE)
+82: mov \rp, #UART_OFFSET(TI81XX_UART2_BASE)
b 98f
-83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE)
+83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
+ b 98f
+84: ldr \rp, =AM33XX_UART1_BASE
+ and \rp, \rp, #0x00ffffff
+ b 97f
+85: ldr \rp, =UART_OFFSET(AM33XX_UART4_BASE)
b 98f
-
95: ldr \rp, =ZOOM_UART_BASE
str \rp, [\tmp, #0] @ omap_uart_phys
ldr \rp, =ZOOM_UART_VIRT
@@ -109,6 +117,17 @@
str \rp, [\tmp, #8] @ omap_uart_lsr
b 10b
+ /* AM33XX: Store both phys and virt address for the uart */
+97: add \rp, \rp, #0x44000000 @ phys base
+ str \rp, [\tmp, #0] @ omap_uart_phys
+ sub \rp, \rp, #0x44000000 @ phys base
+ add \rp, \rp, #0xf9000000 @ virt base
+ str \rp, [\tmp, #4] @ omap_uart_virt
+ mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
+ str \rp, [\tmp, #8] @ omap_uart_lsr
+
+ b 10b
+
/* Store both phys and virt address for the uart */
98: add \rp, \rp, #0x48000000 @ phys base
str \rp, [\tmp, #0] @ omap_uart_phys
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/edma.h kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/edma.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/edma.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/edma.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,250 @@
+/*
+ * TI EDMA3 definitions
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This EDMA3 programming framework exposes two basic kinds of resource:
+ *
+ * Channel Triggers transfers, usually from a hardware event but
+ * also manually or by "chaining" from DMA completions.
+ * Each channel is coupled to a Parameter RAM (PaRAM) slot.
+ *
+ * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
+ * "set"), source and destination addresses, a link to a
+ * next PaRAM slot (if any), options for the transfer, and
+ * instructions for updating those addresses. There are
+ * more than twice as many slots as event channels.
+ *
+ * Each PaRAM set describes a sequence of transfers, either for one large
+ * buffer or for several discontiguous smaller buffers. An EDMA transfer
+ * is driven only from a channel, which performs the transfers specified
+ * in its PaRAM slot until there are no more transfers. When that last
+ * transfer completes, the "link" field may be used to reload the channel's
+ * PaRAM slot with a new transfer descriptor.
+ *
+ * The EDMA Channel Controller (CC) maps requests from channels into physical
+ * Transfer Controller (TC) requests when the channel triggers (by hardware
+ * or software events, or by chaining). The two physical DMA channels provided
+ * by the TCs are thus shared by many logical channels.
+ *
+ * EDMA hardware also has a "QDMA" mechanism which is not currently
+ * supported through this interface. (DSP firmware uses it though.)
+ */
+
+#ifndef EDMA_H_
+#define EDMA_H_
+
+/* PaRAM slots are laid out like this */
+struct edmacc_param {
+ unsigned int opt;
+ unsigned int src;
+ unsigned int a_b_cnt;
+ unsigned int dst;
+ unsigned int src_dst_bidx;
+ unsigned int link_bcntrld;
+ unsigned int src_dst_cidx;
+ unsigned int ccnt;
+};
+
+/* fields in edmacc_param.opt */
+#define SAM BIT(0)
+#define DAM BIT(1)
+#define SYNCDIM BIT(2)
+#define STATIC BIT(3)
+#define EDMA_FWID (0x07 << 8)
+#define TCCMODE BIT(11)
+#define EDMA_TCC(t) ((t) << 12)
+#define TCINTEN BIT(20)
+#define ITCINTEN BIT(21)
+#define TCCHEN BIT(22)
+#define ITCCHEN BIT(23)
+
+#define TRWORD (0x7<<2)
+#define PAENTRY (0x1ff<<5)
+
+/*ch_status paramater of callback function possible values*/
+#define DMA_COMPLETE 1
+#define DMA_CC_ERROR 2
+#define DMA_TC0_ERROR 3
+#define DMA_TC1_ERROR 4
+#define DMA_TC2_ERROR 5
+#define DMA_TC3_ERROR 6
+
+enum address_mode {
+ INCR = 0,
+ FIFO = 1
+};
+
+enum fifo_width {
+ W8BIT = 0,
+ W16BIT = 1,
+ W32BIT = 2,
+ W64BIT = 3,
+ W128BIT = 4,
+ W256BIT = 5
+};
+
+enum dma_event_q {
+ EVENTQ_0 = 0,
+ EVENTQ_1 = 1,
+ EVENTQ_2 = 2,
+ EVENTQ_3 = 3,
+ EVENTQ_DEFAULT = -1
+};
+
+enum sync_dimension {
+ ASYNC = 0,
+ ABSYNC = 1
+};
+
+#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
+#define EDMA_CTLR(i) ((i) >> 16)
+#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
+
+#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
+#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
+#define EDMA_CONT_PARAMS_ANY 1001
+#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
+#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
+
+#define EDMA_MAX_DMACH 64
+#define EDMA_MAX_PARAMENTRY 512
+#define EDMA_MAX_CC 2
+#define EDMA_MAX_REGION 4
+
+
+/* Mapping of crossbar event numbers to actual DMA channels*/
+struct event_to_channel_map {
+ unsigned xbar_event_no;
+ int channel_no;
+};
+
+/* actual number of DMA channels and slots on this silicon */
+struct edma {
+ /* how many dma resources of each type */
+ unsigned num_channels;
+ unsigned num_region;
+ unsigned num_slots;
+ unsigned num_tc;
+ unsigned num_cc;
+ enum dma_event_q default_queue;
+
+ /* list of channels with no even trigger; terminated by "-1" */
+ const s8 *noevent;
+
+ /* The edma_inuse bit for each PaRAM slot is clear unless the
+ * channel is in use ... by ARM or DSP, for QDMA, or whatever.
+ */
+ DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
+
+ /* The edma_unused bit for each channel is clear unless
+ * it is not being used on this platform. It uses a bit
+ * of SOC-specific initialization code.
+ */
+ DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
+
+ unsigned irq_res_start;
+ unsigned irq_res_end;
+
+ struct dma_interrupt_data {
+ void (*callback)(unsigned channel, unsigned short ch_status,
+ void *data);
+ void *data;
+ } intr_data[EDMA_MAX_DMACH];
+
+ unsigned is_xbar;
+ unsigned num_events;
+ struct event_to_channel_map *xbar_event_mapping;
+
+ /* suspend/resume backup parameters */
+ struct edmacc_param *bkp_prm_set;
+ unsigned int *bkp_ch_map; /* 64 registers */
+ unsigned int *bkp_que_num; /* 8 registers */
+ unsigned int *bkp_drae;
+ unsigned int *bkp_draeh;
+ unsigned int *bkp_qrae;
+ unsigned int bkp_sh_esr;
+ unsigned int bkp_sh_esrh;
+ unsigned int bkp_sh_eesr;
+ unsigned int bkp_sh_eesrh;
+ unsigned int bkp_sh_iesr;
+ unsigned int bkp_sh_iesrh;
+ unsigned int bkp_que_tc_map;
+ unsigned int bkp_que_pri;
+};
+
+extern struct edma *edma_cc[EDMA_MAX_CC];
+
+/* alloc/free DMA channels and their dedicated parameter RAM slots */
+int edma_alloc_channel(int channel,
+ void (*callback)(unsigned channel, u16 ch_status, void *data),
+ void *data, enum dma_event_q);
+void edma_free_channel(unsigned channel);
+
+/* alloc/free parameter RAM slots */
+int edma_alloc_slot(unsigned ctlr, int slot);
+void edma_free_slot(unsigned slot);
+
+/* alloc/free a set of contiguous parameter RAM slots */
+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
+int edma_free_cont_slots(unsigned slot, int count);
+
+/* calls that operate on part of a parameter RAM slot */
+void edma_set_src(unsigned slot, dma_addr_t src_port,
+ enum address_mode mode, enum fifo_width);
+void edma_set_dest(unsigned slot, dma_addr_t dest_port,
+ enum address_mode mode, enum fifo_width);
+void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
+void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
+void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
+void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
+ u16 bcnt_rld, enum sync_dimension sync_mode);
+void edma_link(unsigned from, unsigned to);
+void edma_unlink(unsigned from);
+
+/* calls that operate on an entire parameter RAM slot */
+void edma_write_slot(unsigned slot, const struct edmacc_param *params);
+void edma_read_slot(unsigned slot, struct edmacc_param *params);
+
+/* channel control operations */
+int edma_start(unsigned channel);
+void edma_stop(unsigned channel);
+void edma_clean_channel(unsigned channel);
+void edma_clear_event(unsigned channel);
+void edma_pause(unsigned channel);
+void edma_resume(unsigned channel);
+
+/* platform_data for EDMA driver */
+struct edma_soc_info {
+
+ /* how many dma resources of each type */
+ unsigned n_channel;
+ unsigned n_region;
+ unsigned n_slot;
+ unsigned n_tc;
+ unsigned n_cc;
+ enum dma_event_q default_queue;
+
+ const s16 (*rsv_chans)[2];
+ const s16 (*rsv_slots)[2];
+ const s8 (*queue_tc_mapping)[2];
+ const s8 (*queue_priority_mapping)[2];
+ unsigned is_xbar;
+ unsigned n_events;
+ struct event_to_channel_map *xbar_event_mapping;
+ int (*map_xbar_channel)(unsigned event, unsigned *channel,
+ struct event_to_channel_map *xbar_event_map);
+};
+
+#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/entry-macro.S kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/entry-macro.S
--- linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/entry-macro.S 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/entry-macro.S 2012-05-16 12:10:47.000000000 +0100
@@ -10,146 +10,9 @@
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/irqs.h>
-#include <asm/hardware/gic.h>
-
-#include <plat/omap24xx.h>
-#include <plat/omap34xx.h>
-#include <plat/omap44xx.h>
-
-#include <plat/multi.h>
-
-#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
-#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
-#define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
-#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
-#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
.macro disable_fiq
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
-/*
- * Unoptimized irq functions for multi-omap2, 3 and 4
- */
-
-#ifdef MULTI_OMAP2
- /*
- * Configure the interrupt base on the first interrupt.
- * See also omap_irq_base_init for setting omap_irq_base.
- */
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =omap_irq_base @ irq base address
- ldr \base, [\base, #0] @ irq base value
- .endm
-
- /* Check the pending interrupts. Note that base already set */
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- tst \base, #0x100 @ gic address?
- bne 4401f @ found gic
-
- /* Handle omap2 and omap3 */
- ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
- cmp \irqnr, #0x0
- bne 9998f
- ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
- cmp \irqnr, #0x0
- bne 9998f
- ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
- cmp \irqnr, #0x0
- bne 9998f
-
- /*
- * ti816x has additional IRQ pending register. Checking this
- * register on omap2 & omap3 has no effect (read as 0).
- */
- ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
- cmp \irqnr, #0x0
-9998:
- ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
- and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
- b 9999f
-
- /* Handle omap4 */
-4401: ldr \irqstat, [\base, #GIC_CPU_INTACK]
- ldr \tmp, =1021
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #15
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
-9999:
- .endm
-
-#ifdef CONFIG_SMP
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt
- * on the controller, since this requires the original irqstat
- * value which we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- it cc
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- it cs
- cmpcs \irqnr, \irqnr
- .endm
-#endif /* CONFIG_SMP */
-
-#else /* MULTI_OMAP2 */
-
-
-/*
- * Optimized irq functions for omap2, 3 and 4
- */
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
- .macro get_irqnr_preamble, base, tmp
-#ifdef CONFIG_ARCH_OMAP2
- ldr \base, =OMAP2_IRQ_BASE
-#else
- ldr \base, =OMAP3_IRQ_BASE
-#endif
- .endm
-
- /* Check the pending interrupts. Note that base already set */
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
- cmp \irqnr, #0x0
- bne 9999f
- ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
- cmp \irqnr, #0x0
- bne 9999f
- ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
- cmp \irqnr, #0x0
-#ifdef CONFIG_SOC_OMAPTI816X
- bne 9999f
- ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
- cmp \irqnr, #0x0
-#endif
-9999:
- ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
- and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
-
- .endm
-#endif
-
-
-#ifdef CONFIG_ARCH_OMAP4
-#define HAVE_GET_IRQNR_PREAMBLE
-#include <asm/hardware/entry-macro-gic.S>
-
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =OMAP4_IRQ_BASE
- .endm
-
-#endif
-
-#endif /* MULTI_OMAP2 */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/omap4-common.h kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/omap4-common.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/omap4-common.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/omap4-common.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,43 +0,0 @@
-/*
- * omap4-common.h: OMAP4 specific common header file
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- *
- * Author:
- * Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef OMAP_ARCH_OMAP4_COMMON_H
-#define OMAP_ARCH_OMAP4_COMMON_H
-
-/*
- * wfi used in low power code. Directly opcode is used instead
- * of instruction to avoid mulit-omap build break
- */
-#ifdef CONFIG_THUMB2_KERNEL
-#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
-#else
-#define do_wfi() \
- __asm__ __volatile__ (".word 0xe320f003" : : : "memory")
-#endif
-
-#ifdef CONFIG_CACHE_L2X0
-extern void __iomem *l2cache_base;
-#endif
-
-extern void __iomem *gic_dist_base_addr;
-
-extern void __init gic_init_irq(void);
-extern void omap_smc1(u32 fn, u32 arg);
-
-#ifdef CONFIG_SMP
-/* Needed for secondary core boot */
-extern void omap_secondary_startup(void);
-extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
-extern void omap_auxcoreboot_addr(u32 cpu_addr);
-extern u32 omap_read_auxcoreboot0(void);
-#endif
-#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/omap-secure.h kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/omap-secure.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/omap-secure.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/omap-secure.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,57 @@
+/*
+ * omap-secure.h: OMAP Secure infrastructure header.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_OMAP_SECURE_H
+#define OMAP_ARCH_OMAP_SECURE_H
+
+/* Monitor error code */
+#define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
+#define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
+
+/* HAL API error codes */
+#define API_HAL_RET_VALUE_OK 0x00
+#define API_HAL_RET_VALUE_FAIL 0x01
+
+/* Secure HAL API flags */
+#define FLAG_START_CRITICAL 0x4
+#define FLAG_IRQFIQ_MASK 0x3
+#define FLAG_IRQ_ENABLE 0x2
+#define FLAG_FIQ_ENABLE 0x1
+#define NO_FLAG 0x0
+
+/* Maximum Secure memory storage size */
+#define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K)
+
+/* Secure low power HAL API index */
+#define OMAP4_HAL_SAVESECURERAM_INDEX 0x1a
+#define OMAP4_HAL_SAVEHW_INDEX 0x1b
+#define OMAP4_HAL_SAVEALL_INDEX 0x1c
+#define OMAP4_HAL_SAVEGIC_INDEX 0x1d
+
+/* Secure Monitor mode APIs */
+#define OMAP4_MON_SCU_PWR_INDEX 0x108
+#define OMAP4_MON_L2X0_DBG_CTRL_INDEX 0x100
+#define OMAP4_MON_L2X0_CTRL_INDEX 0x102
+#define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109
+#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
+
+/* Secure PPA(Primary Protected Application) APIs */
+#define OMAP4_PPA_L2_POR_INDEX 0x23
+#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25
+
+#ifndef __ASSEMBLER__
+
+extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
+ u32 arg1, u32 arg2, u32 arg3, u32 arg4);
+extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
+extern phys_addr_t omap_secure_ram_mempool_base(void);
+
+#endif /* __ASSEMBLER__ */
+#endif /* OMAP_ARCH_OMAP_SECURE_H */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,39 @@
+/*
+ * OMAP WakeupGen header file
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_WAKEUPGEN_H
+#define OMAP_ARCH_WAKEUPGEN_H
+
+#define OMAP_WKG_CONTROL_0 0x00
+#define OMAP_WKG_ENB_A_0 0x10
+#define OMAP_WKG_ENB_B_0 0x14
+#define OMAP_WKG_ENB_C_0 0x18
+#define OMAP_WKG_ENB_D_0 0x1c
+#define OMAP_WKG_ENB_SECURE_A_0 0x20
+#define OMAP_WKG_ENB_SECURE_B_0 0x24
+#define OMAP_WKG_ENB_SECURE_C_0 0x28
+#define OMAP_WKG_ENB_SECURE_D_0 0x2c
+#define OMAP_WKG_ENB_A_1 0x410
+#define OMAP_WKG_ENB_B_1 0x414
+#define OMAP_WKG_ENB_C_1 0x418
+#define OMAP_WKG_ENB_D_1 0x41c
+#define OMAP_WKG_ENB_SECURE_A_1 0x420
+#define OMAP_WKG_ENB_SECURE_B_1 0x424
+#define OMAP_WKG_ENB_SECURE_C_1 0x428
+#define OMAP_WKG_ENB_SECURE_D_1 0x42c
+#define OMAP_AUX_CORE_BOOT_0 0x800
+#define OMAP_AUX_CORE_BOOT_1 0x804
+#define OMAP_PTMSYNCREQ_MASK 0xc00
+#define OMAP_PTMSYNCREQ_EN 0xc04
+#define OMAP_TIMESTAMPCYCLELO 0xc08
+#define OMAP_TIMESTAMPCYCLEHI 0xc0c
+
+extern int __init omap_wakeupgen_init(void);
+#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/sram.h kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/sram.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/sram.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/sram.h 2012-05-16 12:10:47.000000000 +0100
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-omap2/include/mach/sram.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_SRAM_H
+#define __ARCH_ARM_SRAM_H
+
+#include <plat/sram.h>
+
+#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/vmalloc.h kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/vmalloc.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/include/mach/vmalloc.h 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,20 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/vmalloc.h
- *
- * Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END 0xf8000000UL
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/io.c kernel_3.2.14_patched/arch/arm/mach-omap2/io.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/io.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/io.c 2012-05-16 12:10:47.000000000 +0100
@@ -35,15 +35,17 @@
#include "clock3xxx.h"
#include "clock44xx.h"
-#include <plat/common.h>
+#include "common.h"
#include <plat/omap-pm.h>
#include "voltage.h"
#include "powerdomain.h"
+#include "prminst44xx.h"
+#include "cminst44xx.h"
#include "clockdomain.h"
#include <plat/omap_hwmod.h>
#include <plat/multi.h>
-#include <plat/common.h>
+#include "common.h"
/*
* The machine specific code may provide the extra mapping besides the
@@ -176,14 +178,31 @@
};
#endif
-#ifdef CONFIG_SOC_OMAPTI816X
-static struct map_desc omapti816x_io_desc[] __initdata = {
+#ifdef CONFIG_SOC_OMAPTI81XX
+static struct map_desc omapti81xx_io_desc[] __initdata = {
+ {
+ .virtual = L4_34XX_VIRT,
+ .pfn = __phys_to_pfn(L4_34XX_PHYS),
+ .length = L4_34XX_SIZE,
+ .type = MT_DEVICE
+ }
+};
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+static struct map_desc omapam33xx_io_desc[] __initdata = {
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
.length = L4_34XX_SIZE,
.type = MT_DEVICE
},
+ {
+ .virtual = L4_WK_AM33XX_VIRT,
+ .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
+ .length = L4_WK_AM33XX_SIZE,
+ .type = MT_DEVICE
+ }
};
#endif
@@ -237,6 +256,15 @@
.length = L4_EMU_44XX_SIZE,
.type = MT_DEVICE,
},
+#ifdef CONFIG_OMAP4_ERRATA_I688
+ {
+ .virtual = OMAP4_SRAM_VA,
+ .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
+ .length = PAGE_SIZE,
+ .type = MT_MEMORY_SO,
+ },
+#endif
+
};
#endif
@@ -263,10 +291,17 @@
}
#endif
-#ifdef CONFIG_SOC_OMAPTI816X
-void __init omapti816x_map_common_io(void)
+#ifdef CONFIG_SOC_OMAPTI81XX
+void __init omapti81xx_map_common_io(void)
+{
+ iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
+}
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+void __init omapam33xx_map_common_io(void)
{
- iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
+ iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
}
#endif
@@ -316,13 +351,8 @@
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
}
-/* See irq.c, omap4-common.c and entry-macro.S */
-void __iomem *omap_irq_base;
-
static void __init omap_common_init_early(void)
{
- omap2_check_revision();
- omap_ioremap_init();
omap_init_consistent_dma_size();
}
@@ -363,6 +393,7 @@
void __init omap2420_init_early(void)
{
omap2_set_globals_242x();
+ omap2xxx_check_revision();
omap_common_init_early();
omap2xxx_voltagedomains_init();
omap242x_powerdomains_init();
@@ -375,6 +406,7 @@
void __init omap2430_init_early(void)
{
omap2_set_globals_243x();
+ omap2xxx_check_revision();
omap_common_init_early();
omap2xxx_voltagedomains_init();
omap243x_powerdomains_init();
@@ -393,6 +425,8 @@
void __init omap3_init_early(void)
{
omap2_set_globals_3xxx();
+ omap3xxx_check_revision();
+ omap3xxx_check_features();
omap_common_init_early();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
@@ -422,9 +456,11 @@
omap3_init_early();
}
-void __init ti816x_init_early(void)
+void __init ti81xx_init_early(void)
{
- omap2_set_globals_ti816x();
+ omap2_set_globals_ti81xx();
+ omap3xxx_check_revision();
+ ti81xx_check_features();
omap_common_init_early();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
@@ -433,15 +469,35 @@
omap_hwmod_init_postsetup();
omap3xxx_clk_init();
}
+
+void __init am33xx_init_early(void)
+{
+ omap2_set_globals_am33xx();
+ omap3xxx_check_revision();
+ am33xx_check_features();
+ omap_common_init_early();
+ am33xx_voltagedomains_init();
+ omap44xx_prminst_init();
+ am33xx_powerdomains_init();
+ omap44xx_cminst_init();
+ am33xx_clockdomains_init();
+ am33xx_hwmod_init();
+ omap_hwmod_init_postsetup();
+ omap3xxx_clk_init();
+}
#endif
#ifdef CONFIG_ARCH_OMAP4
void __init omap4430_init_early(void)
{
omap2_set_globals_443x();
+ omap4xxx_check_revision();
+ omap4xxx_check_features();
omap_common_init_early();
omap44xx_voltagedomains_init();
+ omap44xx_prminst_init();
omap44xx_powerdomains_init();
+ omap44xx_cminst_init();
omap44xx_clockdomains_init();
omap44xx_hwmod_init();
omap_hwmod_init_postsetup();
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/irq.c kernel_3.2.14_patched/arch/arm/mach-omap2/irq.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/irq.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/irq.c 2012-05-16 12:10:47.000000000 +0100
@@ -15,6 +15,7 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach/hardware.h>
+#include <asm/exception.h>
#include <asm/mach/irq.h>
@@ -35,6 +36,11 @@
/* Number of IRQ state bits in each MIR register */
#define IRQ_BITS_PER_REG 32
+#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
+#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
+#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
+#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
+
/*
* OMAP2 has a number of different interrupt controllers, each interrupt
* controller is identified as its own "bank". Register definitions are
@@ -143,6 +149,7 @@
static void __init omap_init_irq(u32 base, int nr_irqs)
{
+ void __iomem *omap_irq_base;
unsigned long nr_of_irqs = 0;
unsigned int nr_banks = 0;
int i, j;
@@ -186,11 +193,49 @@
omap_init_irq(OMAP34XX_IC_BASE, 96);
}
-void __init ti816x_init_irq(void)
+void __init ti81xx_init_irq(void)
{
omap_init_irq(OMAP34XX_IC_BASE, 128);
}
+static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
+{
+ u32 irqnr;
+
+ do {
+ irqnr = readl_relaxed(base_addr + 0x98);
+ if (irqnr)
+ goto out;
+
+ irqnr = readl_relaxed(base_addr + 0xb8);
+ if (irqnr)
+ goto out;
+
+ irqnr = readl_relaxed(base_addr + 0xd8);
+#ifdef CONFIG_SOC_OMAPTI816X
+ if (irqnr)
+ goto out;
+ irqnr = readl_relaxed(base_addr + 0xf8);
+#endif
+
+out:
+ if (!irqnr)
+ break;
+
+ irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
+ irqnr &= ACTIVEIRQ_MASK;
+
+ if (irqnr)
+ handle_IRQ(irqnr, regs);
+ } while (irqnr);
+}
+
+asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
+{
+ void __iomem *base_addr = OMAP2_IRQ_BASE;
+ omap_intc_handle_irq(base_addr, regs);
+}
+
#ifdef CONFIG_ARCH_OMAP3
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
@@ -263,4 +308,10 @@
/* Re-enable autoidle */
intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
}
+
+asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
+{
+ void __iomem *base_addr = OMAP3_IRQ_BASE;
+ omap_intc_handle_irq(base_addr, regs);
+}
#endif /* CONFIG_ARCH_OMAP3 */
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/Kconfig kernel_3.2.14_patched/arch/arm/mach-omap2/Kconfig
--- linux-stable-23d8c3f/arch/arm/mach-omap2/Kconfig 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/Kconfig 2012-05-16 12:10:47.000000000 +0100
@@ -25,6 +25,7 @@
depends on ARCH_OMAP2PLUS
default y
select CPU_V6
+ select MULTI_IRQ_HANDLER
config ARCH_OMAP3
bool "TI OMAP3"
@@ -36,6 +37,7 @@
select ARCH_HAS_OPP
select PM_OPP if PM
select ARM_CPU_SUSPEND if PM
+ select MULTI_IRQ_HANDLER
config ARCH_OMAP4
bool "TI OMAP4"
@@ -74,8 +76,13 @@
default y
select ARCH_OMAP_OTG
-config SOC_OMAPTI816X
- bool "TI816X support"
+config SOC_OMAPTI81XX
+ bool "TI81XX support"
+ depends on ARCH_OMAP3
+ default y
+
+config SOC_OMAPAM33XX
+ bool "AM33XX support"
depends on ARCH_OMAP3
default y
@@ -109,7 +116,6 @@
config MACH_OMAP_GENERIC
bool "Generic OMAP2+ board"
depends on ARCH_OMAP2PLUS
- select USE_OF
default y
help
Support for generic TI OMAP2+ boards using Flattened Device Tree.
@@ -177,6 +183,12 @@
for full description please see the products webpage at
http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit
+config MACH_ENCORE
+ bool "Barnes & Noble Encore (Nook Color)"
+ depends on ARCH_OMAP3
+ default y
+ select OMAP_PACKAGE_CBP
+
config MACH_OVERO
bool "Gumstix Overo board"
depends on ARCH_OMAP3
@@ -312,7 +324,22 @@
config MACH_TI8168EVM
bool "TI8168 Evaluation Module"
- depends on SOC_OMAPTI816X
+ depends on SOC_OMAPTI81XX
+ default y
+
+config MACH_TI8148EVM
+ bool "TI8148 Evaluation Module"
+ depends on SOC_OMAPTI81XX
+ default y
+
+config MACH_AM335XEVM
+ bool "AM335X Evaluation Module"
+ depends on SOC_OMAPAM33XX
+ default y
+
+config MACH_AM335XIAEVM
+ bool "AM335X IA Evaluation Module"
+ depends on SOC_OMAPAM33XX
default y
config MACH_OMAP_4430SDP
@@ -331,6 +358,12 @@
select OMAP_PACKAGE_CBS
select REGULATOR_FIXED_VOLTAGE
+config MACH_PCM049
+ bool "OMAP4 based phyCORE OMAP4"
+ depends on ARCH_OMAP4
+ default y
+ select OMAP_PACKAGE_CBS
+
config OMAP3_EMU
bool "OMAP3 debugging peripherals"
depends on ARCH_OMAP3
@@ -351,6 +384,35 @@
wish to say no. Selecting yes without understanding what is
going on could result in system crashes;
+config OMAP4_ERRATA_I688
+ bool "OMAP4 errata: Async Bridge Corruption"
+ depends on ARCH_OMAP4
+ select ARCH_HAS_BARRIERS
+ help
+ If a data is stalled inside asynchronous bridge because of back
+ pressure, it may be accepted multiple times, creating pointer
+ misalignment that will corrupt next transfers on that data path
+ until next reset of the system (No recovery procedure once the
+ issue is hit, the path remains consistently broken). Async bridge
+ can be found on path between MPU to EMIF and MPU to L3 interconnect.
+ This situation can happen only when the idle is initiated by a
+ Master Request Disconnection (which is trigged by software when
+ executing WFI on CPU).
+ The work-around for this errata needs all the initiators connected
+ through async bridge must ensure that data path is properly drained
+ before issuing WFI. This condition will be met if one Strongly ordered
+ access is performed to the target right before executing the WFI.
+ In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
+ IO barrier ensure that there is no synchronisation loss on initiators
+ operating on both interconnect port simultaneously.
+
+config OMAP3_EDMA
+ bool "OMAP3 EDMA support"
+ default n
+ depends on ARCH_OMAP3
+ help
+ Select this option if EDMA is used
+
endmenu
endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/mailbox.c kernel_3.2.14_patched/arch/arm/mach-omap2/mailbox.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/mailbox.c 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/mailbox.c 2012-05-16 12:10:47.000000000 +0100
@@ -20,25 +20,29 @@
#include <mach/irqs.h>
#define MAILBOX_REVISION 0x000
-#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
-#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
-#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
-#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
-#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
-
-#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
+#define MAILBOX_MESSAGE(m) (0x040 + 0x4 * (m))
+#define MAILBOX_FIFOSTATUS(m) (0x080 + 0x4 * (m))
+#define MAILBOX_MSGSTATUS(m) (0x0c0 + 0x4 * (m))
+#define MAILBOX_IRQSTATUS(u) (0x100 + 0x8 * (u))
+#define MAILBOX_IRQENABLE(u) (0x104 + 0x8 * (u))
+
+#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
+/* TODO: This can and should be based on #users and #sub-modules */
#define MBOX_REG_SIZE 0x120
#define OMAP4_MBOX_REG_SIZE 0x130
+#define AM33XX_MBOX_REG_SIZE 0x140
+
#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
+#define AM33XX_MBOX_NR_REGS (AM33XX_MBOX_REG_SIZE / sizeof(u32))
static void __iomem *mbox_base;
@@ -123,6 +127,20 @@
return mbox_read_reg(fifo->fifo_stat);
}
+static int omap2_mbox_fifo_needs_flush(struct omap_mbox *mbox)
+{
+ struct omap_mbox2_fifo *fifo =
+ &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
+ return (mbox_read_reg(fifo->msg_stat) == 0);
+}
+
+static mbox_msg_t omap2_mbox_fifo_readback(struct omap_mbox *mbox)
+{
+ struct omap_mbox2_fifo *fifo =
+ &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
+ return (mbox_msg_t) mbox_read_reg(fifo->msg);
+}
+
/* Mailbox IRQ handle functions */
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq)
@@ -141,7 +159,7 @@
struct omap_mbox2_priv *p = mbox->priv;
u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
- if (!cpu_is_omap44xx())
+ if (!cpu_is_omap44xx() && !cpu_is_am33xx())
bit = mbox_read_reg(p->irqdisable) & ~bit;
mbox_write_reg(bit, p->irqdisable);
@@ -205,19 +223,21 @@
}
static struct omap_mbox_ops omap2_mbox_ops = {
- .type = OMAP_MBOX_TYPE2,
- .startup = omap2_mbox_startup,
- .shutdown = omap2_mbox_shutdown,
- .fifo_read = omap2_mbox_fifo_read,
- .fifo_write = omap2_mbox_fifo_write,
- .fifo_empty = omap2_mbox_fifo_empty,
- .fifo_full = omap2_mbox_fifo_full,
- .enable_irq = omap2_mbox_enable_irq,
- .disable_irq = omap2_mbox_disable_irq,
- .ack_irq = omap2_mbox_ack_irq,
- .is_irq = omap2_mbox_is_irq,
- .save_ctx = omap2_mbox_save_ctx,
- .restore_ctx = omap2_mbox_restore_ctx,
+ .type = OMAP_MBOX_TYPE2,
+ .startup = omap2_mbox_startup,
+ .shutdown = omap2_mbox_shutdown,
+ .fifo_read = omap2_mbox_fifo_read,
+ .fifo_write = omap2_mbox_fifo_write,
+ .fifo_empty = omap2_mbox_fifo_empty,
+ .fifo_full = omap2_mbox_fifo_full,
+ .fifo_needs_flush = omap2_mbox_fifo_needs_flush,
+ .fifo_readback = omap2_mbox_fifo_readback,
+ .enable_irq = omap2_mbox_enable_irq,
+ .disable_irq = omap2_mbox_disable_irq,
+ .ack_irq = omap2_mbox_ack_irq,
+ .is_irq = omap2_mbox_is_irq,
+ .save_ctx = omap2_mbox_save_ctx,
+ .restore_ctx = omap2_mbox_restore_ctx,
};
/*
@@ -229,7 +249,6 @@
/* FIXME: the following structs should be filled automatically by the user id */
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
.tx_fifo = {
@@ -252,13 +271,9 @@
.ops = &omap2_mbox_ops,
.priv = &omap2_mbox_dsp_priv,
};
-#endif
-#if defined(CONFIG_ARCH_OMAP3)
struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
-#endif
-#if defined(CONFIG_SOC_OMAP2420)
/* IVA */
static struct omap_mbox2_priv omap2_mbox_iva_priv = {
.tx_fifo = {
@@ -283,9 +298,34 @@
};
struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
+/* A8 -> Wakeup-M3 */
+static struct omap_mbox2_priv omap2_mbox_m3_priv = {
+ .tx_fifo = {
+ .msg = MAILBOX_MESSAGE(0),
+ .fifo_stat = MAILBOX_FIFOSTATUS(0),
+ .msg_stat = MAILBOX_MSGSTATUS(0),
+ },
+ /* TODO: No M3->A8 so this needs to be removed */
+ .rx_fifo = {
+ .msg = MAILBOX_MESSAGE(1),
+ .msg_stat = MAILBOX_MSGSTATUS(1),
+ },
+ .irqenable = OMAP4_MAILBOX_IRQENABLE(3),
+ .irqstatus = OMAP4_MAILBOX_IRQSTATUS(3),
+ .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
+ .newmsg_bit = MAILBOX_IRQ_NEWMSG(0),
+ .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(3),
+};
+
+struct omap_mbox wkup_m3_info = {
+ .name = "wkup_m3",
+ .ops = &omap2_mbox_ops,
+ .priv = &omap2_mbox_m3_priv,
+};
+
+struct omap_mbox *am33xx_mboxes[] = { &wkup_m3_info, NULL };
+
/* OMAP4 */
static struct omap_mbox2_priv omap2_mbox_1_priv = {
.tx_fifo = {
@@ -332,7 +372,6 @@
};
struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
-#endif
static int __devinit omap2_mbox_probe(struct platform_device *pdev)
{
@@ -342,14 +381,15 @@
if (false)
;
-#if defined(CONFIG_ARCH_OMAP3)
- else if (cpu_is_omap34xx()) {
+ else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
list = omap3_mboxes;
list[0]->irq = platform_get_irq(pdev, 0);
+ } else if (cpu_is_am33xx()) {
+ list = am33xx_mboxes;
+
+ list[0]->irq = platform_get_irq(pdev, 0);
}
-#endif
-#if defined(CONFIG_ARCH_OMAP2)
else if (cpu_is_omap2430()) {
list = omap2_mboxes;
@@ -360,14 +400,11 @@
list[0]->irq = platform_get_irq_byname(pdev, "dsp");
list[1]->irq = platform_get_irq_byname(pdev, "iva");
}
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
else if (cpu_is_omap44xx()) {
list = omap4_mboxes;
list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
}
-#endif
else {
pr_err("%s: platform not supported\n", __func__);
return -ENODEV;
@@ -412,7 +449,7 @@
platform_driver_unregister(&omap2_mbox_driver);
}
-module_init(omap2_mbox_init);
+device_initcall(omap2_mbox_init);
module_exit(omap2_mbox_exit);
MODULE_LICENSE("GPL v2");
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/Makefile kernel_3.2.14_patched/arch/arm/mach-omap2/Makefile
--- linux-stable-23d8c3f/arch/arm/mach-omap2/Makefile 2012-04-02 17:53:31.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/Makefile 2012-05-16 12:10:47.000000000 +0100
@@ -11,10 +11,11 @@
omap_hwmod_common_data.o
clock-common = clock.o clock_common_data.o \
clkt_dpll.o clkt_clksel.o
+secure-common = omap-smc.o omap-secure.o
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
@@ -24,11 +25,13 @@
obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o
obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o
+obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o \
+ sleep44xx.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
-AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_omap-smc.o :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec)
# Functions loaded to SRAM
obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
@@ -44,6 +47,7 @@
obj-$(CONFIG_SOC_OMAP2430) += mux2430.o
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
+obj-$(CONFIG_SOC_OMAPAM33XX) += mux33xx.o
# SMS/SDRC
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
@@ -62,13 +66,17 @@
obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o \
cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o
+obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o \
+ cpuidle44xx.o
+obj-$(CONFIG_SOC_OMAPAM33XX) += cpuidle33xx.o pm33xx.o \
+ sleep33xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_sleep33xx.o :=-Wa,-march=armv7-a$(plus_sec)
ifeq ($(CONFIG_PM_VERBOSE),y)
CFLAGS_pm_bus.o += -DDEBUG
@@ -77,16 +85,19 @@
endif
# PRCM
+obj-y += prm_common.o
obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
vc3xxx_data.o vp3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX) += cminst44xx.o
+
# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
# will be removed once the OMAP4 part of the codebase is converted to
# use OMAP4-specific PRCM functions.
obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
cm44xx.o prcm_mpu44xx.o \
prminst44xx.o vc44xx_data.o \
- vp44xx_data.o
+ vp44xx_data.o prm44xx.o
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
@@ -94,6 +105,8 @@
voltagedomains2xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \
voltagedomains3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX) += $(voltagedomain-common) \
+ voltagedomains33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) \
voltagedomains44xx_data.o
@@ -107,6 +120,9 @@
powerdomain2xxx_3xxx.o \
powerdomains3xxx_data.o \
powerdomains2xxx_3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX) += prminst44xx.o \
+ powerdomain44xx.o \
+ powerdomains33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
powerdomain44xx.o \
powerdomains44xx_data.o
@@ -121,6 +137,8 @@
clockdomain2xxx_3xxx.o \
clockdomains2xxx_3xxx_data.o \
clockdomains3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX) += clockdomain44xx.o \
+ clockdomains33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
clockdomain44xx.o \
clockdomains44xx_data.o
@@ -139,6 +157,7 @@
clock3517.o clock36xx.o \
dpll3xxx.o clock3xxx_data.o \
clkt_iclk.o
+obj-$(CONFIG_SOC_OMAPAM33XX) += clock33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \
dpll3xxx.o dpll44xx.o
@@ -160,6 +179,7 @@
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o \
omap_hwmod_2xxx_3xxx_interconnect_data.o \
omap_hwmod_3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
# EMU peripherals
@@ -232,6 +252,9 @@
obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o
obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o
+obj-$(CONFIG_MACH_TI8148EVM) += board-ti8168evm.o
+obj-$(CONFIG_MACH_AM335XEVM) += board-am335xevm.o
+obj-$(CONFIG_MACH_AM335XIAEVM) += board-am335xevm.o
# Platform specific device init code
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/mux33xx.c kernel_3.2.14_patched/arch/arm/mach-omap2/mux33xx.c
--- linux-stable-23d8c3f/arch/arm/mach-omap2/mux33xx.c 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/mux33xx.c 2012-05-16 12:13:09.000000000 +0100
@@ -0,0 +1,619 @@
+/*
+ * AM33XX mux data
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Derived from: arch/arm/mach-omap2/mux34xx.c Original copyright follows:
+ *
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_OMAP_MUX
+
+#define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
+{ \
+ .reg_offset = (AM33XX_CONTROL_PADCONF_##M0##_OFFSET), \
+ .gpio = (g), \
+ .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
+}
+
+/* AM33XX pin mux super set */
+static struct omap_mux __initdata am33xx_muxmodes[] = {
+ _AM33XX_MUXENTRY(GPMC_AD0, 0,
+ "gpmc_ad0", "mmc1_dat0", NULL, NULL,
+ NULL, NULL, NULL, "gpio1_0"),
+ _AM33XX_MUXENTRY(GPMC_AD1, 0,
+ "gpmc_ad1", "mmc1_dat1", NULL, NULL,
+ NULL, NULL, NULL, "gpio1_1"),
+ _AM33XX_MUXENTRY(GPMC_AD2, 0,
+ "gpmc_ad2", "mmc1_dat2", NULL, NULL,
+ NULL, NULL, NULL, "gpio1_2"),
+ _AM33XX_MUXENTRY(GPMC_AD3, 0,
+ "gpmc_ad3", "mmc1_dat3", NULL, NULL,
+ NULL, NULL, NULL, "gpio1_3"),
+ _AM33XX_MUXENTRY(GPMC_AD4, 0,
+ "gpmc_ad4", "mmc1_dat4", NULL, NULL,
+ NULL, NULL, NULL, "gpio1_4"),
+ _AM33XX_MUXENTRY(GPMC_AD5, 0,
+ "gpmc_ad5", "mmc1_dat5", NULL, NULL,
+ NULL, NULL, NULL, "gpio1_5"),
+ _AM33XX_MUXENTRY(GPMC_AD6, 0,
+ "gpmc_ad6", "mmc1_dat6", NULL, NULL,
+ NULL, NULL, NULL, "gpio1_6"),
+ _AM33XX_MUXENTRY(GPMC_AD7, 0,
+ "gpmc_ad7", "mmc1_dat7", NULL, NULL,
+ NULL, NULL, NULL, "gpio1_7"),
+ _AM33XX_MUXENTRY(GPMC_AD8, 0,
+ "gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
+ NULL, NULL, NULL, "gpio0_22"),
+ _AM33XX_MUXENTRY(GPMC_AD9, 0,
+ "gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
+ "ehrpwm2B", NULL, NULL, "gpio0_23"),
+ _AM33XX_MUXENTRY(GPMC_AD10, 0,
+ "gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
+ NULL, NULL, NULL, "gpio0_26"),
+ _AM33XX_MUXENTRY(GPMC_AD11, 0,
+ "gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
+ NULL, NULL, NULL, "gpio0_27"),
+ _AM33XX_MUXENTRY(GPMC_AD12, 0,
+ "gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
+ NULL, NULL, NULL, "gpio1_12"),
+ _AM33XX_MUXENTRY(GPMC_AD13, 0,
+ "gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
+ NULL, NULL, NULL, "gpio1_13"),
+ _AM33XX_MUXENTRY(GPMC_AD14, 0,
+ "gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",
+ NULL, NULL, NULL, "gpio1_14"),
+ _AM33XX_MUXENTRY(GPMC_AD15, 0,
+ "gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
+ NULL, NULL, NULL, "gpio1_15"),
+ _AM33XX_MUXENTRY(GPMC_A0, 0,
+ "gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
+ NULL, NULL, NULL, "gpio1_16"),
+ _AM33XX_MUXENTRY(GPMC_A1, 0,
+ "gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
+ NULL, NULL, NULL, "gpio1_17"),
+ _AM33XX_MUXENTRY(GPMC_A2, 0,
+ "gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
+ NULL, NULL, "ehrpwm1A", "gpio1_18"),
+ _AM33XX_MUXENTRY(GPMC_A3, 0,
+ "gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
+ NULL, NULL, NULL, "gpio1_19"),
+ _AM33XX_MUXENTRY(GPMC_A4, 0,
+ "gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
+ "gpmc_a20", NULL, NULL, "gpio1_20"),
+ _AM33XX_MUXENTRY(GPMC_A5, 0,
+ "gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
+ "gpmc_a21", NULL, NULL, "gpio1_21"),
+ _AM33XX_MUXENTRY(GPMC_A6, 0,
+ "gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
+ "gpmc_a22", NULL, NULL, "gpio1_22"),
+ _AM33XX_MUXENTRY(GPMC_A7, 0,
+ "gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
+ NULL, NULL, NULL, "gpio1_23"),
+ _AM33XX_MUXENTRY(GPMC_A8, 0,
+ "gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
+ NULL, NULL, "mcasp0_aclkx", "gpio1_24"),
+ _AM33XX_MUXENTRY(GPMC_A9, 0,
+ "gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
+ NULL, NULL, "mcasp0_fsx", "gpio1_25"),
+ _AM33XX_MUXENTRY(GPMC_A10, 0,
+ "gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1",
+ NULL, NULL, "mcasp0_axr0", "gpio1_26"),
+ _AM33XX_MUXENTRY(GPMC_A11, 0,
+ "gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0",
+ NULL, NULL, "mcasp0_axr1", "gpio1_27"),
+ _AM33XX_MUXENTRY(GPMC_WAIT0, 0,
+ "gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv",
+ "mmc1_sdcd", NULL, NULL, "gpio0_30"),
+ _AM33XX_MUXENTRY(GPMC_WPN, 0,
+ "gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr",
+ "mmc2_sdcd", NULL, NULL, "gpio0_31"),
+ _AM33XX_MUXENTRY(GPMC_BEN1, 0,
+ "gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
+ NULL, NULL, "mcasp0_aclkr", "gpio1_28"),
+ _AM33XX_MUXENTRY(GPMC_CSN0, 0,
+ "gpmc_csn0", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio1_29"),
+ _AM33XX_MUXENTRY(GPMC_CSN1, 0,
+ "gpmc_csn1", NULL, "mmc1_clk", NULL,
+ NULL, NULL, NULL, "gpio1_30"),
+ _AM33XX_MUXENTRY(GPMC_CSN2, 0,
+ "gpmc_csn2", NULL, "mmc1_cmd", NULL,
+ NULL, NULL, NULL, "gpio1_31"),
+ _AM33XX_MUXENTRY(GPMC_CSN3, 0,
+ "gpmc_csn3", NULL, NULL, "mmc2_cmd",
+ NULL, NULL, NULL, "gpio2_0"),
+ _AM33XX_MUXENTRY(GPMC_CLK, 0,
+ "gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk",
+ NULL, NULL, "mcasp0_fsr", "gpio2_1"),
+ _AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
+ "gpmc_advn_ale", NULL, NULL, NULL,
+ NULL, NULL, NULL, "mmc1_sdcd"),
+ _AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
+ "gpmc_oen_ren", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_3"),
+ _AM33XX_MUXENTRY(GPMC_WEN, 0,
+ "gpmc_wen", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_4"),
+ _AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
+ "gpmc_ben0_cle", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_5"),
+ _AM33XX_MUXENTRY(LCD_DATA0, 0,
+ "lcd_data0", "gpmc_a0", NULL, NULL,
+ NULL, NULL, NULL, "gpio2_6"),
+ _AM33XX_MUXENTRY(LCD_DATA1, 0,
+ "lcd_data1", "gpmc_a1", NULL, NULL,
+ NULL, NULL, NULL, "gpio2_7"),
+ _AM33XX_MUXENTRY(LCD_DATA2, 0,
+ "lcd_data2", "gpmc_a2", NULL, NULL,
+ NULL, NULL, NULL, "gpio2_8"),
+ _AM33XX_MUXENTRY(LCD_DATA3, 0,
+ "lcd_data3", "gpmc_a3", NULL, NULL,
+ NULL, NULL, NULL, "gpio2_9"),
+ _AM33XX_MUXENTRY(LCD_DATA4, 0,
+ "lcd_data4", "gpmc_a4", NULL, NULL,
+ NULL, NULL, NULL, "gpio2_10"),
+ _AM33XX_MUXENTRY(LCD_DATA5, 0,
+ "lcd_data5", "gpmc_a5", NULL, NULL,
+ NULL, NULL, NULL, "gpio2_11"),
+ _AM33XX_MUXENTRY(LCD_DATA6, 0,
+ "lcd_data6", "gpmc_a6", NULL, NULL,
+ NULL, NULL, NULL, "gpio2_12"),
+ _AM33XX_MUXENTRY(LCD_DATA7, 0,
+ "lcd_data7", "gpmc_a7", NULL, NULL,
+ NULL, NULL, NULL, "gpio2_13"),
+ _AM33XX_MUXENTRY(LCD_DATA8, 0,
+ "lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
+ NULL, NULL, "uart2_ctsn", "gpio2_14"),
+ _AM33XX_MUXENTRY(LCD_DATA9, 0,
+ "lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
+ NULL, NULL, "uart2_rtsn", "gpio2_15"),
+ _AM33XX_MUXENTRY(LCD_DATA10, 0,
+ "lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
+ NULL, NULL, NULL, "gpio2_16"),
+ _AM33XX_MUXENTRY(LCD_DATA11, 0,
+ "lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",
+ "mcasp0_axr2", NULL, NULL, "gpio2_17"),
+ _AM33XX_MUXENTRY(LCD_DATA12, 0,
+ "lcd_data12", "gpmc_a16", NULL, "mcasp0_aclkr",
+ "mcasp0_axr2", NULL, NULL, "gpio0_8"),
+ _AM33XX_MUXENTRY(LCD_DATA13, 0,
+ "lcd_data13", "gpmc_a17", NULL, "mcasp0_fsr",
+ "mcasp0_axr3", NULL, NULL, "gpio0_9"),
+ _AM33XX_MUXENTRY(LCD_DATA14, 0,
+ "lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1",
+ NULL, NULL, NULL, "gpio0_10"),
+ _AM33XX_MUXENTRY(LCD_DATA15, 0,
+ "lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",
+ "mcasp0_axr3", NULL, NULL, "gpio0_11"),
+ _AM33XX_MUXENTRY(LCD_VSYNC, 0,
+ "lcd_vsync", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_22"),
+ _AM33XX_MUXENTRY(LCD_HSYNC, 0,
+ "lcd_hsync", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_23"),
+ _AM33XX_MUXENTRY(LCD_PCLK, 0,
+ "lcd_pclk", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_24"),
+ _AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
+ "lcd_ac_bias_en", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_25"),
+ _AM33XX_MUXENTRY(MMC0_DAT3, 0,
+ "mmc0_dat3", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_26"),
+ _AM33XX_MUXENTRY(MMC0_DAT2, 0,
+ "mmc0_dat2", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_27"),
+ _AM33XX_MUXENTRY(MMC0_DAT1, 0,
+ "mmc0_dat1", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_28"),
+ _AM33XX_MUXENTRY(MMC0_DAT0, 0,
+ "mmc0_dat0", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_29"),
+ _AM33XX_MUXENTRY(MMC0_CLK, 0,
+ "mmc0_clk", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_30"),
+ _AM33XX_MUXENTRY(MMC0_CMD, 0,
+ "mmc0_cmd", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio2_31"),
+ _AM33XX_MUXENTRY(MII1_COL, 0,
+ "mii1_col", "rmii2_refclk", "spi1_sclk", NULL,
+ "mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"),
+ _AM33XX_MUXENTRY(MII1_CRS, 0,
+ "mii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda",
+ "mcasp1_aclkx", NULL, NULL, "gpio3_1"),
+ _AM33XX_MUXENTRY(MII1_RXERR, 0,
+ "mii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl",
+ "mcasp1_fsx", NULL, NULL, "gpio3_2"),
+ _AM33XX_MUXENTRY(MII1_TXEN, 0,
+ "mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,
+ "mcasp1_axr0", NULL, "mmc2_cmd", "gpio3_3"),
+ _AM33XX_MUXENTRY(MII1_RXDV, 0,
+ "mii1_rxdv", NULL, "rgmii1_rctl", NULL,
+ "mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", "gpio3_4"),
+ _AM33XX_MUXENTRY(MII1_TXD3, 0,
+ "mii1_txd3", NULL, "rgmii1_td3", NULL,
+ "mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", "gpio0_16"),
+ _AM33XX_MUXENTRY(MII1_TXD2, 0,
+ "mii1_txd2", NULL, "rgmii1_td2", NULL,
+ "mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", "gpio0_17"),
+ _AM33XX_MUXENTRY(MII1_TXD1, 0,
+ "mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
+ "mcasp1_axr1", NULL, "mmc1_cmd", "gpio0_21"),
+ _AM33XX_MUXENTRY(MII1_TXD0, 0,
+ "mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
+ "mcasp1_aclkr", NULL, "mmc1_clk", "gpio0_28"),
+ _AM33XX_MUXENTRY(MII1_TXCLK, 0,
+ "mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7",
+ "mmc1_dat0", NULL, "mcasp0_aclkx", "gpio3_9"),
+ _AM33XX_MUXENTRY(MII1_RXCLK, 0,
+ "mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6",
+ "mmc1_dat1", NULL, "mcasp0_fsx", "gpio3_10"),
+ _AM33XX_MUXENTRY(MII1_RXD3, 0,
+ "mii1_rxd3", NULL, "rgmii1_rd3", "mmc0_dat5",
+ "mmc1_dat2", NULL, "mcasp0_axr0", "gpio2_18"),
+ _AM33XX_MUXENTRY(MII1_RXD2, 0,
+ "mii1_rxd2", NULL, "rgmii1_rd2", "mmc0_dat4",
+ "mmc1_dat3", NULL, "mcasp0_axr1", "gpio2_19"),
+ _AM33XX_MUXENTRY(MII1_RXD1, 0,
+ "mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",
+ "mcasp1_fsr", NULL, "mmc2_clk", "gpio2_20"),
+ _AM33XX_MUXENTRY(MII1_RXD0, 0,
+ "mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
+ "mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", "gpio2_21"),
+ _AM33XX_MUXENTRY(MII1_REFCLK, 0,
+ "rmii1_refclk", NULL, "spi1_cs0", NULL,
+ "mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", "gpio0_29"),
+ _AM33XX_MUXENTRY(MDIO_DATA, 0,
+ "mdio_data", NULL, NULL, NULL,
+ "mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", "gpio0_0"),
+ _AM33XX_MUXENTRY(MDIO_CLK, 0,
+ "mdio_clk", NULL, NULL, NULL,
+ "mmc0_sdwp", "mmc1_clk", "mmc2_clk", "gpio0_1"),
+ _AM33XX_MUXENTRY(SPI0_SCLK, 0,
+ "spi0_sclk", "uart2_rxd", "i2c2_sda", NULL,
+ NULL, NULL, NULL, "gpio0_2"),
+ _AM33XX_MUXENTRY(SPI0_D0, 0,
+ "spi0_d0", "uart2_txd", "i2c2_scl", NULL,
+ NULL, NULL, NULL, "gpio0_3"),
+ _AM33XX_MUXENTRY(SPI0_D1, 0,
+ "spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL,
+ NULL, NULL, NULL, "gpio0_4"),
+ _AM33XX_MUXENTRY(SPI0_CS0, 0,
+ "spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL,
+ NULL, NULL, NULL, "gpio0_5"),
+ _AM33XX_MUXENTRY(SPI0_CS1, 0,
+ "spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",
+ NULL, "mmc0_sdcd", NULL, "gpio0_6"),
+ _AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
+ "ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL,
+ "spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"),
+ _AM33XX_MUXENTRY(UART0_CTSN, 0,
+ "uart0_ctsn", NULL, "d_can1_tx", "i2c1_sda",
+ "spi1_d0", NULL, NULL, "gpio1_8"),
+ _AM33XX_MUXENTRY(UART0_RTSN, 0,
+ "uart0_rtsn", NULL, "d_can1_rx", "i2c1_scl",
+ "spi1_d1", "spi1_cs0", NULL, "gpio1_9"),
+ _AM33XX_MUXENTRY(UART0_RXD, 0,
+ "uart0_rxd", "spi1_cs0", "d_can0_tx", "i2c2_sda",
+ NULL, NULL, NULL, "gpio1_10"),
+ _AM33XX_MUXENTRY(UART0_TXD, 0,
+ "uart0_txd", "spi1_cs1", "d_can0_rx", "i2c2_scl",
+ NULL, NULL, NULL, "gpio1_11"),
+ _AM33XX_MUXENTRY(UART1_CTSN, 0,
+ "uart1_ctsn", NULL, "d_can0_tx", "i2c2_sda",
+ "spi1_cs0", NULL, NULL, "gpio0_12"),
+ _AM33XX_MUXENTRY(UART1_RTSN, 0,
+ "uart1_rtsn", NULL, "d_can0_rx", "i2c2_scl",
+ "spi1_cs1", NULL, NULL, "gpio0_13"),
+ _AM33XX_MUXENTRY(UART1_RXD, 0,
+ "uart1_rxd", "mmc1_sdwp", "d_can1_tx", "i2c1_sda",
+ NULL, "pr1_uart0_rxd_mux1", NULL, "gpio0_14"),
+ _AM33XX_MUXENTRY(UART1_TXD, 0,
+ "uart1_txd", "mmc2_sdwp", "d_can1_rx", "i2c1_scl",
+ NULL, "pr1_uart0_txd_mux1", NULL, "gpio0_15"),
+ _AM33XX_MUXENTRY(I2C0_SDA, 0,
+ "i2c0_sda", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio3_5"),
+ _AM33XX_MUXENTRY(I2C0_SCL, 0,
+ "i2c0_scl", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio3_6"),
+ _AM33XX_MUXENTRY(MCASP0_ACLKX, 0,
+ "mcasp0_aclkx", NULL, NULL, "spi1_sclk",
+ "mmc0_sdcd", NULL, NULL, "gpio3_14"),
+ _AM33XX_MUXENTRY(MCASP0_FSX, 0,
+ "mcasp0_fsx", NULL, NULL, "spi1_d0",
+ "mmc1_sdcd", NULL, NULL, "gpio3_15"),
+ _AM33XX_MUXENTRY(MCASP0_AXR0, 0,
+ "mcasp0_axr0", NULL, NULL, "spi1_d1",
+ "mmc2_sdcd", NULL, NULL, "gpio3_16"),
+ _AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
+ "mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0",
+ NULL, NULL, NULL, "gpio3_17"),
+ _AM33XX_MUXENTRY(MCASP0_ACLKR, 0,
+ "mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx",
+ "mmc0_sdwp", NULL, NULL, "gpio3_18"),
+ _AM33XX_MUXENTRY(MCASP0_FSR, 0,
+ "mcasp0_fsr", NULL, "mcasp0_axr3", "mcasp1_fsx",
+ NULL, "pr1_pru0_pru_r30_5", NULL, "gpio3_19"),
+ _AM33XX_MUXENTRY(MCASP0_AXR1, 0,
+ "mcasp0_axr1", NULL, NULL, "mcasp1_axr0",
+ NULL, NULL, NULL, "gpio3_20"),
+ _AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,
+ "mcasp0_ahclkx", NULL, "mcasp0_axr3", "mcasp1_axr1",
+ NULL, NULL, NULL, "gpio3_21"),
+ _AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
+ "xdma_event_intr0", NULL, NULL, NULL,
+ "spi1_cs1", NULL, NULL, "gpio0_19"),
+ _AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,
+ "xdma_event_intr1", NULL, NULL, "clkout2",
+ NULL, NULL, NULL, "gpio0_20"),
+ _AM33XX_MUXENTRY(WARMRSTN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(PWRONRSTN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(NMIN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(XTALIN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(XTALOUT, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(TMS, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(TDI, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(TDO, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(TCK, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(TRSTN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(EMU0, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio3_7"),
+ _AM33XX_MUXENTRY(EMU1, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio3_8"),
+ _AM33XX_MUXENTRY(RTC_XTALIN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(RTC_XTALOUT, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(RTC_PWRONRSTN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(PMIC_POWER_EN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(EXT_WAKEUP, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(USB0_DRVVBUS, 0,
+ "usb0_drvvbus", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio0_18"),
+ _AM33XX_MUXENTRY(USB1_DRVVBUS, 0,
+ "usb1_drvvbus", NULL, NULL, NULL,
+ NULL, NULL, NULL, "gpio3_13"),
+ _AM33XX_MUXENTRY(DDR_RESETN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_CSN0, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_CKE, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_CK, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_CKN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_CASN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_RASN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_WEN, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_BA0, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_BA1, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_BA2, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A0, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A1, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A2, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A3, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A4, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A5, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A6, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A7, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A8, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A9, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A10, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A11, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A12, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A13, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A14, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_A15, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_ODT, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D0, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D1, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D2, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D3, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D4, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D5, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D6, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D7, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D8, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D9, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D10, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D11, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D12, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D13, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D14, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_D15, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_DQM0, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_DQM1, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_DQS0, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_DQSN0, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_DQS1, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_DQSN1, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_VREF, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(DDR_VTP, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(AIN0, 0,
+ "ain0", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(AIN1, 0,
+ "ain1", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(AIN2, 0,
+ "ain2", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(AIN3, 0,
+ "ain3", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(AIN4, 0,
+ "ain4", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(AIN5, 0,
+ "ain5", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(AIN6, 0,
+ "ain6", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(AIN7, 0,
+ "ain7", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(VREFP, 0,
+ "vrefp", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _AM33XX_MUXENTRY(VREFN, 0,
+ "vrefn", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+int __init am33xx_mux_init(struct omap_board_mux *board_subset)
+{
+ return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE,
+ AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes,
+ NULL, board_subset, NULL);
+}
+#else
+int __init am33xx_mux_init(struct omap_board_mux *board_subset)
+{
+ return 0;
+}
+#endif
diff -PurN linux-stable-23d8c3f/arch/arm/mach-omap2/mux33xx.h kernel_3.2.14_patched/arch/arm/mach-omap2/mux33xx.h
--- linux-stable-23d8c3f/arch/arm/mach-omap2/mux33xx.h 1970-01-01 01:00:00.000000000 +0100
+++ kernel_3.2.14_patched/arch/arm/mach-omap2/mux33xx.h 2012-05-16 12:13:08.000000000 +0100
@@ -0,0 +1,245 @@
+/*
+ * AM33XX pad control register macros.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_MUX335X_H
+#define __ARCH_ARM_MACH_OMAP2_MUX335X_H
+
+#define AM33XX_CONTROL_PADCONF_MUX_PBASE 0x44E10000LU
+
+/* If pin is not defined as input, pull would get disabled.
+ * If defined as input, flags supplied will determine pull on/off.
+ */
+#define AM33XX_MUX(mode0, mux_value) \
+{ \
+ .reg_offset = (AM33XX_CONTROL_PADCONF_##mode0##_OFFSET), \
+ .value = (((mux_value) & AM33XX_INPUT_EN) ? (mux_value)\
+ : ((mux_value) | AM33XX_PULL_DISA)), \
+}
+
+/*
+ * AM33XX CONTROL_PADCONF* register offsets for pin-muxing
+ *
+ * Add AM33XX_CONTROL_PADCONF_MUX_PBASE to these values to get the
+ * absolute addresses. The macro names below are mode-0 names of
+ * corresponding pins.
+ */
+
+#define AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET 0x0800
+#define AM33XX_CONTROL_PADCONF_GPMC_AD1_OFFSET 0x0804
+#define AM33XX_CONTROL_PADCONF_GPMC_AD2_OFFSET 0x0808
+#define AM33XX_CONTROL_PADCONF_GPMC_AD3_OFFSET 0x080C
+#define AM33XX_CONTROL_PADCONF_GPMC_AD4_OFFSET 0x0810
+#define AM33XX_CONTROL_PADCONF_GPMC_AD5_OFFSET 0x0814
+#define AM33XX_CONTROL_PADCONF_GPMC_AD6_OFFSET 0x0818
+#define AM33XX_CONTROL_PADCONF_GPMC_AD7_OFFSET 0x081C
+#define AM33XX_CONTROL_PADCONF_GPMC_AD8_OFFSET 0x0820
+#define AM33XX_CONTROL_PADCONF_GPMC_AD9_OFFSET 0x0824
+#define AM33XX_CONTROL_PADCONF_GPMC_AD10_OFFSET 0x0828
+#define AM33XX_CONTROL_PADCONF_GPMC_AD11_OFFSET 0x082C
+#define AM33XX_CONTROL_PADCONF_GPMC_AD12_OFFSET 0x0830
+#define AM33XX_CONTROL_PADCONF_GPMC_AD13_OFFSET 0x0834
+#define AM33XX_CONTROL_PADCONF_GPMC_AD14_OFFSET 0x0838
+#define AM33XX_CONTROL_PADCONF_GPMC_AD15_OFFSET 0x083C
+#define AM33XX_CONTROL_PADCONF_GPMC_A0_OFFSET 0x0840
+#define AM33XX_CONTROL_PADCONF_GPMC_A1_OFFSET 0x0844
+#define AM33XX_CONTROL_PADCONF_GPMC_A2_OFFSET 0x0848
+#define AM33XX_CONTROL_PADCONF_GPMC_A3_OFFSET 0x084C
+#define AM33XX_CONTROL_PADCONF_GPMC_A4_OFFSET 0x0850
+#define AM33XX_CONTROL_PADCONF_GPMC_A5_OFFSET 0x0854
+#define AM33XX_CONTROL_PADCONF_GPMC_A6_OFFSET 0x0858
+#define AM33XX_CONTROL_PADCONF_GPMC_A7_OFFSET 0x085C
+#define AM33XX_CONTROL_PADCONF_GPMC_A8_OFFSET 0x0860
+#define AM33XX_CONTROL_PADCONF_GPMC_A9_OFFSET 0x0864
+#define AM33XX_CONTROL_PADCONF_GPMC_A10_OFFSET 0x0868
+#define AM33XX_CONTROL_PADCONF_GPMC_A11_OFFSET 0x086C
+#define AM33XX_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x0870
+#define AM33XX_CONTROL_PADCONF_GPMC_WPN_OFFSET 0x0874
+#define AM33XX_CONTROL_PADCONF_GPMC_BEN1_OFFSET 0x0878
+#define AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET 0x087C
+#define AM33XX_CONTROL_PADCONF_GPMC_CSN1_OFFSET 0x0880
+#define AM33XX_CONTROL_PADCONF_GPMC_CSN2_OFFSET 0x0884
+#define AM33XX_CONTROL_PADCONF_GPMC_CSN3_OFFSET 0x0888
+#define AM33XX_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x088C
+#define AM33XX_CONTROL_PADCONF_GPMC_ADVN_ALE_OFFSET 0x0890
+#define AM33XX_CONTROL_PADCONF_GPMC_OEN_REN_OFFSET 0x0894
+#define AM33XX_CONTROL_PADCONF_GPMC_WEN_OFFSET 0x0898
+#define AM33XX_CONTROL_PADCONF_GPMC_BEN0_CLE_OFFSET 0x089C
+#define AM33XX_CONTROL_PADCONF_LCD_DATA0_OFFSET 0x08A0
+#define AM33XX_CONTROL_PADCONF_LCD_DATA1_OFFSET 0x08A4
+#define AM33XX_CONTROL_PADCONF_LCD_DATA2_OFFSET 0x08A8
+#define AM33XX_CONTROL_PADCONF_LCD_DATA3_OFFSET 0x08AC
+#define AM33XX_CONTROL_PADCONF_LCD_DATA4_OFFSET 0x08B0
+#define AM33XX_CONTROL_PADCONF_LCD_DATA5_OFFSET 0x08B4
+#define AM33XX_CONTROL_PADCONF_LCD_DATA6_OFFSET 0x08B8
+#define AM33XX_CONTROL_PADCONF_LCD_DATA7_OFFSET 0x08BC
+#define AM33XX_CONTROL_PADCONF_LCD_DATA8_OFFSET 0x08C0
+#define AM33XX_CONTROL_PADCONF_LCD_DATA9_OFFSET 0x08C4
+#define AM33XX_CONTROL_PADCONF_LCD_DATA10_OFFSET 0x08C8
+#define AM33XX_CONTROL_PADCONF_LCD_DATA11_OFFSET 0x08CC
+#define AM33XX_CONTROL_PADCONF_LCD_DATA12_OFFSET 0x08D0
+#define AM33XX_CONTROL_PADCONF_LCD_DATA13_OFFSET 0x08D4
+#define AM33XX_CONTROL_PADCONF_LCD_DATA14_OFFSET 0x08D8
+#define AM33XX_CONTROL_PADCONF_LCD_DATA15_OFFSET 0x08DC
+#define AM33XX_CONTROL_PADCONF_LCD_VSYNC_OFFSET 0x08E0
+#define AM33XX_CONTROL_PADCONF_LCD_HSYNC_OFFSET 0x08E4
+#define AM33XX_CONTROL_PADCONF_LCD_PCLK_OFFSET 0x08E8
+#define AM33XX_CONTROL_PADCONF_LCD_AC_BIAS_EN_OFFSET 0x08EC
+#define AM33XX_CONTROL_PADCONF_MMC0_DAT3_OFFSET 0x08F0
+#define AM33XX_CONTROL_PADCONF_MMC0_DAT2_OFFSET 0x08F4
+#define AM33XX_CONTROL_PADCONF_MMC0_DAT1_OFFSET 0x08F8
+#define AM33XX_CONTROL_PADCONF_MMC0_DAT0_OFFSET 0x08FC
+#define AM33XX_CONTROL_PADCONF_MMC0_CLK_OFFSET 0x0900
+#define AM33XX_CONTROL_PADCONF_MMC0_CMD_OFFSET 0x0904
+#define AM33XX_CONTROL_PADCONF_MII1_COL_OFFSET 0x0908
+#define AM33XX_CONTROL_PADCONF_MII1_CRS_OFFSET 0x090C
+#define AM33XX_CONTROL_PADCONF_MII1_RXERR_OFFSET 0x0910
+#define AM33XX_CONTROL_PADCONF_MII1_TXEN_OFFSET 0x0914
+#define AM33XX_CONTROL_PADCONF_MII1_RXDV_OFFSET 0x0918
+#define AM33XX_CONTROL_PADCONF_MII1_TXD3_OFFSET 0x091C
+#define AM33XX_CONTROL_PADCONF_MII1_TXD2_OFFSET 0x0920
+#define AM33XX_CONTROL_PADCONF_MII1_TXD1_OFFSET 0x0924
+#define AM33XX_CONTROL_PADCONF_MII1_TXD0_OFFSET 0x0928
+#define AM33XX_CONTROL_PADCONF_MII1_TXCLK_OFFSET 0x092C
+#define AM33XX_CONTROL_PADCONF_MII1_RXCLK_OFFSET 0x0930
+#define AM33XX_CONTROL_PADCONF_MII1_RXD3_OFFSET 0x0934
+#define AM33XX_CONTROL_PADCONF_MII1_RXD2_OFFSET 0x0938
+#define AM33XX_CONTROL_PADCONF_MII1_RXD1_OFFSET 0x093C
+#define AM33XX_CONTROL_PADCONF_MII1_RXD0_OFFSET 0x0940
+#define AM33XX_CONTROL_PADCONF_MII1_REFCLK_OFFSET 0x0944
+#define AM33XX_CONTROL_PADCONF_MDIO_DATA_OFFSET 0x0948
+#define AM33XX_CONTROL_PADCONF_MDIO_CLK_OFFSET 0x094C
+#define AM33XX_CONTROL_PADCONF_SPI0_SCLK_OFFSET 0x0950
+#define AM33XX_CONTROL_PADCONF_SPI0_D0_OFFSET 0x0954
+#define AM33XX_CONTROL_PADCONF_SPI0_D1_OFFSET 0x0958
+#define AM33XX_CONTROL_PADCONF_SPI0_CS0_OFFSET 0x095C
+#define AM33XX_CONTROL_PADCONF_SPI0_CS1_OFFSET 0x0960
+#define AM33XX_CONTROL_PADCONF_ECAP0_IN_PWM0_OUT_OFFSET 0x0964
+#define AM33XX_CONTROL_PADCONF_UART0_CTSN_OFFSET 0x0968
+#define AM33XX_CONTROL_PADCONF_UART0_RTSN_OFFSET 0x096C
+#define AM33XX_CONTROL_PADCONF_UART0_RXD_OFFSET 0x0970
+#define AM33XX_CONTROL_PADCONF_UART0_TXD_OFFSET 0x0974
+#define AM33XX_CONTROL_PADCONF_UART1_CTSN_OFFSET 0x0978
+#define AM33XX_CONTROL_PADCONF_UART1_RTSN_OFFSET 0x097C
+#define AM33XX_CONTROL_PADCONF_UART1_RXD_OFFSET 0x0980
+#define AM33XX_CONTROL_PADCONF_UART1_TXD_OFFSET 0x0984
+#define AM33XX_CONTROL_PADCONF_I2C0_SDA_OFFSET 0x0988
+#define AM33XX_CONTROL_PADCONF_I2C0_SCL_OFFSET 0x098C
+#define AM33XX_CONTROL_PADCONF_MCASP0_ACLKX_OFFSET 0x0990
+#define AM33XX_CONTROL_PADCONF_MCASP0_FSX_OFFSET 0x0994
+#define AM33XX_CONTROL_PADCONF_MCASP0_AXR0_OFFSET 0x0998
+#define AM33XX_CONTROL_PADCONF_MCASP0_AHCLKR_OFFSET 0x099C
+#define AM33XX_CONTROL_PADCONF_MCASP0_ACLKR_OFFSET 0x09A0
+#define AM33XX_CONTROL_PADCONF_MCASP0_FSR_OFFSET 0x09A4
+#define AM33XX_CONTROL_PADCONF_MCASP0_AXR1_OFFSET 0x09A8
+#define AM33XX_CONTROL_PADCONF_MCASP0_AHCLKX_OFFSET 0x09AC
+#define AM33XX_CONTROL_PADCONF_XDMA_EVENT_INTR0_OFFSET 0x09B0
+#define AM33XX_CONTROL_PADCONF_XDMA_EVENT_INTR1_OFFSET 0x09B4
+#define AM33XX_CONTROL_PADCONF_WARMRSTN_OFFSET 0x09B8
+#define AM33XX_CONTROL_PADCONF_PWRONRSTN_OFFSET 0x09BC
+#define AM33XX_CONTROL_PADCONF_NMIN_OFFSET 0x09C0
+#define AM33XX_CONTROL_PADCONF_XTALIN_OFFSET 0x09C4
+#define AM33XX_CONTROL_PADCONF_XTALOUT_OFFSET 0x09C8
+#define AM33XX_CONTROL_PADCONF_TMS_OFFSET 0x09D0
+#define AM33XX_CONTROL_PADCONF_TDI_OFFSET 0x09D4
+#define AM33XX_CONTROL_PADCONF_TDO_OFFSET 0x09D8
+#define AM33XX_CONTROL_PADCONF_TCK_OFFSET 0x09DC
+#define AM33XX_CONTROL_PADCONF_TRSTN_OFFSET 0x09E0
+#define AM33XX_CONTROL_PADCONF_EMU0_OFFSET 0x09E4
+#define AM33XX_CONTROL_PADCONF_EMU1_OFFSET 0x09E8
+#define AM33XX_CONTROL_PADCONF_RTC_XTALIN_OFFSET 0x09EC
+#define AM33XX_CONTROL_PADCONF_RTC_XTALOUT_OFFSET 0x09F0
+#define AM33XX_CONTROL_PADCONF_RTC_PWRONRSTN_OFFSET 0x09F8
+#define AM33XX_CONTROL_PADCONF_EXT_WAKEUP_OFFSET 0x0A00
+#define AM33XX_CONTROL_PADCONF_PMIC_POWER_EN_OFFSET 0x09F4
+#define AM33XX_CONTROL_PADCONF_RTC_KALDO_ENN_OFFSET 0x0A04
+#define AM33XX_CONTROL_PADCONF_USB0_DM_OFFSET 0x0A08
+#define AM33XX_CONTROL_PADCONF_USB0_DP_OFFSET 0x0A0C
+#define AM33XX_CONTROL_PADCONF_USB0_CE_OFFSET 0x0A10
+#define AM33XX_CONTROL_PADCONF_USB0_ID_OFFSET 0x0A14
+#define AM33XX_CONTROL_PADCONF_USB0_VBUS_OFFSET 0x0A18
+#define AM33XX_CONTROL_PADCONF_USB0_DRVVBUS_OFFSET 0x0A1C
+#define AM33XX_CONTROL_PADCONF_USB1_DM_OFFSET 0x0A20
+#define AM33XX_CONTROL_PADCONF_USB1_DP_OFFSET 0x0A24
+#define AM33XX_CONTROL_PADCONF_USB1_CE_OFFSET 0x0A28
+#define AM33XX_CONTROL_PADCONF_USB1_ID_OFFSET 0x0A2C
+#define AM33XX_CONTROL_PADCONF_USB1_VBUS_OFFSET 0x0A30
+#define AM33XX_CONTROL_PADCONF_USB1_DRVVBUS_OFFSET 0x0A34
+#define AM33XX_CONTROL_PADCONF_DDR_RESETN_OFFSET 0x0A38
+#define AM33XX_CONTROL_PADCONF_DDR_CSN0_OFFSET 0x0A3C
+#define AM33XX_CONTROL_PADCONF_DDR_CKE_OFFSET 0x0A40
+#define AM33XX_CONTROL_PADCONF_DDR_CK_OFFSET 0x0A44
+#define AM33XX_CONTROL_PADCONF_DDR_CKN_OFFSET 0x0A48
+#define AM33XX_CONTROL_PADCONF_DDR_CASN_OFFSET 0x0A4C
+#define AM33XX_CONTROL_PADCONF_DDR_RASN_OFFSET 0x0A50
+#define AM33XX_CONTROL_PADCONF_DDR_WEN_OFFSET 0x0A54
+#define AM33XX_CONTROL_PADCONF_DDR_BA0_OFFSET 0x0A58
+#define AM33XX_CONTROL_PADCONF_DDR_BA1_OFFSET 0x0A5C
+#define AM33XX_CONTROL_PADCONF_DDR_BA2_OFFSET 0x0A60
+#define AM33XX_CONTROL_PADCONF_DDR_A0_OFFSET 0x0A64
+#define AM33XX_CONTROL_PADCONF_DDR_A1_OFFSET 0x0A68
+#define AM33XX_CONTROL_PADCONF_DDR_A2_OFFSET 0x0A6C
+#define AM33XX_CONTROL_PADCONF_DDR_A3_OFFSET 0x0A70
+#define AM33XX_CONTROL_PADCONF_DDR_A4_OFFSET 0x0A74
+#define AM33XX_CONTROL_PADCONF_DDR_A5_OFFSET 0x0A78
+#define AM33XX_CONTROL_PADCONF_DDR_A6_OFFSET 0x0A7C
+#define AM33XX_CONTROL_PADCONF_DDR_A7_OFFSET 0x0A80
+#define AM33XX_CONTROL_PADCONF_DDR_A8_OFFSET 0x0A84
+#define AM33XX_CONTROL_PADCONF_DDR_A9_OFFSET 0x0A88
+#define AM33XX_CONTROL_PADCONF_DDR_A10_OFFSET 0x0A8C
+#define AM33XX_CONTROL_PADCONF_DDR_A11_OFFSET 0x0A90
+#define AM33XX_CONTROL_PADCONF_DDR_A12_OFFSET 0x0A94
+#define AM33XX_CONTROL_PADCONF_DDR_A13_OFFSET 0x0A98
+#define AM33XX_CONTROL_PADCONF_DDR_A14_OFFSET 0x0A9C
+#define AM33XX_CONTROL_PADCONF_DDR_A15_OFFSET 0x0AA0
+#define AM33XX_CONTROL_PADCONF_DDR_ODT_OFFSET 0x0AA4
+#define AM33XX_CONTROL_PADCONF_DDR_D0_OFFSET 0x0AA8
+#define AM33XX_CONTROL_PADCONF_DDR_D1_OFFSET 0x0AAC
+#define AM33XX_CONTROL_PADCONF_DDR_D2_OFFSET 0x0AB0
+#define AM33XX_CONTROL_PADCONF_DDR_D3_OFFSET 0x0AB4
+#define AM33XX_CONTROL_PADCONF_DDR_D4_OFFSET 0x0AB8
+#define AM33XX_CONTROL_PADCONF_DDR_D5_OFFSET 0x0ABC
+#define AM33XX_CONTROL_PADCONF_DDR_D6_OFFSET 0x
@17twenty
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You will also need to download the am335x-pm-firmware.bin from http://arago-project.org/git/projects/?p=am33x-cm3.git;a=tree;f=bin;h=dc6e79180b8c468832e684d631818af31448bd81;hb=HEAD

It goes in as /firmware/am335x-pm-firmware.bin

What a pain!

@sneak
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sneak commented May 25, 2012

Thanks for posting this!

@17twenty
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No problems. I even integrated a beaglebone_defconfig for it. I'm really surprised this wasn't done by default - especially when the .pc and patches folders were added to the kernel :-/

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