sub module call task.

gistfile1.v

module tb; 
  reg      r_a=0;
  reg[1:0] r_b=0;

  sub_m sub_m_inst(.in(r_a));

  initial begin
    sub_m_inst.task1;
    sub_m_inst.task2(r_a);
    sub_m_inst.task3(r_a, r_b); $display("------ Call Task3 output = %d", r_b);
    sub_m_inst.task4(r_a, r_b); $display("------ Call Task4 output = %d", r_b);
  end 

endmodule

module sub_m(input reg in);

  task task1;
    $display("--- Call Task1 ---");
  endtask
  
  task task2(input a); 
    $display("--- Call Task2 input = %d ---", a); 
  endtask

  task task3(input a, output b); 
    begin
      $display("--- Call Task3 input = %d ---", a); 
      b = 1;
    end 
  endtask

  task task4;
    input a; output reg[1:0] b;
    begin
      $display("--- Call Task4 input = %d ---", a); 
      b = 2;
    end 

endmodule

Makefile

RTL=tb.v

run: work compile sim

work:
>   vlib work

compile:
>   vlog ${RTL}

sim:
>   vsim -c -L work tb -do "run -all; quit"

clean:
>   rm -rf work transcript vsim.wlf