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@Kocha
Kocha / systemverilog.vim
Last active August 3, 2022 13:00
Improved indent/systemverilog.vim
" Vim indent file
" Language: SystemVerilog
" Maintainer: kocha <kocha.lsifrontend@gmail.com>
" Last Change: 05-Feb-2017 by Bilal Wasim
" 2022 April: b:undo_indent added by Doug Kearns
" 03-Aug-2022 Improved indent
" Only load this indent file when no other was loaded.
if exists("b:did_indent")
finish
@Kocha
Kocha / gist:7571223
Created November 20, 2013 21:18
Verilog HDL / signed, unsigned
module tb;
reg signed [4:0] s_a, s_b;
reg [4:0] us_a, us_b;
reg signed [9:0] s_mul;
reg [9:0] us_mul;
initial begin
s_a = -1; s_b = 10;
us_a = 'b11111; us_b = 'd10;
@Kocha
Kocha / ams_waves.vcd
Created July 4, 2013 13:04
Try TUV_AMS_LIBRARY - PLL
$date
Thu Jul 4 21:47:09 2013
$end
$version
SystemC AMS 1.0 --- 1.0BETA1 --- Jun 8 2012 06:40:50
$end
$timescale
@Kocha
Kocha / scv_gcc44_32bit.patch
Created February 8, 2013 15:19
SystemC Verification Library install at gcc4.4.0 (32bit) patch.
--- a/configure
+++ configure
@@ -5637,37 +5637,38 @@ EOF
/* So define it here empty. Namespaces are extensible, so this is harmless. */
namespace std {}
using namespace std;
-#include <string>
-#include <stdio.h>
-#include <strstream.h>
+#include <cstring>
@Kocha
Kocha / verilog.vim
Created May 24, 2012 21:27
verilog.vim folding task and function
" Install:This file ~/.vim/after/syntax/verilog.vim
set foldmethod=expr
set foldexpr=MyFoldExpr(v:lnum)
function! MyFoldExpr(line)
let str = getline(a:line)
if str =~ '^\s*task\s' || str =~ '^\s*function\s'
return '>1'
elseif str =~ '^\s*endtask' || str =~ '^\s*endfunction'
return '<1'
else
@Kocha
Kocha / automatic_tb_dut_makefike.diff
Created March 12, 2012 14:46
automatic_tb_dut Makefile patch
--- org/sim/Makefile 2012-03-02 22:31:34.046233486 +0900
+++ modify/sim/Makefile 2012-03-12 23:41:46.189894233 +0900
@@ -1,12 +1,14 @@
AOP_HOME = ../
CODE_KIND ?= "vifs"
+INCULDE_DIR = /home/kocha/tools/modelsim/11.1sp1/modelsim_ase/include
-all: work compile_aop compile_smp compile_vip compile_dut compile_integration create_stub sim
+all: work compile_aop compile_smp compile_vip compile_dut compile_integration compile_dpi create_stub sim
@Kocha
Kocha / Makefile
Created March 5, 2012 01:15
sub module call task.
RTL=tb.v
run: work compile sim
work:
> vlib work
compile:
> vlog ${RTL}
@Kocha
Kocha / Makefile
Created March 1, 2012 21:38
Simple Makefile for SystemC-2.3_pub_rev
SYSTEMC_HOME = ### input SystemC install path ###
TARGET_ARCH = linux
SYSTEMC_INC_DIR = $(SYSTEMC_HOME)/include
SYSTEMC_LIB_DIR = $(SYSTEMC_HOME)/lib-$(TARGET_ARCH)
# LIBTOOL Setting
SHELL = /bin/bash
LIBTOOL_DIR = #### input libtool install path ###
LIBTOOL = $(SHELL) $(LIBTOOL_DIR)/libtool