sn32_spi.h

typedef struct {                      /*!< (@ 0x4001C000) SN_SPIn Structure                              */
  union {                             /*!< (@ 0x00000000) Offset:0x00 SPIn Control register 0            */
    __IOM   uint32_t raw;             /* raw access to CTRL0 register */
    struct {
      __IOM uint32_t SPIEN      : 1;  /* SPI enable bit */
      __IOM uint32_t LOOPBACK   : 1;  /* Loopback mode enable bit */
      __IOM uint32_t SDODIS     : 1;  /* Slave data output disable bit */
      __IOM uint32_t MS         : 1;  /* Master/Slave selection bit */
      __IOM uint32_t FORMAT     : 1;  /* Interface format */
      __IM  uint32_t            : 1;  /* Reserved */
      __OM  uint32_t FRESET     : 2;  /* SPI FSM and FIFO reset bit */
      __IOM uint32_t DL         : 4;  /* Data length */
      __IOM uint32_t TXFIFOTH   : 3;  /* RX FIFO threshold level */
      __IOM uint32_t RXFIFOTH   : 3;  /* TX FIFO threshold level */
      __IOM uint32_t SELDIS     : 1;  /* Auto-SEL disable bit */
      __IM  uint32_t            : 13; /* Reserved */
    };
  } CTRL0;

  union {                             /*!< (@ 0x00000004) Offset:0x04 SPIn Control register 1            */
    __IOM   uint32_t raw;             /* raw access to CTRL1 register */
    struct {
      __IOM uint32_t MLSB       : 1;  /* MSB/LSB selection bit */
      __IOM uint32_t CPOL       : 1;  /* Clock polarity selection bit */
      __IOM uint32_t CPHA       : 1;  /* Clock phase for edge sampling */
      __IM  uint32_t            : 29; /* Reserved */
    };
  } CTRL1;

  __IOM     uint32_t CLKDIV;          /*!< (@ 0x00000008) Offset:0x08 SPIn Clock Divider register        */

  union {                             /*!< (@ 0x0000000C) Offset:0x0C SPIn Status register               */
    __IM    uint32_t raw;
    struct {
      __IM  uint32_t TX_EMPTY   : 1;  /* TX FIFO empty flag */
      __IM  uint32_t TX_FULL    : 1;  /* TX FIFO full flag */
      __IM  uint32_t RX_EMPTY   : 1;  /* RX FIFO empty flag */
      __IM  uint32_t RX_FULL    : 1;  /* RX FIFO full flag */
      __IM  uint32_t BUSY       : 1;  /* SPI busy flag */
      __IM  uint32_t TXFIFOTHF  : 1;  /* TX FIFO threshold flag */
      __IM  uint32_t RXFIFOTHF  : 1;  /* RX FIFO threshold flag */
      __IM  uint32_t            : 25; /* Reserved */
    };
  } STAT;

  union {                               /*!< (@ 0x00000010) Offset:0x10 SPIn Interrupt Enable register     */
    __IOM   uint32_t raw;
    struct {
      __IOM uint32_t RXOVFIE    : 1;
      __IOM uint32_t RXTOIE     : 1;
      __IOM uint32_t RXFIFOTHIE : 1;
      __IOM uint32_t TXFIFOTHIE : 1;
      __IM  uint32_t            : 28;
    };
  } IE;

  union {                               /*!< (@ 0x00000014) Offset:0x14 SPIn Raw Interrupt Status register */
    __IM    uint32_t raw;
    struct {
      __IM  uint32_t RXOVFIF    : 1;
      __IM  uint32_t RXTOIF     : 1;
      __IM  uint32_t RXFIFOTHIF : 1;
      __IM  uint32_t TXFIFOTHIF : 1;
      __IM  uint32_t            : 28;
    };
  } RIS;

  union {                               /*!< (@ 0x00000018) Offset:0x18 SPIn Interrupt Clear register      */
    __IOM   uint32_t raw;
    struct {
      __IOM uint32_t RXOVFIC    : 1;
      __IOM uint32_t RXTOIC     : 1;
      __IOM uint32_t RXFIFOTHIC : 1;
      __IOM uint32_t TXFIFOTHIC : 1;
      __IM  uint32_t            : 28;
    };
  } IC;

  __IOM     uint32_t DATA;               /*!< (@ 0x0000001C) Offset:0x1C SPIn Data register                 */
  __IOM     uint32_t DFDLY;              /*!< (@ 0x00000020) Offset:0x20 SPIn Data Fetch register           */
} sn32_spi_t;                           /*!< Size = 36 (0x20)