The code we wrote as a class together on the projector today

cpu-from-class.v

`timescale 1ps/1ps

module main();

    initial begin
        $dumpfile("cpu.vcd");
        $dumpvars(0,main);
    end

    // clock
    wire clk;
    clock c0(clk);

    reg halt = 0;

    counter ctr(halt,clk);

    // forward
    wire wb_jumping;
    wire [15:0] wb_target;
    
    // F0 //
    reg f0_v = 1;
    reg [15:0] f0_pc = 0;

    always @(posedge clk) begin
	// f0_v <= 1; 
	// //could set this to zero when you need to stall
	
	f0_pc <= wb_jumping ? wb_target : f0_pc + 16'h2;
	//forward declaration
    end

    // F1 //

    reg f1_v = 0;
    reg [15:0] f1_pc;

    always @(posedge clk) begin
	f1_v <= f0_v & (~ wb_jumping); 
//jumps are handled here because wb might invalidate f0_v/pc
	f1_pc <= f0-pc;
    end

    // D //
    wire [15:0] d_inst;
    reg 	d_v = 0;
    reg [15:0] 	d_pc;
    always @(posedge clk) begin
	d_v <= f1_v & (~ wb_jumping); 
// flush pipeline with the wb_jumping
	d_pc <= f1_c;
    end

    // incomplete wb //
    wire [15:0]wb_ldata;
    reg [15:0] wb_result;
    reg        wb_v = 0;
    reg [15:0] wb_inst;

    assign wb_jumping = wb_v & wb_isJump & wb_conditionIsMet;
// plug in values here for wb_conditionIsMet, isJump, etc. 
    
    always @posedge clk) begin
	wb_result <= m_result;
	wb_v <= m_v & (~ wb_jumping); 
//this is based on previous pipelined value of wb_jumping
	wb_inst <= m_inst;
    end
    
    
    // memory //
    mem mem(clk,
            f0_pc[15:1],d_inst,
	    ,wb_ldata,
	    ,,);

    regs regs(clk,
	      regs_raddr1,regs_rdata1_,
	      regs_raddr2,regs_rdata2_,
	      regs_wen,regs_waddr,regs_wdata);


endmodule