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jit_dump_example
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****** START compiling ConsoleApplication.Program:Main(ref) (MethodHash=1499abcb) | |
Generating code for Unix x64 | |
OPTIONS: compCodeOpt = BLENDED_CODE | |
OPTIONS: compDbgCode = true | |
OPTIONS: compDbgInfo = true | |
OPTIONS: compDbgEnC = false | |
OPTIONS: compProcedureSplitting = false | |
OPTIONS: compProcedureSplittingEH = false | |
OPTIONS: Stack probing is DISABLED | |
IL to import: | |
IL_0000 00 nop | |
IL_0001 16 ldc.i4.0 | |
IL_0002 0a stloc.0 | |
IL_0003 2b 0d br.s 13 (IL_0012) | |
IL_0005 00 nop | |
IL_0006 06 ldloc.0 | |
IL_0007 28 0c 00 00 0a call 0xA00000C | |
IL_000c 00 nop | |
IL_000d 00 nop | |
IL_000e 06 ldloc.0 | |
IL_000f 17 ldc.i4.1 | |
IL_0010 58 add | |
IL_0011 0a stloc.0 | |
IL_0012 06 ldloc.0 | |
IL_0013 19 ldc.i4.3 | |
IL_0014 fe 04 clt | |
IL_0016 0b stloc.1 | |
IL_0017 07 ldloc.1 | |
IL_0018 2d eb brtrue.s -21 (IL_0005) | |
IL_001a 2a ret | |
Set preferred register for V00 to [rdi] | |
Arg #0 passed in register(s) rdi | |
; Initial local variable assignments | |
; | |
; V00 arg0 ref | |
; V01 loc0 int | |
; V02 loc1 bool | |
*************** In compInitDebuggingInfo() for ConsoleApplication.Program:Main(ref) | |
getVars() returned cVars = 0, extendOthers = true | |
info.compVarScopesCount = 3 | |
VarNum LVNum Name Beg End | |
0: 00h 00h V00 arg0 000h 01Bh | |
1: 01h 01h V01 loc0 000h 01Bh | |
2: 02h 02h V02 loc1 000h 01Bh | |
New Basic Block BB01 [00000000024701F8] created. | |
New scratch BB01 | |
Debuggable code - Add new BB01 to perform initialization of variables [024701F8] | |
info.compStmtOffsetsCount = 0 | |
info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) | |
*************** In fgFindBasicBlocks() for ConsoleApplication.Program:Main(ref) | |
Jump targets: | |
IL_0005 | |
IL_0012 | |
New Basic Block BB02 [0000000002470470] created. | |
BB02 [000..005) | |
New Basic Block BB03 [0000000002470580] created. | |
BB03 [005..012) | |
New Basic Block BB04 [0000000002470690] created. | |
BB04 [012..01A) | |
New Basic Block BB05 [00000000024707A0] created. | |
BB05 [01A..01B) | |
CLFLG_MINOPT set for method ConsoleApplication.Program:Main(ref) | |
IL Code Size,Instr 27, 20, Basic Block count 5, Local Variable Num,Ref count 3, 7 for method ConsoleApplication.Program:Main(ref) | |
IL Code Size,Instr 27, 20, Basic Block count 5, Local Variable Num,Ref count 3, 7 for method ConsoleApplication.Program:Main(ref) | |
OPTIONS: opts.MinOpts() == true | |
Basic block list for 'ConsoleApplication.Program:Main(ref)' | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal | |
BB02 [0000000002470470] 1 1 [000..005)-> BB04 (always) | |
BB03 [0000000002470580] 1 1 [005..012) bwd | |
BB04 [0000000002470690] 2 1 [012..01A)-> BB03 ( cond ) bwd | |
BB05 [00000000024707A0] 1 1 [01A..01B) (return) | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In impImport() for ConsoleApplication.Program:Main(ref) | |
Marking leading BBF_INTERNAL block BB01 as BBF_IMPORTED | |
impImportBlockPending for BB02 | |
Importing BB02 (PC=000) of 'ConsoleApplication.Program:Main(ref)' | |
[ 0] 0 (0x000) nop | |
[000004] ------------ * stmtExpr void (IL 0x000... ???) | |
[000003] ------------ \--* no_op void | |
[ 0] 1 (0x001) ldc.i4.0 0 | |
[ 1] 2 (0x002) stloc.0 | |
[000008] ------------ * stmtExpr void (IL 0x001... ???) | |
[000005] ------------ | /--* const int 0 | |
[000007] -A---------- \--* = int | |
[000006] D------N---- \--* lclVar int V01 loc0 | |
[ 0] 3 (0x003) br.s | |
[000010] ------------ * stmtExpr void (IL 0x003... ???) | |
[000009] ------------ \--* nop void | |
impImportBlockPending for BB04 | |
Importing BB04 (PC=018) of 'ConsoleApplication.Program:Main(ref)' | |
[ 0] 18 (0x012) ldloc.0 | |
[ 1] 19 (0x013) ldc.i4.3 3 | |
[ 2] 20 (0x014) clt | |
[ 1] 22 (0x016) stloc.1 | |
[000017] ------------ * stmtExpr void (IL 0x012... ???) | |
[000013] ------------ | /--* const int 3 | |
[000014] ------------ | /--* < int | |
[000012] ------------ | | \--* lclVar int V01 loc0 | |
[000016] -A---------- \--* = int | |
[000015] D------N---- \--* lclVar int V02 loc1 | |
[ 0] 23 (0x017) ldloc.1 | |
[ 1] 24 (0x018) brtrue.s | |
[000022] ------------ * stmtExpr void (IL 0x017... ???) | |
[000021] ------------ \--* jmpTrue void | |
[000019] ------------ | /--* const int 0 | |
[000020] ------------ \--* != int | |
[000018] ------------ \--* lclVar int V02 loc1 | |
impImportBlockPending for BB05 | |
impImportBlockPending for BB03 | |
Importing BB03 (PC=005) of 'ConsoleApplication.Program:Main(ref)' | |
[ 0] 5 (0x005) nop | |
[000025] ------------ * stmtExpr void (IL 0x005... ???) | |
[000024] ------------ \--* no_op void | |
[ 0] 6 (0x006) ldloc.0 | |
[ 1] 7 (0x007) call 0A00000C | |
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 | |
[000029] ------------ * stmtExpr void (IL 0x006... ???) | |
[000027] --C-G------- \--* call void System.Console.WriteLine | |
[000026] ------------ arg0 \--* lclVar int V01 loc0 | |
[ 0] 12 (0x00c) nop | |
[000031] ------------ * stmtExpr void (IL 0x00C... ???) | |
[000030] ------------ \--* no_op void | |
[ 0] 13 (0x00d) nop | |
[000033] ------------ * stmtExpr void (IL 0x00D... ???) | |
[000032] ------------ \--* no_op void | |
[ 0] 14 (0x00e) ldloc.0 | |
[ 1] 15 (0x00f) ldc.i4.1 1 | |
[ 2] 16 (0x010) add | |
[ 1] 17 (0x011) stloc.0 | |
[000039] ------------ * stmtExpr void (IL 0x00E... ???) | |
[000035] ------------ | /--* const int 1 | |
[000036] ------------ | /--* + int | |
[000034] ------------ | | \--* lclVar int V01 loc0 | |
[000038] -A---------- \--* = int | |
[000037] D------N---- \--* lclVar int V01 loc0 | |
impImportBlockPending for BB04 | |
Importing BB05 (PC=026) of 'ConsoleApplication.Program:Main(ref)' | |
[ 0] 26 (0x01a) ret | |
[000042] ------------ * stmtExpr void (IL 0x01A... ???) | |
[000041] ------------ \--* return void | |
New BlockSet epoch 1, # of blocks (including unused BB00): 6, bitset array size: 1 (short) | |
*************** In fgMorph() | |
*************** After fgAddInternal() | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal | |
BB02 [0000000002470470] 1 1 [000..005)-> BB04 (always) i | |
BB03 [0000000002470580] 1 1 [005..012) i bwd | |
BB04 [0000000002470690] 2 1 [012..01A)-> BB03 ( cond ) i bwd | |
BB05 [00000000024707A0] 1 1 [01A..01B) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** Exception Handling table is empty | |
*************** In fgDebugCheckBBlist | |
*************** In fgDebugCheckBBlist | |
*************** In fgMarkImplicitByRefs() | |
*************** In fgPromoteStructs() | |
*************** In fgMarkAddressExposedLocals() | |
*************** In fgMorphBlocks() | |
Morphing BB01 of 'ConsoleApplication.Program:Main(ref)' | |
fgMorphTree BB01, stmt 1 (before) | |
[000000] ------------ * nop void | |
fgMorphTree BB01, stmt 2 (before) | |
[000048] ------------ then /--* nop void | |
[000049] --C-G------- /--* colon void | |
[000047] --C-G------- else | \--* call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
[000050] --C-G------- * qmark void | |
[000045] ------------ | /--* const int 0 | |
[000046] Q----------- if \--* == int | |
[000044] ------------ \--* indir int | |
[000043] ------------ \--* const(h) long 0x7f95ea870610 token | |
argSlots=0, preallocatedArgCount=0, nextSlotNum=0, lvaOutgoingArgSpaceSize=0 | |
Morphing BB02 of 'ConsoleApplication.Program:Main(ref)' | |
fgMorphTree BB02, stmt 3 (before) | |
[000003] ------------ * no_op void | |
fgMorphTree BB02, stmt 4 (before) | |
[000005] ------------ /--* const int 0 | |
[000007] -A---------- * = int | |
[000006] D------N---- \--* lclVar int V01 loc0 | |
fgMorphTree BB02, stmt 5 (before) | |
[000009] ------------ * nop void | |
Morphing BB03 of 'ConsoleApplication.Program:Main(ref)' | |
fgMorphTree BB03, stmt 6 (before) | |
[000024] ------------ * no_op void | |
fgMorphTree BB03, stmt 7 (before) | |
[000027] --C-G------- * call void System.Console.WriteLine | |
[000026] ------------ arg0 \--* lclVar int V01 loc0 | |
argSlots=1, preallocatedArgCount=0, nextSlotNum=0, lvaOutgoingArgSpaceSize=0 | |
Sorting the arguments: | |
Deferred argument ('rdi'): | |
[000026] -----+------ * lclVar int V01 loc0 | |
Replaced with placeholder node: | |
[000052] ----------L- * argPlace int | |
Shuffled argument table: rdi | |
fgArgTabEntry[arg 0, rdi, regs=1, align=1, lateArgInx=0, processed] | |
fgMorphTree BB03, stmt 7 (after) | |
[000027] --C-G+------ * call void System.Console.WriteLine | |
[000026] -----+------ arg0 in rdi \--* lclVar int V01 loc0 | |
fgMorphTree BB03, stmt 8 (before) | |
[000030] ------------ * no_op void | |
fgMorphTree BB03, stmt 9 (before) | |
[000032] ------------ * no_op void | |
fgMorphTree BB03, stmt 10 (before) | |
[000035] ------------ /--* const int 1 | |
[000036] ------------ /--* + int | |
[000034] ------------ | \--* lclVar int V01 loc0 | |
[000038] -A---------- * = int | |
[000037] D------N---- \--* lclVar int V01 loc0 | |
Morphing BB04 of 'ConsoleApplication.Program:Main(ref)' | |
fgMorphTree BB04, stmt 11 (before) | |
[000013] ------------ /--* const int 3 | |
[000014] ------------ /--* < int | |
[000012] ------------ | \--* lclVar int V01 loc0 | |
[000016] -A---------- * = int | |
[000015] D------N---- \--* lclVar int V02 loc1 | |
fgMorphTree BB04, stmt 12 (before) | |
[000021] ------------ * jmpTrue void | |
[000019] ------------ | /--* const int 0 | |
[000020] ------------ \--* != int | |
[000018] ------------ \--* lclVar int V02 loc1 | |
Morphing BB05 of 'ConsoleApplication.Program:Main(ref)' | |
fgMorphTree BB05, stmt 13 (before) | |
[000041] ------------ * return void | |
Expanding top-level qmark in BB01 (before) | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB02} | |
***** BB01, stmt 1 | |
[000001] ------------ * stmtExpr void (IL ???... ???) | |
[000000] -----+------ \--* nop void | |
***** BB01, stmt 2 | |
[000051] ------------ * stmtExpr void (IL ???... ???) | |
[000048] -----+?----- then | /--* nop void | |
[000049] --C-G+?----- | /--* colon void | |
[000047] --C-G+?----- else | | \--* call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
[000050] --C-G+------ \--* qmark void | |
[000045] -----+------ | /--* const int 0 | |
[000046] J----+-N---- if \--* == int | |
[000044] -----+------ \--* indir int | |
[000043] -----+------ \--* const(h) long 0x7f95ea870610 token | |
------------------------------------------------------------------------------------------------------------------- | |
New Basic Block BB06 [0000000002473240] created. | |
BB02 previous predecessor was BB01, now is BB06 | |
New Basic Block BB07 [0000000002473350] created. | |
New Basic Block BB08 [0000000002473460] created. | |
Removing statement [000051] in BB01 as useless: | |
[000051] ------------ * stmtExpr void (IL ???... ???) | |
[000048] -----+?----- then | /--* nop void | |
[000049] --C-G+?----- | /--* colon void | |
[000047] --C-G+?----- else | | \--* call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
[000050] --C-G+------ \--* qmark void | |
N003 ( 1, 1) [000045] ------------ | /--* const int 0 | |
N004 ( 7, 14) [000046] J------N---- if \--* == int | |
N002 ( 5, 12) [000044] ------------ \--* indir int | |
N001 ( 3, 10) [000043] ------------ \--* const(h) long 0x7f95ea870610 token | |
Expanding top-level qmark in BB01 (after) | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal | |
BB07 [0000000002473350] 1 1 [???..???)-> BB06 ( cond ) internal | |
BB08 [0000000002473460] 1 0.5 [???..???) internal | |
BB06 [0000000002473240] 2 1 [???..???) i internal label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB07} | |
***** BB01, stmt 1 | |
[000001] ------------ * stmtExpr void (IL ???... ???) | |
[000000] -----+------ \--* nop void | |
------------ BB07 [???..???) -> BB06 (cond), preds={} succs={BB08,BB06} | |
***** BB07, stmt 2 | |
( 9, 16) [000055] ------------ * stmtExpr void (IL ???... ???) | |
N005 ( 9, 16) [000054] ------------ \--* jmpTrue void | |
N003 ( 1, 1) [000045] ------------ | /--* const int 0 | |
N004 ( 7, 14) [000046] J------N---- \--* == int | |
N002 ( 5, 12) [000044] ------------ \--* indir int | |
N001 ( 3, 10) [000043] ------------ \--* const(h) long 0x7f95ea870610 token | |
------------ BB08 [???..???), preds={} succs={BB06} | |
***** BB08, stmt 3 | |
( 14, 5) [000056] ------------ * stmtExpr void (IL ???... ???) | |
N001 ( 14, 5) [000047] --C-G-?----- \--* call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
------------ BB06 [???..???), preds={} succs={BB02} | |
------------------------------------------------------------------------------------------------------------------- | |
Renumbering the basic blocks for fgComputePred | |
*************** Before renumbering the basic blocks | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal | |
BB07 [0000000002473350] 1 1 [???..???)-> BB06 ( cond ) internal | |
BB08 [0000000002473460] 1 0.5 [???..???) internal | |
BB06 [0000000002473240] 2 1 [???..???) i internal label target | |
BB02 [0000000002470470] 1 1 [000..005)-> BB04 (always) i | |
BB03 [0000000002470580] 1 1 [005..012) i gcsafe bwd | |
BB04 [0000000002470690] 2 1 [012..01A)-> BB03 ( cond ) i bwd | |
BB05 [00000000024707A0] 1 1 [01A..01B) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** Exception Handling table is empty | |
Renumber BB07 to BB02 | |
Renumber BB08 to BB03 | |
Renumber BB06 to BB04 | |
Renumber BB02 to BB05 | |
Renumber BB03 to BB06 | |
Renumber BB04 to BB07 | |
Renumber BB05 to BB08 | |
*************** After renumbering the basic blocks | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal | |
BB02 [0000000002473350] 1 1 [???..???)-> BB04 ( cond ) internal | |
BB03 [0000000002473460] 1 0.5 [???..???) internal | |
BB04 [0000000002473240] 2 1 [???..???) i internal label target | |
BB05 [0000000002470470] 1 1 [000..005)-> BB07 (always) i | |
BB06 [0000000002470580] 1 1 [005..012) i gcsafe bwd | |
BB07 [0000000002470690] 2 1 [012..01A)-> BB06 ( cond ) i bwd | |
BB08 [00000000024707A0] 1 1 [01A..01B) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** Exception Handling table is empty | |
New BlockSet epoch 2, # of blocks (including unused BB00): 9, bitset array size: 1 (short) | |
*************** In fgComputePreds() | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal | |
BB02 [0000000002473350] 1 1 [???..???)-> BB04 ( cond ) internal | |
BB03 [0000000002473460] 1 0.5 [???..???) internal | |
BB04 [0000000002473240] 2 1 [???..???) i internal label target | |
BB05 [0000000002470470] 1 1 [000..005)-> BB07 (always) i | |
BB06 [0000000002470580] 1 1 [005..012) i gcsafe bwd | |
BB07 [0000000002470690] 2 1 [012..01A)-> BB06 ( cond ) i bwd | |
BB08 [00000000024707A0] 1 1 [01A..01B) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** After fgComputePreds() | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In fgComputeEdgeWeights() | |
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights | |
*************** In fgCreateFunclets() | |
After fgCreateFunclets() | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** Exception Handling table is empty | |
*************** In fgDebugCheckBBlist | |
*************** In Allocate Objects | |
Trees before Allocate Objects | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB02} | |
***** BB01, stmt 1 | |
[000001] ------------ * stmtExpr void (IL ???... ???) | |
[000000] -----+------ \--* nop void | |
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
***** BB02, stmt 2 | |
( 9, 16) [000055] ------------ * stmtExpr void (IL ???... ???) | |
N005 ( 9, 16) [000054] ------------ \--* jmpTrue void | |
N003 ( 1, 1) [000045] ------------ | /--* const int 0 | |
N004 ( 7, 14) [000046] J------N---- \--* == int | |
N002 ( 5, 12) [000044] ------------ \--* indir int | |
N001 ( 3, 10) [000043] ------------ \--* const(h) long 0x7f95ea870610 token | |
------------ BB03 [???..???), preds={BB02} succs={BB04} | |
***** BB03, stmt 3 | |
( 14, 5) [000056] ------------ * stmtExpr void (IL ???... ???) | |
N001 ( 14, 5) [000047] --C-G-?----- \--* call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
------------ BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
***** BB05, stmt 4 | |
[000004] ------------ * stmtExpr void (IL 0x000...0x000) | |
[000003] -----+------ \--* no_op void | |
***** BB05, stmt 5 | |
[000008] ------------ * stmtExpr void (IL 0x001...0x002) | |
[000005] -----+------ | /--* const int 0 | |
[000007] -A---+------ \--* = int | |
[000006] D----+-N---- \--* lclVar int V01 loc0 | |
***** BB05, stmt 6 | |
[000010] ------------ * stmtExpr void (IL 0x003...0x003) | |
[000009] -----+------ \--* nop void | |
------------ BB06 [005..012), preds={BB07} succs={BB07} | |
***** BB06, stmt 7 | |
[000025] ------------ * stmtExpr void (IL 0x005...0x005) | |
[000024] -----+------ \--* no_op void | |
***** BB06, stmt 8 | |
[000029] ------------ * stmtExpr void (IL 0x006...0x00C) | |
[000027] --C-G+------ \--* call void System.Console.WriteLine | |
[000026] -----+------ arg0 in rdi \--* lclVar int V01 loc0 | |
***** BB06, stmt 9 | |
[000031] ------------ * stmtExpr void (IL 0x00C... ???) | |
[000030] -----+------ \--* no_op void | |
***** BB06, stmt 10 | |
[000033] ------------ * stmtExpr void (IL 0x00D...0x00D) | |
[000032] -----+------ \--* no_op void | |
***** BB06, stmt 11 | |
[000039] ------------ * stmtExpr void (IL 0x00E...0x011) | |
[000035] -----+------ | /--* const int 1 | |
[000036] -----+------ | /--* + int | |
[000034] -----+------ | | \--* lclVar int V01 loc0 | |
[000038] -A---+------ \--* = int | |
[000037] D----+-N---- \--* lclVar int V01 loc0 | |
------------ BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
***** BB07, stmt 12 | |
[000017] ------------ * stmtExpr void (IL 0x012...0x016) | |
[000013] -----+------ | /--* const int 3 | |
[000014] -----+------ | /--* < int | |
[000012] -----+------ | | \--* lclVar int V01 loc0 | |
[000016] -A---+------ \--* = int | |
[000015] D----+-N---- \--* lclVar int V02 loc1 | |
***** BB07, stmt 13 | |
[000022] ------------ * stmtExpr void (IL 0x017...0x018) | |
[000021] -----+------ \--* jmpTrue void | |
[000019] -----+------ | /--* const int 0 | |
[000020] J----+-N---- \--* != int | |
[000018] -----+------ \--* lclVar int V02 loc1 | |
------------ BB08 [01A..01B) (return), preds={BB07} succs={} | |
***** BB08, stmt 14 | |
[000042] ------------ * stmtExpr void (IL 0x01A...0x01A) | |
[000041] -----+------ \--* return void | |
------------------------------------------------------------------------------------------------------------------- | |
*************** Exiting Allocate Objects | |
Trees after Allocate Objects | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB02} | |
***** BB01, stmt 1 | |
[000001] ------------ * stmtExpr void (IL ???... ???) | |
[000000] -----+------ \--* nop void | |
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
***** BB02, stmt 2 | |
( 9, 16) [000055] ------------ * stmtExpr void (IL ???... ???) | |
N005 ( 9, 16) [000054] ------------ \--* jmpTrue void | |
N003 ( 1, 1) [000045] ------------ | /--* const int 0 | |
N004 ( 7, 14) [000046] J------N---- \--* == int | |
N002 ( 5, 12) [000044] ------------ \--* indir int | |
N001 ( 3, 10) [000043] ------------ \--* const(h) long 0x7f95ea870610 token | |
------------ BB03 [???..???), preds={BB02} succs={BB04} | |
***** BB03, stmt 3 | |
( 14, 5) [000056] ------------ * stmtExpr void (IL ???... ???) | |
N001 ( 14, 5) [000047] --C-G-?----- \--* call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
------------ BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
***** BB05, stmt 4 | |
[000004] ------------ * stmtExpr void (IL 0x000...0x000) | |
[000003] -----+------ \--* no_op void | |
***** BB05, stmt 5 | |
[000008] ------------ * stmtExpr void (IL 0x001...0x002) | |
[000005] -----+------ | /--* const int 0 | |
[000007] -A---+------ \--* = int | |
[000006] D----+-N---- \--* lclVar int V01 loc0 | |
***** BB05, stmt 6 | |
[000010] ------------ * stmtExpr void (IL 0x003...0x003) | |
[000009] -----+------ \--* nop void | |
------------ BB06 [005..012), preds={BB07} succs={BB07} | |
***** BB06, stmt 7 | |
[000025] ------------ * stmtExpr void (IL 0x005...0x005) | |
[000024] -----+------ \--* no_op void | |
***** BB06, stmt 8 | |
[000029] ------------ * stmtExpr void (IL 0x006...0x00C) | |
[000027] --C-G+------ \--* call void System.Console.WriteLine | |
[000026] -----+------ arg0 in rdi \--* lclVar int V01 loc0 | |
***** BB06, stmt 9 | |
[000031] ------------ * stmtExpr void (IL 0x00C... ???) | |
[000030] -----+------ \--* no_op void | |
***** BB06, stmt 10 | |
[000033] ------------ * stmtExpr void (IL 0x00D...0x00D) | |
[000032] -----+------ \--* no_op void | |
***** BB06, stmt 11 | |
[000039] ------------ * stmtExpr void (IL 0x00E...0x011) | |
[000035] -----+------ | /--* const int 1 | |
[000036] -----+------ | /--* + int | |
[000034] -----+------ | | \--* lclVar int V01 loc0 | |
[000038] -A---+------ \--* = int | |
[000037] D----+-N---- \--* lclVar int V01 loc0 | |
------------ BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
***** BB07, stmt 12 | |
[000017] ------------ * stmtExpr void (IL 0x012...0x016) | |
[000013] -----+------ | /--* const int 3 | |
[000014] -----+------ | /--* < int | |
[000012] -----+------ | | \--* lclVar int V01 loc0 | |
[000016] -A---+------ \--* = int | |
[000015] D----+-N---- \--* lclVar int V02 loc1 | |
***** BB07, stmt 13 | |
[000022] ------------ * stmtExpr void (IL 0x017...0x018) | |
[000021] -----+------ \--* jmpTrue void | |
[000019] -----+------ | /--* const int 0 | |
[000020] J----+-N---- \--* != int | |
[000018] -----+------ \--* lclVar int V02 loc1 | |
------------ BB08 [01A..01B) (return), preds={BB07} succs={} | |
***** BB08, stmt 14 | |
[000042] ------------ * stmtExpr void (IL 0x01A...0x01A) | |
[000041] -----+------ \--* return void | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDebugCheckBBlist | |
*************** In lvaMarkLocalVars() | |
lvaGrabTemp returning 3 (V03 tmp0) (a long lifetime temp) called for OutgoingArgSpace. | |
*** marking local variables in block BB01 (weight= 1 ) | |
[000001] ------------ * stmtExpr void (IL ???... ???) | |
[000000] -----+------ \--* nop void | |
*** marking local variables in block BB02 (weight= 1 ) | |
( 9, 16) [000055] ------------ * stmtExpr void (IL ???... ???) | |
N005 ( 9, 16) [000054] ------------ \--* jmpTrue void | |
N003 ( 1, 1) [000045] ------------ | /--* const int 0 | |
N004 ( 7, 14) [000046] J------N---- \--* == int | |
N002 ( 5, 12) [000044] ------------ \--* indir int | |
N001 ( 3, 10) [000043] ------------ \--* const(h) long 0x7f95ea870610 token | |
*** marking local variables in block BB03 (weight= 0.5) | |
( 14, 5) [000056] ------------ * stmtExpr void (IL ???... ???) | |
N001 ( 14, 5) [000047] --C-G-?----- \--* call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
*** marking local variables in block BB04 (weight= 1 ) | |
*** marking local variables in block BB05 (weight= 1 ) | |
[000004] ------------ * stmtExpr void (IL 0x000...0x000) | |
[000003] -----+------ \--* no_op void | |
[000008] ------------ * stmtExpr void (IL 0x001...0x002) | |
[000005] -----+------ | /--* const int 0 | |
[000007] -A---+------ \--* = int | |
[000006] D----+-N---- \--* lclVar int V01 loc0 | |
New refCnts for V01: refCnt = 1, refCntWtd = 1 | |
[000010] ------------ * stmtExpr void (IL 0x003...0x003) | |
[000009] -----+------ \--* nop void | |
*** marking local variables in block BB06 (weight= 1 ) | |
[000025] ------------ * stmtExpr void (IL 0x005...0x005) | |
[000024] -----+------ \--* no_op void | |
[000029] ------------ * stmtExpr void (IL 0x006...0x00C) | |
[000027] --C-G+------ \--* call void System.Console.WriteLine | |
[000026] -----+------ arg0 in rdi \--* lclVar int V01 loc0 | |
New refCnts for V01: refCnt = 2, refCntWtd = 2 | |
[000031] ------------ * stmtExpr void (IL 0x00C... ???) | |
[000030] -----+------ \--* no_op void | |
[000033] ------------ * stmtExpr void (IL 0x00D...0x00D) | |
[000032] -----+------ \--* no_op void | |
[000039] ------------ * stmtExpr void (IL 0x00E...0x011) | |
[000035] -----+------ | /--* const int 1 | |
[000036] -----+------ | /--* + int | |
[000034] -----+------ | | \--* lclVar int V01 loc0 | |
[000038] -A---+------ \--* = int | |
[000037] D----+-N---- \--* lclVar int V01 loc0 | |
New refCnts for V01: refCnt = 3, refCntWtd = 3 | |
New refCnts for V01: refCnt = 4, refCntWtd = 4 | |
*** marking local variables in block BB07 (weight= 1 ) | |
[000017] ------------ * stmtExpr void (IL 0x012...0x016) | |
[000013] -----+------ | /--* const int 3 | |
[000014] -----+------ | /--* < int | |
[000012] -----+------ | | \--* lclVar int V01 loc0 | |
[000016] -A---+------ \--* = int | |
[000015] D----+-N---- \--* lclVar int V02 loc1 | |
New refCnts for V02: refCnt = 1, refCntWtd = 1 | |
New refCnts for V01: refCnt = 5, refCntWtd = 5 | |
[000022] ------------ * stmtExpr void (IL 0x017...0x018) | |
[000021] -----+------ \--* jmpTrue void | |
[000019] -----+------ | /--* const int 0 | |
[000020] J----+-N---- \--* != int | |
[000018] -----+------ \--* lclVar int V02 loc1 | |
New refCnts for V02: refCnt = 2, refCntWtd = 2 | |
*** marking local variables in block BB08 (weight= 1 ) | |
[000042] ------------ * stmtExpr void (IL 0x01A...0x01A) | |
[000041] -----+------ \--* return void | |
refCnt table for 'Main': | |
V01 loc0 [ int]: refCnt = 5, refCntWtd = 5 | |
V02 loc1 [ bool]: refCnt = 2, refCntWtd = 2 | |
V03 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1 | |
*************** In fgFindOperOrder() | |
*************** In fgSetBlockOrder() | |
The biggest BB has 5 tree nodes | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB02} | |
***** BB01, stmt 1 | |
( 0, 0) [000001] ------------ * stmtExpr void (IL ???... ???) | |
N001 ( 0, 0) [000000] ------------ \--* nop void | |
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
***** BB02, stmt 2 | |
( 9, 16) [000055] ------------ * stmtExpr void (IL ???... ???) | |
N005 ( 9, 16) [000054] ------------ \--* jmpTrue void | |
N003 ( 1, 1) [000045] ------------ | /--* const int 0 | |
N004 ( 7, 14) [000046] J------N---- \--* == int | |
N002 ( 5, 12) [000044] ------------ \--* indir int | |
N001 ( 3, 10) [000043] ------------ \--* const(h) long 0x7f95ea870610 token | |
------------ BB03 [???..???), preds={BB02} succs={BB04} | |
***** BB03, stmt 3 | |
( 14, 5) [000056] ------------ * stmtExpr void (IL ???... ???) | |
N001 ( 14, 5) [000047] --C-G-?----- \--* call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
------------ BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
***** BB05, stmt 4 | |
( 1, 1) [000004] ------------ * stmtExpr void (IL 0x000...0x000) | |
N001 ( 1, 1) [000003] ------------ \--* no_op void | |
***** BB05, stmt 5 | |
( 1, 3) [000008] ------------ * stmtExpr void (IL 0x001...0x002) | |
N001 ( 1, 1) [000005] ------------ | /--* const int 0 | |
N003 ( 1, 3) [000007] -A------R--- \--* = int | |
N002 ( 1, 1) [000006] D------N---- \--* lclVar int V01 loc0 | |
***** BB05, stmt 6 | |
( 0, 0) [000010] ------------ * stmtExpr void (IL 0x003...0x003) | |
N001 ( 0, 0) [000009] ------------ \--* nop void | |
------------ BB06 [005..012), preds={BB07} succs={BB07} | |
***** BB06, stmt 7 | |
( 1, 1) [000025] ------------ * stmtExpr void (IL 0x005...0x005) | |
N001 ( 1, 1) [000024] ------------ \--* no_op void | |
***** BB06, stmt 8 | |
( 15, 7) [000029] ------------ * stmtExpr void (IL 0x006...0x00C) | |
N005 ( 15, 7) [000027] --C-G------- \--* call void System.Console.WriteLine | |
N003 ( 1, 1) [000026] ------------ arg0 in rdi \--* lclVar int V01 loc0 | |
***** BB06, stmt 9 | |
( 1, 1) [000031] ------------ * stmtExpr void (IL 0x00C... ???) | |
N001 ( 1, 1) [000030] ------------ \--* no_op void | |
***** BB06, stmt 10 | |
( 1, 1) [000033] ------------ * stmtExpr void (IL 0x00D...0x00D) | |
N001 ( 1, 1) [000032] ------------ \--* no_op void | |
***** BB06, stmt 11 | |
( 3, 3) [000039] ------------ * stmtExpr void (IL 0x00E...0x011) | |
N002 ( 1, 1) [000035] ------------ | /--* const int 1 | |
N003 ( 3, 3) [000036] ------------ | /--* + int | |
N001 ( 1, 1) [000034] ------------ | | \--* lclVar int V01 loc0 | |
N005 ( 3, 3) [000038] -A------R--- \--* = int | |
N004 ( 1, 1) [000037] D------N---- \--* lclVar int V01 loc0 | |
------------ BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
***** BB07, stmt 12 | |
( 10, 6) [000017] ------------ * stmtExpr void (IL 0x012...0x016) | |
N002 ( 1, 1) [000013] ------------ | /--* const int 3 | |
N003 ( 6, 3) [000014] ------------ | /--* < int | |
N001 ( 1, 1) [000012] ------------ | | \--* lclVar int V01 loc0 | |
N005 ( 10, 6) [000016] -A------R--- \--* = int | |
N004 ( 3, 2) [000015] D------N---- \--* lclVar int V02 loc1 | |
***** BB07, stmt 13 | |
( 7, 6) [000022] ------------ * stmtExpr void (IL 0x017...0x018) | |
N004 ( 7, 6) [000021] ------------ \--* jmpTrue void | |
N002 ( 1, 1) [000019] ------------ | /--* const int 0 | |
N003 ( 5, 4) [000020] J------N---- \--* != int | |
N001 ( 3, 2) [000018] ------------ \--* lclVar int V02 loc1 | |
------------ BB08 [01A..01B) (return), preds={BB07} succs={} | |
***** BB08, stmt 14 | |
( 0, 0) [000042] ------------ * stmtExpr void (IL 0x01A...0x01A) | |
N001 ( 0, 0) [000041] ------------ \--* return void | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDetermineFirstColdBlock() | |
No procedure splitting will be done for this method | |
*************** In IR Rationalize | |
Trees before IR Rationalize | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB02} | |
***** BB01, stmt 1 | |
( 0, 0) [000001] ------------ * stmtExpr void (IL ???... ???) | |
N001 ( 0, 0) [000000] ------------ \--* nop void | |
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
***** BB02, stmt 2 | |
( 9, 16) [000055] ------------ * stmtExpr void (IL ???... ???) | |
N005 ( 9, 16) [000054] ------------ \--* jmpTrue void | |
N003 ( 1, 1) [000045] ------------ | /--* const int 0 | |
N004 ( 7, 14) [000046] J------N---- \--* == int | |
N002 ( 5, 12) [000044] ------------ \--* indir int | |
N001 ( 3, 10) [000043] ------------ \--* const(h) long 0x7f95ea870610 token | |
------------ BB03 [???..???), preds={BB02} succs={BB04} | |
***** BB03, stmt 3 | |
( 14, 5) [000056] ------------ * stmtExpr void (IL ???... ???) | |
N001 ( 14, 5) [000047] --C-G-?----- \--* call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
------------ BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
***** BB05, stmt 4 | |
( 1, 1) [000004] ------------ * stmtExpr void (IL 0x000...0x000) | |
N001 ( 1, 1) [000003] ------------ \--* no_op void | |
***** BB05, stmt 5 | |
( 1, 3) [000008] ------------ * stmtExpr void (IL 0x001...0x002) | |
N001 ( 1, 1) [000005] ------------ | /--* const int 0 | |
N003 ( 1, 3) [000007] -A------R--- \--* = int | |
N002 ( 1, 1) [000006] D------N---- \--* lclVar int V01 loc0 | |
***** BB05, stmt 6 | |
( 0, 0) [000010] ------------ * stmtExpr void (IL 0x003...0x003) | |
N001 ( 0, 0) [000009] ------------ \--* nop void | |
------------ BB06 [005..012), preds={BB07} succs={BB07} | |
***** BB06, stmt 7 | |
( 1, 1) [000025] ------------ * stmtExpr void (IL 0x005...0x005) | |
N001 ( 1, 1) [000024] ------------ \--* no_op void | |
***** BB06, stmt 8 | |
( 15, 7) [000029] ------------ * stmtExpr void (IL 0x006...0x00C) | |
N005 ( 15, 7) [000027] --C-G------- \--* call void System.Console.WriteLine | |
N003 ( 1, 1) [000026] ------------ arg0 in rdi \--* lclVar int V01 loc0 | |
***** BB06, stmt 9 | |
( 1, 1) [000031] ------------ * stmtExpr void (IL 0x00C... ???) | |
N001 ( 1, 1) [000030] ------------ \--* no_op void | |
***** BB06, stmt 10 | |
( 1, 1) [000033] ------------ * stmtExpr void (IL 0x00D...0x00D) | |
N001 ( 1, 1) [000032] ------------ \--* no_op void | |
***** BB06, stmt 11 | |
( 3, 3) [000039] ------------ * stmtExpr void (IL 0x00E...0x011) | |
N002 ( 1, 1) [000035] ------------ | /--* const int 1 | |
N003 ( 3, 3) [000036] ------------ | /--* + int | |
N001 ( 1, 1) [000034] ------------ | | \--* lclVar int V01 loc0 | |
N005 ( 3, 3) [000038] -A------R--- \--* = int | |
N004 ( 1, 1) [000037] D------N---- \--* lclVar int V01 loc0 | |
------------ BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
***** BB07, stmt 12 | |
( 10, 6) [000017] ------------ * stmtExpr void (IL 0x012...0x016) | |
N002 ( 1, 1) [000013] ------------ | /--* const int 3 | |
N003 ( 6, 3) [000014] ------------ | /--* < int | |
N001 ( 1, 1) [000012] ------------ | | \--* lclVar int V01 loc0 | |
N005 ( 10, 6) [000016] -A------R--- \--* = int | |
N004 ( 3, 2) [000015] D------N---- \--* lclVar int V02 loc1 | |
***** BB07, stmt 13 | |
( 7, 6) [000022] ------------ * stmtExpr void (IL 0x017...0x018) | |
N004 ( 7, 6) [000021] ------------ \--* jmpTrue void | |
N002 ( 1, 1) [000019] ------------ | /--* const int 0 | |
N003 ( 5, 4) [000020] J------N---- \--* != int | |
N001 ( 3, 2) [000018] ------------ \--* lclVar int V02 loc1 | |
------------ BB08 [01A..01B) (return), preds={BB07} succs={} | |
***** BB08, stmt 14 | |
( 0, 0) [000042] ------------ * stmtExpr void (IL 0x01A...0x01A) | |
N001 ( 0, 0) [000041] ------------ \--* return void | |
------------------------------------------------------------------------------------------------------------------- | |
rewriting asg(lclVar, X) to st.lclVar(X) | |
N003 ( 1, 3) [000007] DA---------- * st.lclVar int V01 loc0 | |
rewriting asg(lclVar, X) to st.lclVar(X) | |
N005 ( 3, 3) [000038] DA---------- * st.lclVar int V01 loc0 | |
rewriting asg(lclVar, X) to st.lclVar(X) | |
N005 ( 10, 6) [000016] DA---------- * st.lclVar int V02 loc1 | |
*************** Exiting IR Rationalize | |
Trees after IR Rationalize | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target LIR | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal LIR | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target LIR | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i LIR | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd LIR | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd LIR | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB02} | |
N001 ( 0, 0) [000000] ------------ nop void | |
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
N001 ( 3, 10) [000043] ------------ t43 = const(h) long 0x7f95ea870610 token | |
/--* t43 long | |
N002 ( 5, 12) [000044] ------------ t44 = * indir int | |
N003 ( 1, 1) [000045] ------------ t45 = const int 0 | |
/--* t44 int | |
+--* t45 int | |
N004 ( 7, 14) [000046] J------N---- t46 = * == int | |
/--* t46 int | |
N005 ( 9, 16) [000054] ------------ * jmpTrue void | |
------------ BB03 [???..???), preds={BB02} succs={BB04} | |
N001 ( 14, 5) [000047] --C-G-?----- call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
------------ BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
( 1, 1) [000004] ------------ il_offset void IL offset: 0 | |
N001 ( 1, 1) [000003] ------------ no_op void | |
( 1, 3) [000008] ------------ il_offset void IL offset: 1 | |
N001 ( 1, 1) [000005] ------------ t5 = const int 0 | |
/--* t5 int | |
N003 ( 1, 3) [000007] DA---------- * st.lclVar int V01 loc0 | |
( 0, 0) [000010] ------------ il_offset void IL offset: 3 | |
N001 ( 0, 0) [000009] ------------ nop void | |
------------ BB06 [005..012), preds={BB07} succs={BB07} | |
( 1, 1) [000025] ------------ il_offset void IL offset: 5 | |
N001 ( 1, 1) [000024] ------------ no_op void | |
( 15, 7) [000029] ------------ il_offset void IL offset: 6 | |
N003 ( 1, 1) [000026] ------------ t26 = lclVar int V01 loc0 | |
/--* t26 int arg0 in rdi | |
N005 ( 15, 7) [000027] --C-G------- * call void System.Console.WriteLine | |
( 1, 1) [000031] ------------ il_offset void IL offset: 12 | |
N001 ( 1, 1) [000030] ------------ no_op void | |
( 1, 1) [000033] ------------ il_offset void IL offset: 13 | |
N001 ( 1, 1) [000032] ------------ no_op void | |
( 3, 3) [000039] ------------ il_offset void IL offset: 14 | |
N001 ( 1, 1) [000034] ------------ t34 = lclVar int V01 loc0 | |
N002 ( 1, 1) [000035] ------------ t35 = const int 1 | |
/--* t34 int | |
+--* t35 int | |
N003 ( 3, 3) [000036] ------------ t36 = * + int | |
/--* t36 int | |
N005 ( 3, 3) [000038] DA---------- * st.lclVar int V01 loc0 | |
------------ BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
( 10, 6) [000017] ------------ il_offset void IL offset: 18 | |
N001 ( 1, 1) [000012] ------------ t12 = lclVar int V01 loc0 | |
N002 ( 1, 1) [000013] ------------ t13 = const int 3 | |
/--* t12 int | |
+--* t13 int | |
N003 ( 6, 3) [000014] ------------ t14 = * < int | |
/--* t14 int | |
N005 ( 10, 6) [000016] DA---------- * st.lclVar int V02 loc1 | |
( 7, 6) [000022] ------------ il_offset void IL offset: 23 | |
N001 ( 3, 2) [000018] ------------ t18 = lclVar int V02 loc1 | |
N002 ( 1, 1) [000019] ------------ t19 = const int 0 | |
/--* t18 int | |
+--* t19 int | |
N003 ( 5, 4) [000020] J------N---- t20 = * != int | |
/--* t20 int | |
N004 ( 7, 6) [000021] ------------ * jmpTrue void | |
------------ BB08 [01A..01B) (return), preds={BB07} succs={} | |
( 0, 0) [000042] ------------ il_offset void IL offset: 26 | |
N001 ( 0, 0) [000041] ------------ return void | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDebugCheckBBlist | |
*************** In fgDebugCheckBBlist | |
*************** In Lowering | |
Trees before Lowering | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target LIR | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal LIR | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target LIR | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i LIR | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd LIR | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd LIR | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB02} | |
N001 ( 0, 0) [000000] ------------ nop void | |
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
N001 ( 3, 10) [000043] ------------ t43 = const(h) long 0x7f95ea870610 token | |
/--* t43 long | |
N002 ( 5, 12) [000044] ------------ t44 = * indir int | |
N003 ( 1, 1) [000045] ------------ t45 = const int 0 | |
/--* t44 int | |
+--* t45 int | |
N004 ( 7, 14) [000046] J------N---- t46 = * == int | |
/--* t46 int | |
N005 ( 9, 16) [000054] ------------ * jmpTrue void | |
------------ BB03 [???..???), preds={BB02} succs={BB04} | |
N001 ( 14, 5) [000047] --C-G-?----- call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
------------ BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
( 1, 1) [000004] ------------ il_offset void IL offset: 0 | |
N001 ( 1, 1) [000003] ------------ no_op void | |
( 1, 3) [000008] ------------ il_offset void IL offset: 1 | |
N001 ( 1, 1) [000005] ------------ t5 = const int 0 | |
/--* t5 int | |
N003 ( 1, 3) [000007] DA---------- * st.lclVar int V01 loc0 | |
( 0, 0) [000010] ------------ il_offset void IL offset: 3 | |
N001 ( 0, 0) [000009] ------------ nop void | |
------------ BB06 [005..012), preds={BB07} succs={BB07} | |
( 1, 1) [000025] ------------ il_offset void IL offset: 5 | |
N001 ( 1, 1) [000024] ------------ no_op void | |
( 15, 7) [000029] ------------ il_offset void IL offset: 6 | |
N003 ( 1, 1) [000026] ------------ t26 = lclVar int V01 loc0 | |
/--* t26 int arg0 in rdi | |
N005 ( 15, 7) [000027] --C-G------- * call void System.Console.WriteLine | |
( 1, 1) [000031] ------------ il_offset void IL offset: 12 | |
N001 ( 1, 1) [000030] ------------ no_op void | |
( 1, 1) [000033] ------------ il_offset void IL offset: 13 | |
N001 ( 1, 1) [000032] ------------ no_op void | |
( 3, 3) [000039] ------------ il_offset void IL offset: 14 | |
N001 ( 1, 1) [000034] ------------ t34 = lclVar int V01 loc0 | |
N002 ( 1, 1) [000035] ------------ t35 = const int 1 | |
/--* t34 int | |
+--* t35 int | |
N003 ( 3, 3) [000036] ------------ t36 = * + int | |
/--* t36 int | |
N005 ( 3, 3) [000038] DA---------- * st.lclVar int V01 loc0 | |
------------ BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
( 10, 6) [000017] ------------ il_offset void IL offset: 18 | |
N001 ( 1, 1) [000012] ------------ t12 = lclVar int V01 loc0 | |
N002 ( 1, 1) [000013] ------------ t13 = const int 3 | |
/--* t12 int | |
+--* t13 int | |
N003 ( 6, 3) [000014] ------------ t14 = * < int | |
/--* t14 int | |
N005 ( 10, 6) [000016] DA---------- * st.lclVar int V02 loc1 | |
( 7, 6) [000022] ------------ il_offset void IL offset: 23 | |
N001 ( 3, 2) [000018] ------------ t18 = lclVar int V02 loc1 | |
N002 ( 1, 1) [000019] ------------ t19 = const int 0 | |
/--* t18 int | |
+--* t19 int | |
N003 ( 5, 4) [000020] J------N---- t20 = * != int | |
/--* t20 int | |
N004 ( 7, 6) [000021] ------------ * jmpTrue void | |
------------ BB08 [01A..01B) (return), preds={BB07} succs={} | |
( 0, 0) [000042] ------------ il_offset void IL offset: 26 | |
N001 ( 0, 0) [000041] ------------ return void | |
------------------------------------------------------------------------------------------------------------------- | |
No addressing mode | |
lowering call (before): | |
N001 ( 14, 5) [000047] --C-G-?----- call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
objp: | |
====== | |
args: | |
====== | |
late: | |
====== | |
lowering call (after): | |
N001 ( 14, 5) [000047] --C-G-?----- call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
lowering call (before): | |
N003 ( 1, 1) [000026] ------------ t26 = lclVar int V01 loc0 | |
/--* t26 int arg0 in rdi | |
N005 ( 15, 7) [000027] --C-G------- * call void System.Console.WriteLine | |
objp: | |
====== | |
args: | |
====== | |
lowering arg : N001 ( 0, 0) [000052] ----------L- * argPlace int | |
late: | |
====== | |
lowering arg : N003 ( 1, 1) [000026] ------------ * lclVar int V01 loc0 | |
new node is : [000057] ------------ * putarg_reg int | |
lowering call (after): | |
N003 ( 1, 1) [000026] ------------ t26 = lclVar int V01 loc0 | |
/--* t26 int | |
[000057] ------------ t57 = * putarg_reg int | |
/--* t57 int arg0 in rdi | |
N005 ( 15, 7) [000027] --C-G------- * call void System.Console.WriteLine | |
lowering GT_RETURN | |
N001 ( 0, 0) [000041] ------------ * return void | |
============Lower has completed modifying nodes, proceeding to initialize LSRA TreeNodeInfo structs... | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target LIR | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal LIR | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target LIR | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i LIR | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd LIR | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd LIR | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB02} | |
N001 ( 0, 0) [000000] ------------ nop void | |
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
N001 ( 3, 10) [000043] ------------ t43 = const(h) long 0x7f95ea870610 token | |
/--* t43 long | |
N002 ( 5, 12) [000044] ------------ t44 = * indir int | |
N003 ( 1, 1) [000045] ------------ t45 = const int 0 | |
/--* t44 int | |
+--* t45 int | |
N004 ( 7, 14) [000046] J------N---- t46 = * == int | |
/--* t46 int | |
N005 ( 9, 16) [000054] ------------ * jmpTrue void | |
------------ BB03 [???..???), preds={BB02} succs={BB04} | |
N001 ( 14, 5) [000047] --C-G-?----- call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
------------ BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
( 1, 1) [000004] ------------ il_offset void IL offset: 0 | |
N001 ( 1, 1) [000003] ------------ no_op void | |
( 1, 3) [000008] ------------ il_offset void IL offset: 1 | |
N001 ( 1, 1) [000005] ------------ t5 = const int 0 | |
/--* t5 int | |
N003 ( 1, 3) [000007] DA---------- * st.lclVar int V01 loc0 | |
( 0, 0) [000010] ------------ il_offset void IL offset: 3 | |
N001 ( 0, 0) [000009] ------------ nop void | |
------------ BB06 [005..012), preds={BB07} succs={BB07} | |
( 1, 1) [000025] ------------ il_offset void IL offset: 5 | |
N001 ( 1, 1) [000024] ------------ no_op void | |
( 15, 7) [000029] ------------ il_offset void IL offset: 6 | |
N003 ( 1, 1) [000026] ------------ t26 = lclVar int V01 loc0 | |
/--* t26 int | |
[000057] ------------ t57 = * putarg_reg int | |
/--* t57 int arg0 in rdi | |
N005 ( 15, 7) [000027] --C-G------- * call void System.Console.WriteLine | |
( 1, 1) [000031] ------------ il_offset void IL offset: 12 | |
N001 ( 1, 1) [000030] ------------ no_op void | |
( 1, 1) [000033] ------------ il_offset void IL offset: 13 | |
N001 ( 1, 1) [000032] ------------ no_op void | |
( 3, 3) [000039] ------------ il_offset void IL offset: 14 | |
N001 ( 1, 1) [000034] ------------ t34 = lclVar int V01 loc0 | |
N002 ( 1, 1) [000035] ------------ t35 = const int 1 | |
/--* t34 int | |
+--* t35 int | |
N003 ( 3, 3) [000036] ------------ t36 = * + int | |
/--* t36 int | |
N005 ( 3, 3) [000038] DA---------- * st.lclVar int V01 loc0 | |
------------ BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
( 10, 6) [000017] ------------ il_offset void IL offset: 18 | |
N001 ( 1, 1) [000012] ------------ t12 = lclVar int V01 loc0 | |
N002 ( 1, 1) [000013] ------------ t13 = const int 3 | |
/--* t12 int | |
+--* t13 int | |
N003 ( 6, 3) [000014] ------------ t14 = * < int | |
/--* t14 int | |
N005 ( 10, 6) [000016] DA---------- * st.lclVar int V02 loc1 | |
( 7, 6) [000022] ------------ il_offset void IL offset: 23 | |
N001 ( 3, 2) [000018] ------------ t18 = lclVar int V02 loc1 | |
N002 ( 1, 1) [000019] ------------ t19 = const int 0 | |
/--* t18 int | |
+--* t19 int | |
N003 ( 5, 4) [000020] J------N---- t20 = * != int | |
/--* t20 int | |
N004 ( 7, 6) [000021] ------------ * jmpTrue void | |
------------ BB08 [01A..01B) (return), preds={BB07} succs={} | |
( 0, 0) [000042] ------------ il_offset void IL offset: 26 | |
N001 ( 0, 0) [000041] ------------ return void | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In fgLocalVarLiveness() | |
; Initial local variable assignments | |
; | |
; V00 arg0 ref | |
; V01 loc0 int | |
; V02 loc1 bool | |
; V03 OutArgs lclBlk ( 0) | |
In fgLocalVarLivenessInit, sorting locals | |
refCnt table for 'Main': | |
V01 loc0 [ int]: refCnt = 5, refCntWtd = 5 | |
V02 loc1 [ bool]: refCnt = 2, refCntWtd = 2 | |
V03 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1 | |
*************** In fgPerBlockLocalVarLiveness() | |
*************** In fgInterBlockLocalVarLiveness() | |
BB liveness after fgLiveVarAnalysis(): | |
BB01 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB02 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB03 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB04 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB05 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB06 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB07 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB08 IN (2)={V01 V02} + HEAP | |
OUT(0)={ } | |
*************** In fgExtendDbgLifetimes() | |
Marking vars alive over their entire scope : | |
Local variable scopes = 3 | |
VarNum LVNum Name Beg End | |
Sorted by enter scope: | |
0: 00h 00h V00 arg0 000h 01Bh <-- next enter scope | |
1: 01h 01h V01 loc0 000h 01Bh | |
2: 02h 02h V02 loc1 000h 01Bh | |
Sorted by exit scope: | |
0: 00h 00h V00 arg0 000h 01Bh <-- next exit scope | |
1: 01h 01h V01 loc0 000h 01Bh | |
2: 02h 02h V02 loc1 000h 01Bh | |
Scope info: block BB01 marking in scope: {} | |
Scope info: block BB02 marking in scope: {} | |
Scope info: block BB03 marking in scope: {} | |
Scope info: block BB04 marking in scope: {} | |
Scope info: block BB05 marking in scope: {V01 V02} | |
Scope info: block BB06 marking in scope: {V01 V02} | |
Scope info: block BB07 marking in scope: {V01 V02} | |
Scope info: block BB08 marking in scope: {V01 V02} | |
Debug scopes: | |
BB01: {} | |
BB02: {} | |
BB03: {} | |
BB04: {} | |
BB05: {V01 V02} | |
BB06: {V01 V02} | |
BB07: {V01 V02} | |
BB08: {V01 V02} | |
Scope info: block BB01 UNmarking in scope: {} | |
BB liveness after fgExtendDbgLifetimes(): | |
BB01 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB02 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB03 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB04 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB05 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB06 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB07 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
BB08 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} | |
Liveness pass finished after lowering, IR: | |
lvasortagain = 0 | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target LIR | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal LIR | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target LIR | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i LIR | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd LIR | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd LIR | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB02} | |
N001 ( 0, 0) [000000] ------------ nop void | |
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
N001 ( 3, 10) [000043] ------------ t43 = const(h) long 0x7f95ea870610 token | |
/--* t43 long | |
N002 ( 5, 12) [000044] ------------ t44 = * indir int | |
N003 ( 1, 1) [000045] ------------ t45 = const int 0 | |
/--* t44 int | |
+--* t45 int | |
N004 ( 7, 14) [000046] J------N---- t46 = * == int | |
/--* t46 int | |
N005 ( 9, 16) [000054] ------------ * jmpTrue void | |
------------ BB03 [???..???), preds={BB02} succs={BB04} | |
N001 ( 14, 5) [000047] --C-G-?----- call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
------------ BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
( 1, 1) [000004] ------------ il_offset void IL offset: 0 | |
N001 ( 1, 1) [000003] ------------ no_op void | |
( 1, 3) [000008] ------------ il_offset void IL offset: 1 | |
N001 ( 1, 1) [000005] ------------ t5 = const int 0 | |
/--* t5 int | |
N003 ( 1, 3) [000007] DA---------- * st.lclVar int V01 loc0 | |
( 0, 0) [000010] ------------ il_offset void IL offset: 3 | |
N001 ( 0, 0) [000009] ------------ nop void | |
------------ BB06 [005..012), preds={BB07} succs={BB07} | |
( 1, 1) [000025] ------------ il_offset void IL offset: 5 | |
N001 ( 1, 1) [000024] ------------ no_op void | |
( 15, 7) [000029] ------------ il_offset void IL offset: 6 | |
N003 ( 1, 1) [000026] ------------ t26 = lclVar int V01 loc0 | |
/--* t26 int | |
[000057] ------------ t57 = * putarg_reg int | |
/--* t57 int arg0 in rdi | |
N005 ( 15, 7) [000027] --C-G------- * call void System.Console.WriteLine | |
( 1, 1) [000031] ------------ il_offset void IL offset: 12 | |
N001 ( 1, 1) [000030] ------------ no_op void | |
( 1, 1) [000033] ------------ il_offset void IL offset: 13 | |
N001 ( 1, 1) [000032] ------------ no_op void | |
( 3, 3) [000039] ------------ il_offset void IL offset: 14 | |
N001 ( 1, 1) [000034] ------------ t34 = lclVar int V01 loc0 | |
N002 ( 1, 1) [000035] ------------ t35 = const int 1 | |
/--* t34 int | |
+--* t35 int | |
N003 ( 3, 3) [000036] ------------ t36 = * + int | |
/--* t36 int | |
N005 ( 3, 3) [000038] DA---------- * st.lclVar int V01 loc0 | |
------------ BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
( 10, 6) [000017] ------------ il_offset void IL offset: 18 | |
N001 ( 1, 1) [000012] ------------ t12 = lclVar int V01 loc0 | |
N002 ( 1, 1) [000013] ------------ t13 = const int 3 | |
/--* t12 int | |
+--* t13 int | |
N003 ( 6, 3) [000014] ------------ t14 = * < int | |
/--* t14 int | |
N005 ( 10, 6) [000016] DA---------- * st.lclVar int V02 loc1 | |
( 7, 6) [000022] ------------ il_offset void IL offset: 23 | |
N001 ( 3, 2) [000018] ------------ t18 = lclVar int V02 loc1 | |
N002 ( 1, 1) [000019] ------------ t19 = const int 0 | |
/--* t18 int | |
+--* t19 int | |
N003 ( 5, 4) [000020] J------N---- t20 = * != int | |
/--* t20 int | |
N004 ( 7, 6) [000021] ------------ * jmpTrue void | |
------------ BB08 [01A..01B) (return), preds={BB07} succs={} | |
( 0, 0) [000042] ------------ il_offset void IL offset: 26 | |
N001 ( 0, 0) [000041] ------------ return void | |
------------------------------------------------------------------------------------------------------------------- | |
LSRA Block Sequence: BB01( 1 ) BB02( 1 ) BB03( 0.5) BB04( 1 ) BB05( 1 ) BB07( 1 ) BB06( 1 ) BB08( 1 ) | |
----------------------------- | |
TREE NODE INFO DUMP | |
----------------------------- | |
N003 ( 0, 0) [000000] ------------ * nop void REG NA | |
+<TreeNodeInfo @ 3 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N007 ( 3, 10) [000043] ------------ * const(h) long 0x7f95ea870610 token REG NA | |
+<TreeNodeInfo @ 7 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N009 ( 5, 12) [000044] ------------ * indir int REG NA | |
+<TreeNodeInfo @ 9 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N011 ( 1, 1) [000045] ------------ * const int 0 REG NA | |
+<TreeNodeInfo @ 11 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N013 ( 7, 14) [000046] J------N---- * == int REG NA | |
+<TreeNodeInfo @ 13 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N015 ( 9, 16) [000054] ------------ * jmpTrue void REG NA | |
+<TreeNodeInfo @ 15 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N019 ( 14, 5) [000047] --C-G-?----- * call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
+<TreeNodeInfo @ 19 0=0 0i 0f src=[allInt] int=[allInt] dst=[rax] I> | |
N025 ( 1, 1) [000004] ------------ * il_offset void IL offset: 0 REG NA | |
+<TreeNodeInfo @ 25 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N027 ( 1, 1) [000003] ------------ * no_op void REG NA | |
+<TreeNodeInfo @ 27 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N029 ( 1, 3) [000008] ------------ * il_offset void IL offset: 1 REG NA | |
+<TreeNodeInfo @ 29 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N031 ( 1, 1) [000005] ------------ * const int 0 REG NA | |
+<TreeNodeInfo @ 31 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N033 ( 1, 3) [000007] DA---------- * st.lclVar int V01 loc0 REG NA | |
+<TreeNodeInfo @ 33 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N035 ( 0, 0) [000010] ------------ * il_offset void IL offset: 3 REG NA | |
+<TreeNodeInfo @ 35 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N037 ( 0, 0) [000009] ------------ * nop void REG NA | |
+<TreeNodeInfo @ 37 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N063 ( 1, 1) [000025] ------------ * il_offset void IL offset: 5 REG NA | |
+<TreeNodeInfo @ 63 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N065 ( 1, 1) [000024] ------------ * no_op void REG NA | |
+<TreeNodeInfo @ 65 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N067 ( 15, 7) [000029] ------------ * il_offset void IL offset: 6 REG NA | |
+<TreeNodeInfo @ 67 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N069 ( 1, 1) [000026] ------------ * lclVar int V01 loc0 REG NA | |
+<TreeNodeInfo @ 69 1=0 0i 0f src=[rdi] int=[allInt] dst=[allInt] I> | |
N071 (???,???) [000057] ------------ * putarg_reg int REG NA | |
+<TreeNodeInfo @ 71 1=1 0i 0f src=[rdi] int=[allInt] dst=[rdi] I> | |
N073 ( 15, 7) [000027] --C-G------- * call void System.Console.WriteLine | |
+<TreeNodeInfo @ 73 0=1 0i 0f src=[allInt] int=[allInt] dst=[rax] I> | |
N075 ( 1, 1) [000031] ------------ * il_offset void IL offset: 12 REG NA | |
+<TreeNodeInfo @ 75 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N077 ( 1, 1) [000030] ------------ * no_op void REG NA | |
+<TreeNodeInfo @ 77 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N079 ( 1, 1) [000033] ------------ * il_offset void IL offset: 13 REG NA | |
+<TreeNodeInfo @ 79 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N081 ( 1, 1) [000032] ------------ * no_op void REG NA | |
+<TreeNodeInfo @ 81 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N083 ( 3, 3) [000039] ------------ * il_offset void IL offset: 14 REG NA | |
+<TreeNodeInfo @ 83 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N085 ( 1, 1) [000034] ------------ * lclVar int V01 loc0 REG NA | |
+<TreeNodeInfo @ 85 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I P> | |
N087 ( 1, 1) [000035] ------------ * const int 1 REG NA | |
+<TreeNodeInfo @ 87 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N089 ( 3, 3) [000036] ------------ * + int REG NA | |
+<TreeNodeInfo @ 89 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N091 ( 3, 3) [000038] DA---------- * st.lclVar int V01 loc0 REG NA | |
+<TreeNodeInfo @ 91 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N041 ( 10, 6) [000017] ------------ * il_offset void IL offset: 18 REG NA | |
+<TreeNodeInfo @ 41 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N043 ( 1, 1) [000012] ------------ * lclVar int V01 loc0 REG NA | |
+<TreeNodeInfo @ 43 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N045 ( 1, 1) [000013] ------------ * const int 3 REG NA | |
+<TreeNodeInfo @ 45 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N047 ( 6, 3) [000014] ------------ * < int REG NA | |
+<TreeNodeInfo @ 47 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N049 ( 10, 6) [000016] DA---------- * st.lclVar int V02 loc1 REG NA | |
+<TreeNodeInfo @ 49 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N051 ( 7, 6) [000022] ------------ * il_offset void IL offset: 23 REG NA | |
+<TreeNodeInfo @ 51 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N053 ( 3, 2) [000018] ------------ * lclVar int V02 loc1 REG NA | |
+<TreeNodeInfo @ 53 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N055 ( 1, 1) [000019] ------------ * const int 0 REG NA | |
+<TreeNodeInfo @ 55 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N057 ( 5, 4) [000020] J------N---- * != int REG NA | |
+<TreeNodeInfo @ 57 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N059 ( 7, 6) [000021] ------------ * jmpTrue void REG NA | |
+<TreeNodeInfo @ 59 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N095 ( 0, 0) [000042] ------------ * il_offset void IL offset: 26 REG NA | |
+<TreeNodeInfo @ 95 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N097 ( 0, 0) [000041] ------------ * return void REG NA | |
+<TreeNodeInfo @ 97 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
*************** Exiting Lowering | |
Trees after Lowering | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target LIR | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal LIR | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target LIR | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i LIR | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd LIR | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd LIR | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB02} | |
N003 ( 0, 0) [000000] ------------ nop void REG NA | |
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
N007 ( 3, 10) [000043] ------------ t43 = const(h) long 0x7f95ea870610 token REG NA | |
/--* t43 long | |
N009 ( 5, 12) [000044] ------------ t44 = * indir int REG NA | |
N011 ( 1, 1) [000045] ------------ t45 = const int 0 REG NA | |
/--* t44 int | |
+--* t45 int | |
N013 ( 7, 14) [000046] J------N---- t46 = * == int REG NA | |
/--* t46 int | |
N015 ( 9, 16) [000054] ------------ * jmpTrue void REG NA | |
------------ BB03 [???..???), preds={BB02} succs={BB04} | |
N019 ( 14, 5) [000047] --C-G-?----- call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
------------ BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
N025 ( 1, 1) [000004] ------------ il_offset void IL offset: 0 REG NA | |
N027 ( 1, 1) [000003] ------------ no_op void REG NA | |
N029 ( 1, 3) [000008] ------------ il_offset void IL offset: 1 REG NA | |
N031 ( 1, 1) [000005] ------------ t5 = const int 0 REG NA | |
/--* t5 int | |
N033 ( 1, 3) [000007] DA---------- * st.lclVar int V01 loc0 REG NA | |
N035 ( 0, 0) [000010] ------------ il_offset void IL offset: 3 REG NA | |
N037 ( 0, 0) [000009] ------------ nop void REG NA | |
------------ BB06 [005..012), preds={BB07} succs={BB07} | |
N063 ( 1, 1) [000025] ------------ il_offset void IL offset: 5 REG NA | |
N065 ( 1, 1) [000024] ------------ no_op void REG NA | |
N067 ( 15, 7) [000029] ------------ il_offset void IL offset: 6 REG NA | |
N069 ( 1, 1) [000026] ------------ t26 = lclVar int V01 loc0 REG NA | |
/--* t26 int | |
N071 (???,???) [000057] ------------ t57 = * putarg_reg int REG NA | |
/--* t57 int arg0 in rdi | |
N073 ( 15, 7) [000027] --C-G------- * call void System.Console.WriteLine | |
N075 ( 1, 1) [000031] ------------ il_offset void IL offset: 12 REG NA | |
N077 ( 1, 1) [000030] ------------ no_op void REG NA | |
N079 ( 1, 1) [000033] ------------ il_offset void IL offset: 13 REG NA | |
N081 ( 1, 1) [000032] ------------ no_op void REG NA | |
N083 ( 3, 3) [000039] ------------ il_offset void IL offset: 14 REG NA | |
N085 ( 1, 1) [000034] ------------ t34 = lclVar int V01 loc0 REG NA | |
N087 ( 1, 1) [000035] ------------ t35 = const int 1 REG NA | |
/--* t34 int | |
+--* t35 int | |
N089 ( 3, 3) [000036] ------------ t36 = * + int REG NA | |
/--* t36 int | |
N091 ( 3, 3) [000038] DA---------- * st.lclVar int V01 loc0 REG NA | |
------------ BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
N041 ( 10, 6) [000017] ------------ il_offset void IL offset: 18 REG NA | |
N043 ( 1, 1) [000012] ------------ t12 = lclVar int V01 loc0 REG NA | |
N045 ( 1, 1) [000013] ------------ t13 = const int 3 REG NA | |
/--* t12 int | |
+--* t13 int | |
N047 ( 6, 3) [000014] ------------ t14 = * < int REG NA | |
/--* t14 int | |
N049 ( 10, 6) [000016] DA---------- * st.lclVar int V02 loc1 REG NA | |
N051 ( 7, 6) [000022] ------------ il_offset void IL offset: 23 REG NA | |
N053 ( 3, 2) [000018] ------------ t18 = lclVar int V02 loc1 REG NA | |
N055 ( 1, 1) [000019] ------------ t19 = const int 0 REG NA | |
/--* t18 int | |
+--* t19 int | |
N057 ( 5, 4) [000020] J------N---- t20 = * != int REG NA | |
/--* t20 int | |
N059 ( 7, 6) [000021] ------------ * jmpTrue void REG NA | |
------------ BB08 [01A..01B) (return), preds={BB07} succs={} | |
N095 ( 0, 0) [000042] ------------ il_offset void IL offset: 26 REG NA | |
N097 ( 0, 0) [000041] ------------ return void REG NA | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDebugCheckBBlist | |
*************** In doLinearScan | |
Trees before linear scan register allocator (LSRA) | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target LIR | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal LIR | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target LIR | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i LIR | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd LIR | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd LIR | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB02} | |
N003 ( 0, 0) [000000] ------------ nop void REG NA | |
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
N007 ( 3, 10) [000043] ------------ t43 = const(h) long 0x7f95ea870610 token REG NA | |
/--* t43 long | |
N009 ( 5, 12) [000044] ------------ t44 = * indir int REG NA | |
N011 ( 1, 1) [000045] ------------ t45 = const int 0 REG NA | |
/--* t44 int | |
+--* t45 int | |
N013 ( 7, 14) [000046] J------N---- t46 = * == int REG NA | |
/--* t46 int | |
N015 ( 9, 16) [000054] ------------ * jmpTrue void REG NA | |
------------ BB03 [???..???), preds={BB02} succs={BB04} | |
N019 ( 14, 5) [000047] --C-G-?----- call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
------------ BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
N025 ( 1, 1) [000004] ------------ il_offset void IL offset: 0 REG NA | |
N027 ( 1, 1) [000003] ------------ no_op void REG NA | |
N029 ( 1, 3) [000008] ------------ il_offset void IL offset: 1 REG NA | |
N031 ( 1, 1) [000005] ------------ t5 = const int 0 REG NA | |
/--* t5 int | |
N033 ( 1, 3) [000007] DA---------- * st.lclVar int V01 loc0 REG NA | |
N035 ( 0, 0) [000010] ------------ il_offset void IL offset: 3 REG NA | |
N037 ( 0, 0) [000009] ------------ nop void REG NA | |
------------ BB06 [005..012), preds={BB07} succs={BB07} | |
N063 ( 1, 1) [000025] ------------ il_offset void IL offset: 5 REG NA | |
N065 ( 1, 1) [000024] ------------ no_op void REG NA | |
N067 ( 15, 7) [000029] ------------ il_offset void IL offset: 6 REG NA | |
N069 ( 1, 1) [000026] ------------ t26 = lclVar int V01 loc0 REG NA | |
/--* t26 int | |
N071 (???,???) [000057] ------------ t57 = * putarg_reg int REG NA | |
/--* t57 int arg0 in rdi | |
N073 ( 15, 7) [000027] --C-G------- * call void System.Console.WriteLine | |
N075 ( 1, 1) [000031] ------------ il_offset void IL offset: 12 REG NA | |
N077 ( 1, 1) [000030] ------------ no_op void REG NA | |
N079 ( 1, 1) [000033] ------------ il_offset void IL offset: 13 REG NA | |
N081 ( 1, 1) [000032] ------------ no_op void REG NA | |
N083 ( 3, 3) [000039] ------------ il_offset void IL offset: 14 REG NA | |
N085 ( 1, 1) [000034] ------------ t34 = lclVar int V01 loc0 REG NA | |
N087 ( 1, 1) [000035] ------------ t35 = const int 1 REG NA | |
/--* t34 int | |
+--* t35 int | |
N089 ( 3, 3) [000036] ------------ t36 = * + int REG NA | |
/--* t36 int | |
N091 ( 3, 3) [000038] DA---------- * st.lclVar int V01 loc0 REG NA | |
------------ BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
N041 ( 10, 6) [000017] ------------ il_offset void IL offset: 18 REG NA | |
N043 ( 1, 1) [000012] ------------ t12 = lclVar int V01 loc0 REG NA | |
N045 ( 1, 1) [000013] ------------ t13 = const int 3 REG NA | |
/--* t12 int | |
+--* t13 int | |
N047 ( 6, 3) [000014] ------------ t14 = * < int REG NA | |
/--* t14 int | |
N049 ( 10, 6) [000016] DA---------- * st.lclVar int V02 loc1 REG NA | |
N051 ( 7, 6) [000022] ------------ il_offset void IL offset: 23 REG NA | |
N053 ( 3, 2) [000018] ------------ t18 = lclVar int V02 loc1 REG NA | |
N055 ( 1, 1) [000019] ------------ t19 = const int 0 REG NA | |
/--* t18 int | |
+--* t19 int | |
N057 ( 5, 4) [000020] J------N---- t20 = * != int REG NA | |
/--* t20 int | |
N059 ( 7, 6) [000021] ------------ * jmpTrue void REG NA | |
------------ BB08 [01A..01B) (return), preds={BB07} succs={} | |
N095 ( 0, 0) [000042] ------------ il_offset void IL offset: 26 REG NA | |
N097 ( 0, 0) [000041] ------------ return void REG NA | |
------------------------------------------------------------------------------------------------------------------- | |
Clearing modified regs. | |
; Decided to create an EBP based frame for ETW stackwalking (Debug Code) | |
buildIntervals ======== | |
----------------- | |
LIVENESS: | |
----------------- | |
BB01 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
BB02 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
BB03 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
BB04 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
BB05 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
BB06 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
BB07 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
BB08 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
Interval 0: RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 1: RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 2: RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 3: RefPositions {} physReg:NA Preferences=[allInt] | |
FP callee save candidate vars: None | |
floatVarCount = 0; hasLoops = 0, singleExit = 1 | |
TUPLE STYLE DUMP BEFORE LSRA | |
BB01 [???..???), preds={} succs={BB02} | |
===== | |
N003. nop | |
BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
===== | |
N007. t7 = const(h) 0x7f95ea870610 token REG NA | |
N009. indir | |
N011. const 0 REG NA | |
N013. == ; t7 | |
N015. jmpTrue | |
BB03 [???..???), preds={BB02} succs={BB04} | |
===== | |
N019. call help | |
BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
===== | |
BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
===== | |
N025. il_offset IL offset: 0 REG NA | |
N027. no_op REG NA | |
N029. il_offset IL offset: 1 REG NA | |
N031. t31 = const 0 REG NA | |
N033. V01 MEM; t31 | |
N035. il_offset IL offset: 3 REG NA | |
N037. nop | |
BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
===== | |
N041. il_offset IL offset: 18 REG NA | |
N043. t43 = V01 MEM | |
N045. const 3 REG NA | |
N047. t47 = < ; t43 | |
N049. V02 MEM; t47 | |
N051. il_offset IL offset: 23 REG NA | |
N053. t53 = V02 MEM | |
N055. const 0 REG NA | |
N057. != ; t53 | |
N059. jmpTrue | |
BB06 [005..012), preds={BB07} succs={BB07} | |
===== | |
N063. il_offset IL offset: 5 REG NA | |
N065. no_op REG NA | |
N067. il_offset IL offset: 6 REG NA | |
N069. t69 = V01 MEM | |
N071. t71 = putarg_reg; t69 | |
N073. call ; t71 | |
N075. il_offset IL offset: 12 REG NA | |
N077. no_op REG NA | |
N079. il_offset IL offset: 13 REG NA | |
N081. no_op REG NA | |
N083. il_offset IL offset: 14 REG NA | |
N085. t85 = V01 MEM | |
N087. const 1 REG NA | |
N089. t89 = + ; t85 | |
N091. V01 MEM; t89 | |
BB08 [01A..01B) (return), preds={BB07} succs={} | |
===== | |
N095. il_offset IL offset: 26 REG NA | |
N097. return | |
buildIntervals second part ======== | |
Int arg V00 in reg rdi | |
NEW BLOCK BB01 | |
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]> | |
at start of tree, map contains: { } | |
N003. nop | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
use: {V01 V02} | |
def: {V01 V02} | |
NEW BLOCK BB02 | |
Setting incoming variable registers of BB02 to outVarToRegMap of BB01 | |
<RefPosition #1 @5 RefTypeBB BB02 regmask=[]> | |
at start of tree, map contains: { } | |
N007. t7 = const(h) 0x7f95ea870610 token REG NA | |
consume=0 produce=1 | |
t7 = op | |
Def candidates [allInt], Use candidates [allInt] | |
Interval 4: RefPositions {} physReg:NA Preferences=[allInt] | |
<RefPosition #2 @8 RefTypeDef <Ivl:4> CNS_INT BB02 regmask=[allInt]> | |
<RefPosition #2 @8 RefTypeDef <Ivl:4> CNS_INT BB02 regmask=[allInt]> | |
at start of tree, map contains: { N007. const -> (8.N007) } | |
N009. indir | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { N009. indir -> (8.N007) } | |
N011. const 0 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { N009. indir -> (8.N007) } | |
N013. == | |
consume=1 produce=0 | |
op | |
t8 <RefPosition #3 @13 RefTypeUse <Ivl:4> BB02 regmask=[allInt]> | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N015. jmpTrue | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
use: {V01 V02} | |
def: {V01 V02} | |
NEW BLOCK BB03 | |
Setting incoming variable registers of BB03 to outVarToRegMap of BB02 | |
<RefPosition #4 @17 RefTypeBB BB03 regmask=[]> | |
at start of tree, map contains: { } | |
N019. call help | |
consume=0 produce=0 | |
op | |
Def candidates [rax], Use candidates [allInt] | |
<RefPosition #5 @20 RefTypeKill <Reg:rax> BB03 regmask=[rax]> | |
<RefPosition #6 @20 RefTypeKill <Reg:rcx> BB03 regmask=[rcx]> | |
<RefPosition #7 @20 RefTypeKill <Reg:rdx> BB03 regmask=[rdx]> | |
<RefPosition #8 @20 RefTypeKill <Reg:rsi> BB03 regmask=[rsi]> | |
<RefPosition #9 @20 RefTypeKill <Reg:rdi> BB03 regmask=[rdi]> | |
<RefPosition #10 @20 RefTypeKill <Reg:r8 > BB03 regmask=[r8]> | |
<RefPosition #11 @20 RefTypeKill <Reg:r9 > BB03 regmask=[r9]> | |
<RefPosition #12 @20 RefTypeKill <Reg:r10> BB03 regmask=[r10]> | |
<RefPosition #13 @20 RefTypeKill <Reg:r11> BB03 regmask=[r11]> | |
use: {V01 V02} | |
def: {V01 V02} | |
NEW BLOCK BB04 | |
Setting incoming variable registers of BB04 to outVarToRegMap of BB02 | |
<RefPosition #14 @21 RefTypeBB BB04 regmask=[]> | |
use: {V01 V02} | |
def: {V01 V02} | |
NEW BLOCK BB05 | |
Setting incoming variable registers of BB05 to outVarToRegMap of BB04 | |
<RefPosition #15 @23 RefTypeBB BB05 regmask=[]> | |
at start of tree, map contains: { } | |
N025. il_offset IL offset: 0 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N027. no_op REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N029. il_offset IL offset: 1 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N031. t31 = const 0 REG NA | |
consume=0 produce=1 | |
t31 = op | |
Def candidates [allInt], Use candidates [allInt] | |
Interval 5: RefPositions {} physReg:NA Preferences=[allInt] | |
<RefPosition #16 @32 RefTypeDef <Ivl:5> CNS_INT BB05 regmask=[allInt]> | |
<RefPosition #16 @32 RefTypeDef <Ivl:5> CNS_INT BB05 regmask=[allInt]> | |
at start of tree, map contains: { N031. const -> (32.N031) } | |
N033. V01 MEM | |
consume=1 produce=0 | |
op | |
t32 <RefPosition #17 @33 RefTypeUse <Ivl:5> BB05 regmask=[allInt]> | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N035. il_offset IL offset: 3 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N037. nop | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
use: {V01 V02} | |
def: {V01 V02} | |
NEW BLOCK BB07 | |
Setting incoming variable registers of BB07 to outVarToRegMap of BB05 | |
<RefPosition #18 @39 RefTypeBB BB07 regmask=[]> | |
at start of tree, map contains: { } | |
N041. il_offset IL offset: 18 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N043. t43 = V01 MEM | |
consume=0 produce=1 | |
t43 = op | |
Def candidates [allInt], Use candidates [allInt] | |
Interval 6: RefPositions {} physReg:NA Preferences=[allInt] | |
<RefPosition #19 @44 RefTypeDef <Ivl:6> LCL_VAR BB07 regmask=[allInt]> | |
<RefPosition #19 @44 RefTypeDef <Ivl:6> LCL_VAR BB07 regmask=[allInt]> | |
at start of tree, map contains: { N043. lclVar -> (44.N043) } | |
N045. const 3 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { N043. lclVar -> (44.N043) } | |
N047. t47 = < | |
consume=1 produce=1 | |
t47 = op | |
t44 <RefPosition #20 @47 RefTypeUse <Ivl:6> BB07 regmask=[allInt]> | |
Def candidates [allInt], Use candidates [allInt] | |
Interval 7: RefPositions {} physReg:NA Preferences=[allInt] | |
<RefPosition #21 @48 RefTypeDef <Ivl:7> LT BB07 regmask=[allInt]> | |
<RefPosition #21 @48 RefTypeDef <Ivl:7> LT BB07 regmask=[allInt]> | |
at start of tree, map contains: { N047. < -> (48.N047) } | |
N049. V02 MEM | |
consume=1 produce=0 | |
op | |
t48 <RefPosition #22 @49 RefTypeUse <Ivl:7> BB07 regmask=[allInt]> | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N051. il_offset IL offset: 23 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N053. t53 = V02 MEM | |
consume=0 produce=1 | |
t53 = op | |
Def candidates [allInt], Use candidates [allInt] | |
Interval 8: RefPositions {} physReg:NA Preferences=[allInt] | |
<RefPosition #23 @54 RefTypeDef <Ivl:8> LCL_VAR BB07 regmask=[allInt]> | |
<RefPosition #23 @54 RefTypeDef <Ivl:8> LCL_VAR BB07 regmask=[allInt]> | |
at start of tree, map contains: { N053. lclVar -> (54.N053) } | |
N055. const 0 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { N053. lclVar -> (54.N053) } | |
N057. != | |
consume=1 produce=0 | |
op | |
t54 <RefPosition #24 @57 RefTypeUse <Ivl:8> BB07 regmask=[allInt]> | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N059. jmpTrue | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
use: {V01 V02} | |
def: {V01 V02} | |
NEW BLOCK BB06 | |
Setting incoming variable registers of BB06 to outVarToRegMap of BB07 | |
<RefPosition #25 @61 RefTypeBB BB06 regmask=[]> | |
at start of tree, map contains: { } | |
N063. il_offset IL offset: 5 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N065. no_op REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N067. il_offset IL offset: 6 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N069. t69 = V01 MEM | |
consume=0 produce=1 | |
t69 = op | |
Def candidates [allInt], Use candidates [rdi] | |
Interval 9: RefPositions {} physReg:NA Preferences=[allInt] | |
<RefPosition #26 @70 RefTypeDef <Ivl:9> LCL_VAR BB06 regmask=[allInt]> | |
<RefPosition #26 @70 RefTypeDef <Ivl:9> LCL_VAR BB06 regmask=[allInt]> | |
at start of tree, map contains: { N069. lclVar -> (70.N069) } | |
N071. t71 = putarg_reg | |
consume=1 produce=1 | |
t71 = op | |
t70 <RefPosition #27 @71 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #28 @71 RefTypeUse <Ivl:9> BB06 regmask=[rdi] fixed> | |
Def candidates [rdi], Use candidates [rdi] | |
Interval 10: RefPositions {} physReg:NA Preferences=[allInt] | |
<RefPosition #29 @72 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #30 @72 RefTypeDef <Ivl:10> PUTARG_REG BB06 regmask=[rdi] fixed> | |
<RefPosition #30 @72 RefTypeDef <Ivl:10> PUTARG_REG BB06 regmask=[rdi] fixed> | |
at start of tree, map contains: { N071. putarg_reg -> (72.N071) } | |
N073. call | |
consume=1 produce=0 | |
op | |
t72 <RefPosition #31 @73 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #32 @73 RefTypeUse <Ivl:10> BB06 regmask=[rdi] fixed> | |
Def candidates [rax], Use candidates [allInt] | |
<RefPosition #33 @74 RefTypeKill <Reg:rax> BB06 regmask=[rax]> | |
<RefPosition #34 @74 RefTypeKill <Reg:rcx> BB06 regmask=[rcx]> | |
<RefPosition #35 @74 RefTypeKill <Reg:rdx> BB06 regmask=[rdx]> | |
<RefPosition #36 @74 RefTypeKill <Reg:rsi> BB06 regmask=[rsi]> | |
<RefPosition #37 @74 RefTypeKill <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #38 @74 RefTypeKill <Reg:r8 > BB06 regmask=[r8]> | |
<RefPosition #39 @74 RefTypeKill <Reg:r9 > BB06 regmask=[r9]> | |
<RefPosition #40 @74 RefTypeKill <Reg:r10> BB06 regmask=[r10]> | |
<RefPosition #41 @74 RefTypeKill <Reg:r11> BB06 regmask=[r11]> | |
at start of tree, map contains: { } | |
N075. il_offset IL offset: 12 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N077. no_op REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N079. il_offset IL offset: 13 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N081. no_op REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N083. il_offset IL offset: 14 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N085. t85 = V01 MEM | |
consume=0 produce=1 | |
t85 = op | |
Def candidates [allInt], Use candidates [allInt] | |
Interval 11: RefPositions {} physReg:NA Preferences=[allInt] | |
<RefPosition #42 @86 RefTypeDef <Ivl:11> LCL_VAR BB06 regmask=[allInt]> | |
<RefPosition #42 @86 RefTypeDef <Ivl:11> LCL_VAR BB06 regmask=[allInt]> | |
at start of tree, map contains: { N085. lclVar -> (86.N085) } | |
N087. const 1 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { N085. lclVar -> (86.N085) } | |
N089. t89 = + | |
consume=1 produce=1 | |
t89 = op | |
t86 <RefPosition #43 @89 RefTypeUse <Ivl:11> BB06 regmask=[allInt]> | |
Def candidates [allInt], Use candidates [allInt] | |
Interval 12: RefPositions {} physReg:NA Preferences=[allInt] | |
Assigning related <I11> to <I12> | |
<RefPosition #44 @90 RefTypeDef <Ivl:12> ADD BB06 regmask=[allInt]> | |
<RefPosition #44 @90 RefTypeDef <Ivl:12> ADD BB06 regmask=[allInt]> | |
at start of tree, map contains: { N089. + -> (90.N089) } | |
N091. V01 MEM | |
consume=1 produce=0 | |
op | |
t90 <RefPosition #45 @91 RefTypeUse <Ivl:12> BB06 regmask=[allInt]> | |
Def candidates [allInt], Use candidates [allInt] | |
use: {V01 V02} | |
def: {V01 V02} | |
NEW BLOCK BB08 | |
Setting incoming variable registers of BB08 to outVarToRegMap of BB07 | |
<RefPosition #46 @93 RefTypeBB BB08 regmask=[]> | |
at start of tree, map contains: { } | |
N095. il_offset IL offset: 26 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N097. return | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
Exposed uses: | |
use: {V01 V02} | |
def: {V01 V02} | |
Linear scan intervals BEFORE VALIDATING INTERVALS: | |
Interval 0: (V00) RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 1: (V01) RefPositions {} physReg:NA Preferences=[rbx r12-r15] | |
Interval 2: (V02) RefPositions {} physReg:NA Preferences=[rbx r12-r15] | |
Interval 3: (V03) RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 4: (constant) RefPositions {#2@8 #3@13} physReg:NA Preferences=[allInt] | |
Interval 5: (constant) RefPositions {#16@32 #17@33} physReg:NA Preferences=[allInt] | |
Interval 6: RefPositions {#19@44 #20@47} physReg:NA Preferences=[allInt] | |
Interval 7: RefPositions {#21@48 #22@49} physReg:NA Preferences=[allInt] | |
Interval 8: RefPositions {#23@54 #24@57} physReg:NA Preferences=[allInt] | |
Interval 9: RefPositions {#26@70 #28@71} physReg:NA Preferences=[rdi] | |
Interval 10: RefPositions {#30@72 #32@73} physReg:NA Preferences=[rdi] | |
Interval 11: RefPositions {#42@86 #43@89} physReg:NA Preferences=[allInt] | |
Interval 12: RefPositions {#44@90 #45@91} physReg:NA Preferences=[allInt] RelatedInterval <I11>[0000000002477558] | |
------------ | |
REFPOSITIONS BEFORE VALIDATING INTERVALS: | |
------------ | |
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]> | |
<RefPosition #1 @5 RefTypeBB BB02 regmask=[]> | |
<RefPosition #2 @8 ->#3 RefTypeDef <Ivl:4> CNS_INT BB02 regmask=[allInt]> | |
<RefPosition #3 @13 RefTypeUse <Ivl:4> BB02 regmask=[allInt] last> | |
<RefPosition #4 @17 RefTypeBB BB03 regmask=[]> | |
<RefPosition #5 @20 ->#33 RefTypeKill <Reg:rax> BB03 regmask=[rax] last> | |
<RefPosition #6 @20 ->#34 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] last> | |
<RefPosition #7 @20 ->#35 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] last> | |
<RefPosition #8 @20 ->#36 RefTypeKill <Reg:rsi> BB03 regmask=[rsi] last> | |
<RefPosition #9 @20 ->#27 RefTypeKill <Reg:rdi> BB03 regmask=[rdi] last> | |
<RefPosition #10 @20 ->#38 RefTypeKill <Reg:r8 > BB03 regmask=[r8] last> | |
<RefPosition #11 @20 ->#39 RefTypeKill <Reg:r9 > BB03 regmask=[r9] last> | |
<RefPosition #12 @20 ->#40 RefTypeKill <Reg:r10> BB03 regmask=[r10] last> | |
<RefPosition #13 @20 ->#41 RefTypeKill <Reg:r11> BB03 regmask=[r11] last> | |
<RefPosition #14 @21 RefTypeBB BB04 regmask=[]> | |
<RefPosition #15 @23 RefTypeBB BB05 regmask=[]> | |
<RefPosition #16 @32 ->#17 RefTypeDef <Ivl:5> CNS_INT BB05 regmask=[allInt]> | |
<RefPosition #17 @33 RefTypeUse <Ivl:5> BB05 regmask=[allInt] last> | |
<RefPosition #18 @39 RefTypeBB BB07 regmask=[]> | |
<RefPosition #19 @44 ->#20 RefTypeDef <Ivl:6> LCL_VAR BB07 regmask=[allInt]> | |
<RefPosition #20 @47 RefTypeUse <Ivl:6> BB07 regmask=[allInt] last> | |
<RefPosition #21 @48 ->#22 RefTypeDef <Ivl:7> LT BB07 regmask=[allInt]> | |
<RefPosition #22 @49 RefTypeUse <Ivl:7> BB07 regmask=[allInt] last> | |
<RefPosition #23 @54 ->#24 RefTypeDef <Ivl:8> LCL_VAR BB07 regmask=[allInt]> | |
<RefPosition #24 @57 RefTypeUse <Ivl:8> BB07 regmask=[allInt] last> | |
<RefPosition #25 @61 RefTypeBB BB06 regmask=[]> | |
<RefPosition #26 @70 ->#28 RefTypeDef <Ivl:9> LCL_VAR BB06 regmask=[rdi]> | |
<RefPosition #27 @71 ->#29 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #28 @71 RefTypeUse <Ivl:9> BB06 regmask=[rdi] last fixed> | |
<RefPosition #29 @72 ->#31 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #30 @72 ->#32 RefTypeDef <Ivl:10> PUTARG_REG BB06 regmask=[rdi] fixed> | |
<RefPosition #31 @73 ->#37 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #32 @73 RefTypeUse <Ivl:10> BB06 regmask=[rdi] last fixed> | |
<RefPosition #33 @74 RefTypeKill <Reg:rax> BB06 regmask=[rax] last> | |
<RefPosition #34 @74 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] last> | |
<RefPosition #35 @74 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] last> | |
<RefPosition #36 @74 RefTypeKill <Reg:rsi> BB06 regmask=[rsi] last> | |
<RefPosition #37 @74 RefTypeKill <Reg:rdi> BB06 regmask=[rdi] last> | |
<RefPosition #38 @74 RefTypeKill <Reg:r8 > BB06 regmask=[r8] last> | |
<RefPosition #39 @74 RefTypeKill <Reg:r9 > BB06 regmask=[r9] last> | |
<RefPosition #40 @74 RefTypeKill <Reg:r10> BB06 regmask=[r10] last> | |
<RefPosition #41 @74 RefTypeKill <Reg:r11> BB06 regmask=[r11] last> | |
<RefPosition #42 @86 ->#43 RefTypeDef <Ivl:11> LCL_VAR BB06 regmask=[allInt]> | |
<RefPosition #43 @89 RefTypeUse <Ivl:11> BB06 regmask=[allInt] last> | |
<RefPosition #44 @90 ->#45 RefTypeDef <Ivl:12> ADD BB06 regmask=[allInt]> | |
<RefPosition #45 @91 RefTypeUse <Ivl:12> BB06 regmask=[allInt] last> | |
<RefPosition #46 @93 RefTypeBB BB08 regmask=[]> | |
----------------- | |
----------------- | |
----------------- | |
----------------- | |
TUPLE STYLE DUMP WITH REF POSITIONS | |
Incoming Parameters: | |
BB01 [???..???), preds={} succs={BB02} | |
===== | |
N003. nop | |
BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
===== | |
N007. const(h) 0x7f95ea870610 token REG NA | |
Def:<I4>(#2) | |
N009. indir | |
N011. const 0 REG NA | |
N013. == | |
Use:<I4>(#3) * | |
N015. jmpTrue | |
BB03 [???..???), preds={BB02} succs={BB04} | |
===== | |
N019. call help | |
Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 | |
BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
===== | |
BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
===== | |
N025. il_offset IL offset: 0 REG NA | |
N027. no_op REG NA | |
N029. il_offset IL offset: 1 REG NA | |
N031. const 0 REG NA | |
Def:<I5>(#16) | |
N033. V01 MEM | |
Use:<I5>(#17) * | |
N035. il_offset IL offset: 3 REG NA | |
N037. nop | |
BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
===== | |
N041. il_offset IL offset: 18 REG NA | |
N043. V01 MEM | |
Def:<I6>(#19) | |
N045. const 3 REG NA | |
N047. < | |
Use:<I6>(#20) * | |
Def:<I7>(#21) | |
N049. V02 MEM | |
Use:<I7>(#22) * | |
N051. il_offset IL offset: 23 REG NA | |
N053. V02 MEM | |
Def:<I8>(#23) | |
N055. const 0 REG NA | |
N057. != | |
Use:<I8>(#24) * | |
N059. jmpTrue | |
BB06 [005..012), preds={BB07} succs={BB07} | |
===== | |
N063. il_offset IL offset: 5 REG NA | |
N065. no_op REG NA | |
N067. il_offset IL offset: 6 REG NA | |
N069. V01 MEM | |
Def:<I9>(#26) | |
N071. putarg_reg | |
Use:<I9>(#28) Fixed:rdi(#27) * | |
Def:<I10>(#30) rdi | |
N073. call | |
Use:<I10>(#32) Fixed:rdi(#31) * | |
Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 | |
N075. il_offset IL offset: 12 REG NA | |
N077. no_op REG NA | |
N079. il_offset IL offset: 13 REG NA | |
N081. no_op REG NA | |
N083. il_offset IL offset: 14 REG NA | |
N085. V01 MEM | |
Def:<I11>(#42) | |
N087. const 1 REG NA | |
N089. + | |
Use:<I11>(#43) * | |
Def:<I12>(#44) Pref:<I11> | |
N091. V01 MEM | |
Use:<I12>(#45) * | |
BB08 [01A..01B) (return), preds={BB07} succs={} | |
===== | |
N095. il_offset IL offset: 26 REG NA | |
N097. return | |
Linear scan intervals after buildIntervals: | |
Interval 0: (V00) RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 1: (V01) RefPositions {} physReg:NA Preferences=[rbx r12-r15] | |
Interval 2: (V02) RefPositions {} physReg:NA Preferences=[rbx r12-r15] | |
Interval 3: (V03) RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 4: (constant) RefPositions {#2@8 #3@13} physReg:NA Preferences=[allInt] | |
Interval 5: (constant) RefPositions {#16@32 #17@33} physReg:NA Preferences=[allInt] | |
Interval 6: RefPositions {#19@44 #20@47} physReg:NA Preferences=[allInt] | |
Interval 7: RefPositions {#21@48 #22@49} physReg:NA Preferences=[allInt] | |
Interval 8: RefPositions {#23@54 #24@57} physReg:NA Preferences=[allInt] | |
Interval 9: RefPositions {#26@70 #28@71} physReg:NA Preferences=[rdi] | |
Interval 10: RefPositions {#30@72 #32@73} physReg:NA Preferences=[rdi] | |
Interval 11: RefPositions {#42@86 #43@89} physReg:NA Preferences=[allInt] | |
Interval 12: RefPositions {#44@90 #45@91} physReg:NA Preferences=[allInt] RelatedInterval <I11>[0000000002477558] | |
*************** In LinearScan::allocateRegisters() | |
Linear scan intervals before allocateRegisters: | |
Interval 0: (V00) RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 1: (V01) RefPositions {} physReg:NA Preferences=[rbx r12-r15] | |
Interval 2: (V02) RefPositions {} physReg:NA Preferences=[rbx r12-r15] | |
Interval 3: (V03) RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 4: (constant) RefPositions {#2@8 #3@13} physReg:NA Preferences=[allInt] | |
Interval 5: (constant) RefPositions {#16@32 #17@33} physReg:NA Preferences=[allInt] | |
Interval 6: RefPositions {#19@44 #20@47} physReg:NA Preferences=[allInt] | |
Interval 7: RefPositions {#21@48 #22@49} physReg:NA Preferences=[allInt] | |
Interval 8: RefPositions {#23@54 #24@57} physReg:NA Preferences=[allInt] | |
Interval 9: RefPositions {#26@70 #28@71} physReg:NA Preferences=[rdi] | |
Interval 10: RefPositions {#30@72 #32@73} physReg:NA Preferences=[rdi] | |
Interval 11: RefPositions {#42@86 #43@89} physReg:NA Preferences=[allInt] | |
Interval 12: RefPositions {#44@90 #45@91} physReg:NA Preferences=[allInt] RelatedInterval <I11>[0000000002477558] | |
------------ | |
REFPOSITIONS BEFORE ALLOCATION: | |
------------ | |
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]> | |
<RefPosition #1 @5 RefTypeBB BB02 regmask=[]> | |
<RefPosition #2 @8 ->#3 RefTypeDef <Ivl:4> CNS_INT BB02 regmask=[allInt]> | |
<RefPosition #3 @13 RefTypeUse <Ivl:4> BB02 regmask=[allInt] last> | |
<RefPosition #4 @17 RefTypeBB BB03 regmask=[]> | |
<RefPosition #5 @20 ->#33 RefTypeKill <Reg:rax> BB03 regmask=[rax] last> | |
<RefPosition #6 @20 ->#34 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] last> | |
<RefPosition #7 @20 ->#35 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] last> | |
<RefPosition #8 @20 ->#36 RefTypeKill <Reg:rsi> BB03 regmask=[rsi] last> | |
<RefPosition #9 @20 ->#27 RefTypeKill <Reg:rdi> BB03 regmask=[rdi] last> | |
<RefPosition #10 @20 ->#38 RefTypeKill <Reg:r8 > BB03 regmask=[r8] last> | |
<RefPosition #11 @20 ->#39 RefTypeKill <Reg:r9 > BB03 regmask=[r9] last> | |
<RefPosition #12 @20 ->#40 RefTypeKill <Reg:r10> BB03 regmask=[r10] last> | |
<RefPosition #13 @20 ->#41 RefTypeKill <Reg:r11> BB03 regmask=[r11] last> | |
<RefPosition #14 @21 RefTypeBB BB04 regmask=[]> | |
<RefPosition #15 @23 RefTypeBB BB05 regmask=[]> | |
<RefPosition #16 @32 ->#17 RefTypeDef <Ivl:5> CNS_INT BB05 regmask=[allInt]> | |
<RefPosition #17 @33 RefTypeUse <Ivl:5> BB05 regmask=[allInt] last> | |
<RefPosition #18 @39 RefTypeBB BB07 regmask=[]> | |
<RefPosition #19 @44 ->#20 RefTypeDef <Ivl:6> LCL_VAR BB07 regmask=[allInt]> | |
<RefPosition #20 @47 RefTypeUse <Ivl:6> BB07 regmask=[allInt] last> | |
<RefPosition #21 @48 ->#22 RefTypeDef <Ivl:7> LT BB07 regmask=[allInt]> | |
<RefPosition #22 @49 RefTypeUse <Ivl:7> BB07 regmask=[allInt] last> | |
<RefPosition #23 @54 ->#24 RefTypeDef <Ivl:8> LCL_VAR BB07 regmask=[allInt]> | |
<RefPosition #24 @57 RefTypeUse <Ivl:8> BB07 regmask=[allInt] last> | |
<RefPosition #25 @61 RefTypeBB BB06 regmask=[]> | |
<RefPosition #26 @70 ->#28 RefTypeDef <Ivl:9> LCL_VAR BB06 regmask=[rdi]> | |
<RefPosition #27 @71 ->#29 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #28 @71 RefTypeUse <Ivl:9> BB06 regmask=[rdi] last fixed> | |
<RefPosition #29 @72 ->#31 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #30 @72 ->#32 RefTypeDef <Ivl:10> PUTARG_REG BB06 regmask=[rdi] fixed> | |
<RefPosition #31 @73 ->#37 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #32 @73 RefTypeUse <Ivl:10> BB06 regmask=[rdi] last fixed> | |
<RefPosition #33 @74 RefTypeKill <Reg:rax> BB06 regmask=[rax] last> | |
<RefPosition #34 @74 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] last> | |
<RefPosition #35 @74 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] last> | |
<RefPosition #36 @74 RefTypeKill <Reg:rsi> BB06 regmask=[rsi] last> | |
<RefPosition #37 @74 RefTypeKill <Reg:rdi> BB06 regmask=[rdi] last> | |
<RefPosition #38 @74 RefTypeKill <Reg:r8 > BB06 regmask=[r8] last> | |
<RefPosition #39 @74 RefTypeKill <Reg:r9 > BB06 regmask=[r9] last> | |
<RefPosition #40 @74 RefTypeKill <Reg:r10> BB06 regmask=[r10] last> | |
<RefPosition #41 @74 RefTypeKill <Reg:r11> BB06 regmask=[r11] last> | |
<RefPosition #42 @86 ->#43 RefTypeDef <Ivl:11> LCL_VAR BB06 regmask=[allInt]> | |
<RefPosition #43 @89 RefTypeUse <Ivl:11> BB06 regmask=[allInt] last> | |
<RefPosition #44 @90 ->#45 RefTypeDef <Ivl:12> ADD BB06 regmask=[allInt]> | |
<RefPosition #45 @91 RefTypeUse <Ivl:12> BB06 regmask=[allInt] last> | |
<RefPosition #46 @93 RefTypeBB BB08 regmask=[]> | |
VAR REFPOSITIONS BEFORE ALLOCATION | |
--- V00 | |
--- V01 | |
--- V02 | |
--- V03 | |
Allocating Registers | |
-------------------- | |
The following table has one or more rows for each RefPosition that is handled during allocation. | |
The first column provides the basic information about the RefPosition, with its type (e.g. Def, | |
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the | |
action taken during allocation (e.g. Alloc a new register, or Keep an existing one). | |
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is | |
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which | |
may increase during allocation, in which case additional columns will appear. Registers which are | |
not marked modified have ---- in their column. | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
| | | |----|----|----| | | | | | | | |
0.#0 BB1 PredBB0 | | | |----|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
5.#1 BB2 PredBB1 | | | |----|----|----| | | | | | | | |
8.#2 C4 Def Alloc rax |C4 a| | |----|----|----| | | | | | | | |
13.#3 C4 Use * Keep rax |C4 a| | |----|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
17.#4 BB3 PredBB2 | | | |----|----|----| | | | | | | | |
20.#5 rax Kill Keep rax | | | |----|----|----| | | | | | | | |
20.#6 rcx Kill Keep rcx | | | |----|----|----| | | | | | | | |
20.#7 rdx Kill Keep rdx | | | |----|----|----| | | | | | | | |
20.#8 rsi Kill Keep rsi | | | |----|----|----| | | | | | | | |
20.#9 rdi Kill Keep rdi | | | |----|----|----| | | | | | | | |
20.#10 r8 Kill Keep r8 | | | |----|----|----| | | | | | | | |
20.#11 r9 Kill Keep r9 | | | |----|----|----| | | | | | | | |
20.#12 r10 Kill Keep r10 | | | |----|----|----| | | | | | | | |
20.#13 r11 Kill Keep r11 | | | |----|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
21.#14 BB4 PredBB2 | | | |----|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
23.#15 BB5 PredBB4 | | | |----|----|----| | | | | | | | |
32.#16 C5 Def Alloc rdi | | | |----|----|----| |C5 a| | | | | | |
33.#17 C5 Use * Keep rdi | | | |----|----|----| |C5 a| | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
39.#18 BB7 PredBB5 | | | |----|----|----| | | | | | | | |
44.#19 I6 Def Alloc rdi | | | |----|----|----| |I6 a| | | | | | |
47.#20 I6 Use * Keep rdi | | | |----|----|----| |I6 a| | | | | | |
48.#21 I7 Def Alloc rdi | | | |----|----|----| |I7 a| | | | | | |
49.#22 I7 Use * Keep rdi | | | |----|----|----| |I7 a| | | | | | |
54.#23 I8 Def Alloc rdi | | | |----|----|----| |I8 a| | | | | | |
57.#24 I8 Use * Keep rdi | | | |----|----|----| |I8 a| | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
61.#25 BB6 PredBB7 | | | |----|----|----| | | | | | | | |
70.#26 I9 Def Alloc rdi | | | |----|----|----| |I9 a| | | | | | |
71.#27 rdi Fixd Keep rdi | | | |----|----|----| |I9 a| | | | | | |
71.#28 I9 Use * Keep rdi | | | |----|----|----| |I9 a| | | | | | |
72.#29 rdi Fixd Keep rdi | | | |----|----|----| | | | | | | | |
72.#30 I10 Def Alloc rdi | | | |----|----|----| |I10a| | | | | | |
73.#31 rdi Fixd Keep rdi | | | |----|----|----| |I10a| | | | | | |
73.#32 I10 Use * Keep rdi | | | |----|----|----| |I10a| | | | | | |
74.#33 rax Kill Keep rax | | | |----|----|----| | | | | | | | |
74.#34 rcx Kill Keep rcx | | | |----|----|----| | | | | | | | |
74.#35 rdx Kill Keep rdx | | | |----|----|----| | | | | | | | |
74.#36 rsi Kill Keep rsi | | | |----|----|----| | | | | | | | |
74.#37 rdi Kill Keep rdi | | | |----|----|----| | | | | | | | |
74.#38 r8 Kill Keep r8 | | | |----|----|----| | | | | | | | |
74.#39 r9 Kill Keep r9 | | | |----|----|----| | | | | | | | |
74.#40 r10 Kill Keep r10 | | | |----|----|----| | | | | | | | |
74.#41 r11 Kill Keep r11 | | | |----|----|----| | | | | | | | |
86.#42 I11 Def Alloc rax |I11a| | |----|----|----| | | | | | | | |
89.#43 I11 Use * Keep rax |I11a| | |----|----|----| | | | | | | | |
90.#44 I12 Def Alloc rax |I12a| | |----|----|----| | | | | | | | |
91.#45 I12 Use * Keep rax |I12a| | |----|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
93.#46 BB8 PredBB7 | | | |----|----|----| | | | | | | | |
------------ | |
REFPOSITIONS AFTER ALLOCATION: | |
------------ | |
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]> | |
<RefPosition #1 @5 RefTypeBB BB02 regmask=[]> | |
<RefPosition #2 @8 ->#3 RefTypeDef <Ivl:4> CNS_INT BB02 regmask=[rax]> | |
<RefPosition #3 @13 RefTypeUse <Ivl:4> BB02 regmask=[rax] last> | |
<RefPosition #4 @17 RefTypeBB BB03 regmask=[]> | |
<RefPosition #5 @20 ->#33 RefTypeKill <Reg:rax> BB03 regmask=[rax] last> | |
<RefPosition #6 @20 ->#34 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] last> | |
<RefPosition #7 @20 ->#35 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] last> | |
<RefPosition #8 @20 ->#36 RefTypeKill <Reg:rsi> BB03 regmask=[rsi] last> | |
<RefPosition #9 @20 ->#27 RefTypeKill <Reg:rdi> BB03 regmask=[rdi] last> | |
<RefPosition #10 @20 ->#38 RefTypeKill <Reg:r8 > BB03 regmask=[r8] last> | |
<RefPosition #11 @20 ->#39 RefTypeKill <Reg:r9 > BB03 regmask=[r9] last> | |
<RefPosition #12 @20 ->#40 RefTypeKill <Reg:r10> BB03 regmask=[r10] last> | |
<RefPosition #13 @20 ->#41 RefTypeKill <Reg:r11> BB03 regmask=[r11] last> | |
<RefPosition #14 @21 RefTypeBB BB04 regmask=[]> | |
<RefPosition #15 @23 RefTypeBB BB05 regmask=[]> | |
<RefPosition #16 @32 ->#17 RefTypeDef <Ivl:5> CNS_INT BB05 regmask=[rdi]> | |
<RefPosition #17 @33 RefTypeUse <Ivl:5> BB05 regmask=[rdi] last> | |
<RefPosition #18 @39 RefTypeBB BB07 regmask=[]> | |
<RefPosition #19 @44 ->#20 RefTypeDef <Ivl:6> LCL_VAR BB07 regmask=[rdi]> | |
<RefPosition #20 @47 RefTypeUse <Ivl:6> BB07 regmask=[rdi] last> | |
<RefPosition #21 @48 ->#22 RefTypeDef <Ivl:7> LT BB07 regmask=[rdi]> | |
<RefPosition #22 @49 RefTypeUse <Ivl:7> BB07 regmask=[rdi] last> | |
<RefPosition #23 @54 ->#24 RefTypeDef <Ivl:8> LCL_VAR BB07 regmask=[rdi]> | |
<RefPosition #24 @57 RefTypeUse <Ivl:8> BB07 regmask=[rdi] last> | |
<RefPosition #25 @61 RefTypeBB BB06 regmask=[]> | |
<RefPosition #26 @70 ->#28 RefTypeDef <Ivl:9> LCL_VAR BB06 regmask=[rdi]> | |
<RefPosition #27 @71 ->#29 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #28 @71 RefTypeUse <Ivl:9> BB06 regmask=[rdi] last fixed> | |
<RefPosition #29 @72 ->#31 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #30 @72 ->#32 RefTypeDef <Ivl:10> PUTARG_REG BB06 regmask=[rdi] fixed> | |
<RefPosition #31 @73 ->#37 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
<RefPosition #32 @73 RefTypeUse <Ivl:10> BB06 regmask=[rdi] last fixed> | |
<RefPosition #33 @74 RefTypeKill <Reg:rax> BB06 regmask=[rax] last> | |
<RefPosition #34 @74 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] last> | |
<RefPosition #35 @74 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] last> | |
<RefPosition #36 @74 RefTypeKill <Reg:rsi> BB06 regmask=[rsi] last> | |
<RefPosition #37 @74 RefTypeKill <Reg:rdi> BB06 regmask=[rdi] last> | |
<RefPosition #38 @74 RefTypeKill <Reg:r8 > BB06 regmask=[r8] last> | |
<RefPosition #39 @74 RefTypeKill <Reg:r9 > BB06 regmask=[r9] last> | |
<RefPosition #40 @74 RefTypeKill <Reg:r10> BB06 regmask=[r10] last> | |
<RefPosition #41 @74 RefTypeKill <Reg:r11> BB06 regmask=[r11] last> | |
<RefPosition #42 @86 ->#43 RefTypeDef <Ivl:11> LCL_VAR BB06 regmask=[rax]> | |
<RefPosition #43 @89 RefTypeUse <Ivl:11> BB06 regmask=[rax] last> | |
<RefPosition #44 @90 ->#45 RefTypeDef <Ivl:12> ADD BB06 regmask=[rax]> | |
<RefPosition #45 @91 RefTypeUse <Ivl:12> BB06 regmask=[rax] last> | |
<RefPosition #46 @93 RefTypeBB BB08 regmask=[]> | |
VAR REFPOSITIONS AFTER ALLOCATION | |
--- V00 | |
--- V01 | |
--- V02 | |
--- V03 | |
Active intervals at end of allocation: | |
------------------------ | |
WRITING BACK ASSIGNMENTS | |
------------------------ | |
BB01 [???..???), preds={} succs={BB02} | |
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]> | |
BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
<RefPosition #1 @5 RefTypeBB BB02 regmask=[]> | |
current : <RefPosition #2 @8 ->#3 RefTypeDef <Ivl:4> CNS_INT BB02 regmask=[rax]> | |
N007. t7 = const(h) 0x7f95ea870610 token REG NA | |
curr = 8 mapped = 7 | |
current : <RefPosition #3 @13 RefTypeUse <Ivl:4> BB02 regmask=[rax] last> | |
No tree node to write back to | |
BB03 [???..???), preds={BB02} succs={BB04} | |
<RefPosition #4 @17 RefTypeBB BB03 regmask=[]> | |
current : <RefPosition #5 @20 ->#33 RefTypeKill <Reg:rax> BB03 regmask=[rax] last> | |
current : <RefPosition #6 @20 ->#34 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] last> | |
current : <RefPosition #7 @20 ->#35 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] last> | |
current : <RefPosition #8 @20 ->#36 RefTypeKill <Reg:rsi> BB03 regmask=[rsi] last> | |
current : <RefPosition #9 @20 ->#27 RefTypeKill <Reg:rdi> BB03 regmask=[rdi] last> | |
current : <RefPosition #10 @20 ->#38 RefTypeKill <Reg:r8 > BB03 regmask=[r8] last> | |
current : <RefPosition #11 @20 ->#39 RefTypeKill <Reg:r9 > BB03 regmask=[r9] last> | |
current : <RefPosition #12 @20 ->#40 RefTypeKill <Reg:r10> BB03 regmask=[r10] last> | |
current : <RefPosition #13 @20 ->#41 RefTypeKill <Reg:r11> BB03 regmask=[r11] last> | |
BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
<RefPosition #14 @21 RefTypeBB BB04 regmask=[]> | |
BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
<RefPosition #15 @23 RefTypeBB BB05 regmask=[]> | |
current : <RefPosition #16 @32 ->#17 RefTypeDef <Ivl:5> CNS_INT BB05 regmask=[rdi]> | |
N031. t31 = const 0 REG NA | |
curr = 32 mapped = 31 | |
current : <RefPosition #17 @33 RefTypeUse <Ivl:5> BB05 regmask=[rdi] last> | |
No tree node to write back to | |
BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
<RefPosition #18 @39 RefTypeBB BB07 regmask=[]> | |
current : <RefPosition #19 @44 ->#20 RefTypeDef <Ivl:6> LCL_VAR BB07 regmask=[rdi]> | |
N043. t43 = V01 MEM | |
curr = 44 mapped = 43 | |
current : <RefPosition #20 @47 RefTypeUse <Ivl:6> BB07 regmask=[rdi] last> | |
No tree node to write back to | |
current : <RefPosition #21 @48 ->#22 RefTypeDef <Ivl:7> LT BB07 regmask=[rdi]> | |
N047. t47 = < | |
curr = 48 mapped = 47 | |
current : <RefPosition #22 @49 RefTypeUse <Ivl:7> BB07 regmask=[rdi] last> | |
No tree node to write back to | |
current : <RefPosition #23 @54 ->#24 RefTypeDef <Ivl:8> LCL_VAR BB07 regmask=[rdi]> | |
N053. t53 = V02 MEM | |
curr = 54 mapped = 53 | |
current : <RefPosition #24 @57 RefTypeUse <Ivl:8> BB07 regmask=[rdi] last> | |
No tree node to write back to | |
BB06 [005..012), preds={BB07} succs={BB07} | |
<RefPosition #25 @61 RefTypeBB BB06 regmask=[]> | |
current : <RefPosition #26 @70 ->#28 RefTypeDef <Ivl:9> LCL_VAR BB06 regmask=[rdi]> | |
N069. t69 = V01 MEM | |
curr = 70 mapped = 69 | |
current : <RefPosition #27 @71 ->#29 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
current : <RefPosition #28 @71 RefTypeUse <Ivl:9> BB06 regmask=[rdi] last fixed> | |
No tree node to write back to | |
current : <RefPosition #29 @72 ->#31 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
current : <RefPosition #30 @72 ->#32 RefTypeDef <Ivl:10> PUTARG_REG BB06 regmask=[rdi] fixed> | |
N071. t71 = putarg_reg | |
curr = 72 mapped = 71 | |
current : <RefPosition #31 @73 ->#37 RefTypeFixedReg <Reg:rdi> BB06 regmask=[rdi]> | |
current : <RefPosition #32 @73 RefTypeUse <Ivl:10> BB06 regmask=[rdi] last fixed> | |
No tree node to write back to | |
current : <RefPosition #33 @74 RefTypeKill <Reg:rax> BB06 regmask=[rax] last> | |
current : <RefPosition #34 @74 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] last> | |
current : <RefPosition #35 @74 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] last> | |
current : <RefPosition #36 @74 RefTypeKill <Reg:rsi> BB06 regmask=[rsi] last> | |
current : <RefPosition #37 @74 RefTypeKill <Reg:rdi> BB06 regmask=[rdi] last> | |
current : <RefPosition #38 @74 RefTypeKill <Reg:r8 > BB06 regmask=[r8] last> | |
current : <RefPosition #39 @74 RefTypeKill <Reg:r9 > BB06 regmask=[r9] last> | |
current : <RefPosition #40 @74 RefTypeKill <Reg:r10> BB06 regmask=[r10] last> | |
current : <RefPosition #41 @74 RefTypeKill <Reg:r11> BB06 regmask=[r11] last> | |
current : <RefPosition #42 @86 ->#43 RefTypeDef <Ivl:11> LCL_VAR BB06 regmask=[rax]> | |
N085. t85 = V01 MEM | |
curr = 86 mapped = 85 | |
current : <RefPosition #43 @89 RefTypeUse <Ivl:11> BB06 regmask=[rax] last> | |
No tree node to write back to | |
current : <RefPosition #44 @90 ->#45 RefTypeDef <Ivl:12> ADD BB06 regmask=[rax]> | |
N089. t89 = + | |
curr = 90 mapped = 89 | |
current : <RefPosition #45 @91 RefTypeUse <Ivl:12> BB06 regmask=[rax] last> | |
No tree node to write back to | |
BB08 [01A..01B) (return), preds={BB07} succs={} | |
<RefPosition #46 @93 RefTypeBB BB08 regmask=[]> | |
----------------------- | |
RESOLVING BB BOUNDARIES | |
----------------------- | |
Prior to Resolution | |
BB01 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
Var=Reg beg of BB01: none | |
Var=Reg end of BB01: none | |
BB02 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
Var=Reg beg of BB02: none | |
Var=Reg end of BB02: none | |
BB03 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
Var=Reg beg of BB03: none | |
Var=Reg end of BB03: none | |
BB04 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
Var=Reg beg of BB04: none | |
Var=Reg end of BB04: none | |
BB05 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
Var=Reg beg of BB05: none | |
Var=Reg end of BB05: none | |
BB06 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
Var=Reg beg of BB06: none | |
Var=Reg end of BB06: none | |
BB07 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
Var=Reg beg of BB07: none | |
Var=Reg end of BB07: none | |
BB08 use def in out | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
{V01 V02} | |
Var=Reg beg of BB08: none | |
Var=Reg end of BB08: none | |
RESOLVING EDGES | |
Trees after linear scan register allocator (LSRA) | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target LIR | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal LIR | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target LIR | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i LIR | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd LIR | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd LIR | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [???..???), preds={} succs={BB02} | |
N003 ( 0, 0) [000000] ------------ nop void REG NA | |
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
N007 ( 3, 10) [000043] ------------ t43 = const(h) long 0x7f95ea870610 token REG rax | |
/--* t43 long | |
N009 ( 5, 12) [000044] ------------ t44 = * indir int REG NA | |
N011 ( 1, 1) [000045] ------------ t45 = const int 0 REG NA | |
/--* t44 int | |
+--* t45 int | |
N013 ( 7, 14) [000046] J------N---- t46 = * == int REG NA | |
/--* t46 int | |
N015 ( 9, 16) [000054] ------------ * jmpTrue void REG NA | |
------------ BB03 [???..???), preds={BB02} succs={BB04} | |
N019 ( 14, 5) [000047] --C-G-?----- call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
------------ BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
------------ BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
N025 ( 1, 1) [000004] ------------ il_offset void IL offset: 0 REG NA | |
N027 ( 1, 1) [000003] ------------ no_op void REG NA | |
N029 ( 1, 3) [000008] ------------ il_offset void IL offset: 1 REG NA | |
N031 ( 1, 1) [000005] ------------ t5 = const int 0 REG rdi | |
/--* t5 int | |
N033 ( 1, 3) [000007] DA---------- * st.lclVar int V01 loc0 REG NA | |
N035 ( 0, 0) [000010] ------------ il_offset void IL offset: 3 REG NA | |
N037 ( 0, 0) [000009] ------------ nop void REG NA | |
------------ BB06 [005..012), preds={BB07} succs={BB07} | |
N063 ( 1, 1) [000025] ------------ il_offset void IL offset: 5 REG NA | |
N065 ( 1, 1) [000024] ------------ no_op void REG NA | |
N067 ( 15, 7) [000029] ------------ il_offset void IL offset: 6 REG NA | |
N069 ( 1, 1) [000026] ------------ t26 = lclVar int V01 loc0 REG rdi | |
/--* t26 int | |
N071 (???,???) [000057] ------------ t57 = * putarg_reg int REG rdi | |
/--* t57 int arg0 in rdi | |
N073 ( 15, 7) [000027] --C-G------- * call void System.Console.WriteLine | |
N075 ( 1, 1) [000031] ------------ il_offset void IL offset: 12 REG NA | |
N077 ( 1, 1) [000030] ------------ no_op void REG NA | |
N079 ( 1, 1) [000033] ------------ il_offset void IL offset: 13 REG NA | |
N081 ( 1, 1) [000032] ------------ no_op void REG NA | |
N083 ( 3, 3) [000039] ------------ il_offset void IL offset: 14 REG NA | |
N085 ( 1, 1) [000034] ------------ t34 = lclVar int V01 loc0 REG rax | |
N087 ( 1, 1) [000035] ------------ t35 = const int 1 REG NA | |
/--* t34 int | |
+--* t35 int | |
N089 ( 3, 3) [000036] ------------ t36 = * + int REG rax | |
/--* t36 int | |
N091 ( 3, 3) [000038] DA---------- * st.lclVar int V01 loc0 REG NA | |
------------ BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
N041 ( 10, 6) [000017] ------------ il_offset void IL offset: 18 REG NA | |
N043 ( 1, 1) [000012] ------------ t12 = lclVar int V01 loc0 REG rdi | |
N045 ( 1, 1) [000013] ------------ t13 = const int 3 REG NA | |
/--* t12 int | |
+--* t13 int | |
N047 ( 6, 3) [000014] ------------ t14 = * < int REG rdi | |
/--* t14 int | |
N049 ( 10, 6) [000016] DA---------- * st.lclVar int V02 loc1 REG NA | |
N051 ( 7, 6) [000022] ------------ il_offset void IL offset: 23 REG NA | |
N053 ( 3, 2) [000018] ------------ t18 = lclVar int V02 loc1 REG rdi | |
N055 ( 1, 1) [000019] ------------ t19 = const int 0 REG NA | |
/--* t18 int | |
+--* t19 int | |
N057 ( 5, 4) [000020] J------N---- t20 = * != int REG NA | |
/--* t20 int | |
N059 ( 7, 6) [000021] ------------ * jmpTrue void REG NA | |
------------ BB08 [01A..01B) (return), preds={BB07} succs={} | |
N095 ( 0, 0) [000042] ------------ il_offset void IL offset: 26 REG NA | |
N097 ( 0, 0) [000041] ------------ return void REG NA | |
------------------------------------------------------------------------------------------------------------------- | |
Final allocation | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
0.#0 BB1 PredBB0 | | | |----|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
5.#1 BB2 PredBB1 | | | |----|----|----| | | | | | | | |
8.#2 C4 Def Alloc rax |C4 a| | |----|----|----| | | | | | | | |
13.#3 C4 Use * Keep rax |C4 i| | |----|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
17.#4 BB3 PredBB2 | | | |----|----|----| | | | | | | | |
20.#5 rax Kill Keep rax | | | |----|----|----| | | | | | | | |
20.#6 rcx Kill Keep rcx | | | |----|----|----| | | | | | | | |
20.#7 rdx Kill Keep rdx | | | |----|----|----| | | | | | | | |
20.#8 rsi Kill Keep rsi | | | |----|----|----| | | | | | | | |
20.#9 rdi Kill Keep rdi | | | |----|----|----| | | | | | | | |
20.#10 r8 Kill Keep r8 | | | |----|----|----| | | | | | | | |
20.#11 r9 Kill Keep r9 | | | |----|----|----| | | | | | | | |
20.#12 r10 Kill Keep r10 | | | |----|----|----| | | | | | | | |
20.#13 r11 Kill Keep r11 | | | |----|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
21.#14 BB4 PredBB2 | | | |----|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
23.#15 BB5 PredBB4 | | | |----|----|----| | | | | | | | |
32.#16 C5 Def Alloc rdi | | | |----|----|----| |C5 a| | | | | | |
33.#17 C5 Use * Keep rdi | | | |----|----|----| |C5 i| | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
39.#18 BB7 PredBB5 | | | |----|----|----| | | | | | | | |
44.#19 I6 Def Alloc rdi | | | |----|----|----| |I6 a| | | | | | |
47.#20 I6 Use * Keep rdi | | | |----|----|----| |I6 i| | | | | | |
48.#21 I7 Def Alloc rdi | | | |----|----|----| |I7 a| | | | | | |
49.#22 I7 Use * Keep rdi | | | |----|----|----| |I7 i| | | | | | |
54.#23 I8 Def Alloc rdi | | | |----|----|----| |I8 a| | | | | | |
57.#24 I8 Use * Keep rdi | | | |----|----|----| |I8 i| | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
61.#25 BB6 PredBB7 | | | |----|----|----| | | | | | | | |
70.#26 I9 Def Alloc rdi | | | |----|----|----| |I9 a| | | | | | |
71.#27 rdi Fixd Keep rdi | | | |----|----|----| |I9 a| | | | | | |
71.#28 I9 Use * Keep rdi | | | |----|----|----| |I9 i| | | | | | |
72.#29 rdi Fixd Keep rdi | | | |----|----|----| | | | | | | | |
72.#30 I10 Def Alloc rdi | | | |----|----|----| |I10a| | | | | | |
73.#31 rdi Fixd Keep rdi | | | |----|----|----| |I10a| | | | | | |
73.#32 I10 Use * Keep rdi | | | |----|----|----| |I10i| | | | | | |
74.#33 rax Kill Keep rax | | | |----|----|----| | | | | | | | |
74.#34 rcx Kill Keep rcx | | | |----|----|----| | | | | | | | |
74.#35 rdx Kill Keep rdx | | | |----|----|----| | | | | | | | |
74.#36 rsi Kill Keep rsi | | | |----|----|----| | | | | | | | |
74.#37 rdi Kill Keep rdi | | | |----|----|----| | | | | | | | |
74.#38 r8 Kill Keep r8 | | | |----|----|----| | | | | | | | |
74.#39 r9 Kill Keep r9 | | | |----|----|----| | | | | | | | |
74.#40 r10 Kill Keep r10 | | | |----|----|----| | | | | | | | |
74.#41 r11 Kill Keep r11 | | | |----|----|----| | | | | | | | |
86.#42 I11 Def Alloc rax |I11a| | |----|----|----| | | | | | | | |
89.#43 I11 Use * Keep rax |I11i| | |----|----|----| | | | | | | | |
90.#44 I12 Def Alloc rax |I12a| | |----|----|----| | | | | | | | |
91.#45 I12 Use * Keep rax |I12i| | |----|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
93.#46 BB8 PredBB7 | | | |----|----|----| | | | | | | | |
Recording the maximum number of concurrent spills: | |
<UNDEF>: 0 | |
void: 0 | |
bool: 0 | |
byte: 0 | |
ubyte: 0 | |
char: 0 | |
short: 0 | |
ushort: 0 | |
int: 0 | |
uint: 0 | |
long: 0 | |
ulong: 0 | |
float: 0 | |
double: 0 | |
ref: 0 | |
byref: 0 | |
array: 0 | |
struct: 0 | |
blk: 0 | |
lclBlk: 0 | |
pointer: 0 | |
function: 0 | |
simd8: 0 | |
simd12: 0 | |
simd16: 0 | |
simd32: 0 | |
unknown: 0 | |
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS | |
Incoming Parameters: | |
BB01 [???..???), preds={} succs={BB02} | |
===== | |
N003. nop | |
Var=Reg end of BB01: none | |
BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} | |
===== | |
Predecessor for variable locations: BB01 | |
Var=Reg beg of BB02: none | |
N007. rax = const(h) 0x7f95ea870610 token REG rax | |
N009. indir | |
N011. const 0 REG NA | |
N013. == ; rax | |
N015. jmpTrue | |
Var=Reg end of BB02: none | |
BB03 [???..???), preds={BB02} succs={BB04} | |
===== | |
Predecessor for variable locations: BB02 | |
Var=Reg beg of BB03: none | |
N019. call help | |
Var=Reg end of BB03: none | |
BB04 [???..???), preds={BB02,BB03} succs={BB05} | |
===== | |
Predecessor for variable locations: BB02 | |
Var=Reg beg of BB04: none | |
Var=Reg end of BB04: none | |
BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} | |
===== | |
Predecessor for variable locations: BB04 | |
Var=Reg beg of BB05: none | |
N025. il_offset IL offset: 0 REG NA | |
N027. no_op REG NA | |
N029. il_offset IL offset: 1 REG NA | |
N031. rdi = const 0 REG rdi | |
N033. V01 MEM; rdi | |
N035. il_offset IL offset: 3 REG NA | |
N037. nop | |
Var=Reg end of BB05: none | |
BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} | |
===== | |
Predecessor for variable locations: BB05 | |
Var=Reg beg of BB07: none | |
N041. il_offset IL offset: 18 REG NA | |
N043. rdi = V01 MEM | |
N045. const 3 REG NA | |
N047. rdi = < ; rdi | |
N049. V02 MEM; rdi | |
N051. il_offset IL offset: 23 REG NA | |
N053. rdi = V02 MEM | |
N055. const 0 REG NA | |
N057. != ; rdi | |
N059. jmpTrue | |
Var=Reg end of BB07: none | |
BB06 [005..012), preds={BB07} succs={BB07} | |
===== | |
Predecessor for variable locations: BB07 | |
Var=Reg beg of BB06: none | |
N063. il_offset IL offset: 5 REG NA | |
N065. no_op REG NA | |
N067. il_offset IL offset: 6 REG NA | |
N069. rdi = V01 MEM | |
N071. rdi = putarg_reg; rdi | |
N073. call ; rdi | |
N075. il_offset IL offset: 12 REG NA | |
N077. no_op REG NA | |
N079. il_offset IL offset: 13 REG NA | |
N081. no_op REG NA | |
N083. il_offset IL offset: 14 REG NA | |
N085. rax = V01 MEM | |
N087. const 1 REG NA | |
N089. rax = + ; rax | |
N091. V01 MEM; rax | |
Var=Reg end of BB06: none | |
BB08 [01A..01B) (return), preds={BB07} succs={} | |
===== | |
Predecessor for variable locations: BB07 | |
Var=Reg beg of BB08: none | |
N095. il_offset IL offset: 26 REG NA | |
N097. return | |
Var=Reg end of BB08: none | |
*************** In genGenerateCode() | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000024701F8] 1 1 [???..???) i internal label target LIR | |
BB02 [0000000002473350] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR | |
BB03 [0000000002473460] 1 BB02 0.5 [???..???) internal LIR | |
BB04 [0000000002473240] 2 BB02,BB03 1 [???..???) i internal label target LIR | |
BB05 [0000000002470470] 1 BB04 1 [000..005)-> BB07 (always) i LIR | |
BB06 [0000000002470580] 1 BB07 1 [005..012) i label target gcsafe bwd LIR | |
BB07 [0000000002470690] 2 BB05,BB06 1 [012..01A)-> BB06 ( cond ) i label target bwd LIR | |
BB08 [00000000024707A0] 1 BB07 1 [01A..01B) (return) i LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDebugCheckBBlist | |
Finalizing stack frame | |
Recording Var Locations at start of BB01 | |
<none> | |
Modified regs: [rax rcx rdx rsi rdi r8-r11] | |
Callee-saved registers pushed: 0 [] | |
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) | |
Assign V00 arg0, size=8, stkOffs=-0x18 | |
Assign V01 loc0, size=4, stkOffs=-0x1c | |
Assign V02 loc1, size=4, stkOffs=-0x20 | |
; Final local variable assignments | |
; | |
; V00 arg0 [V00 ] ( 1, 0 ) ref -> [rbp-0x08] | |
; V01 loc0 [V01,T00] ( 5, 5 ) int -> [rbp-0x0C] must-init | |
; V02 loc1 [V02,T01] ( 2, 2 ) bool -> [rbp-0x10] must-init | |
;# V03 OutArgs [V03 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00] | |
; | |
; Lcl frame size = 16 | |
=============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x40030060: i internal label target LIR | |
BB01 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
Recording Var Locations at start of BB01 | |
<none> | |
Change life 0000000000000000 {} -> 0000000000000003 {V01 V02} | |
Live regs: (unchanged) 00000000 {} | |
GC regs: (unchanged) 00000000 {} | |
Byref regs: (unchanged) 00000000 {} | |
L_M21556_BB01: | |
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
Scope info: begin block BB01, IL range [???..???) | |
Scope info: ignoring block beginning | |
Generating: N003 ( 0, 0) [000000] ------------ * nop void REG NA | |
Scope info: end block BB01, IL range [???..???) | |
Scope info: ignoring block end | |
=============== Generating BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} flags=0x40000040: internal LIR | |
BB02 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
Recording Var Locations at start of BB02 | |
<none> | |
Liveness not changing: 0000000000000003 {V01 V02} | |
Live regs: (unchanged) 00000000 {} | |
GC regs: (unchanged) 00000000 {} | |
Byref regs: (unchanged) 00000000 {} | |
L_M21556_BB02: | |
Scope info: begin block BB02, IL range [???..???) | |
Scope info: ignoring block beginning | |
Added IP mapping: NO_MAP STACK_EMPTY (G_M21556_IG02,ins#0,ofs#0) label | |
Generating: N007 ( 3, 10) [000043] ------------ * const(h) long 0x7f95ea870610 token REG rax | |
IN0001: mov rax, 0x7F95EA870610 | |
Generating: N009 ( 5, 12) [000044] ------------ * indir int REG NA | |
Generating: N011 ( 1, 1) [000045] ------------ * const int 0 REG NA | |
Generating: N013 ( 7, 14) [000046] J------N---- * == int REG NA | |
IN0002: cmp dword ptr [rax], 0 | |
Generating: N015 ( 9, 16) [000054] ------------ * jmpTrue void REG NA | |
IN0003: je L_M21556_BB04 | |
Scope info: end block BB02, IL range [???..???) | |
Scope info: ignoring block end | |
=============== Generating BB03 [???..???), preds={BB02} succs={BB04} flags=0x40000040: internal LIR | |
BB03 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
Recording Var Locations at start of BB03 | |
<none> | |
Liveness not changing: 0000000000000003 {V01 V02} | |
Live regs: (unchanged) 00000000 {} | |
GC regs: (unchanged) 00000000 {} | |
Byref regs: (unchanged) 00000000 {} | |
L_M21556_BB03: | |
Scope info: begin block BB03, IL range [???..???) | |
Scope info: ignoring block beginning | |
genIPmappingAdd: ignoring duplicate IL offset 0xffffffff | |
Generating: N019 ( 14, 5) [000047] --C-G-?----- * call help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
IN0004: call CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
Scope info: end block BB03, IL range [???..???) | |
Scope info: ignoring block end | |
=============== Generating BB04 [???..???), preds={BB02,BB03} succs={BB05} flags=0x40030060: i internal label target LIR | |
BB04 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
Recording Var Locations at start of BB04 | |
<none> | |
Liveness not changing: 0000000000000003 {V01 V02} | |
Live regs: (unchanged) 00000000 {} | |
GC regs: (unchanged) 00000000 {} | |
Byref regs: (unchanged) 00000000 {} | |
L_M21556_BB04: | |
G_M21556_IG02: ; offs=000000H, funclet=00 | |
Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
Scope info: begin block BB04, IL range [???..???) | |
Scope info: ignoring block beginning | |
genIPmappingAdd: ignoring duplicate IL offset 0xffffffff | |
Scope info: end block BB04, IL range [???..???) | |
Scope info: ignoring block end | |
=============== Generating BB05 [000..005) -> BB07 (always), preds={BB04} succs={BB07} flags=0x40000020: i LIR | |
BB05 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
Recording Var Locations at start of BB05 | |
<none> | |
Liveness not changing: 0000000000000003 {V01 V02} | |
Live regs: (unchanged) 00000000 {} | |
GC regs: (unchanged) 00000000 {} | |
Byref regs: (unchanged) 00000000 {} | |
L_M21556_BB05: | |
Scope info: begin block BB05, IL range [000..005) | |
Scope info: opening scope, LVnum=0 [000..01B) | |
Scope info: >> new scope, VarNum=0, tracked? no, VarIndex=0, bbLiveIn=0000000000000003 {V01 V02} | |
Scope info: opening scope, LVnum=1 [000..01B) | |
Scope info: >> new scope, VarNum=1, tracked? yes, VarIndex=0, bbLiveIn=0000000000000003 {V01 V02} | |
Scope info: opening scope, LVnum=2 [000..01B) | |
Scope info: >> new scope, VarNum=2, tracked? yes, VarIndex=1, bbLiveIn=0000000000000003 {V01 V02} | |
Scope info: open scopes = | |
0 (V00 arg0) [000..01B) | |
1 (V01 loc0) [000..01B) | |
2 (V02 loc1) [000..01B) | |
Added IP mapping: 0x0000 STACK_EMPTY (G_M21556_IG03,ins#0,ofs#0) label | |
Generating: N025 ( 1, 1) [000004] ------------ * il_offset void IL offset: 0 REG NA | |
Generating: N027 ( 1, 1) [000003] ------------ * no_op void REG NA | |
IN0005: nop | |
Added IP mapping: 0x0001 STACK_EMPTY (G_M21556_IG03,ins#1,ofs#1) | |
Generating: N029 ( 1, 3) [000008] ------------ * il_offset void IL offset: 1 REG NA | |
Generating: N031 ( 1, 1) [000005] ------------ * const int 0 REG rdi | |
IN0006: xor edi, edi | |
Generating: N033 ( 1, 3) [000007] DA---------- * st.lclVar int V01 loc0 REG NA | |
IN0007: mov dword ptr [V01 rbp-0CH], edi | |
Added IP mapping: 0x0003 STACK_EMPTY (G_M21556_IG03,ins#3,ofs#6) | |
Generating: N035 ( 0, 0) [000010] ------------ * il_offset void IL offset: 3 REG NA | |
Generating: N037 ( 0, 0) [000009] ------------ * nop void REG NA | |
IN0008: nop | |
Scope info: end block BB05, IL range [000..005) | |
Scope info: open scopes = | |
0 (V00 arg0) [000..01B) | |
1 (V01 loc0) [000..01B) | |
2 (V02 loc1) [000..01B) | |
IN0009: jmp L_M21556_BB07 | |
=============== Generating BB06 [005..012), preds={BB07} succs={BB07} flags=0x420b0020: i label target gcsafe bwd LIR | |
BB06 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
Recording Var Locations at start of BB06 | |
<none> | |
Liveness not changing: 0000000000000003 {V01 V02} | |
Live regs: (unchanged) 00000000 {} | |
GC regs: (unchanged) 00000000 {} | |
Byref regs: (unchanged) 00000000 {} | |
L_M21556_BB06: | |
G_M21556_IG03: ; offs=000018H, funclet=00 | |
Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
Scope info: begin block BB06, IL range [005..012) | |
Scope info: open scopes = | |
0 (V00 arg0) [000..01B) | |
1 (V01 loc0) [000..01B) | |
2 (V02 loc1) [000..01B) | |
Added IP mapping: 0x0005 STACK_EMPTY (G_M21556_IG04,ins#0,ofs#0) label | |
Generating: N063 ( 1, 1) [000025] ------------ * il_offset void IL offset: 5 REG NA | |
Generating: N065 ( 1, 1) [000024] ------------ * no_op void REG NA | |
IN000a: nop | |
Added IP mapping: 0x0006 STACK_EMPTY (G_M21556_IG04,ins#1,ofs#1) | |
Generating: N067 ( 15, 7) [000029] ------------ * il_offset void IL offset: 6 REG NA | |
Generating: N069 ( 1, 1) [000026] ------------ * lclVar int V01 loc0 REG rdi | |
IN000b: mov edi, dword ptr [V01 rbp-0CH] | |
Generating: N071 (???,???) [000057] ------------ * putarg_reg int REG rdi | |
Generating: N073 ( 15, 7) [000027] --C-G------- * call void System.Console.WriteLine | |
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
Added IP mapping: 0x0007 CALL_INSTRUCTION (G_M21556_IG04,ins#2,ofs#4) | |
IN000c: call System.Console:WriteLine(int) | |
Added IP mapping: 0x000C STACK_EMPTY (G_M21556_IG04,ins#3,ofs#9) | |
Generating: N075 ( 1, 1) [000031] ------------ * il_offset void IL offset: 12 REG NA | |
Generating: N077 ( 1, 1) [000030] ------------ * no_op void REG NA | |
IN000d: nop | |
Added IP mapping: 0x000D STACK_EMPTY (G_M21556_IG04,ins#4,ofs#10) | |
Generating: N079 ( 1, 1) [000033] ------------ * il_offset void IL offset: 13 REG NA | |
Generating: N081 ( 1, 1) [000032] ------------ * no_op void REG NA | |
IN000e: nop | |
Added IP mapping: 0x000E STACK_EMPTY (G_M21556_IG04,ins#5,ofs#11) | |
Generating: N083 ( 3, 3) [000039] ------------ * il_offset void IL offset: 14 REG NA | |
Generating: N085 ( 1, 1) [000034] ------------ * lclVar int V01 loc0 REG rax | |
IN000f: mov eax, dword ptr [V01 rbp-0CH] | |
Generating: N087 ( 1, 1) [000035] ------------ * const int 1 REG NA | |
Generating: N089 ( 3, 3) [000036] ------------ * + int REG rax | |
IN0010: inc eax | |
Generating: N091 ( 3, 3) [000038] DA---------- * st.lclVar int V01 loc0 REG NA | |
IN0011: mov dword ptr [V01 rbp-0CH], eax | |
Scope info: end block BB06, IL range [005..012) | |
Scope info: open scopes = | |
0 (V00 arg0) [000..01B) | |
1 (V01 loc0) [000..01B) | |
2 (V02 loc1) [000..01B) | |
=============== Generating BB07 [012..01A) -> BB06 (cond), preds={BB05,BB06} succs={BB08,BB06} flags=0x42030020: i label target bwd LIR | |
BB07 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} + HEAP | |
Recording Var Locations at start of BB07 | |
<none> | |
Liveness not changing: 0000000000000003 {V01 V02} | |
Live regs: (unchanged) 00000000 {} | |
GC regs: (unchanged) 00000000 {} | |
Byref regs: (unchanged) 00000000 {} | |
L_M21556_BB07: | |
G_M21556_IG04: ; offs=000024H, funclet=00 | |
Label: IG05, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
Scope info: begin block BB07, IL range [012..01A) | |
Scope info: open scopes = | |
0 (V00 arg0) [000..01B) | |
1 (V01 loc0) [000..01B) | |
2 (V02 loc1) [000..01B) | |
Added IP mapping: 0x0012 STACK_EMPTY (G_M21556_IG05,ins#0,ofs#0) label | |
Generating: N041 ( 10, 6) [000017] ------------ * il_offset void IL offset: 18 REG NA | |
Generating: N043 ( 1, 1) [000012] ------------ * lclVar int V01 loc0 REG rdi | |
IN0012: mov edi, dword ptr [V01 rbp-0CH] | |
Generating: N045 ( 1, 1) [000013] ------------ * const int 3 REG NA | |
Generating: N047 ( 6, 3) [000014] ------------ * < int REG rdi | |
IN0013: cmp edi, 3 | |
IN0014: setl dil | |
IN0015: movzx rdi, dil | |
Generating: N049 ( 10, 6) [000016] DA---------- * st.lclVar int V02 loc1 REG NA | |
IN0016: mov dword ptr [V02 rbp-10H], edi | |
Added IP mapping: 0x0017 STACK_EMPTY (G_M21556_IG05,ins#5,ofs#17) | |
Generating: N051 ( 7, 6) [000022] ------------ * il_offset void IL offset: 23 REG NA | |
Generating: N053 ( 3, 2) [000018] ------------ * lclVar int V02 loc1 REG rdi | |
IN0017: mov edi, dword ptr [V02 rbp-10H] | |
Generating: N055 ( 1, 1) [000019] ------------ * const int 0 REG NA | |
Generating: N057 ( 5, 4) [000020] J------N---- * != int REG NA | |
IN0018: test edi, edi | |
Generating: N059 ( 7, 6) [000021] ------------ * jmpTrue void REG NA | |
IN0019: jne SHORT L_M21556_BB06 | |
Scope info: end block BB07, IL range [012..01A) | |
Scope info: open scopes = | |
0 (V00 arg0) [000..01B) | |
1 (V01 loc0) [000..01B) | |
2 (V02 loc1) [000..01B) | |
=============== Generating BB08 [01A..01B) (return), preds={BB07} succs={} flags=0x40000020: i LIR | |
BB08 IN (2)={V01 V02} + HEAP | |
OUT(2)={V01 V02} | |
Recording Var Locations at start of BB08 | |
<none> | |
Liveness not changing: 0000000000000003 {V01 V02} | |
Live regs: (unchanged) 00000000 {} | |
GC regs: (unchanged) 00000000 {} | |
Byref regs: (unchanged) 00000000 {} | |
L_M21556_BB08: | |
Scope info: begin block BB08, IL range [01A..01B) | |
Scope info: open scopes = | |
0 (V00 arg0) [000..01B) | |
1 (V01 loc0) [000..01B) | |
2 (V02 loc1) [000..01B) | |
Added IP mapping: 0x001A STACK_EMPTY (G_M21556_IG05,ins#8,ofs#24) label | |
Generating: N095 ( 0, 0) [000042] ------------ * il_offset void IL offset: 26 REG NA | |
Generating: N097 ( 0, 0) [000041] ------------ * return void REG NA | |
IN001a: nop | |
Scope info: end block BB08, IL range [01A..01B) | |
Scope info: ending scope, LVnum=0 [000..01B) | |
Scope info: ending scope, LVnum=1 [000..01B) | |
Scope info: ending scope, LVnum=2 [000..01B) | |
Scope info: open scopes = | |
<none> | |
Added IP mapping: EPILOG STACK_EMPTY (G_M21556_IG05,ins#9,ofs#25) label | |
Reserving epilog IG for block BB08 | |
G_M21556_IG05: ; offs=000037H, funclet=00 | |
*************** After placeholder IG creation | |
G_M21556_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG | |
G_M21556_IG02: ; offs=000000H, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M21556_IG03: ; offs=000018H, size=000CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M21556_IG04: ; offs=000024H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M21556_IG05: ; offs=000037H, size=0019H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M21556_IG06: ; epilog placeholder, next placeholder=<END>, BB=024707A0H (BB08), epilog, emitadd <-- First placeholder <-- Last placeholder | |
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} | |
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} | |
Change life 0000000000000003 {V01 V02} -> 0000000000000000 {} | |
# compCycleEstimate = 63, compSizeEstimate = 50 ConsoleApplication.Program:Main(ref) | |
; Final local variable assignments | |
; | |
; V00 arg0 [V00 ] ( 1, 0 ) ref -> [rbp-0x08] | |
; V01 loc0 [V01,T00] ( 5, 5 ) int -> [rbp-0x0C] must-init | |
; V02 loc1 [V02,T01] ( 2, 2 ) bool -> [rbp-0x10] must-init | |
;# V03 OutArgs [V03 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00] | |
; | |
; Lcl frame size = 16 | |
*************** Before prolog / epilog generation | |
G_M21556_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG | |
G_M21556_IG02: ; offs=000000H, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M21556_IG03: ; offs=000018H, size=000CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M21556_IG04: ; offs=000024H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M21556_IG05: ; offs=000037H, size=0019H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M21556_IG06: ; epilog placeholder, next placeholder=<END>, BB=024707A0H (BB08), epilog, emitadd <-- First placeholder <-- Last placeholder | |
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} | |
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} | |
Recording Var Locations at start of BB01 | |
<none> | |
*************** In genFnProlog() | |
Added IP mapping to front: PROLOG STACK_EMPTY (G_M21556_IG01,ins#0,ofs#0) label | |
__prolog: | |
Found 4 lvMustInit stk vars, frame offsets 16 through 8 | |
IN001b: push rbp | |
IN001c: sub rsp, 16 | |
IN001d: lea rbp, [rsp+10H] | |
IN001e: xor rax, rax | |
IN001f: mov dword ptr [V01 rbp-0CH], eax | |
IN0020: mov dword ptr [V02 rbp-10H], eax | |
*************** In genClearStackVec3ArgUpperBits() | |
*************** In genFnPrologCalleeRegArgs() for int regs | |
IN0021: mov gword ptr [V00 rbp-08H], rdi | |
*************** In genEnregisterIncomingStackArgs() | |
G_M21556_IG01: ; offs=000000H, funclet=00 | |
*************** In genFnEpilog() | |
__epilog: | |
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {} | |
IN0022: lea rsp, [rbp] | |
IN0023: pop rbp | |
IN0024: ret | |
G_M21556_IG06: ; offs=000050H, funclet=00 | |
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs | |
*************** After prolog / epilog generation | |
G_M21556_IG01: ; func=00, offs=000000H, size=0016H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG | |
G_M21556_IG02: ; offs=000016H, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M21556_IG03: ; offs=00002EH, size=000CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M21556_IG04: ; offs=00003AH, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M21556_IG05: ; offs=00004DH, size=0019H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M21556_IG06: ; offs=000066H, size=0006H, epilog, nogc, emitadd | |
*************** In emitJumpDistBind() | |
Binding: IN0003: 000000 je L_M21556_BB04 | |
Binding L_M21556_BB04 to G_M21556_IG03 | |
Estimate of fwd jump [024782A4/003]: 0023 -> 002E = 0009 | |
Shrinking jump [024782A4/003] | |
Binding: IN0009: 000000 jmp L_M21556_BB07 | |
Binding L_M21556_BB07 to G_M21556_IG05 | |
Estimate of fwd jump [0247882C/009]: 0031 -> 0049 = 0016 | |
Shrinking jump [0247882C/009] | |
Binding: IN0019: 000000 jne SHORT L_M21556_BB06 | |
Binding L_M21556_BB06 to G_M21556_IG04 | |
Estimate of bwd jump [024796C4/025]: 005C -> 0033 = 002B | |
Shrinking jump [024796C4/025] | |
Total shrinkage = 7, min extra jump size = 4294967295 | |
Hot code size = 0x65 bytes | |
Cold code size = 0x0 bytes | |
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x8) | |
*************** In emitEndCodeGen() | |
*************************************************************************** | |
Instructions as they come out of the scheduler | |
G_M21556_IG01: ; func=00, offs=000000H, size=0016H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG | |
IN001b: 000000 55 push rbp | |
IN001c: 000001 4883EC10 sub rsp, 16 | |
IN001d: 000005 488D6C2410 lea rbp, [rsp+10H] | |
IN001e: 00000A 33C0 xor rax, rax | |
IN001f: 00000C 8945F4 mov dword ptr [rbp-0CH], eax | |
IN0020: 00000F 8945F0 mov dword ptr [rbp-10H], eax | |
IN0021: 000012 48897DF8 mov gword ptr [rbp-08H], rdi | |
G_M21556_IG02: ; func=00, offs=000016H, size=0014H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz | |
IN0001: 000016 48B8100687EA957F0000 mov rax, 0x7F95EA870610 | |
IN0002: 000020 833800 cmp dword ptr [rax], 0 | |
IN0003: 000023 7405 je SHORT G_M21556_IG03 | |
[02479BA8] ptr arg pop 0 | |
IN0004: 000025 E8D6E0B578 call CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
G_M21556_IG03: ; func=00, offs=00002AH, size=0009H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz | |
IN0005: 00002A 90 nop | |
IN0006: 00002B 33FF xor edi, edi | |
IN0007: 00002D 897DF4 mov dword ptr [rbp-0CH], edi | |
IN0008: 000030 90 nop | |
IN0009: 000031 EB13 jmp SHORT G_M21556_IG05 | |
G_M21556_IG04: ; func=00, offs=000033H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
IN000a: 000033 90 nop | |
IN000b: 000034 8B7DF4 mov edi, dword ptr [rbp-0CH] | |
[02479BC0] ptr arg pop 0 | |
IN000c: 000037 E864F7FFFF call System.Console:WriteLine(int) | |
IN000d: 00003C 90 nop | |
IN000e: 00003D 90 nop | |
IN000f: 00003E 8B45F4 mov eax, dword ptr [rbp-0CH] | |
IN0010: 000041 FFC0 inc eax | |
IN0011: 000043 8945F4 mov dword ptr [rbp-0CH], eax | |
G_M21556_IG05: ; func=00, offs=000046H, size=0019H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz | |
IN0012: 000046 8B7DF4 mov edi, dword ptr [rbp-0CH] | |
IN0013: 000049 83FF03 cmp edi, 3 | |
IN0014: 00004C 400F9CC7 setl dil | |
IN0015: 000050 400FB6FF movzx rdi, dil | |
IN0016: 000054 897DF0 mov dword ptr [rbp-10H], edi | |
IN0017: 000057 8B7DF0 mov edi, dword ptr [rbp-10H] | |
IN0018: 00005A 85FF test edi, edi | |
IN0019: 00005C 75D5 jne SHORT G_M21556_IG04 | |
IN001a: 00005E 90 nop | |
G_M21556_IG06: ; func=00, offs=00005FH, size=0006H, epilog, nogc, emitadd | |
IN0022: 00005F 488D6500 lea rsp, [rbp] | |
IN0023: 000063 5D pop rbp | |
IN0024: 000064 C3 ret | |
Allocated method code size = 101 , actual size = 101 | |
*************** After end code gen, before unwindEmit() | |
G_M21556_IG01: ; func=00, offs=000000H, size=0016H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG | |
IN001b: 000000 push rbp | |
IN001c: 000001 sub rsp, 16 | |
IN001d: 000005 lea rbp, [rsp+10H] | |
IN001e: 00000A xor rax, rax | |
IN001f: 00000C mov dword ptr [V01 rbp-0CH], eax | |
IN0020: 00000F mov dword ptr [V02 rbp-10H], eax | |
IN0021: 000012 mov gword ptr [V00 rbp-08H], rdi | |
G_M21556_IG02: ; offs=000016H, size=0014H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz | |
IN0001: 000016 mov rax, 0x7F95EA870610 | |
IN0002: 000020 cmp dword ptr [rax], 0 | |
IN0003: 000023 je SHORT G_M21556_IG03 | |
IN0004: 000025 call CORINFO_HELP_DBG_IS_JUST_MY_CODE | |
G_M21556_IG03: ; offs=00002AH, size=0009H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz | |
IN0005: 00002A nop | |
IN0006: 00002B xor edi, edi | |
IN0007: 00002D mov dword ptr [V01 rbp-0CH], edi | |
IN0008: 000030 nop | |
IN0009: 000031 jmp SHORT G_M21556_IG05 | |
G_M21556_IG04: ; offs=000033H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
IN000a: 000033 nop | |
IN000b: 000034 mov edi, dword ptr [V01 rbp-0CH] | |
IN000c: 000037 call System.Console:WriteLine(int) | |
IN000d: 00003C nop | |
IN000e: 00003D nop | |
IN000f: 00003E mov eax, dword ptr [V01 rbp-0CH] | |
IN0010: 000041 inc eax | |
IN0011: 000043 mov dword ptr [V01 rbp-0CH], eax | |
G_M21556_IG05: ; offs=000046H, size=0019H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz | |
IN0012: 000046 mov edi, dword ptr [V01 rbp-0CH] | |
IN0013: 000049 cmp edi, 3 | |
IN0014: 00004C setl dil | |
IN0015: 000050 movzx rdi, dil | |
IN0016: 000054 mov dword ptr [V02 rbp-10H], edi | |
IN0017: 000057 mov edi, dword ptr [V02 rbp-10H] | |
IN0018: 00005A test edi, edi | |
IN0019: 00005C jne SHORT G_M21556_IG04 | |
IN001a: 00005E nop | |
G_M21556_IG06: ; offs=00005FH, size=0006H, epilog, nogc, emitadd | |
IN0022: 00005F lea rsp, [rbp] | |
IN0023: 000063 pop rbp | |
IN0024: 000064 ret | |
Unwind Info: | |
>> Start offset : 0x000000 (not in unwind data) | |
>> End offset : 0x000065 (not in unwind data) | |
Version : 1 | |
Flags : 0x00 | |
SizeOfProlog : 0x05 | |
CountOfUnwindCodes: 2 | |
FrameRegister : none (0) | |
FrameOffset : N/A (no FrameRegister) (Value=0) | |
UnwindCodes : | |
CodeOffset: 0x05 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 1 * 8 + 8 = 16 = 0x10 | |
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) | |
allocUnwindInfo(pHotCode=0x00007F95EBC68920, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x65, unwindSize=0x8, pUnwindBlock=0x0000000002473BD0, funKind=0 (main function)) | |
*************** In genIPmappingGen() | |
IP mapping count : 15 | |
IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) | |
IL offs NO_MAP : 0x00000016 ( STACK_EMPTY ) | |
IL offs 0x0000 : 0x0000002A ( STACK_EMPTY ) | |
IL offs 0x0001 : 0x0000002B ( STACK_EMPTY ) | |
IL offs 0x0003 : 0x00000030 ( STACK_EMPTY ) | |
IL offs 0x0005 : 0x00000033 ( STACK_EMPTY ) | |
IL offs 0x0006 : 0x00000034 ( STACK_EMPTY ) | |
IL offs 0x0007 : 0x00000037 ( CALL_INSTRUCTION ) | |
IL offs 0x000C : 0x0000003C ( STACK_EMPTY ) | |
IL offs 0x000D : 0x0000003D ( STACK_EMPTY ) | |
IL offs 0x000E : 0x0000003E ( STACK_EMPTY ) | |
IL offs 0x0012 : 0x00000046 ( STACK_EMPTY ) | |
IL offs 0x0017 : 0x00000057 ( STACK_EMPTY ) | |
IL offs 0x001A : 0x0000005E ( STACK_EMPTY ) | |
IL offs EPILOG : 0x0000005F ( STACK_EMPTY ) | |
*************** In genSetScopeInfo() | |
VarLocInfo count is 4 | |
*************** Variable debug info | |
4 vars | |
0( UNKNOWN) : From 00000000h to 00000016h, in rdi | |
0( UNKNOWN) : From 0000002Ah to 0000005Fh, in rbp[-8] (1 slot) | |
1( UNKNOWN) : From 0000002Ah to 0000005Fh, in rbp[-12] (1 slot) | |
2( UNKNOWN) : From 0000002Ah to 0000005Fh, in rbp[-16] (1 slot) | |
*************** In gcInfoBlockHdrSave() | |
Set code length to 101. | |
Set ReturnKind to Scalar. | |
Set stack base register to rbp. | |
Set Outgoing stack arg area size to 0. | |
Stack slot id for offset -8 (0xfffffff8) (frame) (untracked) = 0. | |
Defining interruptible range: [0x16, 0x5f). | |
Allocations for ConsoleApplication.Program:Main(ref) (MethodHash=1499abcb) | |
count: 519, size: 43004, max = 2528 | |
allocateMemory: 65536, nraUsed: 61728 | |
Alloc'd bytes by kind: | |
kind | size | pct | |
---------------------+------------+-------- | |
AssertionProp | 0 | 0.00% | |
ASTNode | 8896 | 20.69% | |
InstDesc | 4740 | 11.02% | |
ImpStack | 0 | 0.00% | |
BasicBlock | 2792 | 6.49% | |
fgArgInfo | 64 | 0.15% | |
fgArgInfoPtrArr | 8 | 0.02% | |
FlowList | 288 | 0.67% | |
TreeStatementList | 0 | 0.00% | |
SiScope | 264 | 0.61% | |
FlatFPStateX87 | 0 | 0.00% | |
DominatorMemory | 0 | |
1 | |
2 | |
0 | 0.00% | |
LSRA | 3548 | 8.25% | |
LSRA_Interval | 1040 | 2.42% | |
LSRA_RefPosition | 3008 | 6.99% | |
Reachability | 0 | 0.00% | |
SSA | 0 | 0.00% | |
ValueNumber | 0 | 0.00% | |
LvaTable | 1984 | 4.61% | |
UnwindInfo | 0 | 0.00% | |
hashBv | 200 | 0.47% | |
bitset | 0 | 0.00% | |
FixedBitVect | 0 | 0.00% | |
AsIAllocator | 420 | 0.98% | |
IndirAssignMap | 64 | 0.15% | |
FieldSeqStore | 0 | 0.00% | |
ZeroOffsetFieldMap | 0 | 0.00% | |
ArrayInfoMap | 0 | 0.00% | |
HeapPhiArg | 0 | 0.00% | |
CSE | 0 | 0.00% | |
GC | 1124 | 2.61% | |
CorSig | 104 | 0.24% | |
Inlining | 0 | 0.00% | |
ArrayStack | 0 | 0.00% | |
DebugInfo | 744 | 1.73% | |
DebugOnly | 13248 | 30.81% | |
Codegen | 0 | 0.00% | |
LoopOpt | 0 | 0.00% | |
LoopHoist | 0 | 0.00% | |
Unknown | 468 | 1.09% | |
****** DONE compiling ConsoleApplication.Program:Main(ref) |
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****** START compiling ConsoleApplication.Program:Main(ref) (MethodHash=1499abcb) | |
Generating code for Unix x64 | |
OPTIONS: compCodeOpt = BLENDED_CODE | |
OPTIONS: compDbgCode = false | |
OPTIONS: compDbgInfo = true | |
OPTIONS: compDbgEnC = false | |
OPTIONS: compProcedureSplitting = false | |
OPTIONS: compProcedureSplittingEH = false | |
OPTIONS: Stack probing is DISABLED | |
IL to import: | |
IL_0000 16 ldc.i4.0 | |
IL_0001 0a stloc.0 | |
IL_0002 2b 0a br.s 10 (IL_000e) | |
IL_0004 06 ldloc.0 | |
IL_0005 28 0c 00 00 0a call 0xA00000C | |
IL_000a 06 ldloc.0 | |
IL_000b 17 ldc.i4.1 | |
IL_000c 58 add | |
IL_000d 0a stloc.0 | |
IL_000e 06 ldloc.0 | |
IL_000f 28 02 00 00 06 call 0x6000002 | |
IL_0014 32 ee blt.s -18 (IL_0004) | |
IL_0016 2a ret | |
Set preferred register for V00 to [rdi] | |
Arg #0 passed in register(s) rdi | |
; Initial local variable assignments | |
; | |
; V00 arg0 ref | |
; V01 loc0 int | |
*************** In compInitDebuggingInfo() for ConsoleApplication.Program:Main(ref) | |
getVars() returned cVars = 0, extendOthers = true | |
info.compVarScopesCount = 2 | |
VarNum LVNum Name Beg End | |
0: 00h 00h V00 arg0 000h 017h | |
1: 01h 01h V01 loc0 000h 017h | |
info.compStmtOffsetsCount = 0 | |
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE ) | |
*************** In fgFindBasicBlocks() for ConsoleApplication.Program:Main(ref) | |
Jump targets: | |
IL_0004 | |
IL_000e | |
New Basic Block BB01 [00000000022746C0] created. | |
BB01 [000..004) | |
New Basic Block BB02 [00000000022747D0] created. | |
BB02 [004..00E) | |
New Basic Block BB03 [00000000022748E0] created. | |
BB03 [00E..016) | |
New Basic Block BB04 [00000000022749F0] created. | |
BB04 [016..017) | |
IL Code Size,Instr 23, 13, Basic Block count 4, Local Variable Num,Ref count 2, 5 for method ConsoleApplication.Program:Main(ref) | |
OPTIONS: opts.MinOpts() == false | |
Basic block list for 'ConsoleApplication.Program:Main(ref)' | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 (always) | |
BB02 [00000000022747D0] 1 1 [004..00E) bwd | |
BB03 [00000000022748E0] 2 1 [00E..016)-> BB02 ( cond ) bwd | |
BB04 [00000000022749F0] 1 1 [016..017) (return) | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In impImport() for ConsoleApplication.Program:Main(ref) | |
impImportBlockPending for BB01 | |
Importing BB01 (PC=000) of 'ConsoleApplication.Program:Main(ref)' | |
[ 0] 0 (0x000) ldc.i4.0 0 | |
[ 1] 1 (0x001) stloc.0 | |
[000004] ------------ * stmtExpr void (IL 0x000... ???) | |
[000001] ------------ | /--* const int 0 | |
[000003] -A---------- \--* = int | |
[000002] D------N---- \--* lclVar int V01 loc0 | |
[ 0] 2 (0x002) br.s | |
impImportBlockPending for BB03 | |
Importing BB03 (PC=014) of 'ConsoleApplication.Program:Main(ref)' | |
[ 0] 14 (0x00e) ldloc.0 | |
[ 1] 15 (0x00f) call 06000002 | |
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 | |
[000008] ------------ * stmtExpr void (IL 0x00E... ???) | |
[000007] I-C-G------- \--* call int ConsoleApplication.Program.GetNumber (exactContextHnd=0x00007F7D14FC52B9) | |
[ 2] 20 (0x014) blt.s | |
[000012] ------------ * stmtExpr void (IL ???... ???) | |
[000011] --C--------- \--* jmpTrue void | |
[000009] --C--------- | /--* retExpr int (inl return from call [000007]) | |
[000010] --C--------- \--* < int | |
[000006] ------------ \--* lclVar int V01 loc0 | |
impImportBlockPending for BB04 | |
impImportBlockPending for BB02 | |
Importing BB02 (PC=004) of 'ConsoleApplication.Program:Main(ref)' | |
[ 0] 4 (0x004) ldloc.0 | |
[ 1] 5 (0x005) call 0A00000C | |
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 | |
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'ConsoleApplication.Program:Main(ref)' calling 'System.Console:WriteLine(int)' | |
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' | |
[000017] ------------ * stmtExpr void (IL 0x004... ???) | |
[000015] --C-G------- \--* call void System.Console.WriteLine | |
[000014] ------------ arg0 \--* lclVar int V01 loc0 | |
[ 0] 10 (0x00a) ldloc.0 | |
[ 1] 11 (0x00b) ldc.i4.1 1 | |
[ 2] 12 (0x00c) add | |
[ 1] 13 (0x00d) stloc.0 | |
[000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
[000019] ------------ | /--* const int 1 | |
[000020] ------------ | /--* + int | |
[000018] ------------ | | \--* lclVar int V01 loc0 | |
[000022] -A---------- \--* = int | |
[000021] D------N---- \--* lclVar int V01 loc0 | |
impImportBlockPending for BB03 | |
Importing BB04 (PC=022) of 'ConsoleApplication.Program:Main(ref)' | |
[ 0] 22 (0x016) ret | |
[000026] ------------ * stmtExpr void (IL 0x016... ???) | |
[000025] ------------ \--* return void | |
New BlockSet epoch 1, # of blocks (including unused BB00): 5, bitset array size: 1 (short) | |
*************** In fgMorph() | |
*************** After fgAddInternal() | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 (always) i | |
BB02 [00000000022747D0] 1 1 [004..00E) i bwd | |
BB03 [00000000022748E0] 2 1 [00E..016)-> BB02 ( cond ) i bwd | |
BB04 [00000000022749F0] 1 1 [016..017) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** Exception Handling table is empty | |
*************** In fgDebugCheckBBlist | |
*************** In fgInline() | |
Expanding INLINE_CANDIDATE in statement [000008] in BB03: | |
[000008] ------------ * stmtExpr void (IL 0x00E...0x014) | |
[000007] I-C-G------- \--* call int ConsoleApplication.Program.GetNumber (exactContextHnd=0x00007F7D14FC52B9) | |
INLINER: inlineInfo.tokenLookupContextHandle for ConsoleApplication.Program:GetNumber():int set to 0x00007F7D14FC52B9: | |
Invoking compiler for the inlinee method ConsoleApplication.Program:GetNumber():int : | |
IL to import: | |
IL_0000 28 01 00 00 06 call 0x6000001 | |
IL_0005 2a ret | |
INLINER impTokenLookupContextHandle for ConsoleApplication.Program:GetNumber():int is 0x00007F7D14FC52B9. | |
*************** In fgFindBasicBlocks() for ConsoleApplication.Program:GetNumber():int | |
Jump targets: | |
none | |
New Basic Block BB05 [00000000022792F8] created. | |
BB05 [000..006) | |
Basic block list for 'ConsoleApplication.Program:GetNumber():int' | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB05 [00000000022792F8] 1 1 [000..006) (return) | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In impImport() for ConsoleApplication.Program:GetNumber():int | |
impImportBlockPending for BB05 | |
Importing BB05 (PC=000) of 'ConsoleApplication.Program:GetNumber():int' | |
[ 0] 0 (0x000) call 06000001 | |
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 | |
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'ConsoleApplication.Program:GetNumber():int' calling 'ConsoleApplication.Program:GetNumberNoInline():int' | |
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' | |
[ 1] 5 (0x005) ret | |
Inlinee Return expression (before normalization) => | |
[000028] --C-G------- * call int ConsoleApplication.Program.GetNumberNoInline | |
Inlinee Return expression (after normalization) => | |
[000028] --C-G------- * call int ConsoleApplication.Program.GetNumberNoInline | |
----------- Statements (and blocks) added due to the inlining of call [000007] ----------- | |
Inlinee method body: | |
Return expression for call at [000007] is | |
[000028] --C-G------- * call int ConsoleApplication.Program.GetNumberNoInline | |
Successfully inlined ConsoleApplication.Program:GetNumber():int (6 IL bytes) (depth 1) [below ALWAYS_INLINE size] | |
-------------------------------------------------------------------------------------------- | |
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'ConsoleApplication.Program:Main(ref)' calling 'ConsoleApplication.Program:GetNumber():int' | |
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' | |
Replacing the return expression placeholder [000009] with [000028] | |
[000009] --C--------- * retExpr int (inl return from call [000028]) | |
Inserting the inline return expression | |
[000028] --C-G------- * call int ConsoleApplication.Program.GetNumberNoInline | |
*************** After fgInline() | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 (always) i | |
BB02 [00000000022747D0] 1 1 [004..00E) i bwd | |
BB03 [00000000022748E0] 2 1 [00E..016)-> BB02 ( cond ) i bwd | |
BB04 [00000000022749F0] 1 1 [016..017) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03} | |
***** BB01, stmt 1 | |
[000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
[000001] ------------ | /--* const int 0 | |
[000003] -A---------- \--* = int | |
[000002] D------N---- \--* lclVar int V01 loc0 | |
------------ BB02 [004..00E), preds={} succs={BB03} | |
***** BB02, stmt 2 | |
[000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
[000015] --C-G------- \--* call void System.Console.WriteLine | |
[000014] ------------ arg0 \--* lclVar int V01 loc0 | |
***** BB02, stmt 3 | |
[000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
[000019] ------------ | /--* const int 1 | |
[000020] ------------ | /--* + int | |
[000018] ------------ | | \--* lclVar int V01 loc0 | |
[000022] -A---------- \--* = int | |
[000021] D------N---- \--* lclVar int V01 loc0 | |
------------ BB03 [00E..016) -> BB02 (cond), preds={} succs={BB04,BB02} | |
***** BB03, stmt 4 | |
[000012] ------------ * stmtExpr void (IL ???... ???) | |
[000011] --C--------- \--* jmpTrue void | |
[000028] --C-G------- | /--* call int ConsoleApplication.Program.GetNumberNoInline | |
[000010] --C--------- \--* < int | |
[000006] ------------ \--* lclVar int V01 loc0 | |
------------ BB04 [016..017) (return), preds={} succs={} | |
***** BB04, stmt 5 | |
[000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
[000025] ------------ \--* return void | |
------------------------------------------------------------------------------------------------------------------- | |
*************** Exception Handling table is empty | |
**************** Inline Tree | |
Inlines into 06000003 ConsoleApplication.Program:Main(ref) | |
[0 IL=0005 TR=000015 0600005E] [FAILED: noinline per IL/cached result] System.Console:WriteLine(int) | |
[1 IL=0015 TR=000007 06000002] [below ALWAYS_INLINE size] ConsoleApplication.Program:GetNumber():int | |
Budget: initialTime=129, finalTime=127, initialBudget=1290, currentBudget=1290 | |
Budget: initialSize=655, finalSize=655 | |
*************** In fgDebugCheckBBlist | |
*************** In fgMarkImplicitByRefs() | |
*************** In fgPromoteStructs() | |
*************** In fgMarkAddressExposedLocals() | |
*************** In fgMorphBlocks() | |
Morphing BB01 of 'ConsoleApplication.Program:Main(ref)' | |
fgMorphTree BB01, stmt 1 (before) | |
[000001] ------------ /--* const int 0 | |
[000003] -A---------- * = int | |
[000002] D------N---- \--* lclVar int V01 loc0 | |
GenTreeNode creates assertion: | |
[000003] -A---------- * = int | |
In BB01 New Local Constant Assertion: V01 == 0 index=#01, mask=0000000000000001 | |
Morphing BB02 of 'ConsoleApplication.Program:Main(ref)' | |
fgMorphTree BB02, stmt 2 (before) | |
[000015] --C-G------- * call void System.Console.WriteLine | |
[000014] ------------ arg0 \--* lclVar int V01 loc0 | |
argSlots=1, preallocatedArgCount=0, nextSlotNum=0, lvaOutgoingArgSpaceSize=0 | |
Sorting the arguments: | |
Deferred argument ('rdi'): | |
[000014] -----+------ * lclVar int V01 loc0 | |
Replaced with placeholder node: | |
[000030] ----------L- * argPlace int | |
Shuffled argument table: rdi | |
fgArgTabEntry[arg 0, rdi, regs=1, align=1, lateArgInx=0, processed] | |
fgMorphTree BB02, stmt 2 (after) | |
[000015] --C-G+------ * call void System.Console.WriteLine | |
[000014] -----+------ arg0 in rdi \--* lclVar int V01 loc0 | |
fgMorphTree BB02, stmt 3 (before) | |
[000019] ------------ /--* const int 1 | |
[000020] ------------ /--* + int | |
[000018] ------------ | \--* lclVar int V01 loc0 | |
[000022] -A---------- * = int | |
[000021] D------N---- \--* lclVar int V01 loc0 | |
Morphing BB03 of 'ConsoleApplication.Program:Main(ref)' | |
fgMorphTree BB03, stmt 4 (before) | |
[000011] --C--------- * jmpTrue void | |
[000028] --C-G------- | /--* call int ConsoleApplication.Program.GetNumberNoInline | |
[000010] --C--------- \--* < int | |
[000006] ------------ \--* lclVar int V01 loc0 | |
argSlots=0, preallocatedArgCount=0, nextSlotNum=0, lvaOutgoingArgSpaceSize=0 | |
Morphing BB04 of 'ConsoleApplication.Program:Main(ref)' | |
fgMorphTree BB04, stmt 5 (before) | |
[000025] ------------ * return void | |
Renumbering the basic blocks for fgComputePred | |
*************** Before renumbering the basic blocks | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 (always) i | |
BB02 [00000000022747D0] 1 1 [004..00E) i gcsafe bwd | |
BB03 [00000000022748E0] 2 1 [00E..016)-> BB02 ( cond ) i gcsafe bwd | |
BB04 [00000000022749F0] 1 1 [016..017) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** Exception Handling table is empty | |
*************** After renumbering the basic blocks | |
=============== No blocks renumbered! | |
New BlockSet epoch 2, # of blocks (including unused BB00): 5, bitset array size: 1 (short) | |
*************** In fgComputePreds() | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 (always) i | |
BB02 [00000000022747D0] 1 1 [004..00E) i gcsafe bwd | |
BB03 [00000000022748E0] 2 1 [00E..016)-> BB02 ( cond ) i gcsafe bwd | |
BB04 [00000000022749F0] 1 1 [016..017) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** After fgComputePreds() | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 (always) i label target | |
BB02 [00000000022747D0] 1 BB03 1 [004..00E) i label target gcsafe bwd | |
BB03 [00000000022748E0] 2 BB01,BB02 1 [00E..016)-> BB02 ( cond ) i label target gcsafe bwd | |
BB04 [00000000022749F0] 1 BB03 1 [016..017) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In fgComputeEdgeWeights() | |
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 (always) i label target | |
BB02 [00000000022747D0] 1 BB03 1 [004..00E) i label target gcsafe bwd | |
BB03 [00000000022748E0] 2 BB01,BB02 1 [00E..016)-> BB02 ( cond ) i label target gcsafe bwd | |
BB04 [00000000022749F0] 1 BB03 1 [016..017) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights | |
*************** In fgCreateFunclets() | |
After fgCreateFunclets() | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 (always) i label target | |
BB02 [00000000022747D0] 1 BB03 1 [004..00E) i label target gcsafe bwd | |
BB03 [00000000022748E0] 2 BB01,BB02 1 [00E..016)-> BB02 ( cond ) i label target gcsafe bwd | |
BB04 [00000000022749F0] 1 BB03 1 [016..017) (return) i | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** Exception Handling table is empty | |
*************** In fgDebugCheckBBlist | |
*************** In optOptimizeLayout() | |
*************** Exception Handling table is empty | |
*************** In fgDebugCheckBBlist | |
Duplication of loop condition [000010] is performed, because the cost of duplication (8) is less or equal than 32, | |
loopIterations = 8.000, countOfHelpers = 0, validProfileWeights = false | |
Duplicating loop condition in BB01 for loop (BB02 - BB03) | |
Estimated code size expansion is 8 | |
[000038] ------------ * stmtExpr void (IL ???... ???) | |
[000037] --C-G------- \--* jmpTrue void | |
( 3, 2) [000036] ------------ | /--* lclVar int V01 loc0 | |
( 18, 8) [000032] J-C-G--N---- \--* <= int | |
( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
*************** In fgComputeEdgeWeights() | |
fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB04 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB03 1 [004..00E) i label target gcsafe bwd | |
BB03 [00000000022748E0] 1 BB02 1 [00E..016)-> BB02 ( cond ) i label target gcsafe bwd | |
BB04 [00000000022749F0] 2 BB01,BB03 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
fgComputeEdgeWeights() was able to compute exact edge weights for 1 of the 5 edges, using 2 passes. | |
Edge weights into BB02 :BB01 ( 0 .. 1 ), BB03 ( 0 .. 1 ) | |
Edge weights into BB03 :BB02 ( 1 ) | |
Edge weights into BB04 :BB01 ( 0 .. 1 ), BB03 ( 0 .. 1 ) | |
*************** In fgUpdateFlowGraph() | |
Before updating the flow graph: | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB04 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB03 1 [004..00E) i label target gcsafe bwd | |
BB03 [00000000022748E0] 1 BB02 1 [00E..016)-> BB02 ( cond ) i label target gcsafe bwd | |
BB04 [00000000022749F0] 2 BB01,BB03 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
Compacting blocks BB02 and BB03: | |
*************** In fgDebugCheckBBlist | |
After updating the flow graph: | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB04 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 1 [004..016)-> BB02 ( cond ) i label target gcsafe bwd | |
BB04 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** Exception Handling table is empty | |
*************** In fgDebugCheckBBlist | |
*************** In fgExpandRarelyRunBlocks() | |
*************** In fgReorderBlocks() | |
Initial BasicBlocks | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB04 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 1 [004..016)-> BB02 ( cond ) i label target gcsafe bwd | |
BB04 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In fgUpdateFlowGraph() | |
Before updating the flow graph: | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB04 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 1 [004..016)-> BB02 ( cond ) i label target gcsafe bwd | |
BB04 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDebugCheckBBlist | |
*************** In fgComputeReachability | |
*************** In fgDebugCheckBBlist | |
Renumbering the basic blocks for fgComputeReachability pass #1 | |
*************** Before renumbering the basic blocks | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB04 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 1 [004..016)-> BB02 ( cond ) i label target gcsafe bwd | |
BB04 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** Exception Handling table is empty | |
Renumber BB04 to BB03 | |
*************** After renumbering the basic blocks | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 1 [004..016)-> BB02 ( cond ) i label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** Exception Handling table is empty | |
New BlockSet epoch 3, # of blocks (including unused BB00): 4, bitset array size: 1 (short) | |
Enter blocks: BB01 | |
After computing reachability sets: | |
------------------------------------------------ | |
BBnum Reachable by | |
------------------------------------------------ | |
BB01 : BB01 | |
BB02 : BB01 BB02 | |
BB03 : BB01 BB02 BB03 | |
After computing reachability: | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 1 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDebugCheckBBlist | |
*************** In fgComputeDoms | |
*************** In fgDebugCheckBBlist | |
Dominator computation start blocks (those blocks with no incoming edges): | |
BB01 | |
------------------------------------------------ | |
BBnum Dominated by | |
------------------------------------------------ | |
BB01: BB01 | |
BB02: BB02 BB01 | |
BB03: BB03 BB01 | |
Inside fgBuildDomTree | |
After computing the Dominance Tree: | |
BB01 : BB03 BB02 | |
*************** In Allocate Objects | |
Trees before Allocate Objects | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 1 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
***** BB01, stmt 1 | |
[000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
[000001] -----+------ | /--* const int 0 | |
[000003] -A---+------ \--* = int | |
[000002] D----+-N---- \--* lclVar int V01 loc0 | |
***** BB01, stmt 2 | |
[000038] ------------ * stmtExpr void (IL ???... ???) | |
[000037] --C-G------- \--* jmpTrue void | |
( 3, 2) [000036] ------------ | /--* lclVar int V01 loc0 | |
( 18, 8) [000032] J-C-G--N---- \--* <= int | |
( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
***** BB02, stmt 3 | |
[000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
[000015] --C-G+------ \--* call void System.Console.WriteLine | |
[000014] -----+------ arg0 in rdi \--* lclVar int V01 loc0 | |
***** BB02, stmt 4 | |
[000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
[000019] -----+------ | /--* const int 1 | |
[000020] -----+------ | /--* + int | |
[000018] -----+------ | | \--* lclVar int V01 loc0 | |
[000022] -A---+------ \--* = int | |
[000021] D----+-N---- \--* lclVar int V01 loc0 | |
***** BB02, stmt 5 | |
[000012] ------------ * stmtExpr void (IL ???... ???) | |
[000011] --C-G+------ \--* jmpTrue void | |
( 3, 2) [000006] ------------ | /--* lclVar int V01 loc0 | |
( 18, 8) [000010] J-C-G--N---- \--* > int | |
( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
***** BB03, stmt 6 | |
[000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
[000025] -----+------ \--* return void | |
------------------------------------------------------------------------------------------------------------------- | |
*************** Exiting Allocate Objects | |
Trees after Allocate Objects | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 1 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
***** BB01, stmt 1 | |
[000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
[000001] -----+------ | /--* const int 0 | |
[000003] -A---+------ \--* = int | |
[000002] D----+-N---- \--* lclVar int V01 loc0 | |
***** BB01, stmt 2 | |
[000038] ------------ * stmtExpr void (IL ???... ???) | |
[000037] --C-G------- \--* jmpTrue void | |
( 3, 2) [000036] ------------ | /--* lclVar int V01 loc0 | |
( 18, 8) [000032] J-C-G--N---- \--* <= int | |
( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
***** BB02, stmt 3 | |
[000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
[000015] --C-G+------ \--* call void System.Console.WriteLine | |
[000014] -----+------ arg0 in rdi \--* lclVar int V01 loc0 | |
***** BB02, stmt 4 | |
[000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
[000019] -----+------ | /--* const int 1 | |
[000020] -----+------ | /--* + int | |
[000018] -----+------ | | \--* lclVar int V01 loc0 | |
[000022] -A---+------ \--* = int | |
[000021] D----+-N---- \--* lclVar int V01 loc0 | |
***** BB02, stmt 5 | |
[000012] ------------ * stmtExpr void (IL ???... ???) | |
[000011] --C-G+------ \--* jmpTrue void | |
( 3, 2) [000006] ------------ | /--* lclVar int V01 loc0 | |
( 18, 8) [000010] J-C-G--N---- \--* > int | |
( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
***** BB03, stmt 6 | |
[000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
[000025] -----+------ \--* return void | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDebugCheckBBlist | |
*************** In optOptimizeLoops() | |
After optSetBlockWeights: | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 0.5 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDebugCheckBBlist | |
*************** In optFindNaturalLoops() | |
Recorded loop L00, from BB02 to BB02 (Head=BB01, Entry=BB02, ExitCnt=1 at BB02) | |
Final natural loop table: | |
L00, from BB02 to BB02 (Head=BB01, Entry=BB02, ExitCnt=1 at BB02) | |
Marking loop L01 | |
BB02(wt= 4 ) | |
Found a total of 1 loops. | |
After loop weight marking: | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In optCloneLoops() | |
Blocks/Trees at start of phase | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
***** BB01, stmt 1 | |
[000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
[000001] -----+------ | /--* const int 0 | |
[000003] -A---+------ \--* = int | |
[000002] D----+-N---- \--* lclVar int V01 loc0 | |
***** BB01, stmt 2 | |
[000038] ------------ * stmtExpr void (IL ???... ???) | |
[000037] --C-G------- \--* jmpTrue void | |
( 3, 2) [000036] ------------ | /--* lclVar int V01 loc0 | |
( 18, 8) [000032] J-C-G--N---- \--* <= int | |
( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
***** BB02, stmt 3 | |
[000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
[000015] --C-G+------ \--* call void System.Console.WriteLine | |
[000014] -----+------ arg0 in rdi \--* lclVar int V01 loc0 | |
***** BB02, stmt 4 | |
[000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
[000019] -----+------ | /--* const int 1 | |
[000020] -----+------ | /--* + int | |
[000018] -----+------ | | \--* lclVar int V01 loc0 | |
[000022] -A---+------ \--* = int | |
[000021] D----+-N---- \--* lclVar int V01 loc0 | |
***** BB02, stmt 5 | |
[000012] ------------ * stmtExpr void (IL ???... ???) | |
[000011] --C-G+------ \--* jmpTrue void | |
( 3, 2) [000006] ------------ | /--* lclVar int V01 loc0 | |
( 18, 8) [000010] J-C-G--N---- \--* > int | |
( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
***** BB03, stmt 6 | |
[000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
[000025] -----+------ \--* return void | |
------------------------------------------------------------------------------------------------------------------- | |
Considering loop 0 to clone for optimizations. | |
> No iter flag on loop 0. | |
------------------------------------------------------------ | |
After loop cloning: | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
***** BB01, stmt 1 | |
[000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
[000001] -----+------ | /--* const int 0 | |
[000003] -A---+------ \--* = int | |
[000002] D----+-N---- \--* lclVar int V01 loc0 | |
***** BB01, stmt 2 | |
[000038] ------------ * stmtExpr void (IL ???... ???) | |
[000037] --C-G------- \--* jmpTrue void | |
( 3, 2) [000036] ------------ | /--* lclVar int V01 loc0 | |
( 18, 8) [000032] J-C-G--N---- \--* <= int | |
( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
***** BB02, stmt 3 | |
[000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
[000015] --C-G+------ \--* call void System.Console.WriteLine | |
[000014] -----+------ arg0 in rdi \--* lclVar int V01 loc0 | |
***** BB02, stmt 4 | |
[000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
[000019] -----+------ | /--* const int 1 | |
[000020] -----+------ | /--* + int | |
[000018] -----+------ | | \--* lclVar int V01 loc0 | |
[000022] -A---+------ \--* = int | |
[000021] D----+-N---- \--* lclVar int V01 loc0 | |
***** BB02, stmt 5 | |
[000012] ------------ * stmtExpr void (IL ???... ???) | |
[000011] --C-G+------ \--* jmpTrue void | |
( 3, 2) [000006] ------------ | /--* lclVar int V01 loc0 | |
( 18, 8) [000010] J-C-G--N---- \--* > int | |
( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
***** BB03, stmt 6 | |
[000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
[000025] -----+------ \--* return void | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In lvaMarkLocalVars() | |
lvaGrabTemp returning 2 (V02 tmp0) (a long lifetime temp) called for OutgoingArgSpace. | |
*** marking local variables in block BB01 (weight= 1 ) | |
[000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
[000001] -----+------ | /--* const int 0 | |
[000003] -A---+------ \--* = int | |
[000002] D----+-N---- \--* lclVar int V01 loc0 | |
New refCnts for V01: refCnt = 1, refCntWtd = 1 | |
[000038] ------------ * stmtExpr void (IL ???... ???) | |
[000037] --C-G------- \--* jmpTrue void | |
( 3, 2) [000036] ------------ | /--* lclVar int V01 loc0 | |
( 18, 8) [000032] J-C-G--N---- \--* <= int | |
( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
New refCnts for V01: refCnt = 2, refCntWtd = 2 | |
*** marking local variables in block BB02 (weight= 4 ) | |
[000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
[000015] --C-G+------ \--* call void System.Console.WriteLine | |
[000014] -----+------ arg0 in rdi \--* lclVar int V01 loc0 | |
New refCnts for V01: refCnt = 3, refCntWtd = 6 | |
[000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
[000019] -----+------ | /--* const int 1 | |
[000020] -----+------ | /--* + int | |
[000018] -----+------ | | \--* lclVar int V01 loc0 | |
[000022] -A---+------ \--* = int | |
[000021] D----+-N---- \--* lclVar int V01 loc0 | |
New refCnts for V01: refCnt = 4, refCntWtd = 10 | |
New refCnts for V01: refCnt = 5, refCntWtd = 14 | |
[000012] ------------ * stmtExpr void (IL ???... ???) | |
[000011] --C-G+------ \--* jmpTrue void | |
( 3, 2) [000006] ------------ | /--* lclVar int V01 loc0 | |
( 18, 8) [000010] J-C-G--N---- \--* > int | |
( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
New refCnts for V01: refCnt = 6, refCntWtd = 18 | |
*** marking local variables in block BB03 (weight= 1 ) | |
[000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
[000025] -----+------ \--* return void | |
*************** In optAddCopies() | |
refCnt table for 'Main': | |
V01 loc0 [ int]: refCnt = 6, refCntWtd = 18 | |
V02 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1 | |
*************** In optOptimizeBools() | |
*************** In fgDebugCheckBBlist | |
*************** In fgFindOperOrder() | |
*************** In fgSetBlockOrder() | |
fgMarkLoopHead: Checking loop head block BB02: this block will execute a call | |
The biggest BB has 5 tree nodes | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
***** BB01, stmt 1 | |
( 1, 3) [000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
N001 ( 1, 1) [000001] ------------ | /--* const int 0 | |
N003 ( 1, 3) [000003] -A------R--- \--* = int | |
N002 ( 1, 1) [000002] D------N---- \--* lclVar int V01 loc0 | |
***** BB01, stmt 2 | |
( 18, 9) [000038] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000037] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000036] ------------ | /--* lclVar int V01 loc0 | |
N003 ( 16, 7) [000032] J-C-G--N---- \--* <= int | |
N001 ( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
***** BB02, stmt 3 | |
( 15, 7) [000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
N005 ( 15, 7) [000015] --C-G------- \--* call void System.Console.WriteLine | |
N003 ( 1, 1) [000014] ------------ arg0 in rdi \--* lclVar int V01 loc0 | |
***** BB02, stmt 4 | |
( 3, 3) [000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
N002 ( 1, 1) [000019] ------------ | /--* const int 1 | |
N003 ( 3, 3) [000020] ------------ | /--* + int | |
N001 ( 1, 1) [000018] ------------ | | \--* lclVar int V01 loc0 | |
N005 ( 3, 3) [000022] -A------R--- \--* = int | |
N004 ( 1, 1) [000021] D------N---- \--* lclVar int V01 loc0 | |
***** BB02, stmt 5 | |
( 18, 9) [000012] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000011] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000006] ------------ | /--* lclVar int V01 loc0 | |
N003 ( 16, 7) [000010] J-C-G--N---- \--* > int | |
N001 ( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
***** BB03, stmt 6 | |
( 0, 0) [000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
N001 ( 0, 0) [000025] ------------ \--* return void | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In SsaBuilder::Build() | |
[SsaBuilder] Max block count is 4. | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** Exception Handling table is empty | |
[SsaBuilder] Topologically sorted the graph. | |
[SsaBuilder::ComputeImmediateDom] | |
*************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...) | |
*************** In SsaBuilder::InsertPhiFunctions() | |
*************** In fgLocalVarLiveness() | |
*************** In fgPerBlockLocalVarLiveness() | |
BB01 USE(0)={ } + HEAP | |
DEF(1)={V01} + HEAP* | |
BB02 USE(1)={V01} + HEAP | |
DEF(1)={V01} + HEAP* | |
BB03 USE(0)={} | |
DEF(0)={} | |
*************** In fgInterBlockLocalVarLiveness() | |
BB liveness after fgLiveVarAnalysis(): | |
BB01 IN (0)={ } + HEAP | |
OUT(1)={V01} + HEAP | |
BB02 IN (1)={V01} + HEAP | |
OUT(1)={V01} + HEAP | |
BB03 IN (0)={} | |
OUT(0)={} | |
Inserting phi functions: | |
Inserting phi definition for V01 at start of BB02. | |
Inserting phi definition for Heap at start of BB02. | |
*************** In SsaBuilder::RenameVariables() | |
After fgSsaBuild: | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
***** BB01, stmt 1 | |
( 1, 3) [000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
N001 ( 1, 1) [000001] ------------ | /--* const int 0 | |
N003 ( 1, 3) [000003] -A------R--- \--* = int | |
N002 ( 1, 1) [000002] D------N---- \--* lclVar int V01 loc0 d:3 | |
***** BB01, stmt 2 | |
( 18, 9) [000038] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000037] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000036] ------------ | /--* lclVar int V01 loc0 u:3 | |
N003 ( 16, 7) [000032] J-C-G--N---- \--* <= int | |
N001 ( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
***** BB02, stmt 3 | |
( 2, 3) [000042] ------------ * stmtExpr void (IL ???... ???) | |
N005 ( 2, 2) [000040] ------------ | * phi int | |
N001 ( 0, 0) [000045] ------------ | /--* phiArg int V01 loc0 u:5 | |
N002 ( 0, 0) [000043] ------------ | \--* phiArg int V01 loc0 u:3 | |
N007 ( 2, 3) [000041] -A------R--- \--* = int | |
N006 ( 1, 1) [000039] D------N---- \--* lclVar int V01 loc0 d:4 | |
***** BB02, stmt 4 | |
( 15, 7) [000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
N005 ( 15, 7) [000015] --C-G------- \--* call void System.Console.WriteLine | |
N003 ( 1, 1) [000014] ------------ arg0 in rdi \--* lclVar int V01 loc0 u:4 | |
***** BB02, stmt 5 | |
( 3, 3) [000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
N002 ( 1, 1) [000019] ------------ | /--* const int 1 | |
N003 ( 3, 3) [000020] ------------ | /--* + int | |
N001 ( 1, 1) [000018] ------------ | | \--* lclVar int V01 loc0 u:4 (last use) | |
N005 ( 3, 3) [000022] -A------R--- \--* = int | |
N004 ( 1, 1) [000021] B------N---- \--* lclVar int V01 loc0 d:5 | |
***** BB02, stmt 6 | |
( 18, 9) [000012] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000011] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000006] ------------ | /--* lclVar int V01 loc0 u:5 | |
N003 ( 16, 7) [000010] J-C-G--N---- \--* > int | |
N001 ( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
***** BB03, stmt 7 | |
( 0, 0) [000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
N001 ( 0, 0) [000025] ------------ \--* return void | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In optEarlyProp() | |
*************** In fgValueNumber() | |
Heap Initial Value in BB01 is: $81 | |
The SSA definition for heap (#2) at start of BB01 is $81 {InitVal($41)} | |
***** BB01, stmt 1 (before) | |
N001 ( 1, 1) [000001] ------------ /--* const int 0 | |
N003 ( 1, 3) [000003] -A------R--- * = int | |
N002 ( 1, 1) [000002] D------N---- \--* lclVar int V01 loc0 d:3 | |
N001 [000001] const 0 => $40 {IntCns 0} | |
N002 [000002] lclVar V01 loc0 d:3 => $40 {IntCns 0} | |
N003 [000003] = => $40 {IntCns 0} | |
***** BB01, stmt 1 (after) | |
N001 ( 1, 1) [000001] ------------ /--* const int 0 $40 | |
N003 ( 1, 3) [000003] -A------R--- * = int $40 | |
N002 ( 1, 1) [000002] D------N---- \--* lclVar int V01 loc0 d:3 $40 | |
--------- | |
***** BB01, stmt 2 (before) | |
N004 ( 18, 9) [000037] --C-G------- * jmpTrue void | |
N002 ( 1, 1) [000036] ------------ | /--* lclVar int V01 loc0 u:3 | |
N003 ( 16, 7) [000032] J-C-G--N---- \--* <= int | |
N001 ( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
fgCurHeapVN assigned by CALL at [000033] to new unique VN: $140. | |
N001 [000033] call => $101 {101} | |
N002 [000036] lclVar V01 loc0 u:3 => $40 {IntCns 0} | |
N003 [000032] <= => $180 {<=($101, $40)} | |
***** BB01, stmt 2 (after) | |
N004 ( 18, 9) [000037] --C-G------- * jmpTrue void | |
N002 ( 1, 1) [000036] ------------ | /--* lclVar int V01 loc0 u:3 $40 | |
N003 ( 16, 7) [000032] J-C-G--N---- \--* <= int $180 | |
N001 ( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $101 | |
finish(BB01). | |
Succ(BB02). | |
Not yet completed. | |
Not all preds complete Adding to notallDone, if necessary... | |
Was necessary. | |
Succ(BB03). | |
Not yet completed. | |
Not all preds complete Adding to notallDone, if necessary... | |
Was necessary. | |
SSA definition: set VN of local 1/4 to $1c0 {PhiDef($1, $4, $181)}. | |
Computing heap state for block BB02, entry block for loops 0 to 0: | |
Loop 0 has heap havoc effect; heap state is new fresh $200. | |
The SSA definition for heap (#4) at start of BB02 is $200 {200} | |
***** BB02, stmt 3 (before) | |
N005 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine | |
N003 ( 1, 1) [000014] ------------ arg0 in rdi \--* lclVar int V01 loc0 u:4 | |
N001 [000030] argPlace => $240 {240} | |
N002 [000016] <list> => $280 {<list>($240, $0)} | |
N003 [000014] lclVar V01 loc0 u:4 => $1c0 {PhiDef($1, $4, $181)} | |
N004 [000031] <list> => $281 {<list>($1c0, $0)} | |
VN of ARGPLACE tree [000030] updated to $1c0 {PhiDef($1, $4, $181)} | |
N002 [000016] <list> => $281 {<list>($1c0, $0)} | |
fgCurHeapVN assigned by CALL at [000015] to new unique VN: $201. | |
N005 [000015] call => $VN.Void | |
***** BB02, stmt 3 (after) | |
N005 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine $VN.Void | |
N003 ( 1, 1) [000014] ------------ arg0 in rdi \--* lclVar int V01 loc0 u:4 $1c0 | |
--------- | |
***** BB02, stmt 4 (before) | |
N002 ( 1, 1) [000019] ------------ /--* const int 1 | |
N003 ( 3, 3) [000020] ------------ /--* + int | |
N001 ( 1, 1) [000018] ------------ | \--* lclVar int V01 loc0 u:4 (last use) | |
N005 ( 3, 3) [000022] -A------R--- * = int | |
N004 ( 1, 1) [000021] B------N---- \--* lclVar int V01 loc0 d:5 | |
N001 [000018] lclVar V01 loc0 u:4 (last use) => $1c0 {PhiDef($1, $4, $181)} | |
N002 [000019] const 1 => $44 {IntCns 1} | |
N003 [000020] + => $182 {+($44, $1c0)} | |
N004 [000021] lclVar V01 loc0 d:5 => $182 {+($44, $1c0)} | |
N005 [000022] = => $182 {+($44, $1c0)} | |
***** BB02, stmt 4 (after) | |
N002 ( 1, 1) [000019] ------------ /--* const int 1 $44 | |
N003 ( 3, 3) [000020] ------------ /--* + int $182 | |
N001 ( 1, 1) [000018] ------------ | \--* lclVar int V01 loc0 u:4 (last use) $1c0 | |
N005 ( 3, 3) [000022] -A------R--- * = int $182 | |
N004 ( 1, 1) [000021] B------N---- \--* lclVar int V01 loc0 d:5 $182 | |
--------- | |
***** BB02, stmt 5 (before) | |
N004 ( 18, 9) [000011] --C-G------- * jmpTrue void | |
N002 ( 1, 1) [000006] ------------ | /--* lclVar int V01 loc0 u:5 | |
N003 ( 16, 7) [000010] J-C-G--N---- \--* > int | |
N001 ( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline | |
fgCurHeapVN assigned by CALL at [000028] to new unique VN: $202. | |
N001 [000028] call => $242 {242} | |
N002 [000006] lclVar V01 loc0 u:5 => $182 {+($44, $1c0)} | |
N003 [000010] > => $183 {>($242, $182)} | |
***** BB02, stmt 5 (after) | |
N004 ( 18, 9) [000011] --C-G------- * jmpTrue void | |
N002 ( 1, 1) [000006] ------------ | /--* lclVar int V01 loc0 u:5 $182 | |
N003 ( 16, 7) [000010] J-C-G--N---- \--* > int $183 | |
N001 ( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $242 | |
finish(BB02). | |
Succ(BB03). | |
Not yet completed. | |
All preds complete, adding to allDone. | |
Succ(BB02). | |
The SSA definition for heap (#3) at start of BB03 is $140 {140} | |
***** BB03, stmt 7 (before) | |
N001 ( 0, 0) [000025] ------------ * return void | |
N001 [000025] return => $2c0 {2c0} | |
***** BB03, stmt 7 (after) | |
N001 ( 0, 0) [000025] ------------ * return void $2c0 | |
finish(BB03). | |
*************** In optHoistLoopCode() | |
Blocks/Trees before phase | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
***** BB01, stmt 1 | |
( 1, 3) [000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
N001 ( 1, 1) [000001] ------------ | /--* const int 0 $40 | |
N003 ( 1, 3) [000003] -A------R--- \--* = int $40 | |
N002 ( 1, 1) [000002] D------N---- \--* lclVar int V01 loc0 d:3 $40 | |
***** BB01, stmt 2 | |
( 18, 9) [000038] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000037] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000036] ------------ | /--* lclVar int V01 loc0 u:3 $40 | |
N003 ( 16, 7) [000032] J-C-G--N---- \--* <= int $180 | |
N001 ( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $101 | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
***** BB02, stmt 3 | |
( 2, 3) [000042] ------------ * stmtExpr void (IL ???... ???) | |
N005 ( 2, 2) [000040] ------------ | * phi int | |
N001 ( 0, 0) [000045] ------------ | /--* phiArg int V01 loc0 u:5 | |
N002 ( 0, 0) [000043] ------------ | \--* phiArg int V01 loc0 u:3 $40 | |
N007 ( 2, 3) [000041] -A------R--- \--* = int | |
N006 ( 1, 1) [000039] D------N---- \--* lclVar int V01 loc0 d:4 | |
***** BB02, stmt 4 | |
( 15, 7) [000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
N005 ( 15, 7) [000015] --C-G------- \--* call void System.Console.WriteLine $VN.Void | |
N003 ( 1, 1) [000014] ------------ arg0 in rdi \--* lclVar int V01 loc0 u:4 $1c0 | |
***** BB02, stmt 5 | |
( 3, 3) [000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
N002 ( 1, 1) [000019] ------------ | /--* const int 1 $44 | |
N003 ( 3, 3) [000020] ------------ | /--* + int $182 | |
N001 ( 1, 1) [000018] ------------ | | \--* lclVar int V01 loc0 u:4 (last use) $1c0 | |
N005 ( 3, 3) [000022] -A------R--- \--* = int $182 | |
N004 ( 1, 1) [000021] B------N---- \--* lclVar int V01 loc0 d:5 $182 | |
***** BB02, stmt 6 | |
( 18, 9) [000012] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000011] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000006] ------------ | /--* lclVar int V01 loc0 u:5 $182 | |
N003 ( 16, 7) [000010] J-C-G--N---- \--* > int $183 | |
N001 ( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $242 | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
***** BB03, stmt 7 | |
( 0, 0) [000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
N001 ( 0, 0) [000025] ------------ \--* return void $2c0 | |
------------------------------------------------------------------------------------------------------------------- | |
optHoistLoopCode for loop L00 <BB02..BB02>: | |
Loop body contains a call | |
USEDEF (1)={V01} | |
INOUT (1)={V01} | |
LOOPVARS(1)={V01} | |
optHoistLoopExprsForBlock BB02 (weight= 4 ) of loop L00 <BB02..BB02>, firstBlock is true | |
*************** In optVnCopyProp() | |
*************** In SsaBuilder::ComputeDominators(Compiler*, ...) | |
Copy Assertion for BB01 | |
Live vars: {} => {V01} | |
Copy Assertion for BB03 | |
Copy Assertion for BB02 | |
Live vars: {V01} => {} | |
Live vars: {} => {V01} | |
*************** In optOptimizeCSEs() | |
Blocks/Trees at start of optOptimizeCSE phase | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
***** BB01, stmt 1 | |
( 1, 3) [000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
N001 ( 1, 1) [000001] ------------ | /--* const int 0 $40 | |
N003 ( 1, 3) [000003] -A------R--- \--* = int $40 | |
N002 ( 1, 1) [000002] D------N---- \--* lclVar int V01 loc0 d:3 $40 | |
***** BB01, stmt 2 | |
( 18, 9) [000038] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000037] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000036] ------------ | /--* lclVar int V01 loc0 u:3 $40 | |
N003 ( 16, 7) [000032] J-C-G--N---- \--* <= int $180 | |
N001 ( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $101 | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
***** BB02, stmt 3 | |
( 2, 3) [000042] ------------ * stmtExpr void (IL ???... ???) | |
N005 ( 2, 2) [000040] ------------ | * phi int | |
N001 ( 0, 0) [000045] ------------ | /--* phiArg int V01 loc0 u:5 | |
N002 ( 0, 0) [000043] ------------ | \--* phiArg int V01 loc0 u:3 $40 | |
N007 ( 2, 3) [000041] -A------R--- \--* = int | |
N006 ( 1, 1) [000039] D------N---- \--* lclVar int V01 loc0 d:4 | |
***** BB02, stmt 4 | |
( 15, 7) [000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
N005 ( 15, 7) [000015] --C-G------- \--* call void System.Console.WriteLine $VN.Void | |
N003 ( 1, 1) [000014] ------------ arg0 in rdi \--* lclVar int V01 loc0 u:4 $1c0 | |
***** BB02, stmt 5 | |
( 3, 3) [000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
N002 ( 1, 1) [000019] ------------ | /--* const int 1 $44 | |
N003 ( 3, 3) [000020] ------------ | /--* + int $182 | |
N001 ( 1, 1) [000018] ------------ | | \--* lclVar int V01 loc0 u:4 (last use) $1c0 | |
N005 ( 3, 3) [000022] -A------R--- \--* = int $182 | |
N004 ( 1, 1) [000021] B------N---- \--* lclVar int V01 loc0 d:5 $182 | |
***** BB02, stmt 6 | |
( 18, 9) [000012] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000011] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000006] ------------ | /--* lclVar int V01 loc0 u:5 $182 | |
N003 ( 16, 7) [000010] J-C-G--N---- \--* > int $183 | |
N001 ( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $242 | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
***** BB03, stmt 7 | |
( 0, 0) [000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
N001 ( 0, 0) [000025] ------------ \--* return void $2c0 | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In optOptimizeValnumCSEs() | |
*************** In optAssertionPropMain() | |
Blocks/Trees at start of phase | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
***** BB01, stmt 1 | |
( 1, 3) [000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
N001 ( 1, 1) [000001] ------------ | /--* const int 0 $40 | |
N003 ( 1, 3) [000003] -A------R--- \--* = int $40 | |
N002 ( 1, 1) [000002] D------N---- \--* lclVar int V01 loc0 d:3 $40 | |
***** BB01, stmt 2 | |
( 18, 9) [000038] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000037] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000036] ------------ | /--* lclVar int V01 loc0 u:3 $40 | |
N003 ( 16, 7) [000032] J-C-G--N---- \--* <= int $180 | |
N001 ( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $101 | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
***** BB02, stmt 3 | |
( 2, 3) [000042] ------------ * stmtExpr void (IL ???... ???) | |
N005 ( 2, 2) [000040] ------------ | * phi int | |
N001 ( 0, 0) [000045] ------------ | /--* phiArg int V01 loc0 u:5 | |
N002 ( 0, 0) [000043] ------------ | \--* phiArg int V01 loc0 u:3 $40 | |
N007 ( 2, 3) [000041] -A------R--- \--* = int | |
N006 ( 1, 1) [000039] D------N---- \--* lclVar int V01 loc0 d:4 | |
***** BB02, stmt 4 | |
( 15, 7) [000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
N005 ( 15, 7) [000015] --C-G------- \--* call void System.Console.WriteLine $VN.Void | |
N003 ( 1, 1) [000014] ------------ arg0 in rdi \--* lclVar int V01 loc0 u:4 $1c0 | |
***** BB02, stmt 5 | |
( 3, 3) [000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
N002 ( 1, 1) [000019] ------------ | /--* const int 1 $44 | |
N003 ( 3, 3) [000020] ------------ | /--* + int $182 | |
N001 ( 1, 1) [000018] ------------ | | \--* lclVar int V01 loc0 u:4 (last use) $1c0 | |
N005 ( 3, 3) [000022] -A------R--- \--* = int $182 | |
N004 ( 1, 1) [000021] B------N---- \--* lclVar int V01 loc0 d:5 $182 | |
***** BB02, stmt 6 | |
( 18, 9) [000012] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000011] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000006] ------------ | /--* lclVar int V01 loc0 u:5 $182 | |
N003 ( 16, 7) [000010] J-C-G--N---- \--* > int $183 | |
N001 ( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $242 | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
***** BB03, stmt 7 | |
( 0, 0) [000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
N001 ( 0, 0) [000025] ------------ \--* return void $2c0 | |
------------------------------------------------------------------------------------------------------------------- | |
New refCnts for V01: refCnt = 5, refCntWtd = 17 | |
After constant propagation on [000036]: | |
( 18, 9) [000038] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000037] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000036] ------------ | /--* const int 0 $40 | |
N003 ( 16, 7) [000032] J-C-G--N---- \--* <= int $180 | |
N001 ( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $101 | |
argSlots=0, preallocatedArgCount=0, nextSlotNum=0, lvaOutgoingArgSpaceSize=0 | |
optVNAssertionPropCurStmt morphed tree: | |
N004 ( 18, 9) [000037] --C-G------- * jmpTrue void | |
N002 ( 1, 1) [000036] ------------ | /--* const int 0 $40 | |
N003 ( 16, 7) [000032] J-C-G--N---- \--* <= int $180 | |
N001 ( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $101 | |
GenTreeNode creates assertion: | |
N004 ( 18, 9) [000037] --C-G------- * jmpTrue void | |
In BB01 New Global Constant Assertion: (384, 64) ($180,$40) Loop_Bnd {<=($101, $40)} is not {IntCns 0} index=#01, mask=0000000000000001 | |
GenTreeNode creates assertion: | |
N004 ( 18, 9) [000037] --C-G------- * jmpTrue void | |
In BB01 New Global Constant Assertion: (384, 64) ($180,$40) Loop_Bnd {<=($101, $40)} is {IntCns 0} index=#02, mask=0000000000000002 | |
BB01 valueGen = 0000000000000002 => BB03 valueGen = 0000000000000001, | |
BB02 valueGen = 0000000000000000 => BB02 valueGen = 0000000000000000, | |
BB03 valueGen = 0000000000000000AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000 | |
AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000 | |
AssertionPropCallback::Changed : BB01 before out -> 0000000000000003; after out -> 0000000000000002; | |
jumpDest before out -> 0000000000000003; jumpDest after out -> 0000000000000001; | |
AssertionPropCallback::StartMerge: BB02 in -> 0000000000000003 | |
AssertionPropCallback::Merge : BB02 in -> 0000000000000003, predBlock BB01 out -> 0000000000000002 | |
AssertionPropCallback::Merge : BB02 in -> 0000000000000002, predBlock BB02 out -> 0000000000000003 | |
AssertionPropCallback::EndMerge : BB02 in -> 0000000000000002 | |
AssertionPropCallback::Changed : BB02 before out -> 0000000000000003; after out -> 0000000000000002; | |
jumpDest before out -> 0000000000000003; jumpDest after out -> 0000000000000002; | |
AssertionPropCallback::StartMerge: BB03 in -> 0000000000000003 | |
AssertionPropCallback::Merge : BB03 in -> 0000000000000003, predBlock BB01 out -> 0000000000000002 | |
AssertionPropCallback::Merge : BB03 in -> 0000000000000001, predBlock BB02 out -> 0000000000000002 | |
AssertionPropCallback::EndMerge : BB03 in -> 0000000000000000 | |
AssertionPropCallback::Changed : BB03 before out -> 0000000000000003; after out -> 0000000000000000; | |
jumpDest before out -> 0000000000000003; jumpDest after out -> 0000000000000000; | |
AssertionPropCallback::StartMerge: BB03 in -> 0000000000000000 | |
AssertionPropCallback::Merge : BB03 in -> 0000000000000000, predBlock BB01 out -> 0000000000000002 | |
AssertionPropCallback::Merge : BB03 in -> 0000000000000000, predBlock BB02 out -> 0000000000000002 | |
AssertionPropCallback::EndMerge : BB03 in -> 0000000000000000 | |
AssertionPropCallback::Unchanged : BB03 out -> 0000000000000000; jumpDest out -> 0000000000000000 | |
AssertionPropCallback::StartMerge: BB02 in -> 0000000000000002 | |
AssertionPropCallback::Merge : BB02 in -> 0000000000000002, predBlock BB01 out -> 0000000000000002 | |
AssertionPropCallback::Merge : BB02 in -> 0000000000000002, predBlock BB02 out -> 0000000000000002 | |
AssertionPropCallback::EndMerge : BB02 in -> 0000000000000002 | |
AssertionPropCallback::Unchanged : BB02 out -> 0000000000000002; jumpDest out -> 0000000000000002 | |
BB01 valueIn = 0000000000000000 valueOut = 0000000000000002 => BB03 valueOut= 0000000000000001 | |
BB02 valueIn = 0000000000000002 valueOut = 0000000000000002 => BB02 valueOut= 0000000000000002 | |
BB03 valueIn = 0000000000000000 valueOut = 0000000000000000 | |
Propagating 0000000000000000 assertions for BB01, stmt [000004], tree [000001], tree -> 0 | |
Propagating 0000000000000000 assertions for BB01, stmt [000004], tree [000002], tree -> 0 | |
Propagating 0000000000000000 assertions for BB01, stmt [000004], tree [000003], tree -> 0 | |
Propagating 0000000000000000 assertions for BB01, stmt [000038], tree [000033], tree -> 0 | |
Propagating 0000000000000000 assertions for BB01, stmt [000038], tree [000036], tree -> 0 | |
Propagating 0000000000000000 assertions for BB01, stmt [000038], tree [000032], tree -> 0 | |
Propagating 0000000000000000 assertions for BB01, stmt [000038], tree [000037], tree -> 1 | |
Propagating 0000000000000002 assertions for BB02, stmt [000017], tree [000030], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000017], tree [000016], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000017], tree [000014], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000017], tree [000031], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000017], tree [000015], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000023], tree [000018], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000023], tree [000019], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000023], tree [000020], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000023], tree [000021], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000023], tree [000022], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000012], tree [000028], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000012], tree [000006], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000012], tree [000010], tree -> 0 | |
Propagating 0000000000000002 assertions for BB02, stmt [000012], tree [000011], tree -> 0 | |
Propagating 0000000000000000 assertions for BB03, stmt [000026], tree [000025], tree -> 0 | |
*************** In fgDebugCheckBBlist | |
*************** In OptimizeRangeChecks() | |
Blocks/trees before phase | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target gcsafe | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
***** BB01, stmt 1 | |
( 1, 3) [000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
N001 ( 1, 1) [000001] ------------ | /--* const int 0 $40 | |
N003 ( 1, 3) [000003] -A------R--- \--* = int $40 | |
N002 ( 1, 1) [000002] D------N---- \--* lclVar int V01 loc0 d:3 $40 | |
***** BB01, stmt 2 | |
( 18, 9) [000038] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000037] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000036] ------------ | /--* const int 0 $40 | |
N003 ( 16, 7) [000032] J-C-G--N---- \--* <= int $180 | |
N001 ( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $101 | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
***** BB02, stmt 3 | |
( 2, 3) [000042] ------------ * stmtExpr void (IL ???... ???) | |
N005 ( 2, 2) [000040] ------------ | * phi int | |
N001 ( 0, 0) [000045] ------------ | /--* phiArg int V01 loc0 u:5 | |
N002 ( 0, 0) [000043] ------------ | \--* phiArg int V01 loc0 u:3 $40 | |
N007 ( 2, 3) [000041] -A------R--- \--* = int | |
N006 ( 1, 1) [000039] D------N---- \--* lclVar int V01 loc0 d:4 | |
***** BB02, stmt 4 | |
( 15, 7) [000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
N005 ( 15, 7) [000015] --C-G------- \--* call void System.Console.WriteLine $VN.Void | |
N003 ( 1, 1) [000014] ------------ arg0 in rdi \--* lclVar int V01 loc0 u:4 $1c0 | |
***** BB02, stmt 5 | |
( 3, 3) [000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
N002 ( 1, 1) [000019] ------------ | /--* const int 1 $44 | |
N003 ( 3, 3) [000020] ------------ | /--* + int $182 | |
N001 ( 1, 1) [000018] ------------ | | \--* lclVar int V01 loc0 u:4 (last use) $1c0 | |
N005 ( 3, 3) [000022] -A------R--- \--* = int $182 | |
N004 ( 1, 1) [000021] B------N---- \--* lclVar int V01 loc0 d:5 $182 | |
***** BB02, stmt 6 | |
( 18, 9) [000012] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000011] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000006] ------------ | /--* lclVar int V01 loc0 u:5 $182 | |
N003 ( 16, 7) [000010] J-C-G--N---- \--* > int $183 | |
N001 ( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $242 | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
***** BB03, stmt 7 | |
( 0, 0) [000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
N001 ( 0, 0) [000025] ------------ \--* return void $2c0 | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDetermineFirstColdBlock() | |
No procedure splitting will be done for this method | |
*************** In IR Rationalize | |
Trees before IR Rationalize | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target gcsafe | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
***** BB01, stmt 1 | |
( 1, 3) [000004] ------------ * stmtExpr void (IL 0x000...0x001) | |
N001 ( 1, 1) [000001] ------------ | /--* const int 0 $40 | |
N003 ( 1, 3) [000003] -A------R--- \--* = int $40 | |
N002 ( 1, 1) [000002] D------N---- \--* lclVar int V01 loc0 d:3 $40 | |
***** BB01, stmt 2 | |
( 18, 9) [000038] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000037] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000036] ------------ | /--* const int 0 $40 | |
N003 ( 16, 7) [000032] J-C-G--N---- \--* <= int $180 | |
N001 ( 14, 5) [000033] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $101 | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
***** BB02, stmt 3 | |
( 2, 3) [000042] ------------ * stmtExpr void (IL ???... ???) | |
N005 ( 2, 2) [000040] ------------ | * phi int | |
N001 ( 0, 0) [000045] ------------ | /--* phiArg int V01 loc0 u:5 | |
N002 ( 0, 0) [000043] ------------ | \--* phiArg int V01 loc0 u:3 $40 | |
N007 ( 2, 3) [000041] -A------R--- \--* = int | |
N006 ( 1, 1) [000039] D------N---- \--* lclVar int V01 loc0 d:4 | |
***** BB02, stmt 4 | |
( 15, 7) [000017] ------------ * stmtExpr void (IL 0x004...0x00D) | |
N005 ( 15, 7) [000015] --C-G------- \--* call void System.Console.WriteLine $VN.Void | |
N003 ( 1, 1) [000014] ------------ arg0 in rdi \--* lclVar int V01 loc0 u:4 $1c0 | |
***** BB02, stmt 5 | |
( 3, 3) [000023] ------------ * stmtExpr void (IL 0x00A... ???) | |
N002 ( 1, 1) [000019] ------------ | /--* const int 1 $44 | |
N003 ( 3, 3) [000020] ------------ | /--* + int $182 | |
N001 ( 1, 1) [000018] ------------ | | \--* lclVar int V01 loc0 u:4 (last use) $1c0 | |
N005 ( 3, 3) [000022] -A------R--- \--* = int $182 | |
N004 ( 1, 1) [000021] B------N---- \--* lclVar int V01 loc0 d:5 $182 | |
***** BB02, stmt 6 | |
( 18, 9) [000012] ------------ * stmtExpr void (IL ???... ???) | |
N004 ( 18, 9) [000011] --C-G------- \--* jmpTrue void | |
N002 ( 1, 1) [000006] ------------ | /--* lclVar int V01 loc0 u:5 $182 | |
N003 ( 16, 7) [000010] J-C-G--N---- \--* > int $183 | |
N001 ( 14, 5) [000028] --C-G------- \--* call int ConsoleApplication.Program.GetNumberNoInline $242 | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
***** BB03, stmt 7 | |
( 0, 0) [000026] ------------ * stmtExpr void (IL 0x016...0x016) | |
N001 ( 0, 0) [000025] ------------ \--* return void $2c0 | |
------------------------------------------------------------------------------------------------------------------- | |
rewriting asg(lclVar, X) to st.lclVar(X) | |
N003 ( 1, 3) [000003] DA---------- * st.lclVar int V01 loc0 d:3 | |
rewriting asg(lclVar, X) to st.lclVar(X) | |
N007 ( 2, 3) [000041] DA---------- * st.lclVar int V01 loc0 d:4 | |
rewriting asg(lclVar, X) to st.lclVar(X) | |
N005 ( 3, 3) [000022] DA---------- * st.lclVar int V01 loc0 d:5 | |
*************** Exiting IR Rationalize | |
Trees after IR Rationalize | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target gcsafe LIR | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd LIR | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
( 1, 3) [000004] ------------ il_offset void IL offset: 0 | |
N001 ( 1, 1) [000001] ------------ t1 = const int 0 $40 | |
/--* t1 int | |
N003 ( 1, 3) [000003] DA---------- * st.lclVar int V01 loc0 d:3 | |
N001 ( 14, 5) [000033] --C-G------- t33 = call int ConsoleApplication.Program.GetNumberNoInline $101 | |
N002 ( 1, 1) [000036] ------------ t36 = const int 0 $40 | |
/--* t33 int | |
+--* t36 int | |
N003 ( 16, 7) [000032] J-C-G--N---- t32 = * <= int $180 | |
/--* t32 int | |
N004 ( 18, 9) [000037] --C-G------- * jmpTrue void | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
N001 ( 0, 0) [000045] ------------ t45 = phiArg int V01 loc0 u:5 | |
N002 ( 0, 0) [000043] ------------ t43 = phiArg int V01 loc0 u:3 $40 | |
/--* t45 int | |
+--* t43 int | |
N005 ( 2, 2) [000040] ------------ t40 = * phi int | |
/--* t40 int | |
N007 ( 2, 3) [000041] DA---------- * st.lclVar int V01 loc0 d:4 | |
( 15, 7) [000017] ------------ il_offset void IL offset: 4 | |
N003 ( 1, 1) [000014] ------------ t14 = lclVar int V01 loc0 u:4 $1c0 | |
/--* t14 int arg0 in rdi | |
N005 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine $VN.Void | |
( 3, 3) [000023] ------------ il_offset void IL offset: 10 | |
N001 ( 1, 1) [000018] ------------ t18 = lclVar int V01 loc0 u:4 (last use) $1c0 | |
N002 ( 1, 1) [000019] ------------ t19 = const int 1 $44 | |
/--* t18 int | |
+--* t19 int | |
N003 ( 3, 3) [000020] ------------ t20 = * + int $182 | |
/--* t20 int | |
N005 ( 3, 3) [000022] DA---------- * st.lclVar int V01 loc0 d:5 | |
N001 ( 14, 5) [000028] --C-G------- t28 = call int ConsoleApplication.Program.GetNumberNoInline $242 | |
N002 ( 1, 1) [000006] ------------ t6 = lclVar int V01 loc0 u:5 $182 | |
/--* t28 int | |
+--* t6 int | |
N003 ( 16, 7) [000010] J-C-G--N---- t10 = * > int $183 | |
/--* t10 int | |
N004 ( 18, 9) [000011] --C-G------- * jmpTrue void | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
( 0, 0) [000026] ------------ il_offset void IL offset: 22 | |
N001 ( 0, 0) [000025] ------------ return void $2c0 | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDebugCheckBBlist | |
*************** In fgDebugCheckBBlist | |
*************** In Lowering | |
Trees before Lowering | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target gcsafe LIR | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd LIR | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
( 1, 3) [000004] ------------ il_offset void IL offset: 0 | |
N001 ( 1, 1) [000001] ------------ t1 = const int 0 $40 | |
/--* t1 int | |
N003 ( 1, 3) [000003] DA---------- * st.lclVar int V01 loc0 d:3 | |
N001 ( 14, 5) [000033] --C-G------- t33 = call int ConsoleApplication.Program.GetNumberNoInline $101 | |
N002 ( 1, 1) [000036] ------------ t36 = const int 0 $40 | |
/--* t33 int | |
+--* t36 int | |
N003 ( 16, 7) [000032] J-C-G--N---- t32 = * <= int $180 | |
/--* t32 int | |
N004 ( 18, 9) [000037] --C-G------- * jmpTrue void | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
N001 ( 0, 0) [000045] ------------ t45 = phiArg int V01 loc0 u:5 | |
N002 ( 0, 0) [000043] ------------ t43 = phiArg int V01 loc0 u:3 $40 | |
/--* t45 int | |
+--* t43 int | |
N005 ( 2, 2) [000040] ------------ t40 = * phi int | |
/--* t40 int | |
N007 ( 2, 3) [000041] DA---------- * st.lclVar int V01 loc0 d:4 | |
( 15, 7) [000017] ------------ il_offset void IL offset: 4 | |
N003 ( 1, 1) [000014] ------------ t14 = lclVar int V01 loc0 u:4 $1c0 | |
/--* t14 int arg0 in rdi | |
N005 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine $VN.Void | |
( 3, 3) [000023] ------------ il_offset void IL offset: 10 | |
N001 ( 1, 1) [000018] ------------ t18 = lclVar int V01 loc0 u:4 (last use) $1c0 | |
N002 ( 1, 1) [000019] ------------ t19 = const int 1 $44 | |
/--* t18 int | |
+--* t19 int | |
N003 ( 3, 3) [000020] ------------ t20 = * + int $182 | |
/--* t20 int | |
N005 ( 3, 3) [000022] DA---------- * st.lclVar int V01 loc0 d:5 | |
N001 ( 14, 5) [000028] --C-G------- t28 = call int ConsoleApplication.Program.GetNumberNoInline $242 | |
N002 ( 1, 1) [000006] ------------ t6 = lclVar int V01 loc0 u:5 $182 | |
/--* t28 int | |
+--* t6 int | |
N003 ( 16, 7) [000010] J-C-G--N---- t10 = * > int $183 | |
/--* t10 int | |
N004 ( 18, 9) [000011] --C-G------- * jmpTrue void | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
( 0, 0) [000026] ------------ il_offset void IL offset: 22 | |
N001 ( 0, 0) [000025] ------------ return void $2c0 | |
------------------------------------------------------------------------------------------------------------------- | |
lowering call (before): | |
N001 ( 14, 5) [000033] --C-G------- t33 = call int ConsoleApplication.Program.GetNumberNoInline $101 | |
objp: | |
====== | |
args: | |
====== | |
late: | |
====== | |
lowering call (after): | |
N001 ( 14, 5) [000033] --C-G------- t33 = call int ConsoleApplication.Program.GetNumberNoInline $101 | |
lowering call (before): | |
N003 ( 1, 1) [000014] ------------ t14 = lclVar int V01 loc0 u:4 $1c0 | |
/--* t14 int arg0 in rdi | |
N005 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine $VN.Void | |
objp: | |
====== | |
args: | |
====== | |
lowering arg : N001 ( 0, 0) [000030] ----------L- * argPlace int $1c0 | |
late: | |
====== | |
lowering arg : N003 ( 1, 1) [000014] ------------ * lclVar int V01 loc0 u:4 $1c0 | |
new node is : [000047] ------------ * putarg_reg int | |
lowering call (after): | |
N003 ( 1, 1) [000014] ------------ t14 = lclVar int V01 loc0 u:4 $1c0 | |
/--* t14 int | |
[000047] ------------ t47 = * putarg_reg int | |
/--* t47 int arg0 in rdi | |
N005 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine $VN.Void | |
lowering call (before): | |
N001 ( 14, 5) [000028] --C-G------- t28 = call int ConsoleApplication.Program.GetNumberNoInline $242 | |
objp: | |
====== | |
args: | |
====== | |
late: | |
====== | |
lowering call (after): | |
N001 ( 14, 5) [000028] --C-G------- t28 = call int ConsoleApplication.Program.GetNumberNoInline $242 | |
lowering GT_RETURN | |
N001 ( 0, 0) [000025] ------------ * return void $2c0 | |
============Lower has completed modifying nodes, proceeding to initialize LSRA TreeNodeInfo structs... | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target gcsafe LIR | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd LIR | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
( 1, 3) [000004] ------------ il_offset void IL offset: 0 | |
N001 ( 1, 1) [000001] ------------ t1 = const int 0 $40 | |
/--* t1 int | |
N003 ( 1, 3) [000003] DA---------- * st.lclVar int V01 loc0 d:3 | |
N001 ( 14, 5) [000033] --C-G------- t33 = call int ConsoleApplication.Program.GetNumberNoInline $101 | |
N002 ( 1, 1) [000036] ------------ t36 = const int 0 $40 | |
/--* t33 int | |
+--* t36 int | |
N003 ( 16, 7) [000032] J-C-G--N---- t32 = * <= int $180 | |
/--* t32 int | |
N004 ( 18, 9) [000037] --C-G------- * jmpTrue void | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
N001 ( 0, 0) [000045] ------------ t45 = phiArg int V01 loc0 u:5 | |
N002 ( 0, 0) [000043] ------------ t43 = phiArg int V01 loc0 u:3 $40 | |
/--* t45 int | |
+--* t43 int | |
N005 ( 2, 2) [000040] ------------ t40 = * phi int | |
/--* t40 int | |
N007 ( 2, 3) [000041] DA---------- * st.lclVar int V01 loc0 d:4 | |
( 15, 7) [000017] ------------ il_offset void IL offset: 4 | |
N003 ( 1, 1) [000014] ------------ t14 = lclVar int V01 loc0 u:4 $1c0 | |
/--* t14 int | |
[000047] ------------ t47 = * putarg_reg int | |
/--* t47 int arg0 in rdi | |
N005 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine $VN.Void | |
( 3, 3) [000023] ------------ il_offset void IL offset: 10 | |
N001 ( 1, 1) [000018] ------------ t18 = lclVar int V01 loc0 u:4 (last use) $1c0 | |
N002 ( 1, 1) [000019] ------------ t19 = const int 1 $44 | |
/--* t18 int | |
+--* t19 int | |
N003 ( 3, 3) [000020] ------------ t20 = * + int $182 | |
/--* t20 int | |
N005 ( 3, 3) [000022] DA---------- * st.lclVar int V01 loc0 d:5 | |
N001 ( 14, 5) [000028] --C-G------- t28 = call int ConsoleApplication.Program.GetNumberNoInline $242 | |
N002 ( 1, 1) [000006] ------------ t6 = lclVar int V01 loc0 u:5 $182 | |
/--* t28 int | |
+--* t6 int | |
N003 ( 16, 7) [000010] J-C-G--N---- t10 = * > int $183 | |
/--* t10 int | |
N004 ( 18, 9) [000011] --C-G------- * jmpTrue void | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
( 0, 0) [000026] ------------ il_offset void IL offset: 22 | |
N001 ( 0, 0) [000025] ------------ return void $2c0 | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In fgLocalVarLiveness() | |
; Initial local variable assignments | |
; | |
; V00 arg0 ref | |
; V01 loc0 int | |
; V02 OutArgs lclBlk ( 0) | |
In fgLocalVarLivenessInit, sorting locals | |
refCnt table for 'Main': | |
V01 loc0 [ int]: refCnt = 5, refCntWtd = 17 | |
V02 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1 | |
*************** In fgPerBlockLocalVarLiveness() | |
BB01 USE(0)={ } + HEAP | |
DEF(1)={V01} + HEAP* | |
BB02 USE(1)={V01} + HEAP | |
DEF(1)={V01} + HEAP* | |
BB03 USE(0)={} | |
DEF(0)={} | |
*************** In fgInterBlockLocalVarLiveness() | |
BB liveness after fgLiveVarAnalysis(): | |
BB01 IN (0)={ } + HEAP | |
OUT(1)={V01} + HEAP | |
BB02 IN (1)={V01} + HEAP | |
OUT(1)={V01} + HEAP | |
BB03 IN (0)={} | |
OUT(0)={} | |
*************** In fgUpdateFlowGraph() | |
Before updating the flow graph: | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target gcsafe LIR | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd LIR | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDebugCheckBBlist | |
Liveness pass finished after lowering, IR: | |
lvasortagain = 0 | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target gcsafe LIR | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd LIR | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
( 1, 3) [000004] ------------ il_offset void IL offset: 0 | |
N001 ( 1, 1) [000001] ------------ t1 = const int 0 $40 | |
/--* t1 int | |
N003 ( 1, 3) [000003] DA---------- * st.lclVar int V01 loc0 d:3 | |
N001 ( 14, 5) [000033] --C-G------- t33 = call int ConsoleApplication.Program.GetNumberNoInline $101 | |
N002 ( 1, 1) [000036] ------------ t36 = const int 0 $40 | |
/--* t33 int | |
+--* t36 int | |
N003 ( 16, 7) [000032] J-C-G--N---- t32 = * <= int $180 | |
/--* t32 int | |
N004 ( 18, 9) [000037] --C-G------- * jmpTrue void | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
N001 ( 0, 0) [000045] ------------ t45 = phiArg int V01 loc0 u:5 | |
N002 ( 0, 0) [000043] ------------ t43 = phiArg int V01 loc0 u:3 $40 | |
/--* t45 int | |
+--* t43 int | |
N005 ( 2, 2) [000040] ------------ t40 = * phi int | |
/--* t40 int | |
N007 ( 2, 3) [000041] DA---------- * st.lclVar int V01 loc0 d:4 | |
( 15, 7) [000017] ------------ il_offset void IL offset: 4 | |
N003 ( 1, 1) [000014] ------------ t14 = lclVar int V01 loc0 u:4 $1c0 | |
/--* t14 int | |
[000047] ------------ t47 = * putarg_reg int | |
/--* t47 int arg0 in rdi | |
N005 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine $VN.Void | |
( 3, 3) [000023] ------------ il_offset void IL offset: 10 | |
N001 ( 1, 1) [000018] ------------ t18 = lclVar int V01 loc0 u:4 (last use) $1c0 | |
N002 ( 1, 1) [000019] ------------ t19 = const int 1 $44 | |
/--* t18 int | |
+--* t19 int | |
N003 ( 3, 3) [000020] ------------ t20 = * + int $182 | |
/--* t20 int | |
N005 ( 3, 3) [000022] DA---------- * st.lclVar int V01 loc0 d:5 | |
N001 ( 14, 5) [000028] --C-G------- t28 = call int ConsoleApplication.Program.GetNumberNoInline $242 | |
N002 ( 1, 1) [000006] ------------ t6 = lclVar int V01 loc0 u:5 $182 | |
/--* t28 int | |
+--* t6 int | |
N003 ( 16, 7) [000010] J-C-G--N---- t10 = * > int $183 | |
/--* t10 int | |
N004 ( 18, 9) [000011] --C-G------- * jmpTrue void | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
( 0, 0) [000026] ------------ il_offset void IL offset: 22 | |
N001 ( 0, 0) [000025] ------------ return void $2c0 | |
------------------------------------------------------------------------------------------------------------------- | |
LSRA Block Sequence: BB01( 1 ) BB02( 4 ) BB03( 1 ) | |
----------------------------- | |
TREE NODE INFO DUMP | |
----------------------------- | |
N003 ( 1, 3) [000004] ------------ * il_offset void IL offset: 0 REG NA | |
+<TreeNodeInfo @ 3 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N005 ( 1, 1) [000001] ------------ * const int 0 REG NA $40 | |
+<TreeNodeInfo @ 5 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N007 ( 1, 3) [000003] DA---------- * st.lclVar int V01 loc0 d:3 REG NA | |
+<TreeNodeInfo @ 7 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N009 ( 14, 5) [000033] --C-G------- * call int ConsoleApplication.Program.GetNumberNoInline $101 | |
+<TreeNodeInfo @ 9 1=0 0i 0f src=[allInt] int=[allInt] dst=[rax] I> | |
N011 ( 1, 1) [000036] ------------ * const int 0 REG NA $40 | |
+<TreeNodeInfo @ 11 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N013 ( 16, 7) [000032] J-C-G--N---- * <= int REG NA $180 | |
+<TreeNodeInfo @ 13 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N015 ( 18, 9) [000037] --C-G------- * jmpTrue void REG NA | |
+<TreeNodeInfo @ 15 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N019 ( 15, 7) [000017] ------------ * il_offset void IL offset: 4 REG NA | |
+<TreeNodeInfo @ 19 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N021 ( 1, 1) [000014] ------------ * lclVar int V01 loc0 u:4 REG NA $1c0 | |
+<TreeNodeInfo @ 21 1=0 0i 0f src=[rdi] int=[allInt] dst=[allInt] I> | |
N023 (???,???) [000047] ------------ * putarg_reg int REG NA | |
+<TreeNodeInfo @ 23 1=1 0i 0f src=[rdi] int=[allInt] dst=[rdi] I> | |
N025 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine $VN.Void | |
+<TreeNodeInfo @ 25 0=1 0i 0f src=[allInt] int=[allInt] dst=[rax] I> | |
N027 ( 3, 3) [000023] ------------ * il_offset void IL offset: 10 REG NA | |
+<TreeNodeInfo @ 27 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N029 ( 1, 1) [000018] ------------ * lclVar int V01 loc0 u:4 (last use) REG NA $1c0 | |
+<TreeNodeInfo @ 29 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I P> | |
N031 ( 1, 1) [000019] ------------ * const int 1 REG NA $44 | |
+<TreeNodeInfo @ 31 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N033 ( 3, 3) [000020] ------------ * + int REG NA $182 | |
+<TreeNodeInfo @ 33 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N035 ( 3, 3) [000022] DA---------- * st.lclVar int V01 loc0 d:5 REG NA | |
+<TreeNodeInfo @ 35 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N037 ( 14, 5) [000028] --C-G------- * call int ConsoleApplication.Program.GetNumberNoInline $242 | |
+<TreeNodeInfo @ 37 1=0 0i 0f src=[allInt] int=[allInt] dst=[rax] I> | |
N039 ( 1, 1) [000006] ------------ * lclVar int V01 loc0 u:5 REG NA $182 | |
+<TreeNodeInfo @ 39 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N041 ( 16, 7) [000010] J-C-G--N---- * > int REG NA $183 | |
+<TreeNodeInfo @ 41 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N043 ( 18, 9) [000011] --C-G------- * jmpTrue void REG NA | |
+<TreeNodeInfo @ 43 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N047 ( 0, 0) [000026] ------------ * il_offset void IL offset: 22 REG NA | |
+<TreeNodeInfo @ 47 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
N049 ( 0, 0) [000025] ------------ * return void REG NA $2c0 | |
+<TreeNodeInfo @ 49 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I> | |
*************** Exiting Lowering | |
Trees after Lowering | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target gcsafe LIR | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd LIR | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
N003 ( 1, 3) [000004] ------------ il_offset void IL offset: 0 REG NA | |
N005 ( 1, 1) [000001] ------------ t1 = const int 0 REG NA $40 | |
/--* t1 int | |
N007 ( 1, 3) [000003] DA---------- * st.lclVar int V01 loc0 d:3 REG NA | |
N009 ( 14, 5) [000033] --C-G------- t33 = call int ConsoleApplication.Program.GetNumberNoInline $101 | |
N011 ( 1, 1) [000036] ------------ t36 = const int 0 REG NA $40 | |
/--* t33 int | |
+--* t36 int | |
N013 ( 16, 7) [000032] J-C-G--N---- t32 = * <= int REG NA $180 | |
/--* t32 int | |
N015 ( 18, 9) [000037] --C-G------- * jmpTrue void REG NA | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
N001 ( 0, 0) [000045] ------------ t45 = phiArg int V01 loc0 u:5 | |
N002 ( 0, 0) [000043] ------------ t43 = phiArg int V01 loc0 u:3 $40 | |
/--* t45 int | |
+--* t43 int | |
N005 ( 2, 2) [000040] ------------ t40 = * phi int | |
/--* t40 int | |
N007 ( 2, 3) [000041] DA---------- * st.lclVar int V01 loc0 d:4 | |
N019 ( 15, 7) [000017] ------------ il_offset void IL offset: 4 REG NA | |
N021 ( 1, 1) [000014] ------------ t14 = lclVar int V01 loc0 u:4 REG NA $1c0 | |
/--* t14 int | |
N023 (???,???) [000047] ------------ t47 = * putarg_reg int REG NA | |
/--* t47 int arg0 in rdi | |
N025 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine $VN.Void | |
N027 ( 3, 3) [000023] ------------ il_offset void IL offset: 10 REG NA | |
N029 ( 1, 1) [000018] ------------ t18 = lclVar int V01 loc0 u:4 (last use) REG NA $1c0 | |
N031 ( 1, 1) [000019] ------------ t19 = const int 1 REG NA $44 | |
/--* t18 int | |
+--* t19 int | |
N033 ( 3, 3) [000020] ------------ t20 = * + int REG NA $182 | |
/--* t20 int | |
N035 ( 3, 3) [000022] DA---------- * st.lclVar int V01 loc0 d:5 REG NA | |
N037 ( 14, 5) [000028] --C-G------- t28 = call int ConsoleApplication.Program.GetNumberNoInline $242 | |
N039 ( 1, 1) [000006] ------------ t6 = lclVar int V01 loc0 u:5 REG NA $182 | |
/--* t28 int | |
+--* t6 int | |
N041 ( 16, 7) [000010] J-C-G--N---- t10 = * > int REG NA $183 | |
/--* t10 int | |
N043 ( 18, 9) [000011] --C-G------- * jmpTrue void REG NA | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
N047 ( 0, 0) [000026] ------------ il_offset void IL offset: 22 REG NA | |
N049 ( 0, 0) [000025] ------------ return void REG NA $2c0 | |
------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDebugCheckBBlist | |
*************** In doLinearScan | |
Trees before linear scan register allocator (LSRA) | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target gcsafe LIR | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd LIR | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
N003 ( 1, 3) [000004] ------------ il_offset void IL offset: 0 REG NA | |
N005 ( 1, 1) [000001] ------------ t1 = const int 0 REG NA $40 | |
/--* t1 int | |
N007 ( 1, 3) [000003] DA---------- * st.lclVar int V01 loc0 d:3 REG NA | |
N009 ( 14, 5) [000033] --C-G------- t33 = call int ConsoleApplication.Program.GetNumberNoInline $101 | |
N011 ( 1, 1) [000036] ------------ t36 = const int 0 REG NA $40 | |
/--* t33 int | |
+--* t36 int | |
N013 ( 16, 7) [000032] J-C-G--N---- t32 = * <= int REG NA $180 | |
/--* t32 int | |
N015 ( 18, 9) [000037] --C-G------- * jmpTrue void REG NA | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
N001 ( 0, 0) [000045] ------------ t45 = phiArg int V01 loc0 u:5 | |
N002 ( 0, 0) [000043] ------------ t43 = phiArg int V01 loc0 u:3 $40 | |
/--* t45 int | |
+--* t43 int | |
N005 ( 2, 2) [000040] ------------ t40 = * phi int | |
/--* t40 int | |
N007 ( 2, 3) [000041] DA---------- * st.lclVar int V01 loc0 d:4 | |
N019 ( 15, 7) [000017] ------------ il_offset void IL offset: 4 REG NA | |
N021 ( 1, 1) [000014] ------------ t14 = lclVar int V01 loc0 u:4 REG NA $1c0 | |
/--* t14 int | |
N023 (???,???) [000047] ------------ t47 = * putarg_reg int REG NA | |
/--* t47 int arg0 in rdi | |
N025 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine $VN.Void | |
N027 ( 3, 3) [000023] ------------ il_offset void IL offset: 10 REG NA | |
N029 ( 1, 1) [000018] ------------ t18 = lclVar int V01 loc0 u:4 (last use) REG NA $1c0 | |
N031 ( 1, 1) [000019] ------------ t19 = const int 1 REG NA $44 | |
/--* t18 int | |
+--* t19 int | |
N033 ( 3, 3) [000020] ------------ t20 = * + int REG NA $182 | |
/--* t20 int | |
N035 ( 3, 3) [000022] DA---------- * st.lclVar int V01 loc0 d:5 REG NA | |
N037 ( 14, 5) [000028] --C-G------- t28 = call int ConsoleApplication.Program.GetNumberNoInline $242 | |
N039 ( 1, 1) [000006] ------------ t6 = lclVar int V01 loc0 u:5 REG NA $182 | |
/--* t28 int | |
+--* t6 int | |
N041 ( 16, 7) [000010] J-C-G--N---- t10 = * > int REG NA $183 | |
/--* t10 int | |
N043 ( 18, 9) [000011] --C-G------- * jmpTrue void REG NA | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
N047 ( 0, 0) [000026] ------------ il_offset void IL offset: 22 REG NA | |
N049 ( 0, 0) [000025] ------------ return void REG NA $2c0 | |
------------------------------------------------------------------------------------------------------------------- | |
Clearing modified regs. | |
; Decided to create an EBP based frame for ETW stackwalking (Method has Loops) | |
buildIntervals ======== | |
----------------- | |
LIVENESS: | |
----------------- | |
BB01 use def in out | |
{} | |
{V01} | |
{} | |
{V01} | |
BB02 use def in out | |
{V01} | |
{V01} | |
{V01} | |
{V01} | |
BB03 use def in out | |
{} | |
{} | |
{} | |
{} | |
Interval 0: RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 1: RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 2: RefPositions {} physReg:NA Preferences=[allInt] | |
FP callee save candidate vars: None | |
floatVarCount = 0; hasLoops = 1, singleExit = 1 | |
TUPLE STYLE DUMP BEFORE LSRA | |
BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
===== | |
N003. il_offset IL offset: 0 REG NA | |
N005. t5 = const 0 REG NA | |
N007. V01(t7); t5 | |
N009. t9 = call | |
N011. const 0 REG NA | |
N013. <= ; t9 | |
N015. jmpTrue | |
BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
===== | |
N019. il_offset IL offset: 4 REG NA | |
N021. V01(t21) | |
N023. t23 = putarg_reg; t21 | |
N025. call ; t23 | |
N027. il_offset IL offset: 10 REG NA | |
N029. V01(t29*) | |
N031. const 1 REG NA | |
N033. t33 = + ; t29* | |
N035. V01(t35); t33 | |
N037. t37 = call | |
N039. V01(t39) | |
N041. > ; t37,t39 | |
N043. jmpTrue | |
BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
===== | |
N047. il_offset IL offset: 22 REG NA | |
N049. return | |
buildIntervals second part ======== | |
Int arg V00 in reg rdi | |
NEW BLOCK BB01 | |
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]> | |
at start of tree, map contains: { } | |
N003. il_offset IL offset: 0 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N005. t5 = const 0 REG NA | |
consume=0 produce=1 | |
t5 = op | |
Def candidates [allInt], Use candidates [allInt] | |
Interval 3: RefPositions {} physReg:NA Preferences=[allInt] | |
<RefPosition #1 @6 RefTypeDef <Ivl:3> CNS_INT BB01 regmask=[allInt]> | |
<RefPosition #1 @6 RefTypeDef <Ivl:3> CNS_INT BB01 regmask=[allInt]> | |
at start of tree, map contains: { N005. const -> (6.N005) } | |
N007. V01(L1) | |
consume=1 produce=0 | |
Assigning related <L1> to <I3> | |
t7 (i:1) = op | |
t6 <RefPosition #2 @7 RefTypeUse <Ivl:3> BB01 regmask=[allInt]> | |
Def candidates [allInt], Use candidates [allInt] | |
<RefPosition #3 @8 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt]> | |
<RefPosition #3 @8 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt]> | |
at start of tree, map contains: { } | |
N009. t9 = call | |
consume=0 produce=1 | |
t9 = op | |
Def candidates [rax], Use candidates [allInt] | |
<RefPosition #4 @10 RefTypeKill <Reg:rax> BB01 regmask=[rax]> | |
<RefPosition #5 @10 RefTypeKill <Reg:rcx> BB01 regmask=[rcx]> | |
<RefPosition #6 @10 RefTypeKill <Reg:rdx> BB01 regmask=[rdx]> | |
<RefPosition #7 @10 RefTypeKill <Reg:rsi> BB01 regmask=[rsi]> | |
<RefPosition #8 @10 RefTypeKill <Reg:rdi> BB01 regmask=[rdi]> | |
<RefPosition #9 @10 RefTypeKill <Reg:r8 > BB01 regmask=[r8]> | |
<RefPosition #10 @10 RefTypeKill <Reg:r9 > BB01 regmask=[r9]> | |
<RefPosition #11 @10 RefTypeKill <Reg:r10> BB01 regmask=[r10]> | |
<RefPosition #12 @10 RefTypeKill <Reg:r11> BB01 regmask=[r11]> | |
Interval 4: RefPositions {} physReg:NA Preferences=[allInt] | |
<RefPosition #13 @10 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax]> | |
<RefPosition #14 @10 RefTypeDef <Ivl:4> CALL BB01 regmask=[rax] fixed> | |
<RefPosition #14 @10 RefTypeDef <Ivl:4> CALL BB01 regmask=[rax] fixed> | |
at start of tree, map contains: { N009. call() -> (10.N009) } | |
N011. const 0 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { N009. call() -> (10.N009) } | |
N013. <= | |
consume=1 produce=0 | |
op | |
t10 <RefPosition #15 @13 RefTypeUse <Ivl:4> BB01 regmask=[allInt]> | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N015. jmpTrue | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
CALCULATING LAST USES for block 1, liveout={V01} | |
============================== | |
use: {} | |
def: {V01} | |
NEW BLOCK BB02 | |
Setting incoming variable registers of BB02 to outVarToRegMap of BB01 | |
<RefPosition #16 @17 RefTypeBB BB02 regmask=[]> | |
at start of tree, map contains: { } | |
N019. il_offset IL offset: 4 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
t21 (i:1) | |
at start of tree, map contains: { N021. lclVar -> (21.N021) } | |
N023. t23 = putarg_reg | |
consume=1 produce=1 | |
t23 = op | |
Setting putarg_reg as a pass-through of a non-last use lclVar | |
t21 <RefPosition #17 @23 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #18 @23 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rdi] fixed> | |
Def candidates [rdi], Use candidates [rdi] | |
Interval 5: RefPositions {} physReg:NA Preferences=[allInt] | |
Assigning related <L1> to <I5> | |
<RefPosition #19 @24 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #20 @24 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[rdi] fixed> | |
<RefPosition #20 @24 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[rdi] fixed> | |
at start of tree, map contains: { N023. putarg_reg -> (24.N023) } | |
N025. call | |
consume=1 produce=0 | |
op | |
t24 <RefPosition #21 @25 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #22 @25 RefTypeUse <Ivl:5> BB02 regmask=[rdi] fixed> | |
Def candidates [rax], Use candidates [allInt] | |
<RefPosition #23 @26 RefTypeKill <Reg:rax> BB02 regmask=[rax]> | |
<RefPosition #24 @26 RefTypeKill <Reg:rcx> BB02 regmask=[rcx]> | |
<RefPosition #25 @26 RefTypeKill <Reg:rdx> BB02 regmask=[rdx]> | |
<RefPosition #26 @26 RefTypeKill <Reg:rsi> BB02 regmask=[rsi]> | |
<RefPosition #27 @26 RefTypeKill <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #28 @26 RefTypeKill <Reg:r8 > BB02 regmask=[r8]> | |
<RefPosition #29 @26 RefTypeKill <Reg:r9 > BB02 regmask=[r9]> | |
<RefPosition #30 @26 RefTypeKill <Reg:r10> BB02 regmask=[r10]> | |
<RefPosition #31 @26 RefTypeKill <Reg:r11> BB02 regmask=[r11]> | |
at start of tree, map contains: { } | |
N027. il_offset IL offset: 10 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
t29 (i:1) | |
at start of tree, map contains: { N029. lclVar -> (29.N029) } | |
N031. const 1 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { N029. lclVar -> (29.N029) } | |
N033. t33 = + | |
consume=1 produce=1 | |
t33 = op | |
t29 <RefPosition #32 @33 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt]> | |
Def candidates [allInt], Use candidates [allInt] | |
Interval 6: RefPositions {} physReg:NA Preferences=[allInt] | |
Assigning related <L1> to <I6> | |
<RefPosition #33 @34 RefTypeDef <Ivl:6> ADD BB02 regmask=[allInt]> | |
<RefPosition #33 @34 RefTypeDef <Ivl:6> ADD BB02 regmask=[allInt]> | |
at start of tree, map contains: { N033. + -> (34.N033) } | |
N035. V01(L1) | |
consume=1 produce=0 | |
Assigning related <L1> to <I6> | |
t35 (i:1) = op | |
t34 <RefPosition #34 @35 RefTypeUse <Ivl:6> BB02 regmask=[allInt]> | |
Def candidates [allInt], Use candidates [allInt] | |
<RefPosition #35 @36 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB02 regmask=[allInt]> | |
<RefPosition #35 @36 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB02 regmask=[allInt]> | |
at start of tree, map contains: { } | |
N037. t37 = call | |
consume=0 produce=1 | |
t37 = op | |
Def candidates [rax], Use candidates [allInt] | |
<RefPosition #36 @38 RefTypeKill <Reg:rax> BB02 regmask=[rax]> | |
<RefPosition #37 @38 RefTypeKill <Reg:rcx> BB02 regmask=[rcx]> | |
<RefPosition #38 @38 RefTypeKill <Reg:rdx> BB02 regmask=[rdx]> | |
<RefPosition #39 @38 RefTypeKill <Reg:rsi> BB02 regmask=[rsi]> | |
<RefPosition #40 @38 RefTypeKill <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #41 @38 RefTypeKill <Reg:r8 > BB02 regmask=[r8]> | |
<RefPosition #42 @38 RefTypeKill <Reg:r9 > BB02 regmask=[r9]> | |
<RefPosition #43 @38 RefTypeKill <Reg:r10> BB02 regmask=[r10]> | |
<RefPosition #44 @38 RefTypeKill <Reg:r11> BB02 regmask=[r11]> | |
Interval 7: RefPositions {} physReg:NA Preferences=[allInt] | |
<RefPosition #45 @38 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax]> | |
<RefPosition #46 @38 RefTypeDef <Ivl:7> CALL BB02 regmask=[rax] fixed> | |
<RefPosition #46 @38 RefTypeDef <Ivl:7> CALL BB02 regmask=[rax] fixed> | |
at start of tree, map contains: { N037. call() -> (38.N037) } | |
t39 (i:1) | |
at start of tree, map contains: { N039. lclVar -> (39.N039); N037. call() -> (38.N037) } | |
N041. > | |
consume=2 produce=0 | |
op | |
t38 <RefPosition #47 @41 RefTypeUse <Ivl:7> BB02 regmask=[allInt]> | |
t39 <RefPosition #48 @41 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt]> | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N043. jmpTrue | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
Exposed uses:<RefPosition #49 @45 RefTypeExpUse <Ivl:1 V01> BB02 regmask=[allInt]> | |
V01 | |
CALCULATING LAST USES for block 2, liveout={V01} | |
============================== | |
last use of V01 @33 | |
use: {V01} | |
def: {V01} | |
NEW BLOCK BB03 | |
Setting incoming variable registers of BB03 to outVarToRegMap of BB02 | |
<RefPosition #50 @45 RefTypeBB BB03 regmask=[]> | |
at start of tree, map contains: { } | |
N047. il_offset IL offset: 22 REG NA | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
at start of tree, map contains: { } | |
N049. return | |
consume=0 produce=0 | |
op | |
Def candidates [allInt], Use candidates [allInt] | |
CALCULATING LAST USES for block 3, liveout={} | |
============================== | |
use: {} | |
def: {} | |
Linear scan intervals BEFORE VALIDATING INTERVALS: | |
Interval 0: (V00) RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 1: (V01) RefPositions {#3@8 #18@23 #32@33 #35@36 #48@41 #49@45} physReg:NA Preferences=[rbx r12-r15] | |
Interval 2: (V02) RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 3: (constant) RefPositions {#1@6 #2@7} physReg:NA Preferences=[allInt] RelatedInterval <L1>[00000000022A3820] | |
Interval 4: RefPositions {#14@10 #15@13} physReg:NA Preferences=[rax] | |
Interval 5: (specialPutArg) RefPositions {#20@24 #22@25} physReg:NA Preferences=[rdi] RelatedInterval <L1>[00000000022A3820] | |
Interval 6: RefPositions {#33@34 #34@35} physReg:NA Preferences=[allInt] RelatedInterval <L1>[00000000022A3820] | |
Interval 7: RefPositions {#46@38 #47@41} physReg:NA Preferences=[rax] | |
------------ | |
REFPOSITIONS BEFORE VALIDATING INTERVALS: | |
------------ | |
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]> | |
<RefPosition #1 @6 ->#2 RefTypeDef <Ivl:3> CNS_INT BB01 regmask=[allInt]> | |
<RefPosition #2 @7 RefTypeUse <Ivl:3> BB01 regmask=[allInt] last> | |
<RefPosition #3 @8 ->#18 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt]> | |
<RefPosition #4 @10 ->#13 RefTypeKill <Reg:rax> BB01 regmask=[rax] last> | |
<RefPosition #5 @10 ->#24 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] last> | |
<RefPosition #6 @10 ->#25 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] last> | |
<RefPosition #7 @10 ->#26 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] last> | |
<RefPosition #8 @10 ->#17 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] last> | |
<RefPosition #9 @10 ->#28 RefTypeKill <Reg:r8 > BB01 regmask=[r8] last> | |
<RefPosition #10 @10 ->#29 RefTypeKill <Reg:r9 > BB01 regmask=[r9] last> | |
<RefPosition #11 @10 ->#30 RefTypeKill <Reg:r10> BB01 regmask=[r10] last> | |
<RefPosition #12 @10 ->#31 RefTypeKill <Reg:r11> BB01 regmask=[r11] last> | |
<RefPosition #13 @10 ->#23 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax]> | |
<RefPosition #14 @10 ->#15 RefTypeDef <Ivl:4> CALL BB01 regmask=[rax] fixed> | |
<RefPosition #15 @13 RefTypeUse <Ivl:4> BB01 regmask=[allInt] last> | |
<RefPosition #16 @17 RefTypeBB BB02 regmask=[]> | |
<RefPosition #17 @23 ->#19 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #18 @23 ->#32 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rdi] fixed> | |
<RefPosition #19 @24 ->#21 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #20 @24 ->#22 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[rdi] fixed> | |
<RefPosition #21 @25 ->#27 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #22 @25 RefTypeUse <Ivl:5> BB02 regmask=[rdi] last fixed> | |
<RefPosition #23 @26 ->#36 RefTypeKill <Reg:rax> BB02 regmask=[rax] last> | |
<RefPosition #24 @26 ->#37 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] last> | |
<RefPosition #25 @26 ->#38 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] last> | |
<RefPosition #26 @26 ->#39 RefTypeKill <Reg:rsi> BB02 regmask=[rsi] last> | |
<RefPosition #27 @26 ->#40 RefTypeKill <Reg:rdi> BB02 regmask=[rdi] last> | |
<RefPosition #28 @26 ->#41 RefTypeKill <Reg:r8 > BB02 regmask=[r8] last> | |
<RefPosition #29 @26 ->#42 RefTypeKill <Reg:r9 > BB02 regmask=[r9] last> | |
<RefPosition #30 @26 ->#43 RefTypeKill <Reg:r10> BB02 regmask=[r10] last> | |
<RefPosition #31 @26 ->#44 RefTypeKill <Reg:r11> BB02 regmask=[r11] last> | |
<RefPosition #32 @33 ->#35 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] last> | |
<RefPosition #33 @34 ->#34 RefTypeDef <Ivl:6> ADD BB02 regmask=[allInt]> | |
<RefPosition #34 @35 RefTypeUse <Ivl:6> BB02 regmask=[allInt] last> | |
<RefPosition #35 @36 ->#48 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB02 regmask=[allInt]> | |
<RefPosition #36 @38 ->#45 RefTypeKill <Reg:rax> BB02 regmask=[rax] last> | |
<RefPosition #37 @38 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] last> | |
<RefPosition #38 @38 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] last> | |
<RefPosition #39 @38 RefTypeKill <Reg:rsi> BB02 regmask=[rsi] last> | |
<RefPosition #40 @38 RefTypeKill <Reg:rdi> BB02 regmask=[rdi] last> | |
<RefPosition #41 @38 RefTypeKill <Reg:r8 > BB02 regmask=[r8] last> | |
<RefPosition #42 @38 RefTypeKill <Reg:r9 > BB02 regmask=[r9] last> | |
<RefPosition #43 @38 RefTypeKill <Reg:r10> BB02 regmask=[r10] last> | |
<RefPosition #44 @38 RefTypeKill <Reg:r11> BB02 regmask=[r11] last> | |
<RefPosition #45 @38 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax]> | |
<RefPosition #46 @38 ->#47 RefTypeDef <Ivl:7> CALL BB02 regmask=[rax] fixed> | |
<RefPosition #47 @41 RefTypeUse <Ivl:7> BB02 regmask=[allInt] last> | |
<RefPosition #48 @41 ->#49 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt]> | |
<RefPosition #49 @45 RefTypeExpUse <Ivl:1 V01> BB02 regmask=[allInt]> | |
<RefPosition #50 @45 RefTypeBB BB03 regmask=[]> | |
----------------- | |
----------------- | |
<RefPosition #3 @8 ->#18 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt]> | |
<RefPosition #18 @23 ->#32 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rdi] fixed> | |
<RefPosition #32 @33 ->#35 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] last> | |
<RefPosition #35 @36 ->#48 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB02 regmask=[allInt]> | |
<RefPosition #48 @41 ->#49 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt]> | |
<RefPosition #49 @45 RefTypeExpUse <Ivl:1 V01> BB02 regmask=[allInt]> | |
----------------- | |
TUPLE STYLE DUMP WITH REF POSITIONS | |
Incoming Parameters: | |
BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
===== | |
N003. il_offset IL offset: 0 REG NA | |
N005. const 0 REG NA | |
Def:<I3>(#1) Pref:<L1> | |
N007. V01(L1) | |
Use:<I3>(#2) * | |
Def:<L1>(#3) | |
N009. call | |
Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 | |
Def:<I4>(#14) rax | |
N011. const 0 REG NA | |
N013. <= | |
Use:<I4>(#15) * | |
N015. jmpTrue | |
BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
===== | |
N019. il_offset IL offset: 4 REG NA | |
N021. V01(L1) | |
N023. putarg_reg | |
Use:<L1>(#18) Fixed:rdi(#17) | |
Def:<I5>(#20) rdi Pref:<L1> | |
N025. call | |
Use:<I5>(#22) Fixed:rdi(#21) * | |
Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 | |
N027. il_offset IL offset: 10 REG NA | |
N029. V01(L1) | |
N031. const 1 REG NA | |
N033. + | |
Use:<L1>(#32) * | |
Def:<I6>(#33) Pref:<L1> | |
N035. V01(L1) | |
Use:<I6>(#34) * | |
Def:<L1>(#35) | |
N037. call | |
Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 | |
Def:<I7>(#46) rax | |
N039. V01(L1) | |
N041. > | |
Use:<I7>(#47) * | |
Use:<L1>(#48) | |
N043. jmpTrue | |
Exposed use of V01 at #49 | |
BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
===== | |
N047. il_offset IL offset: 22 REG NA | |
N049. return | |
Linear scan intervals after buildIntervals: | |
Interval 0: (V00) RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 1: (V01) RefPositions {#3@8 #18@23 #32@33 #35@36 #48@41 #49@45} physReg:NA Preferences=[rbx r12-r15] | |
Interval 2: (V02) RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 3: (constant) RefPositions {#1@6 #2@7} physReg:NA Preferences=[allInt] RelatedInterval <L1>[00000000022A3820] | |
Interval 4: RefPositions {#14@10 #15@13} physReg:NA Preferences=[rax] | |
Interval 5: (specialPutArg) RefPositions {#20@24 #22@25} physReg:NA Preferences=[rdi] RelatedInterval <L1>[00000000022A3820] | |
Interval 6: RefPositions {#33@34 #34@35} physReg:NA Preferences=[allInt] RelatedInterval <L1>[00000000022A3820] | |
Interval 7: RefPositions {#46@38 #47@41} physReg:NA Preferences=[rax] | |
*************** In LinearScan::allocateRegisters() | |
Linear scan intervals before allocateRegisters: | |
Interval 0: (V00) RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 1: (V01) RefPositions {#3@8 #18@23 #32@33 #35@36 #48@41 #49@45} physReg:NA Preferences=[rbx r12-r15] | |
Interval 2: (V02) RefPositions {} physReg:NA Preferences=[allInt] | |
Interval 3: (constant) RefPositions {#1@6 #2@7} physReg:NA Preferences=[allInt] RelatedInterval <L1>[00000000022A3820] | |
Interval 4: RefPositions {#14@10 #15@13} physReg:NA Preferences=[rax] | |
Interval 5: (specialPutArg) RefPositions {#20@24 #22@25} physReg:NA Preferences=[rdi] RelatedInterval <L1>[00000000022A3820] | |
Interval 6: RefPositions {#33@34 #34@35} physReg:NA Preferences=[allInt] RelatedInterval <L1>[00000000022A3820] | |
Interval 7: RefPositions {#46@38 #47@41} physReg:NA Preferences=[rax] | |
------------ | |
REFPOSITIONS BEFORE ALLOCATION: | |
------------ | |
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]> | |
<RefPosition #1 @6 ->#2 RefTypeDef <Ivl:3> CNS_INT BB01 regmask=[allInt]> | |
<RefPosition #2 @7 RefTypeUse <Ivl:3> BB01 regmask=[allInt] last> | |
<RefPosition #3 @8 ->#18 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt]> | |
<RefPosition #4 @10 ->#13 RefTypeKill <Reg:rax> BB01 regmask=[rax] last> | |
<RefPosition #5 @10 ->#24 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] last> | |
<RefPosition #6 @10 ->#25 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] last> | |
<RefPosition #7 @10 ->#26 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] last> | |
<RefPosition #8 @10 ->#17 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] last> | |
<RefPosition #9 @10 ->#28 RefTypeKill <Reg:r8 > BB01 regmask=[r8] last> | |
<RefPosition #10 @10 ->#29 RefTypeKill <Reg:r9 > BB01 regmask=[r9] last> | |
<RefPosition #11 @10 ->#30 RefTypeKill <Reg:r10> BB01 regmask=[r10] last> | |
<RefPosition #12 @10 ->#31 RefTypeKill <Reg:r11> BB01 regmask=[r11] last> | |
<RefPosition #13 @10 ->#23 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax]> | |
<RefPosition #14 @10 ->#15 RefTypeDef <Ivl:4> CALL BB01 regmask=[rax] fixed> | |
<RefPosition #15 @13 RefTypeUse <Ivl:4> BB01 regmask=[allInt] last> | |
<RefPosition #16 @17 RefTypeBB BB02 regmask=[]> | |
<RefPosition #17 @23 ->#19 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #18 @23 ->#32 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rdi] fixed> | |
<RefPosition #19 @24 ->#21 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #20 @24 ->#22 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[rdi] fixed> | |
<RefPosition #21 @25 ->#27 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #22 @25 RefTypeUse <Ivl:5> BB02 regmask=[rdi] last fixed> | |
<RefPosition #23 @26 ->#36 RefTypeKill <Reg:rax> BB02 regmask=[rax] last> | |
<RefPosition #24 @26 ->#37 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] last> | |
<RefPosition #25 @26 ->#38 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] last> | |
<RefPosition #26 @26 ->#39 RefTypeKill <Reg:rsi> BB02 regmask=[rsi] last> | |
<RefPosition #27 @26 ->#40 RefTypeKill <Reg:rdi> BB02 regmask=[rdi] last> | |
<RefPosition #28 @26 ->#41 RefTypeKill <Reg:r8 > BB02 regmask=[r8] last> | |
<RefPosition #29 @26 ->#42 RefTypeKill <Reg:r9 > BB02 regmask=[r9] last> | |
<RefPosition #30 @26 ->#43 RefTypeKill <Reg:r10> BB02 regmask=[r10] last> | |
<RefPosition #31 @26 ->#44 RefTypeKill <Reg:r11> BB02 regmask=[r11] last> | |
<RefPosition #32 @33 ->#35 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] last> | |
<RefPosition #33 @34 ->#34 RefTypeDef <Ivl:6> ADD BB02 regmask=[allInt]> | |
<RefPosition #34 @35 RefTypeUse <Ivl:6> BB02 regmask=[allInt] last> | |
<RefPosition #35 @36 ->#48 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB02 regmask=[allInt]> | |
<RefPosition #36 @38 ->#45 RefTypeKill <Reg:rax> BB02 regmask=[rax] last> | |
<RefPosition #37 @38 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] last> | |
<RefPosition #38 @38 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] last> | |
<RefPosition #39 @38 RefTypeKill <Reg:rsi> BB02 regmask=[rsi] last> | |
<RefPosition #40 @38 RefTypeKill <Reg:rdi> BB02 regmask=[rdi] last> | |
<RefPosition #41 @38 RefTypeKill <Reg:r8 > BB02 regmask=[r8] last> | |
<RefPosition #42 @38 RefTypeKill <Reg:r9 > BB02 regmask=[r9] last> | |
<RefPosition #43 @38 RefTypeKill <Reg:r10> BB02 regmask=[r10] last> | |
<RefPosition #44 @38 RefTypeKill <Reg:r11> BB02 regmask=[r11] last> | |
<RefPosition #45 @38 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax]> | |
<RefPosition #46 @38 ->#47 RefTypeDef <Ivl:7> CALL BB02 regmask=[rax] fixed> | |
<RefPosition #47 @41 RefTypeUse <Ivl:7> BB02 regmask=[allInt] last> | |
<RefPosition #48 @41 ->#49 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt]> | |
<RefPosition #49 @45 RefTypeExpUse <Ivl:1 V01> BB02 regmask=[allInt]> | |
<RefPosition #50 @45 RefTypeBB BB03 regmask=[]> | |
VAR REFPOSITIONS BEFORE ALLOCATION | |
--- V00 | |
--- V01 | |
<RefPosition #3 @8 ->#18 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt]> | |
<RefPosition #18 @23 ->#32 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rdi] fixed> | |
<RefPosition #32 @33 ->#35 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] last> | |
<RefPosition #35 @36 ->#48 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB02 regmask=[allInt]> | |
<RefPosition #48 @41 ->#49 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt]> | |
<RefPosition #49 @45 RefTypeExpUse <Ivl:1 V01> BB02 regmask=[allInt]> | |
--- V02 | |
Allocating Registers | |
-------------------- | |
The following table has one or more rows for each RefPosition that is handled during allocation. | |
The first column provides the basic information about the RefPosition, with its type (e.g. Def, | |
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the | |
action taken during allocation (e.g. Alloc a new register, or Keep an existing one). | |
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is | |
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which | |
may increase during allocation, in which case additional columns will appear. Registers which are | |
not marked modified have ---- in their column. | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
| | | |----|----|----| | | | | | | | |
0.#0 BB1 PredBB0 | | | |----|----|----| | | | | | | | |
6.#1 C3 Def Alloc rbx | | | |C3 a|----|----| | | | | | | | |
7.#2 C3 Use * Keep rbx | | | |C3 a|----|----| | | | | | | | |
8.#3 V1 Def Alloc rbx | | | |V1 a|----|----| | | | | | | | |
10.#4 rax Kill Keep rax | | | |V1 a|----|----| | | | | | | | |
10.#5 rcx Kill Keep rcx | | | |V1 a|----|----| | | | | | | | |
10.#6 rdx Kill Keep rdx | | | |V1 a|----|----| | | | | | | | |
10.#7 rsi Kill Keep rsi | | | |V1 a|----|----| | | | | | | | |
10.#8 rdi Kill Keep rdi | | | |V1 a|----|----| | | | | | | | |
10.#9 r8 Kill Keep r8 | | | |V1 a|----|----| | | | | | | | |
10.#10 r9 Kill Keep r9 | | | |V1 a|----|----| | | | | | | | |
10.#11 r10 Kill Keep r10 | | | |V1 a|----|----| | | | | | | | |
10.#12 r11 Kill Keep r11 | | | |V1 a|----|----| | | | | | | | |
10.#13 rax Fixd Keep rax | | | |V1 a|----|----| | | | | | | | |
10.#14 I4 Def Alloc rax |I4 a| | |V1 a|----|----| | | | | | | | |
13.#15 I4 Use * Keep rax |I4 a| | |V1 a|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
17.#16 BB2 PredBB1 | | | |V1 a|----|----| | | | | | | | |
23.#17 rdi Fixd Keep rdi | | | |V1 a|----|----| | | | | | | | |
23.#18 V1 Use Keep rbx | | | |V1 a|----|----| | | | | | | | |
24.#19 rdi Fixd Keep rdi | | | |V1 a|----|----| | | | | | | | |
24.#20 I5 Def Alloc rdi | | | |V1 a|----|----| |I5 a| | | | | | |
25.#21 rdi Fixd Keep rdi | | | |V1 a|----|----| |I5 a| | | | | | |
25.#22 I5 Use * Keep rdi | | | |V1 a|----|----| |I5 a| | | | | | |
26.#23 rax Kill Keep rax | | | |V1 a|----|----| | | | | | | | |
26.#24 rcx Kill Keep rcx | | | |V1 a|----|----| | | | | | | | |
26.#25 rdx Kill Keep rdx | | | |V1 a|----|----| | | | | | | | |
26.#26 rsi Kill Keep rsi | | | |V1 a|----|----| | | | | | | | |
26.#27 rdi Kill Keep rdi | | | |V1 a|----|----| | | | | | | | |
26.#28 r8 Kill Keep r8 | | | |V1 a|----|----| | | | | | | | |
26.#29 r9 Kill Keep r9 | | | |V1 a|----|----| | | | | | | | |
26.#30 r10 Kill Keep r10 | | | |V1 a|----|----| | | | | | | | |
26.#31 r11 Kill Keep r11 | | | |V1 a|----|----| | | | | | | | |
33.#32 V1 Use * Keep rbx | | | |V1 i|----|----| | | | | | | | |
34.#33 I6 Def Alloc rbx | | | |I6 a|----|----| | | | | | | | |
35.#34 I6 Use * Keep rbx | | | |I6 a|----|----| | | | | | | | |
Restr rbx | | | |V1 i|----|----| | | | | | | | |
36.#35 V1 Def Alloc rbx | | | |V1 a|----|----| | | | | | | | |
38.#36 rax Kill Keep rax | | | |V1 a|----|----| | | | | | | | |
38.#37 rcx Kill Keep rcx | | | |V1 a|----|----| | | | | | | | |
38.#38 rdx Kill Keep rdx | | | |V1 a|----|----| | | | | | | | |
38.#39 rsi Kill Keep rsi | | | |V1 a|----|----| | | | | | | | |
38.#40 rdi Kill Keep rdi | | | |V1 a|----|----| | | | | | | | |
38.#41 r8 Kill Keep r8 | | | |V1 a|----|----| | | | | | | | |
38.#42 r9 Kill Keep r9 | | | |V1 a|----|----| | | | | | | | |
38.#43 r10 Kill Keep r10 | | | |V1 a|----|----| | | | | | | | |
38.#44 r11 Kill Keep r11 | | | |V1 a|----|----| | | | | | | | |
38.#45 rax Fixd Keep rax | | | |V1 a|----|----| | | | | | | | |
38.#46 I7 Def Alloc rax |I7 a| | |V1 a|----|----| | | | | | | | |
41.#47 I7 Use * Keep rax |I7 a| | |V1 a|----|----| | | | | | | | |
41.#48 V1 Use Keep rbx |I7 a| | |V1 a|----|----| | | | | | | | |
45.#49 V1 ExpU Keep NA | | | |V1 a|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
45.#50 BB3 PredBB2 | | | | |----|----| | | | | | | | |
------------ | |
REFPOSITIONS AFTER ALLOCATION: | |
------------ | |
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]> | |
<RefPosition #1 @6 ->#2 RefTypeDef <Ivl:3> CNS_INT BB01 regmask=[rbx]> | |
<RefPosition #2 @7 RefTypeUse <Ivl:3> BB01 regmask=[rbx] last> | |
<RefPosition #3 @8 ->#18 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[rbx]> | |
<RefPosition #4 @10 ->#13 RefTypeKill <Reg:rax> BB01 regmask=[rax] last> | |
<RefPosition #5 @10 ->#24 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] last> | |
<RefPosition #6 @10 ->#25 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] last> | |
<RefPosition #7 @10 ->#26 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] last> | |
<RefPosition #8 @10 ->#17 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] last> | |
<RefPosition #9 @10 ->#28 RefTypeKill <Reg:r8 > BB01 regmask=[r8] last> | |
<RefPosition #10 @10 ->#29 RefTypeKill <Reg:r9 > BB01 regmask=[r9] last> | |
<RefPosition #11 @10 ->#30 RefTypeKill <Reg:r10> BB01 regmask=[r10] last> | |
<RefPosition #12 @10 ->#31 RefTypeKill <Reg:r11> BB01 regmask=[r11] last> | |
<RefPosition #13 @10 ->#23 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax]> | |
<RefPosition #14 @10 ->#15 RefTypeDef <Ivl:4> CALL BB01 regmask=[rax] fixed> | |
<RefPosition #15 @13 RefTypeUse <Ivl:4> BB01 regmask=[rax] last> | |
<RefPosition #16 @17 RefTypeBB BB02 regmask=[]> | |
<RefPosition #17 @23 ->#19 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #18 @23 ->#32 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rbx] fixed> | |
<RefPosition #19 @24 ->#21 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #20 @24 ->#22 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[rdi] fixed> | |
<RefPosition #21 @25 ->#27 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
<RefPosition #22 @25 RefTypeUse <Ivl:5> BB02 regmask=[rdi] last fixed> | |
<RefPosition #23 @26 ->#36 RefTypeKill <Reg:rax> BB02 regmask=[rax] last> | |
<RefPosition #24 @26 ->#37 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] last> | |
<RefPosition #25 @26 ->#38 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] last> | |
<RefPosition #26 @26 ->#39 RefTypeKill <Reg:rsi> BB02 regmask=[rsi] last> | |
<RefPosition #27 @26 ->#40 RefTypeKill <Reg:rdi> BB02 regmask=[rdi] last> | |
<RefPosition #28 @26 ->#41 RefTypeKill <Reg:r8 > BB02 regmask=[r8] last> | |
<RefPosition #29 @26 ->#42 RefTypeKill <Reg:r9 > BB02 regmask=[r9] last> | |
<RefPosition #30 @26 ->#43 RefTypeKill <Reg:r10> BB02 regmask=[r10] last> | |
<RefPosition #31 @26 ->#44 RefTypeKill <Reg:r11> BB02 regmask=[r11] last> | |
<RefPosition #32 @33 ->#35 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rbx] last> | |
<RefPosition #33 @34 ->#34 RefTypeDef <Ivl:6> ADD BB02 regmask=[rbx]> | |
<RefPosition #34 @35 RefTypeUse <Ivl:6> BB02 regmask=[rbx] last> | |
<RefPosition #35 @36 ->#48 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB02 regmask=[rbx]> | |
<RefPosition #36 @38 ->#45 RefTypeKill <Reg:rax> BB02 regmask=[rax] last> | |
<RefPosition #37 @38 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] last> | |
<RefPosition #38 @38 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] last> | |
<RefPosition #39 @38 RefTypeKill <Reg:rsi> BB02 regmask=[rsi] last> | |
<RefPosition #40 @38 RefTypeKill <Reg:rdi> BB02 regmask=[rdi] last> | |
<RefPosition #41 @38 RefTypeKill <Reg:r8 > BB02 regmask=[r8] last> | |
<RefPosition #42 @38 RefTypeKill <Reg:r9 > BB02 regmask=[r9] last> | |
<RefPosition #43 @38 RefTypeKill <Reg:r10> BB02 regmask=[r10] last> | |
<RefPosition #44 @38 RefTypeKill <Reg:r11> BB02 regmask=[r11] last> | |
<RefPosition #45 @38 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax]> | |
<RefPosition #46 @38 ->#47 RefTypeDef <Ivl:7> CALL BB02 regmask=[rax] fixed> | |
<RefPosition #47 @41 RefTypeUse <Ivl:7> BB02 regmask=[rax] last> | |
<RefPosition #48 @41 ->#49 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rbx]> | |
<RefPosition #49 @45 RefTypeExpUse <Ivl:1 V01> BB02 regmask=[allInt]> | |
<RefPosition #50 @45 RefTypeBB BB03 regmask=[]> | |
VAR REFPOSITIONS AFTER ALLOCATION | |
--- V00 | |
--- V01 | |
<RefPosition #3 @8 ->#18 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[rbx]> | |
<RefPosition #18 @23 ->#32 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rbx] fixed> | |
<RefPosition #32 @33 ->#35 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rbx] last> | |
<RefPosition #35 @36 ->#48 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB02 regmask=[rbx]> | |
<RefPosition #48 @41 ->#49 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rbx]> | |
<RefPosition #49 @45 RefTypeExpUse <Ivl:1 V01> BB02 regmask=[allInt]> | |
--- V02 | |
Active intervals at end of allocation: | |
------------------------ | |
WRITING BACK ASSIGNMENTS | |
------------------------ | |
BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
<RefPosition #0 @0 RefTypeBB BB01 regmask=[]> | |
current : <RefPosition #1 @6 ->#2 RefTypeDef <Ivl:3> CNS_INT BB01 regmask=[rbx]> | |
N005. t5 = const 0 REG NA | |
curr = 6 mapped = 5 | |
current : <RefPosition #2 @7 RefTypeUse <Ivl:3> BB01 regmask=[rbx] last> | |
No tree node to write back to | |
current : <RefPosition #3 @8 ->#18 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[rbx]> | |
N007. V01(L1) | |
curr = 8 mapped = 7 | |
current : <RefPosition #4 @10 ->#13 RefTypeKill <Reg:rax> BB01 regmask=[rax] last> | |
current : <RefPosition #5 @10 ->#24 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] last> | |
current : <RefPosition #6 @10 ->#25 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] last> | |
current : <RefPosition #7 @10 ->#26 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] last> | |
current : <RefPosition #8 @10 ->#17 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] last> | |
current : <RefPosition #9 @10 ->#28 RefTypeKill <Reg:r8 > BB01 regmask=[r8] last> | |
current : <RefPosition #10 @10 ->#29 RefTypeKill <Reg:r9 > BB01 regmask=[r9] last> | |
current : <RefPosition #11 @10 ->#30 RefTypeKill <Reg:r10> BB01 regmask=[r10] last> | |
current : <RefPosition #12 @10 ->#31 RefTypeKill <Reg:r11> BB01 regmask=[r11] last> | |
current : <RefPosition #13 @10 ->#23 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax]> | |
current : <RefPosition #14 @10 ->#15 RefTypeDef <Ivl:4> CALL BB01 regmask=[rax] fixed> | |
N009. t9 = call | |
curr = 10 mapped = 9 | |
current : <RefPosition #15 @13 RefTypeUse <Ivl:4> BB01 regmask=[rax] last> | |
No tree node to write back to | |
BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
<RefPosition #16 @17 RefTypeBB BB02 regmask=[]> | |
current : <RefPosition #17 @23 ->#19 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
current : <RefPosition #18 @23 ->#32 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rbx] fixed> | |
N021. V01(L1) | |
curr = 23 mapped = 21 | |
current : <RefPosition #19 @24 ->#21 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
current : <RefPosition #20 @24 ->#22 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[rdi] fixed> | |
N023. t23 = putarg_reg | |
curr = 24 mapped = 23 | |
current : <RefPosition #21 @25 ->#27 RefTypeFixedReg <Reg:rdi> BB02 regmask=[rdi]> | |
current : <RefPosition #22 @25 RefTypeUse <Ivl:5> BB02 regmask=[rdi] last fixed> | |
No tree node to write back to | |
current : <RefPosition #23 @26 ->#36 RefTypeKill <Reg:rax> BB02 regmask=[rax] last> | |
current : <RefPosition #24 @26 ->#37 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] last> | |
current : <RefPosition #25 @26 ->#38 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] last> | |
current : <RefPosition #26 @26 ->#39 RefTypeKill <Reg:rsi> BB02 regmask=[rsi] last> | |
current : <RefPosition #27 @26 ->#40 RefTypeKill <Reg:rdi> BB02 regmask=[rdi] last> | |
current : <RefPosition #28 @26 ->#41 RefTypeKill <Reg:r8 > BB02 regmask=[r8] last> | |
current : <RefPosition #29 @26 ->#42 RefTypeKill <Reg:r9 > BB02 regmask=[r9] last> | |
current : <RefPosition #30 @26 ->#43 RefTypeKill <Reg:r10> BB02 regmask=[r10] last> | |
current : <RefPosition #31 @26 ->#44 RefTypeKill <Reg:r11> BB02 regmask=[r11] last> | |
current : <RefPosition #32 @33 ->#35 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rbx] last> | |
N029. V01(L1) | |
curr = 33 mapped = 29 | |
current : <RefPosition #33 @34 ->#34 RefTypeDef <Ivl:6> ADD BB02 regmask=[rbx]> | |
N033. t33 = + | |
curr = 34 mapped = 33 | |
current : <RefPosition #34 @35 RefTypeUse <Ivl:6> BB02 regmask=[rbx] last> | |
No tree node to write back to | |
current : <RefPosition #35 @36 ->#48 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB02 regmask=[rbx]> | |
N035. V01(L1) | |
curr = 36 mapped = 35 | |
current : <RefPosition #36 @38 ->#45 RefTypeKill <Reg:rax> BB02 regmask=[rax] last> | |
current : <RefPosition #37 @38 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] last> | |
current : <RefPosition #38 @38 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] last> | |
current : <RefPosition #39 @38 RefTypeKill <Reg:rsi> BB02 regmask=[rsi] last> | |
current : <RefPosition #40 @38 RefTypeKill <Reg:rdi> BB02 regmask=[rdi] last> | |
current : <RefPosition #41 @38 RefTypeKill <Reg:r8 > BB02 regmask=[r8] last> | |
current : <RefPosition #42 @38 RefTypeKill <Reg:r9 > BB02 regmask=[r9] last> | |
current : <RefPosition #43 @38 RefTypeKill <Reg:r10> BB02 regmask=[r10] last> | |
current : <RefPosition #44 @38 RefTypeKill <Reg:r11> BB02 regmask=[r11] last> | |
current : <RefPosition #45 @38 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax]> | |
current : <RefPosition #46 @38 ->#47 RefTypeDef <Ivl:7> CALL BB02 regmask=[rax] fixed> | |
N037. t37 = call | |
curr = 38 mapped = 37 | |
current : <RefPosition #47 @41 RefTypeUse <Ivl:7> BB02 regmask=[rax] last> | |
No tree node to write back to | |
current : <RefPosition #48 @41 ->#49 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[rbx]> | |
N039. V01(L1) | |
curr = 41 mapped = 39 | |
current : <RefPosition #49 @45 RefTypeExpUse <Ivl:1 V01> BB02 regmask=[allInt]> | |
BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
<RefPosition #50 @45 RefTypeBB BB03 regmask=[]> | |
----------------------- | |
RESOLVING BB BOUNDARIES | |
----------------------- | |
Prior to Resolution | |
BB01 use def in out | |
{} | |
{V01} | |
{} | |
{V01} | |
Var=Reg beg of BB01: none | |
Var=Reg end of BB01: V01=rbx | |
BB02 use def in out | |
{V01} | |
{V01} | |
{V01} | |
{V01} | |
Var=Reg beg of BB02: V01=rbx | |
Var=Reg end of BB02: V01=rbx | |
BB03 use def in out | |
{} | |
{} | |
{} | |
{} | |
Var=Reg beg of BB03: none | |
Var=Reg end of BB03: none | |
RESOLVING EDGES | |
Trees after linear scan register allocator (LSRA) | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target gcsafe LIR | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd LIR | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
------------ BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
N003 ( 1, 3) [000004] ------------ il_offset void IL offset: 0 REG NA | |
N005 ( 1, 1) [000001] ------------ t1 = const int 0 REG rbx $40 | |
/--* t1 int | |
N007 ( 1, 3) [000003] DA---------- * st.lclVar int V01 loc0 d:3 rbx REG rbx RV | |
N009 ( 14, 5) [000033] --C-G------- t33 = call int ConsoleApplication.Program.GetNumberNoInline $101 | |
N011 ( 1, 1) [000036] ------------ t36 = const int 0 REG NA $40 | |
/--* t33 int | |
+--* t36 int | |
N013 ( 16, 7) [000032] J-C-G--N---- t32 = * <= int REG NA $180 | |
/--* t32 int | |
N015 ( 18, 9) [000037] --C-G------- * jmpTrue void REG NA | |
------------ BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
N001 ( 0, 0) [000045] ------------ t45 = phiArg int V01 loc0 u:5 rbx | |
N002 ( 0, 0) [000043] ------------ t43 = phiArg int V01 loc0 u:3 rbx $40 | |
/--* t45 int | |
+--* t43 int | |
N005 ( 2, 2) [000040] ------------ t40 = * phi int | |
/--* t40 int | |
N007 ( 2, 3) [000041] DA---------- * st.lclVar int V01 loc0 d:4 rbx | |
N019 ( 15, 7) [000017] ------------ il_offset void IL offset: 4 REG NA | |
N021 ( 1, 1) [000014] ------------ t14 = lclVar int V01 loc0 u:4 rbx REG rbx RV $1c0 | |
/--* t14 int | |
N023 (???,???) [000047] ------------ t47 = * putarg_reg int REG rdi | |
/--* t47 int arg0 in rdi | |
N025 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine $VN.Void | |
N027 ( 3, 3) [000023] ------------ il_offset void IL offset: 10 REG NA | |
N029 ( 1, 1) [000018] ------------ t18 = lclVar int V01 loc0 u:4 rbx (last use) REG rbx RV $1c0 | |
N031 ( 1, 1) [000019] ------------ t19 = const int 1 REG NA $44 | |
/--* t18 int | |
+--* t19 int | |
N033 ( 3, 3) [000020] ------------ t20 = * + int REG rbx $182 | |
/--* t20 int | |
N035 ( 3, 3) [000022] DA---------- * st.lclVar int V01 loc0 d:5 rbx REG rbx RV | |
N037 ( 14, 5) [000028] --C-G------- t28 = call int ConsoleApplication.Program.GetNumberNoInline $242 | |
N039 ( 1, 1) [000006] ------------ t6 = lclVar int V01 loc0 u:5 rbx REG rbx RV $182 | |
/--* t28 int | |
+--* t6 int | |
N041 ( 16, 7) [000010] J-C-G--N---- t10 = * > int REG NA $183 | |
/--* t10 int | |
N043 ( 18, 9) [000011] --C-G------- * jmpTrue void REG NA | |
------------ BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
N047 ( 0, 0) [000026] ------------ il_offset void IL offset: 22 REG NA | |
N049 ( 0, 0) [000025] ------------ return void REG NA $2c0 | |
------------------------------------------------------------------------------------------------------------------- | |
Final allocation | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
0.#0 BB1 PredBB0 | | | | |----|----| | | | | | | | |
6.#1 C3 Def Alloc rbx | | | |C3 a|----|----| | | | | | | | |
7.#2 C3 Use * Keep rbx | | | |C3 i|----|----| | | | | | | | |
8.#3 V1 Def Alloc rbx | | | |V1 a|----|----| | | | | | | | |
10.#4 rax Kill Keep rax | | | |V1 a|----|----| | | | | | | | |
10.#5 rcx Kill Keep rcx | | | |V1 a|----|----| | | | | | | | |
10.#6 rdx Kill Keep rdx | | | |V1 a|----|----| | | | | | | | |
10.#7 rsi Kill Keep rsi | | | |V1 a|----|----| | | | | | | | |
10.#8 rdi Kill Keep rdi | | | |V1 a|----|----| | | | | | | | |
10.#9 r8 Kill Keep r8 | | | |V1 a|----|----| | | | | | | | |
10.#10 r9 Kill Keep r9 | | | |V1 a|----|----| | | | | | | | |
10.#11 r10 Kill Keep r10 | | | |V1 a|----|----| | | | | | | | |
10.#12 r11 Kill Keep r11 | | | |V1 a|----|----| | | | | | | | |
10.#13 rax Fixd Keep rax | | | |V1 a|----|----| | | | | | | | |
10.#14 I4 Def Alloc rax |I4 a| | |V1 a|----|----| | | | | | | | |
13.#15 I4 Use * Keep rax |I4 i| | |V1 a|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
17.#16 BB2 PredBB1 | | | |V1 a|----|----| | | | | | | | |
23.#17 rdi Fixd Keep rdi | | | |V1 a|----|----| | | | | | | | |
23.#18 V1 Use Keep rbx | | | |V1 a|----|----| | | | | | | | |
24.#19 rdi Fixd Keep rdi | | | |V1 a|----|----| | | | | | | | |
24.#20 I5 Def Alloc rdi | | | |V1 a|----|----| |I5 a| | | | | | |
25.#21 rdi Fixd Keep rdi | | | |V1 a|----|----| |I5 a| | | | | | |
25.#22 I5 Use * Keep rdi | | | |V1 a|----|----| |I5 i| | | | | | |
26.#23 rax Kill Keep rax | | | |V1 a|----|----| | | | | | | | |
26.#24 rcx Kill Keep rcx | | | |V1 a|----|----| | | | | | | | |
26.#25 rdx Kill Keep rdx | | | |V1 a|----|----| | | | | | | | |
26.#26 rsi Kill Keep rsi | | | |V1 a|----|----| | | | | | | | |
26.#27 rdi Kill Keep rdi | | | |V1 a|----|----| | | | | | | | |
26.#28 r8 Kill Keep r8 | | | |V1 a|----|----| | | | | | | | |
26.#29 r9 Kill Keep r9 | | | |V1 a|----|----| | | | | | | | |
26.#30 r10 Kill Keep r10 | | | |V1 a|----|----| | | | | | | | |
26.#31 r11 Kill Keep r11 | | | |V1 a|----|----| | | | | | | | |
33.#32 V1 Use * Keep rbx | | | |V1 i|----|----| | | | | | | | |
34.#33 I6 Def Alloc rbx | | | |I6 a|----|----| | | | | | | | |
35.#34 I6 Use * Keep rbx | | | |I6 i|----|----| | | | | | | | |
36.#35 V1 Def Alloc rbx | | | |V1 a|----|----| | | | | | | | |
38.#36 rax Kill Keep rax | | | |V1 a|----|----| | | | | | | | |
38.#37 rcx Kill Keep rcx | | | |V1 a|----|----| | | | | | | | |
38.#38 rdx Kill Keep rdx | | | |V1 a|----|----| | | | | | | | |
38.#39 rsi Kill Keep rsi | | | |V1 a|----|----| | | | | | | | |
38.#40 rdi Kill Keep rdi | | | |V1 a|----|----| | | | | | | | |
38.#41 r8 Kill Keep r8 | | | |V1 a|----|----| | | | | | | | |
38.#42 r9 Kill Keep r9 | | | |V1 a|----|----| | | | | | | | |
38.#43 r10 Kill Keep r10 | | | |V1 a|----|----| | | | | | | | |
38.#44 r11 Kill Keep r11 | | | |V1 a|----|----| | | | | | | | |
38.#45 rax Fixd Keep rax | | | |V1 a|----|----| | | | | | | | |
38.#46 I7 Def Alloc rax |I7 a| | |V1 a|----|----| | | | | | | | |
41.#47 I7 Use * Keep rax |I7 i| | |V1 a|----|----| | | | | | | | |
41.#48 V1 Use Keep rbx | | | |V1 a|----|----| | | | | | | | |
45.#49 V1 ExpU | | | |V1 a|----|----| | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsp |rbp |rsi |rdi |r8 |r9 |r10 |r11 | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ | |
45.#50 BB3 PredBB2 | | | | |----|----| | | | | | | | |
Recording the maximum number of concurrent spills: | |
<UNDEF>: 0 | |
void: 0 | |
bool: 0 | |
byte: 0 | |
ubyte: 0 | |
char: 0 | |
short: 0 | |
ushort: 0 | |
int: 0 | |
uint: 0 | |
long: 0 | |
ulong: 0 | |
float: 0 | |
double: 0 | |
ref: 0 | |
byref: 0 | |
array: 0 | |
struct: 0 | |
blk: 0 | |
lclBlk: 0 | |
pointer: 0 | |
function: 0 | |
simd8: 0 | |
simd12: 0 | |
simd16: 0 | |
simd32: 0 | |
unknown: 0 | |
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS | |
Incoming Parameters: | |
BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} | |
===== | |
N003. il_offset IL offset: 0 REG NA | |
N005. rbx = const 0 REG rbx | |
* N007. V01(rbx); rbx | |
N009. rax = call | |
N011. const 0 REG NA | |
N013. <= ; rax | |
N015. jmpTrue | |
Var=Reg end of BB01: V01=rbx | |
BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} | |
===== | |
Predecessor for variable locations: BB01 | |
Var=Reg beg of BB02: V01=rbx | |
N019. il_offset IL offset: 4 REG NA | |
N021. V01(rbx) | |
N023. rdi = putarg_reg; rbx | |
N025. call ; rdi | |
N027. il_offset IL offset: 10 REG NA | |
N029. V01(rbx*) | |
N031. const 1 REG NA | |
N033. rbx = + ; rbx* | |
* N035. V01(rbx); rbx | |
N037. rax = call | |
N039. V01(rbx) | |
N041. > ; rax,rbx | |
N043. jmpTrue | |
Var=Reg end of BB02: V01=rbx | |
BB03 [016..017) (return), preds={BB01,BB02} succs={} | |
===== | |
Predecessor for variable locations: BB02 | |
Var=Reg beg of BB03: none | |
N047. il_offset IL offset: 22 REG NA | |
N049. return | |
Var=Reg end of BB03: none | |
*************** In genGenerateCode() | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BBnum descAddr ref try hnd preds weight [IL range] [jump] [EH region] [flags] | |
------------------------------------------------------------------------------------------------------------------------------------- | |
BB01 [00000000022746C0] 1 1 [000..004)-> BB03 ( cond ) i label target gcsafe LIR | |
BB02 [00000000022747D0] 2 BB01,BB02 4 [004..016)-> BB02 ( cond ) i Loop label target gcsafe bwd LIR | |
BB03 [00000000022749F0] 2 BB01,BB02 1 [016..017) (return) i label target LIR | |
------------------------------------------------------------------------------------------------------------------------------------- | |
*************** In fgDebugCheckBBlist | |
Finalizing stack frame | |
Recording Var Locations at start of BB01 | |
<none> | |
Modified regs: [rax rcx rdx rbx rsi rdi r8-r11] | |
Callee-saved registers pushed: 1 [rbx] | |
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) | |
; Final local variable assignments | |
; | |
;* V00 arg0 [V00 ] ( 0, 0 ) ref -> zero-ref | |
; V01 loc0 [V01,T00] ( 5, 17 ) int -> rbx | |
;# V02 OutArgs [V02 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00] | |
; | |
; Lcl frame size = 8 | |
=============== Generating BB01 [000..004) -> BB03 (cond), preds={} succs={BB02,BB03} flags=0x400b0020: i label target gcsafe LIR | |
BB01 IN (0)={ } + HEAP | |
OUT(1)={V01} + HEAP | |
Recording Var Locations at start of BB01 | |
<none> | |
Liveness not changing: 0000000000000000 {} | |
Live regs: (unchanged) 00000000 {} | |
GC regs: (unchanged) 00000000 {} | |
Byref regs: (unchanged) 00000000 {} | |
L_M35690_BB01: | |
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
Scope info: begin block BB01, IL range [000..004) | |
Scope info: open scopes = | |
<none> | |
Added IP mapping: 0x0000 STACK_EMPTY (G_M35690_IG02,ins#0,ofs#0) label | |
Generating: N003 ( 1, 3) [000004] ------------ * il_offset void IL offset: 0 REG NA | |
Generating: N005 ( 1, 1) [000001] ------------ * const int 0 REG rbx $40 | |
IN0001: xor ebx, ebx | |
Generating: N007 ( 1, 3) [000003] DA---------- * st.lclVar int V01 loc0 d:3 rbx REG rbx RV | |
V01 in reg rbx is becoming live [000003] | |
Live regs: 00000000 {} => 00000008 {rbx} | |
Live vars: {} => {V01} | |
Generating: N009 ( 14, 5) [000033] --C-G------- * call int ConsoleApplication.Program.GetNumberNoInline $101 | |
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
IN0002: call ConsoleApplication.Program:GetNumberNoInline():int | |
Generating: N011 ( 1, 1) [000036] ------------ * const int 0 REG NA $40 | |
Generating: N013 ( 16, 7) [000032] J-C-G--N---- * <= int REG NA $180 | |
IN0003: test eax, eax | |
Generating: N015 ( 18, 9) [000037] --C-G------- * jmpTrue void REG NA | |
IN0004: jle L_M35690_BB03 | |
Scope info: end block BB01, IL range [000..004) | |
Scope info: open scopes = | |
<none> | |
=============== Generating BB02 [004..016) -> BB02 (cond), preds={BB01,BB02} succs={BB03,BB02} flags=0x420b2020: i Loop label target gcsafe bwd LIR | |
BB02 IN (1)={V01} + HEAP | |
OUT(1)={V01} + HEAP | |
Recording Var Locations at start of BB02 | |
V01(rbx) | |
Liveness not changing: 0000000000000001 {V01} | |
Live regs: 00000000 {} => 00000008 {rbx} | |
GC regs: (unchanged) 00000000 {} | |
Byref regs: (unchanged) 00000000 {} | |
L_M35690_BB02: | |
G_M35690_IG02: ; offs=000000H, funclet=00 | |
Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
Scope info: begin block BB02, IL range [004..016) | |
Scope info: open scopes = | |
1 (V01 loc0) [000..017) | |
Added IP mapping: 0x0004 STACK_EMPTY (G_M35690_IG03,ins#0,ofs#0) label | |
Generating: N019 ( 15, 7) [000017] ------------ * il_offset void IL offset: 4 REG NA | |
Generating: N021 ( 1, 1) [000014] ------------ * lclVar int V01 loc0 u:4 rbx REG rbx RV $1c0 | |
Generating: N023 (???,???) [000047] ------------ * putarg_reg int REG rdi | |
IN0005: mov edi, ebx | |
Generating: N025 ( 15, 7) [000015] --C-G------- * call void System.Console.WriteLine $VN.Void | |
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
IN0006: call System.Console:WriteLine(int) | |
Added IP mapping: 0x000A STACK_EMPTY (G_M35690_IG03,ins#2,ofs#7) | |
Generating: N027 ( 3, 3) [000023] ------------ * il_offset void IL offset: 10 REG NA | |
Generating: N029 ( 1, 1) [000018] ------------ * lclVar int V01 loc0 u:4 rbx (last use) REG rbx RV $1c0 | |
Generating: N031 ( 1, 1) [000019] ------------ * const int 1 REG NA $44 | |
Generating: N033 ( 3, 3) [000020] ------------ * + int REG rbx $182 | |
V01 in reg rbx is becoming dead [000018] | |
Live regs: 00000008 {rbx} => 00000000 {} | |
Live vars: {V01} => {} | |
IN0007: inc ebx | |
Generating: N035 ( 3, 3) [000022] DA---------- * st.lclVar int V01 loc0 d:5 rbx REG rbx RV | |
V01 in reg rbx is becoming live [000022] | |
Live regs: 00000000 {} => 00000008 {rbx} | |
Live vars: {} => {V01} | |
Generating: N037 ( 14, 5) [000028] --C-G------- * call int ConsoleApplication.Program.GetNumberNoInline $242 | |
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
IN0008: call ConsoleApplication.Program:GetNumberNoInline():int | |
Generating: N039 ( 1, 1) [000006] ------------ * lclVar int V01 loc0 u:5 rbx REG rbx RV $182 | |
Generating: N041 ( 16, 7) [000010] J-C-G--N---- * > int REG NA $183 | |
IN0009: cmp eax, ebx | |
Generating: N043 ( 18, 9) [000011] --C-G------- * jmpTrue void REG NA | |
IN000a: jg SHORT L_M35690_BB02 | |
Scope info: end block BB02, IL range [004..016) | |
Scope info: open scopes = | |
<none> | |
=============== Generating BB03 [016..017) (return), preds={BB01,BB02} succs={} flags=0x40030020: i label target LIR | |
BB03 IN (0)={} | |
OUT(0)={} | |
Recording Var Locations at start of BB03 | |
<none> | |
Change life 0000000000000001 {V01} -> 0000000000000000 {} | |
V01 in reg rbx is becoming dead [------] | |
Live regs: (unchanged) 00000000 {} | |
Live regs: (unchanged) 00000000 {} | |
GC regs: (unchanged) 00000000 {} | |
Byref regs: (unchanged) 00000000 {} | |
L_M35690_BB03: | |
G_M35690_IG03: ; offs=00000FH, funclet=00 | |
Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
Scope info: begin block BB03, IL range [016..017) | |
Scope info: open scopes = | |
<none> | |
Added IP mapping: 0x0016 STACK_EMPTY (G_M35690_IG04,ins#0,ofs#0) label | |
Generating: N047 ( 0, 0) [000026] ------------ * il_offset void IL offset: 22 REG NA | |
Generating: N049 ( 0, 0) [000025] ------------ * return void REG NA $2c0 | |
Scope info: end block BB03, IL range [016..017) | |
Scope info: ending scope, LVnum=0 [000..017) | |
Scope info: ending scope, LVnum=1 [000..017) | |
Scope info: open scopes = | |
<none> | |
Added IP mapping: EPILOG STACK_EMPTY (G_M35690_IG04,ins#0,ofs#0) label | |
Reserving epilog IG for block BB03 | |
*************** After placeholder IG creation | |
G_M35690_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG | |
G_M35690_IG02: ; offs=000000H, size=000FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M35690_IG03: ; offs=00000FH, size=0012H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M35690_IG04: ; epilog placeholder, next placeholder=<END>, BB=022749F0H (BB03), epilog <-- First placeholder <-- Last placeholder | |
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} | |
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} | |
Liveness not changing: 0000000000000000 {} | |
# compCycleEstimate = 57, compSizeEstimate = 34 ConsoleApplication.Program:Main(ref) | |
; Final local variable assignments | |
; | |
;* V00 arg0 [V00 ] ( 0, 0 ) ref -> zero-ref | |
; V01 loc0 [V01,T00] ( 5, 17 ) int -> rbx | |
;# V02 OutArgs [V02 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00] | |
; | |
; Lcl frame size = 8 | |
*************** Before prolog / epilog generation | |
G_M35690_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG | |
G_M35690_IG02: ; offs=000000H, size=000FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M35690_IG03: ; offs=00000FH, size=0012H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M35690_IG04: ; epilog placeholder, next placeholder=<END>, BB=022749F0H (BB03), epilog <-- First placeholder <-- Last placeholder | |
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} | |
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} | |
Recording Var Locations at start of BB01 | |
<none> | |
*************** In genFnProlog() | |
Added IP mapping to front: PROLOG STACK_EMPTY (G_M35690_IG01,ins#0,ofs#0) label | |
__prolog: | |
IN000b: push rbp | |
IN000c: push rbx | |
IN000d: push rax | |
IN000e: lea rbp, [rsp+10H] | |
*************** In genClearStackVec3ArgUpperBits() | |
*************** In genFnPrologCalleeRegArgs() for int regs | |
*************** In genEnregisterIncomingStackArgs() | |
G_M35690_IG01: ; offs=000000H, funclet=00 | |
*************** In genFnEpilog() | |
__epilog: | |
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {} | |
IN000f: lea rsp, [rbp-08H] | |
IN0010: pop rbx | |
IN0011: pop rbp | |
IN0012: ret | |
G_M35690_IG04: ; offs=000021H, funclet=00 | |
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs | |
*************** After prolog / epilog generation | |
G_M35690_IG01: ; func=00, offs=000000H, size=0008H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG | |
G_M35690_IG02: ; offs=000008H, size=000FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M35690_IG03: ; offs=000017H, size=0012H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref | |
G_M35690_IG04: ; offs=000029H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc | |
*************** In emitJumpDistBind() | |
Binding: IN0004: 000000 jle L_M35690_BB03 | |
Binding L_M35690_BB03 to G_M35690_IG04 | |
Estimate of fwd jump [022A527C/004]: 0011 -> 0029 = 0016 | |
Shrinking jump [022A527C/004] | |
Binding: IN000a: 000000 jg SHORT L_M35690_BB02 | |
Binding L_M35690_BB02 to G_M35690_IG03 | |
Estimate of bwd jump [022A5944/010]: 0023 -> 0013 = 0012 | |
Shrinking jump [022A5944/010] | |
Total shrinkage = 4, min extra jump size = 4294967295 | |
Hot code size = 0x2C bytes | |
Cold code size = 0x0 bytes | |
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0xa) | |
*************** In emitEndCodeGen() | |
*************************************************************************** | |
Instructions as they come out of the scheduler | |
G_M35690_IG01: ; func=00, offs=000000H, size=0008H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG | |
IN000b: 000000 55 push rbp | |
IN000c: 000001 53 push rbx | |
IN000d: 000002 50 push rax | |
IN000e: 000003 488D6C2410 lea rbp, [rsp+10H] | |
G_M35690_IG02: ; func=00, offs=000008H, size=000BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz | |
IN0001: 000008 33DB xor ebx, ebx | |
; Call at 000A [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
IN0002: 00000A E849F7FFFF call ConsoleApplication.Program:GetNumberNoInline():int | |
IN0003: 00000F 85C0 test eax, eax | |
IN0004: 000011 7E12 jle SHORT G_M35690_IG04 | |
G_M35690_IG03: ; func=00, offs=000013H, size=0012H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz | |
IN0005: 000013 8BFB mov edi, ebx | |
; Call at 0015 [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
IN0006: 000015 E8A6F7FFFF call System.Console:WriteLine(int) | |
IN0007: 00001A FFC3 inc ebx | |
; Call at 001C [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} | |
IN0008: 00001C E837F7FFFF call ConsoleApplication.Program:GetNumberNoInline():int | |
IN0009: 000021 3BC3 cmp eax, ebx | |
IN000a: 000023 7FEE jg SHORT G_M35690_IG03 | |
G_M35690_IG04: ; func=00, offs=000025H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc | |
IN000f: 000025 488D65F8 lea rsp, [rbp-08H] | |
IN0010: 000029 5B pop rbx | |
IN0011: 00002A 5D pop rbp | |
IN0012: 00002B C3 ret | |
Allocated method code size = 44 , actual size = 44 | |
*************** After end code gen, before unwindEmit() | |
G_M35690_IG01: ; func=00, offs=000000H, size=0008H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG | |
IN000b: 000000 push rbp | |
IN000c: 000001 push rbx | |
IN000d: 000002 push rax | |
IN000e: 000003 lea rbp, [rsp+10H] | |
G_M35690_IG02: ; offs=000008H, size=000BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz | |
IN0001: 000008 xor ebx, ebx | |
IN0002: 00000A call ConsoleApplication.Program:GetNumberNoInline():int | |
IN0003: 00000F test eax, eax | |
IN0004: 000011 jle SHORT G_M35690_IG04 | |
G_M35690_IG03: ; offs=000013H, size=0012H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz | |
IN0005: 000013 mov edi, ebx | |
IN0006: 000015 call System.Console:WriteLine(int) | |
IN0007: 00001A inc ebx | |
IN0008: 00001C call ConsoleApplication.Program:GetNumberNoInline():int | |
IN0009: 000021 cmp eax, ebx | |
IN000a: 000023 jg SHORT G_M35690_IG03 | |
G_M35690_IG04: ; offs=000025H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc | |
IN000f: 000025 lea rsp, [rbp-08H] | |
IN0010: 000029 pop rbx | |
IN0011: 00002A pop rbp | |
IN0012: 00002B ret | |
Unwind Info: | |
>> Start offset : 0x000000 (not in unwind data) | |
>> End offset : 0x00002c (not in unwind data) | |
Version : 1 | |
Flags : 0x00 | |
SizeOfProlog : 0x03 | |
CountOfUnwindCodes: 3 | |
FrameRegister : none (0) | |
FrameOffset : N/A (no FrameRegister) (Value=0) | |
UnwindCodes : | |
CodeOffset: 0x03 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 0 * 8 + 8 = 8 = 0x08 | |
CodeOffset: 0x02 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3) | |
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpIn0 | |
1 | |
2 | |
fo: rbp (5) | |
allocUnwindInfo(pHotCode=0x00007F7D163BB920, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x2c, unwindSize=0xa, pUnwindBlock=0x000000000227AEE6, funKind=0 (main function)) | |
*************** In genIPmappingGen() | |
IP mapping count : 6 | |
IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) | |
IL offs 0x0000 : 0x00000008 ( STACK_EMPTY ) | |
IL offs 0x0004 : 0x00000013 ( STACK_EMPTY ) | |
IL offs 0x000A : 0x0000001A ( STACK_EMPTY ) | |
IL offs 0x0016 : 0x00000025 ( STACK_EMPTY ) | |
IL offs EPILOG : 0x00000025 ( STACK_EMPTY ) | |
*************** In genSetScopeInfo() | |
VarLocInfo count is 2 | |
*************** Variable debug info | |
2 vars | |
0( UNKNOWN) : From 00000000h to 00000008h, in rdi | |
1( UNKNOWN) : From 00000013h to 0000001Ah, in rbx | |
*************** In gcInfoBlockHdrSave() | |
Set code length to 44. | |
Set ReturnKind to Scalar. | |
Set stack base register to rbp. | |
Set Outgoing stack arg area size to 0. | |
Defining 3 call sites: | |
Offset 0xa, size 5. | |
Offset 0x15, size 5. | |
Offset 0x1c, size 5. | |
Allocations for ConsoleApplication.Program:Main(ref) (MethodHash=1499abcb) | |
count: 674, size: 57680, max = 3072 | |
allocateMemory: 131072, nraUsed: 89816 | |
Alloc'd bytes by kind: | |
kind | size | pct | |
---------------------+------------+-------- | |
AssertionProp | 0 | 0.00% | |
ASTNode | 6688 | 11.60% | |
InstDesc | 3144 | 5.45% | |
ImpStack | 0 | 0.00% | |
BasicBlock | 1696 | 2.94% | |
fgArgInfo | 64 | 0.11% | |
fgArgInfoPtrArr | 8 | 0.01% | |
FlowList | 224 | 0.39% | |
TreeStatementList | 0 | 0.00% | |
SiScope | 136 | 0.24% | |
FlatFPStateX87 | 0 | 0.00% | |
DominatorMemory | 128 | 0.22% | |
LSRA | 3120 | 5.41% | |
LSRA_Interval | 640 | 1.11% | |
LSRA_RefPosition | 3264 | 5.66% | |
Reachability | 16 | 0.03% | |
SSA | 884 | 1.53% | |
ValueNumber | 7540 | 13.07% | |
LvaTable | 1968 | 3.41% | |
UnwindInfo | 0 | 0.00% | |
hashBv | 160 | 0.28% | |
bitset | 0 | 0.00% | |
FixedBitVect | 0 | 0.00% | |
AsIAllocator | 9352 | 16.21% | |
IndirAssignMap | 64 | 0.11% | |
FieldSeqStore | 0 | 0.00% | |
ZeroOffsetFieldMap | 0 | 0.00% | |
ArrayInfoMap | 64 | 0.11% | |
HeapPhiArg | 48 | 0.08% | |
CSE | 1096 | 1.90% | |
GC | 1080 | 1.87% | |
CorSig | 208 | 0.36% | |
Inlining | 1016 | 1.76% | |
ArrayStack | 0 | 0.00% | |
DebugInfo | 336 | 0.58% | |
DebugOnly | 13984 | 24.24% | |
Codegen | 0 | 0.00% | |
LoopOpt | 0 | 0.00% | |
LoopHoist | 128 | 0.22% | |
Unknown | 624 | 1.08% | |
****** DONE compiling ConsoleApplication.Program:Main(ref) |
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