Tri-state VHDL principle

gistfile1.vhdl

 tri_st_data : process (mem_write_data, data, cur_memc_st)
 begin 
   if (cur_memc_st = ctrl_wait_for_write) then
     data <= mem_write_data; 
   else 
     data <= (others => 'Z');  
   end if; 
	mem_read_data <= data;
 end process tri_st_data;