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3Nigma/gist:5962112

Created July 9, 2013 23:03
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G+ VHDL SDRAM reading problem
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gistfile1.vhdl
addr : out std_logic_vector (SDR_ADDR_WIDTH - 1 downto 0);
data : in std_logic_vector (SDR_DATA_WIDTH - 1 downto 0);
...
addr(addr'length - 1 downto 0) <= data(addr'length - 1 downto 0);
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