A Cheat Sheet for a bunch of the stuff we did I my Makefile talk

makeComands.sh

make # runs the first target in the makefile named Makefile

make -f MyMakefile # Runs the first target in the Makefile named MyMakefile

make -f MyMakefile app # Runs the target called app

make -f MyMakefile app --dry-run # Does a dry run of the target called app

make -f MyMakefile app --debug=v  --dry-run # Turns on verbose debugging for a command

Makefile

# Basic Syntax
target: dependency dependency2 ...
	command1
	command2
	
# Note that those must BE TABs

# Setting variables
variable_name = "blah"

# Expanding variables
target: $(variable_name)

# Remember in Make everything is just text

# Settting Variables that can be overridden at the command line
VARIABLE_NAME_2 ?= "blah blah"

# Overriding at the command line is then done by
# VARIABLE_NAME_2 = "not blah" make

# Finding files in a path with wildcard
files = $(wildcard path)

# Phony targets (ergo - tasks)
.PHONY: taskname

# Ignoring errors in commands
clean:
	# Add a dash before each line
	-rm filename
	-rm filename
	
# To Add
# := vs = vs ?=
# recursive search (wildcard doesn't do it)
# The automatic variables