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diningyo/module_3.2_exercise_regfile.v

Created December 2, 2018 03:24
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Module3.2練習問題のレジスタファイルのRTL
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module_3.2_exercise_regfile.v
module cmd5HelperRegisterFile( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input io_wen, // @[:@6.4]
input [4:0] io_waddr, // @[:@6.4]
input [31:0] io_wdata, // @[:@6.4]
input [4:0] io_raddr_0, // @[:@6.4]
input [4:0] io_raddr_1, // @[:@6.4]
output [31:0] io_rdata_0, // @[:@6.4]
output [31:0] io_rdata_1 // @[:@6.4]
);
reg [31:0] reg_0; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_0;
reg [31:0] reg_1; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_1;
reg [31:0] reg_2; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_2;
reg [31:0] reg_3; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_3;
reg [31:0] reg_4; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_4;
reg [31:0] reg_5; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_5;
reg [31:0] reg_6; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_6;
reg [31:0] reg_7; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_7;
reg [31:0] reg_8; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_8;
reg [31:0] reg_9; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_9;
reg [31:0] reg_10; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_10;
reg [31:0] reg_11; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_11;
reg [31:0] reg_12; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_12;
reg [31:0] reg_13; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_13;
reg [31:0] reg_14; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_14;
reg [31:0] reg_15; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_15;
reg [31:0] reg_16; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_16;
reg [31:0] reg_17; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_17;
reg [31:0] reg_18; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_18;
reg [31:0] reg_19; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_19;
reg [31:0] reg_20; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_20;
reg [31:0] reg_21; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_21;
reg [31:0] reg_22; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_22;
reg [31:0] reg_23; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_23;
reg [31:0] reg_24; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_24;
reg [31:0] reg_25; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_25;
reg [31:0] reg_26; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_26;
reg [31:0] reg_27; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_27;
reg [31:0] reg_28; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_28;
reg [31:0] reg_29; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_29;
reg [31:0] reg_30; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_30;
reg [31:0] reg_31; // @[cmd5.sc 13:22:@75.4]
reg [31:0] _RAND_31;
wire _T_415; // @[cmd5.sc 17:24:@77.6]
wire [31:0] _GEN_0; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_1; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_2; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_3; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_4; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_5; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_6; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_7; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_8; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_9; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_10; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_11; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_12; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_13; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_14; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_15; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_16; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_17; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_18; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_19; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_20; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_21; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_22; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_23; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_24; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_25; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_26; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_27; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_28; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_29; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_30; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_31; // @[cmd5.sc 18:27:@79.8]
wire [31:0] _GEN_32; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_33; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_34; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_35; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_36; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_37; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_38; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_39; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_40; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_41; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_42; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_43; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_44; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_45; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_46; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_47; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_48; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_49; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_50; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_51; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_52; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_53; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_54; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_55; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_56; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_57; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_58; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_59; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_60; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_61; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_62; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_63; // @[cmd5.sc 17:32:@78.6]
wire [31:0] _GEN_64; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_65; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_66; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_67; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_68; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_69; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_70; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_71; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_72; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_73; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_74; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_75; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_76; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_77; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_78; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_79; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_80; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_81; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_82; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_83; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_84; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_85; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_86; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_87; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_88; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_89; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_90; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_91; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_92; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_93; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_94; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_95; // @[cmd5.sc 16:18:@76.4]
wire [31:0] _GEN_97; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_98; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_99; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_100; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_101; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_102; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_103; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_104; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_105; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_106; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_107; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_108; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_109; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_110; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_111; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_112; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_113; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_114; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_115; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_116; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_117; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_118; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_119; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_120; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_121; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_122; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_123; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_124; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_125; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_126; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_127; // @[cmd5.sc 24:21:@82.4]
wire [31:0] _GEN_129; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_130; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_131; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_132; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_133; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_134; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_135; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_136; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_137; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_138; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_139; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_140; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_141; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_142; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_143; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_144; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_145; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_146; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_147; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_148; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_149; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_150; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_151; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_152; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_153; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_154; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_155; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_156; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_157; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_158; // @[cmd5.sc 24:21:@83.4]
wire [31:0] _GEN_159; // @[cmd5.sc 24:21:@83.4]
assign _T_415 = io_waddr != 5'h0; // @[cmd5.sc 17:24:@77.6]
assign _GEN_0 = 5'h0 == io_waddr ? io_wdata : reg_0; // @[cmd5.sc 18:27:@79.8]
assign _GEN_1 = 5'h1 == io_waddr ? io_wdata : reg_1; // @[cmd5.sc 18:27:@79.8]
assign _GEN_2 = 5'h2 == io_waddr ? io_wdata : reg_2; // @[cmd5.sc 18:27:@79.8]
assign _GEN_3 = 5'h3 == io_waddr ? io_wdata : reg_3; // @[cmd5.sc 18:27:@79.8]
assign _GEN_4 = 5'h4 == io_waddr ? io_wdata : reg_4; // @[cmd5.sc 18:27:@79.8]
assign _GEN_5 = 5'h5 == io_waddr ? io_wdata : reg_5; // @[cmd5.sc 18:27:@79.8]
assign _GEN_6 = 5'h6 == io_waddr ? io_wdata : reg_6; // @[cmd5.sc 18:27:@79.8]
assign _GEN_7 = 5'h7 == io_waddr ? io_wdata : reg_7; // @[cmd5.sc 18:27:@79.8]
assign _GEN_8 = 5'h8 == io_waddr ? io_wdata : reg_8; // @[cmd5.sc 18:27:@79.8]
assign _GEN_9 = 5'h9 == io_waddr ? io_wdata : reg_9; // @[cmd5.sc 18:27:@79.8]
assign _GEN_10 = 5'ha == io_waddr ? io_wdata : reg_10; // @[cmd5.sc 18:27:@79.8]
assign _GEN_11 = 5'hb == io_waddr ? io_wdata : reg_11; // @[cmd5.sc 18:27:@79.8]
assign _GEN_12 = 5'hc == io_waddr ? io_wdata : reg_12; // @[cmd5.sc 18:27:@79.8]
assign _GEN_13 = 5'hd == io_waddr ? io_wdata : reg_13; // @[cmd5.sc 18:27:@79.8]
assign _GEN_14 = 5'he == io_waddr ? io_wdata : reg_14; // @[cmd5.sc 18:27:@79.8]
assign _GEN_15 = 5'hf == io_waddr ? io_wdata : reg_15; // @[cmd5.sc 18:27:@79.8]
assign _GEN_16 = 5'h10 == io_waddr ? io_wdata : reg_16; // @[cmd5.sc 18:27:@79.8]
assign _GEN_17 = 5'h11 == io_waddr ? io_wdata : reg_17; // @[cmd5.sc 18:27:@79.8]
assign _GEN_18 = 5'h12 == io_waddr ? io_wdata : reg_18; // @[cmd5.sc 18:27:@79.8]
assign _GEN_19 = 5'h13 == io_waddr ? io_wdata : reg_19; // @[cmd5.sc 18:27:@79.8]
assign _GEN_20 = 5'h14 == io_waddr ? io_wdata : reg_20; // @[cmd5.sc 18:27:@79.8]
assign _GEN_21 = 5'h15 == io_waddr ? io_wdata : reg_21; // @[cmd5.sc 18:27:@79.8]
assign _GEN_22 = 5'h16 == io_waddr ? io_wdata : reg_22; // @[cmd5.sc 18:27:@79.8]
assign _GEN_23 = 5'h17 == io_waddr ? io_wdata : reg_23; // @[cmd5.sc 18:27:@79.8]
assign _GEN_24 = 5'h18 == io_waddr ? io_wdata : reg_24; // @[cmd5.sc 18:27:@79.8]
assign _GEN_25 = 5'h19 == io_waddr ? io_wdata : reg_25; // @[cmd5.sc 18:27:@79.8]
assign _GEN_26 = 5'h1a == io_waddr ? io_wdata : reg_26; // @[cmd5.sc 18:27:@79.8]
assign _GEN_27 = 5'h1b == io_waddr ? io_wdata : reg_27; // @[cmd5.sc 18:27:@79.8]
assign _GEN_28 = 5'h1c == io_waddr ? io_wdata : reg_28; // @[cmd5.sc 18:27:@79.8]
assign _GEN_29 = 5'h1d == io_waddr ? io_wdata : reg_29; // @[cmd5.sc 18:27:@79.8]
assign _GEN_30 = 5'h1e == io_waddr ? io_wdata : reg_30; // @[cmd5.sc 18:27:@79.8]
assign _GEN_31 = 5'h1f == io_waddr ? io_wdata : reg_31; // @[cmd5.sc 18:27:@79.8]
assign _GEN_32 = _T_415 ? _GEN_0 : reg_0; // @[cmd5.sc 17:32:@78.6]
assign _GEN_33 = _T_415 ? _GEN_1 : reg_1; // @[cmd5.sc 17:32:@78.6]
assign _GEN_34 = _T_415 ? _GEN_2 : reg_2; // @[cmd5.sc 17:32:@78.6]
assign _GEN_35 = _T_415 ? _GEN_3 : reg_3; // @[cmd5.sc 17:32:@78.6]
assign _GEN_36 = _T_415 ? _GEN_4 : reg_4; // @[cmd5.sc 17:32:@78.6]
assign _GEN_37 = _T_415 ? _GEN_5 : reg_5; // @[cmd5.sc 17:32:@78.6]
assign _GEN_38 = _T_415 ? _GEN_6 : reg_6; // @[cmd5.sc 17:32:@78.6]
assign _GEN_39 = _T_415 ? _GEN_7 : reg_7; // @[cmd5.sc 17:32:@78.6]
assign _GEN_40 = _T_415 ? _GEN_8 : reg_8; // @[cmd5.sc 17:32:@78.6]
assign _GEN_41 = _T_415 ? _GEN_9 : reg_9; // @[cmd5.sc 17:32:@78.6]
assign _GEN_42 = _T_415 ? _GEN_10 : reg_10; // @[cmd5.sc 17:32:@78.6]
assign _GEN_43 = _T_415 ? _GEN_11 : reg_11; // @[cmd5.sc 17:32:@78.6]
assign _GEN_44 = _T_415 ? _GEN_12 : reg_12; // @[cmd5.sc 17:32:@78.6]
assign _GEN_45 = _T_415 ? _GEN_13 : reg_13; // @[cmd5.sc 17:32:@78.6]
assign _GEN_46 = _T_415 ? _GEN_14 : reg_14; // @[cmd5.sc 17:32:@78.6]
assign _GEN_47 = _T_415 ? _GEN_15 : reg_15; // @[cmd5.sc 17:32:@78.6]
assign _GEN_48 = _T_415 ? _GEN_16 : reg_16; // @[cmd5.sc 17:32:@78.6]
assign _GEN_49 = _T_415 ? _GEN_17 : reg_17; // @[cmd5.sc 17:32:@78.6]
assign _GEN_50 = _T_415 ? _GEN_18 : reg_18; // @[cmd5.sc 17:32:@78.6]
assign _GEN_51 = _T_415 ? _GEN_19 : reg_19; // @[cmd5.sc 17:32:@78.6]
assign _GEN_52 = _T_415 ? _GEN_20 : reg_20; // @[cmd5.sc 17:32:@78.6]
assign _GEN_53 = _T_415 ? _GEN_21 : reg_21; // @[cmd5.sc 17:32:@78.6]
assign _GEN_54 = _T_415 ? _GEN_22 : reg_22; // @[cmd5.sc 17:32:@78.6]
assign _GEN_55 = _T_415 ? _GEN_23 : reg_23; // @[cmd5.sc 17:32:@78.6]
assign _GEN_56 = _T_415 ? _GEN_24 : reg_24; // @[cmd5.sc 17:32:@78.6]
assign _GEN_57 = _T_415 ? _GEN_25 : reg_25; // @[cmd5.sc 17:32:@78.6]
assign _GEN_58 = _T_415 ? _GEN_26 : reg_26; // @[cmd5.sc 17:32:@78.6]
assign _GEN_59 = _T_415 ? _GEN_27 : reg_27; // @[cmd5.sc 17:32:@78.6]
assign _GEN_60 = _T_415 ? _GEN_28 : reg_28; // @[cmd5.sc 17:32:@78.6]
assign _GEN_61 = _T_415 ? _GEN_29 : reg_29; // @[cmd5.sc 17:32:@78.6]
assign _GEN_62 = _T_415 ? _GEN_30 : reg_30; // @[cmd5.sc 17:32:@78.6]
assign _GEN_63 = _T_415 ? _GEN_31 : reg_31; // @[cmd5.sc 17:32:@78.6]
assign _GEN_64 = io_wen ? _GEN_32 : reg_0; // @[cmd5.sc 16:18:@76.4]
assign _GEN_65 = io_wen ? _GEN_33 : reg_1; // @[cmd5.sc 16:18:@76.4]
assign _GEN_66 = io_wen ? _GEN_34 : reg_2; // @[cmd5.sc 16:18:@76.4]
assign _GEN_67 = io_wen ? _GEN_35 : reg_3; // @[cmd5.sc 16:18:@76.4]
assign _GEN_68 = io_wen ? _GEN_36 : reg_4; // @[cmd5.sc 16:18:@76.4]
assign _GEN_69 = io_wen ? _GEN_37 : reg_5; // @[cmd5.sc 16:18:@76.4]
assign _GEN_70 = io_wen ? _GEN_38 : reg_6; // @[cmd5.sc 16:18:@76.4]
assign _GEN_71 = io_wen ? _GEN_39 : reg_7; // @[cmd5.sc 16:18:@76.4]
assign _GEN_72 = io_wen ? _GEN_40 : reg_8; // @[cmd5.sc 16:18:@76.4]
assign _GEN_73 = io_wen ? _GEN_41 : reg_9; // @[cmd5.sc 16:18:@76.4]
assign _GEN_74 = io_wen ? _GEN_42 : reg_10; // @[cmd5.sc 16:18:@76.4]
assign _GEN_75 = io_wen ? _GEN_43 : reg_11; // @[cmd5.sc 16:18:@76.4]
assign _GEN_76 = io_wen ? _GEN_44 : reg_12; // @[cmd5.sc 16:18:@76.4]
assign _GEN_77 = io_wen ? _GEN_45 : reg_13; // @[cmd5.sc 16:18:@76.4]
assign _GEN_78 = io_wen ? _GEN_46 : reg_14; // @[cmd5.sc 16:18:@76.4]
assign _GEN_79 = io_wen ? _GEN_47 : reg_15; // @[cmd5.sc 16:18:@76.4]
assign _GEN_80 = io_wen ? _GEN_48 : reg_16; // @[cmd5.sc 16:18:@76.4]
assign _GEN_81 = io_wen ? _GEN_49 : reg_17; // @[cmd5.sc 16:18:@76.4]
assign _GEN_82 = io_wen ? _GEN_50 : reg_18; // @[cmd5.sc 16:18:@76.4]
assign _GEN_83 = io_wen ? _GEN_51 : reg_19; // @[cmd5.sc 16:18:@76.4]
assign _GEN_84 = io_wen ? _GEN_52 : reg_20; // @[cmd5.sc 16:18:@76.4]
assign _GEN_85 = io_wen ? _GEN_53 : reg_21; // @[cmd5.sc 16:18:@76.4]
assign _GEN_86 = io_wen ? _GEN_54 : reg_22; // @[cmd5.sc 16:18:@76.4]
assign _GEN_87 = io_wen ? _GEN_55 : reg_23; // @[cmd5.sc 16:18:@76.4]
assign _GEN_88 = io_wen ? _GEN_56 : reg_24; // @[cmd5.sc 16:18:@76.4]
assign _GEN_89 = io_wen ? _GEN_57 : reg_25; // @[cmd5.sc 16:18:@76.4]
assign _GEN_90 = io_wen ? _GEN_58 : reg_26; // @[cmd5.sc 16:18:@76.4]
assign _GEN_91 = io_wen ? _GEN_59 : reg_27; // @[cmd5.sc 16:18:@76.4]
assign _GEN_92 = io_wen ? _GEN_60 : reg_28; // @[cmd5.sc 16:18:@76.4]
assign _GEN_93 = io_wen ? _GEN_61 : reg_29; // @[cmd5.sc 16:18:@76.4]
assign _GEN_94 = io_wen ? _GEN_62 : reg_30; // @[cmd5.sc 16:18:@76.4]
assign _GEN_95 = io_wen ? _GEN_63 : reg_31; // @[cmd5.sc 16:18:@76.4]
assign _GEN_97 = 5'h1 == io_raddr_0 ? reg_1 : reg_0; // @[cmd5.sc 24:21:@82.4]
assign _GEN_98 = 5'h2 == io_raddr_0 ? reg_2 : _GEN_97; // @[cmd5.sc 24:21:@82.4]
assign _GEN_99 = 5'h3 == io_raddr_0 ? reg_3 : _GEN_98; // @[cmd5.sc 24:21:@82.4]
assign _GEN_100 = 5'h4 == io_raddr_0 ? reg_4 : _GEN_99; // @[cmd5.sc 24:21:@82.4]
assign _GEN_101 = 5'h5 == io_raddr_0 ? reg_5 : _GEN_100; // @[cmd5.sc 24:21:@82.4]
assign _GEN_102 = 5'h6 == io_raddr_0 ? reg_6 : _GEN_101; // @[cmd5.sc 24:21:@82.4]
assign _GEN_103 = 5'h7 == io_raddr_0 ? reg_7 : _GEN_102; // @[cmd5.sc 24:21:@82.4]
assign _GEN_104 = 5'h8 == io_raddr_0 ? reg_8 : _GEN_103; // @[cmd5.sc 24:21:@82.4]
assign _GEN_105 = 5'h9 == io_raddr_0 ? reg_9 : _GEN_104; // @[cmd5.sc 24:21:@82.4]
assign _GEN_106 = 5'ha == io_raddr_0 ? reg_10 : _GEN_105; // @[cmd5.sc 24:21:@82.4]
assign _GEN_107 = 5'hb == io_raddr_0 ? reg_11 : _GEN_106; // @[cmd5.sc 24:21:@82.4]
assign _GEN_108 = 5'hc == io_raddr_0 ? reg_12 : _GEN_107; // @[cmd5.sc 24:21:@82.4]
assign _GEN_109 = 5'hd == io_raddr_0 ? reg_13 : _GEN_108; // @[cmd5.sc 24:21:@82.4]
assign _GEN_110 = 5'he == io_raddr_0 ? reg_14 : _GEN_109; // @[cmd5.sc 24:21:@82.4]
assign _GEN_111 = 5'hf == io_raddr_0 ? reg_15 : _GEN_110; // @[cmd5.sc 24:21:@82.4]
assign _GEN_112 = 5'h10 == io_raddr_0 ? reg_16 : _GEN_111; // @[cmd5.sc 24:21:@82.4]
assign _GEN_113 = 5'h11 == io_raddr_0 ? reg_17 : _GEN_112; // @[cmd5.sc 24:21:@82.4]
assign _GEN_114 = 5'h12 == io_raddr_0 ? reg_18 : _GEN_113; // @[cmd5.sc 24:21:@82.4]
assign _GEN_115 = 5'h13 == io_raddr_0 ? reg_19 : _GEN_114; // @[cmd5.sc 24:21:@82.4]
assign _GEN_116 = 5'h14 == io_raddr_0 ? reg_20 : _GEN_115; // @[cmd5.sc 24:21:@82.4]
assign _GEN_117 = 5'h15 == io_raddr_0 ? reg_21 : _GEN_116; // @[cmd5.sc 24:21:@82.4]
assign _GEN_118 = 5'h16 == io_raddr_0 ? reg_22 : _GEN_117; // @[cmd5.sc 24:21:@82.4]
assign _GEN_119 = 5'h17 == io_raddr_0 ? reg_23 : _GEN_118; // @[cmd5.sc 24:21:@82.4]
assign _GEN_120 = 5'h18 == io_raddr_0 ? reg_24 : _GEN_119; // @[cmd5.sc 24:21:@82.4]
assign _GEN_121 = 5'h19 == io_raddr_0 ? reg_25 : _GEN_120; // @[cmd5.sc 24:21:@82.4]
assign _GEN_122 = 5'h1a == io_raddr_0 ? reg_26 : _GEN_121; // @[cmd5.sc 24:21:@82.4]
assign _GEN_123 = 5'h1b == io_raddr_0 ? reg_27 : _GEN_122; // @[cmd5.sc 24:21:@82.4]
assign _GEN_124 = 5'h1c == io_raddr_0 ? reg_28 : _GEN_123; // @[cmd5.sc 24:21:@82.4]
assign _GEN_125 = 5'h1d == io_raddr_0 ? reg_29 : _GEN_124; // @[cmd5.sc 24:21:@82.4]
assign _GEN_126 = 5'h1e == io_raddr_0 ? reg_30 : _GEN_125; // @[cmd5.sc 24:21:@82.4]
assign _GEN_127 = 5'h1f == io_raddr_0 ? reg_31 : _GEN_126; // @[cmd5.sc 24:21:@82.4]
assign _GEN_129 = 5'h1 == io_raddr_1 ? reg_1 : reg_0; // @[cmd5.sc 24:21:@83.4]
assign _GEN_130 = 5'h2 == io_raddr_1 ? reg_2 : _GEN_129; // @[cmd5.sc 24:21:@83.4]
assign _GEN_131 = 5'h3 == io_raddr_1 ? reg_3 : _GEN_130; // @[cmd5.sc 24:21:@83.4]
assign _GEN_132 = 5'h4 == io_raddr_1 ? reg_4 : _GEN_131; // @[cmd5.sc 24:21:@83.4]
assign _GEN_133 = 5'h5 == io_raddr_1 ? reg_5 : _GEN_132; // @[cmd5.sc 24:21:@83.4]
assign _GEN_134 = 5'h6 == io_raddr_1 ? reg_6 : _GEN_133; // @[cmd5.sc 24:21:@83.4]
assign _GEN_135 = 5'h7 == io_raddr_1 ? reg_7 : _GEN_134; // @[cmd5.sc 24:21:@83.4]
assign _GEN_136 = 5'h8 == io_raddr_1 ? reg_8 : _GEN_135; // @[cmd5.sc 24:21:@83.4]
assign _GEN_137 = 5'h9 == io_raddr_1 ? reg_9 : _GEN_136; // @[cmd5.sc 24:21:@83.4]
assign _GEN_138 = 5'ha == io_raddr_1 ? reg_10 : _GEN_137; // @[cmd5.sc 24:21:@83.4]
assign _GEN_139 = 5'hb == io_raddr_1 ? reg_11 : _GEN_138; // @[cmd5.sc 24:21:@83.4]
assign _GEN_140 = 5'hc == io_raddr_1 ? reg_12 : _GEN_139; // @[cmd5.sc 24:21:@83.4]
assign _GEN_141 = 5'hd == io_raddr_1 ? reg_13 : _GEN_140; // @[cmd5.sc 24:21:@83.4]
assign _GEN_142 = 5'he == io_raddr_1 ? reg_14 : _GEN_141; // @[cmd5.sc 24:21:@83.4]
assign _GEN_143 = 5'hf == io_raddr_1 ? reg_15 : _GEN_142; // @[cmd5.sc 24:21:@83.4]
assign _GEN_144 = 5'h10 == io_raddr_1 ? reg_16 : _GEN_143; // @[cmd5.sc 24:21:@83.4]
assign _GEN_145 = 5'h11 == io_raddr_1 ? reg_17 : _GEN_144; // @[cmd5.sc 24:21:@83.4]
assign _GEN_146 = 5'h12 == io_raddr_1 ? reg_18 : _GEN_145; // @[cmd5.sc 24:21:@83.4]
assign _GEN_147 = 5'h13 == io_raddr_1 ? reg_19 : _GEN_146; // @[cmd5.sc 24:21:@83.4]
assign _GEN_148 = 5'h14 == io_raddr_1 ? reg_20 : _GEN_147; // @[cmd5.sc 24:21:@83.4]
assign _GEN_149 = 5'h15 == io_raddr_1 ? reg_21 : _GEN_148; // @[cmd5.sc 24:21:@83.4]
assign _GEN_150 = 5'h16 == io_raddr_1 ? reg_22 : _GEN_149; // @[cmd5.sc 24:21:@83.4]
assign _GEN_151 = 5'h17 == io_raddr_1 ? reg_23 : _GEN_150; // @[cmd5.sc 24:21:@83.4]
assign _GEN_152 = 5'h18 == io_raddr_1 ? reg_24 : _GEN_151; // @[cmd5.sc 24:21:@83.4]
assign _GEN_153 = 5'h19 == io_raddr_1 ? reg_25 : _GEN_152; // @[cmd5.sc 24:21:@83.4]
assign _GEN_154 = 5'h1a == io_raddr_1 ? reg_26 : _GEN_153; // @[cmd5.sc 24:21:@83.4]
assign _GEN_155 = 5'h1b == io_raddr_1 ? reg_27 : _GEN_154; // @[cmd5.sc 24:21:@83.4]
assign _GEN_156 = 5'h1c == io_raddr_1 ? reg_28 : _GEN_155; // @[cmd5.sc 24:21:@83.4]
assign _GEN_157 = 5'h1d == io_raddr_1 ? reg_29 : _GEN_156; // @[cmd5.sc 24:21:@83.4]
assign _GEN_158 = 5'h1e == io_raddr_1 ? reg_30 : _GEN_157; // @[cmd5.sc 24:21:@83.4]
assign _GEN_159 = 5'h1f == io_raddr_1 ? reg_31 : _GEN_158; // @[cmd5.sc 24:21:@83.4]
assign io_rdata_0 = _GEN_127;
assign io_rdata_1 = _GEN_159;
always @(posedge clock) begin
if (reset) begin
reg_0 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h0 == io_waddr) begin
reg_0 <= io_wdata;
end
end
end
end
if (reset) begin
reg_1 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h1 == io_waddr) begin
reg_1 <= io_wdata;
end
end
end
end
if (reset) begin
reg_2 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h2 == io_waddr) begin
reg_2 <= io_wdata;
end
end
end
end
if (reset) begin
reg_3 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h3 == io_waddr) begin
reg_3 <= io_wdata;
end
end
end
end
if (reset) begin
reg_4 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h4 == io_waddr) begin
reg_4 <= io_wdata;
end
end
end
end
if (reset) begin
reg_5 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h5 == io_waddr) begin
reg_5 <= io_wdata;
end
end
end
end
if (reset) begin
reg_6 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h6 == io_waddr) begin
reg_6 <= io_wdata;
end
end
end
end
if (reset) begin
reg_7 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h7 == io_waddr) begin
reg_7 <= io_wdata;
end
end
end
end
if (reset) begin
reg_8 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h8 == io_waddr) begin
reg_8 <= io_wdata;
end
end
end
end
if (reset) begin
reg_9 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h9 == io_waddr) begin
reg_9 <= io_wdata;
end
end
end
end
if (reset) begin
reg_10 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'ha == io_waddr) begin
reg_10 <= io_wdata;
end
end
end
end
if (reset) begin
reg_11 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'hb == io_waddr) begin
reg_11 <= io_wdata;
end
end
end
end
if (reset) begin
reg_12 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'hc == io_waddr) begin
reg_12 <= io_wdata;
end
end
end
end
if (reset) begin
reg_13 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'hd == io_waddr) begin
reg_13 <= io_wdata;
end
end
end
end
if (reset) begin
reg_14 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'he == io_waddr) begin
reg_14 <= io_wdata;
end
end
end
end
if (reset) begin
reg_15 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'hf == io_waddr) begin
reg_15 <= io_wdata;
end
end
end
end
if (reset) begin
reg_16 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h10 == io_waddr) begin
reg_16 <= io_wdata;
end
end
end
end
if (reset) begin
reg_17 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h11 == io_waddr) begin
reg_17 <= io_wdata;
end
end
end
end
if (reset) begin
reg_18 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h12 == io_waddr) begin
reg_18 <= io_wdata;
end
end
end
end
if (reset) begin
reg_19 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h13 == io_waddr) begin
reg_19 <= io_wdata;
end
end
end
end
if (reset) begin
reg_20 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h14 == io_waddr) begin
reg_20 <= io_wdata;
end
end
end
end
if (reset) begin
reg_21 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h15 == io_waddr) begin
reg_21 <= io_wdata;
end
end
end
end
if (reset) begin
reg_22 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h16 == io_waddr) begin
reg_22 <= io_wdata;
end
end
end
end
if (reset) begin
reg_23 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h17 == io_waddr) begin
reg_23 <= io_wdata;
end
end
end
end
if (reset) begin
reg_24 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h18 == io_waddr) begin
reg_24 <= io_wdata;
end
end
end
end
if (reset) begin
reg_25 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h19 == io_waddr) begin
reg_25 <= io_wdata;
end
end
end
end
if (reset) begin
reg_26 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h1a == io_waddr) begin
reg_26 <= io_wdata;
end
end
end
end
if (reset) begin
reg_27 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h1b == io_waddr) begin
reg_27 <= io_wdata;
end
end
end
end
if (reset) begin
reg_28 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h1c == io_waddr) begin
reg_28 <= io_wdata;
end
end
end
end
if (reset) begin
reg_29 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h1d == io_waddr) begin
reg_29 <= io_wdata;
end
end
end
end
if (reset) begin
reg_30 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h1e == io_waddr) begin
reg_30 <= io_wdata;
end
end
end
end
if (reset) begin
reg_31 <= 32'h0;
end else begin
if (io_wen) begin
if (_T_415) begin
if (5'h1f == io_waddr) begin
reg_31 <= io_wdata;
end
end
end
end
end
endmodule
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