basic PAC blinky for ch32v003

Cargo.toml

[package]
name = "hello-wch"
version = "0.1.0"
edition = "2021"

[dependencies]
panic-halt = "0.2.0"
riscv-rt = "0.11.0"
embedded-hal = "0.2.7"

[patch.crates-io]
riscv-rt = { git = "https://github.com/9names/riscv-rt", branch = "rv32e" }

[dependencies.ch32v0]
version = "0.1.6"
features = ["ch32v003", "critical-section"]

[dependencies.riscv]
version = "0.10.1"
features = ["critical-section-single-hart"]

[profile.dev]
codegen-units = 1
opt-level = "z"
debug-assertions = false
incremental = false
overflow-checks = false

[profile.release]
codegen-units = 1
opt-level = "z"
debug-assertions = false
incremental = false
overflow-checks = false
lto = 'fat'

config.toml

[build]
target = "riscv32ec-unknown-none-elf"

[target.riscv32ec-unknown-none-elf]
rustflags = [
  "-C", "linker=ld.lld",
]

# we can't afford much space for debug messages, panic_immediate_abort helps
# [unstable]
# build-std = ["core", "compiler_builtins"]
# build-std-features = ["panic_immediate_abort"]

main.rs

#![no_std]
#![no_main]

use ch32v0::ch32v003;
use panic_halt as _;
use riscv_rt::entry;

#[entry]
fn main() -> ! {
    // not using take() saves us a panic and some program space
    // let peripherals = ch32v003::Peripherals::take().unwrap();
    let peripherals = unsafe {ch32v003::Peripherals::steal()};

    let gpioc = peripherals.GPIOC;
    let gpiod = peripherals.GPIOD;
    let rcc = peripherals.RCC;
    let mut mcycle = riscv::delay::McycleDelay::new(48_000_000);

    unsafe {
        // Enable clocks to GPIO banks C and D
        rcc.apb2pcenr.write_with_zero(|w| {
            w.iopcen().set_bit();
            w.iopden().set_bit();
            w
        });

        // Set GPIOs as push-pull outputs, low drive strength
        gpioc.cfglr.write_with_zero(|w| {
            w.cnf1().bits(0b00);
            w.mode1().bits(0b01);
            w
        });
        // led is on PD6 on nanoch32v003. the debug pin is PD1, if you do a write you'll clear it's mode.
        // using modify will preserve its value
        gpiod.cfglr.modify(|_, w| {
            w.cnf6().bits(0b00);
            w.mode6().bits(0b01);
            w
        });

        loop {
            gpioc.outdr.write_with_zero(|w| w.odr1().set_bit());
            // Set GPIO D pin 6 high
            gpiod.outdr.write_with_zero(|w| w.odr6().set_bit());
            riscv::asm::delay(1_000_000);

            // Set GPIO C pin 1 low
            gpioc.outdr.write_with_zero(|w| w.odr1().clear_bit());
            // Set GPIO D pin 1 low
            gpiod.outdr.write_with_zero(|w| w.odr6().clear_bit());
            riscv::asm::delay(1_000_000);
        }
    }
}