Skip to content

Instantly share code, notes, and snippets.

@9names
9names / main.S
Last active January 10, 2021 07:04
Writing
.set GPIO_CFGCTL2, 0x40000108
.set GPIO_CFGCTL32, 0x40000188
.set GPIO_CFGCTL34, 0x40000190
.set GPIO_CFG_GPIO5, 0b00001011001000000000000000000000
.set GPIO_BITSET_GPIO5, 0b00000000000000000000000000100000
.section .text
main:
la t1, GPIO_CFGCTL2
la t2, GPIO_CFG_GPIO5
@9names
9names / main.S
Created January 11, 2021 05:32
Toggle GPIO11 (JTAG TDO) on BL602
# memory mapped register for gpio0/1 cfg. used as base for other registers
.set GPIO_CFGCTL0, 0x40000100
# memory mapped register for gpio10/11 cfg
.set GPIO_CFGCTL5_OFS, 0x14
# memory mapped register for GPIO output (whether GPIO is high or low)
.set GPIO_CFGCTL32_OFS, 0x88
# memory mapped register for GPIO output-enable (whether GPIO gets driven)
.set GPIO_CFGCTL34_OFS, 0x90
# config for two GPIO is stored in each CFG register, choose the appropriate one
# based on your GPIO number (ie GPIO11 is ODD, GPIO2 is EVEN)
#![no_std]
#![no_main]
use panic_halt as _;
use bl602_hal as hal;
use hal::{
clock::{self, SysclkFreq, UART_PLL_FREQ},
serial::{Serial, Config},
pac,
prelude::*,
@9names
9names / main.rs
Created May 15, 2021 03:43
Blinky on TM4C123GXL
#![no_std]
#![no_main]
use panic_halt as _;
use cortex_m_rt::entry;
use tm4c123x_hal::{self as hal, prelude::*, delay::Delay};
#[entry]
fn main() -> ! {
let p = hal::Peripherals::take().unwrap();
@9names
9names / main.rs
Created November 24, 2021 12:50
Use the Pimoroni Pico display pack from Rust
//! Show ferris on the Pimoroni Pico Display pack
#![no_std]
#![no_main]
use cortex_m_rt::entry;
use defmt::*;
use defmt_rtt as _;
use embedded_hal::digital::v2::OutputPin;
use embedded_time::{fixed_point::FixedPoint, rate::Extensions};
@9names
9names / spi.rs
Created December 18, 2021 12:12
RP2040 DMA: SPI tx on one peripheral, rx on the second
//! Serial Peripheral Interface (SPI)
//!
//! See [Chapter 4 Section 4](https://datasheets.raspberrypi.org/rp2040/rp2040_datasheet.pdf) for more details
//!
//! ## Usage
//!
//! ```no_run
//! use embedded_hal::spi::MODE_0;
//! use embedded_time::rate::*;
//! use rp2040_hal::{spi::Spi, gpio::{Pins, FunctionSpi}, pac, sio::Sio};
uart1_pins_split-join_flow-control.rs: configuring pins as TX/RX/CTS/RTS, split and join functions, UART HW flow control
uart0_split_flow-control.rs: test UART HW flow control on UART0 but uses split TX/RX for all operations
flow_control_debugging.rs: attempting to work out if we could unblock UART after errors (unsuccessfully)
I also tested without the CTS/RTS pins enabled, and that worked fine (HW flow control is currently always enabled)
@9names
9names / uart.rs
Created January 5, 2022 00:33
rp2040 uart0 + uart 1
//! # UART Example
//!
//! This application demonstrates how to use the UART Driver to talk to a serial
//! connection.
//!
//! It may need to be adapted to your particular board layout and/or pin
//! assignment.
//!
//! See the `Cargo.toml` file for Copyright and licence details.
@9names
9names / segger_rtt_pipe.rs
Created February 24, 2022 12:01
Just a toy program to pipe segger-rtt output to stdout for using with defmt-print
use std::net::{TcpStream};
use std::io::{Read, Write};
use memchr::memmem;
// Update this to match what your tool says.
const END_OF_SEGGER_RTT_HEADER: &[u8; 28] = b"Process: JLinkGDBServerCLExe";
fn main() {
match TcpStream::connect("localhost:19021") {
Ok(mut stream) => {
{
"arch": "riscv32",
"cpu": "generic-rv32",
"data-layout": "e-m:e-p:32:32-i64:64-n32-S128",
"eh-frame-header": false,
"emit-debug-gdb-scripts": false,
"executables": true,
"features": "+m,+a",
"linker": "rust-lld",
"linker-flavor": "ld.lld",