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.set GPIO_CFGCTL2, 0x40000108 | |
.set GPIO_CFGCTL32, 0x40000188 | |
.set GPIO_CFGCTL34, 0x40000190 | |
.set GPIO_CFG_GPIO5, 0b00001011001000000000000000000000 | |
.set GPIO_BITSET_GPIO5, 0b00000000000000000000000000100000 | |
.section .text | |
main: | |
la t1, GPIO_CFGCTL2 | |
la t2, GPIO_CFG_GPIO5 |
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# memory mapped register for gpio0/1 cfg. used as base for other registers | |
.set GPIO_CFGCTL0, 0x40000100 | |
# memory mapped register for gpio10/11 cfg | |
.set GPIO_CFGCTL5_OFS, 0x14 | |
# memory mapped register for GPIO output (whether GPIO is high or low) | |
.set GPIO_CFGCTL32_OFS, 0x88 | |
# memory mapped register for GPIO output-enable (whether GPIO gets driven) | |
.set GPIO_CFGCTL34_OFS, 0x90 | |
# config for two GPIO is stored in each CFG register, choose the appropriate one | |
# based on your GPIO number (ie GPIO11 is ODD, GPIO2 is EVEN) |
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#![no_std] | |
#![no_main] | |
use panic_halt as _; | |
use bl602_hal as hal; | |
use hal::{ | |
clock::{self, SysclkFreq, UART_PLL_FREQ}, | |
serial::{Serial, Config}, | |
pac, | |
prelude::*, |
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#![no_std] | |
#![no_main] | |
use panic_halt as _; | |
use cortex_m_rt::entry; | |
use tm4c123x_hal::{self as hal, prelude::*, delay::Delay}; | |
#[entry] | |
fn main() -> ! { | |
let p = hal::Peripherals::take().unwrap(); |
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//! Show ferris on the Pimoroni Pico Display pack | |
#![no_std] | |
#![no_main] | |
use cortex_m_rt::entry; | |
use defmt::*; | |
use defmt_rtt as _; | |
use embedded_hal::digital::v2::OutputPin; | |
use embedded_time::{fixed_point::FixedPoint, rate::Extensions}; |
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//! Serial Peripheral Interface (SPI) | |
//! | |
//! See [Chapter 4 Section 4](https://datasheets.raspberrypi.org/rp2040/rp2040_datasheet.pdf) for more details | |
//! | |
//! ## Usage | |
//! | |
//! ```no_run | |
//! use embedded_hal::spi::MODE_0; | |
//! use embedded_time::rate::*; | |
//! use rp2040_hal::{spi::Spi, gpio::{Pins, FunctionSpi}, pac, sio::Sio}; |
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uart1_pins_split-join_flow-control.rs: configuring pins as TX/RX/CTS/RTS, split and join functions, UART HW flow control | |
uart0_split_flow-control.rs: test UART HW flow control on UART0 but uses split TX/RX for all operations | |
flow_control_debugging.rs: attempting to work out if we could unblock UART after errors (unsuccessfully) | |
I also tested without the CTS/RTS pins enabled, and that worked fine (HW flow control is currently always enabled) |
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//! # UART Example | |
//! | |
//! This application demonstrates how to use the UART Driver to talk to a serial | |
//! connection. | |
//! | |
//! It may need to be adapted to your particular board layout and/or pin | |
//! assignment. | |
//! | |
//! See the `Cargo.toml` file for Copyright and licence details. |
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use std::net::{TcpStream}; | |
use std::io::{Read, Write}; | |
use memchr::memmem; | |
// Update this to match what your tool says. | |
const END_OF_SEGGER_RTT_HEADER: &[u8; 28] = b"Process: JLinkGDBServerCLExe"; | |
fn main() { | |
match TcpStream::connect("localhost:19021") { | |
Ok(mut stream) => { |
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{ | |
"arch": "riscv32", | |
"cpu": "generic-rv32", | |
"data-layout": "e-m:e-p:32:32-i64:64-n32-S128", | |
"eh-frame-header": false, | |
"emit-debug-gdb-scripts": false, | |
"executables": true, | |
"features": "+m,+a", | |
"linker": "rust-lld", | |
"linker-flavor": "ld.lld", |
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