llvm atomic load

diff --git a/lib/Target/VectorProc/Disassembler/VectorProcDisassembler.cpp b/lib/Target/VectorProc/Disassembler/VectorProcDisassembler.cpp
index 6c7acb2..b49258e 100644
--- a/lib/Target/VectorProc/Disassembler/VectorProcDisassembler.cpp
+++ b/lib/Target/VectorProc/Disassembler/VectorProcDisassembler.cpp
@@ -23,6 +23,8 @@
 #include "llvm/Support/MemoryObject.h"
 #include "llvm/Support/TargetRegistry.h"
 
+#define DEBUG_TYPE "vectorproc-disassembler"
+
 using namespace llvm;
 
 typedef MCDisassembler::DecodeStatus DecodeStatus;
diff --git a/lib/Target/VectorProc/VectorProcISelLowering.cpp b/lib/Target/VectorProc/VectorProcISelLowering.cpp
index ee2c895..6651287 100644
--- a/lib/Target/VectorProc/VectorProcISelLowering.cpp
+++ b/lib/Target/VectorProc/VectorProcISelLowering.cpp
@@ -448,6 +448,14 @@ VectorProcTargetLowering::VectorProcTargetLowering(TargetMachine &TM)
   setOperationAction(ISD::VACOPY, MVT::Other, Expand);
   setOperationAction(ISD::VAEND, MVT::Other, Expand);
 
+  setOperationAction(ISD::ATOMIC_LOAD,       MVT::i32,    Expand);
+  setOperationAction(ISD::ATOMIC_LOAD,       MVT::i64,    Expand);
+  setOperationAction(ISD::ATOMIC_STORE,      MVT::i32,    Expand);
+  setOperationAction(ISD::ATOMIC_STORE,      MVT::i64,    Expand);
+
+  setInsertFencesForAtomic(true);
+
+
   // Hardware does not have an integer divider, so convert these to
   // library calls
   setOperationAction(ISD::UDIV, MVT::i32, Expand); // __udivsi3
diff --git a/lib/Target/VectorProc/VectorProcSubtarget.cpp b/lib/Target/VectorProc/VectorProcSubtarget.cpp
index fe8e634..0297bcd 100644
--- a/lib/Target/VectorProc/VectorProcSubtarget.cpp
+++ b/lib/Target/VectorProc/VectorProcSubtarget.cpp
@@ -17,6 +17,7 @@
 
 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
+#define DEBUG_TYPE "vectorproc-subtarget"
 #include "VectorProcGenSubtargetInfo.inc"
 
 using namespace llvm;