A simple example of a moving average block (four last samples)

moving_avg.vhd

library ieee ;
    use ieee.std_logic_1164.all ;
    use ieee.std_logic_unsigned.all;

entity moving_avg is
    generic(
        g_data_width : integer:= 16
    );
    port (
        clk      : in   std_logic;
        reset_n  : in   std_logic;
        data_in  : in   std_logic_vector(g_data_width-1 downto 0);
        data_out : out  std_logic_vector(g_data_width-1 downto 0)
    );

end moving_avg;


architecture rtl of moving_avg is

    signal   data_out_i  : std_logic_vector(g_data_width+1 downto 0);
    signal   data_in_d1  : std_logic_vector(g_data_width+1 downto 0);
    signal   data_in_d2  : std_logic_vector(g_data_width+1 downto 0);
    signal   data_in_d3  : std_logic_vector(g_data_width+1 downto 0);

begin

    p_delay : process(clk, reset_n)
    begin
        if reset_n = '0' then
           data_in_d1 <= (others => '0');
           data_in_d2 <= (others => '0');
           data_in_d3 <= (others => '0');

        elsif rising_edge(clk) then
           data_in_d1 <= "00" & data_in;
           data_in_d2 <= data_in_d1;
           data_in_d3 <= data_in_d2;

        end if ;
    end process p_delay;

    data_out_i <= "00" & data_in + data_in_d1 + data_in_d2 + data_in_d3;
    data_out <= data_out_i(g_data_width+1 downto 2);

end rtl;