reg.vhd

library ieee;
use ieee.std_logic_1164.all;

entity BancoRegistros is
   generic(
      nbits               : integer : = 16
      );
   port(
      clk                 : in  std_logic;
      wr                  : in  std_logic;
      AddrA, AddrB, WAddr : in  std_logic_vector(2 downto 0);
      WData               : in  std_logic_vector(nbits-1 downto 0);
      DataA, DataB        : out std_logic_vector(nbits-1 downto 0)
      );
   end BancoRegistros;

architecture rtl of BancoRegistros is
begin
   process(clk)
   begin
      if (clk'event and clk='1') then
         if wr='1' then
            reg(to_integer(unsigned(WAddr))) <= WData;
         end if;
         reg(0) <= (others=>'0');

         DataA <= reg(to_integer(unsigned(AddrA)));
         DataB <= reg(to_integer(unsigned(AddrB)));
      end if;
   end process ;
end rtl;