Abhishek-Varma/8_16_8_i32.log Secret

## 8_16_8_i32.log
// -----// IR Dump Before AssignTargetDevicesPass (iree-hal-assign-target-devices) //----- //
module {
  func.func @matmul_static(%arg0: tensor<8x8xi32>, %arg1: tensor<8x16xi32>) -> tensor<8x16xi32> {
    %0 = tensor.empty() : tensor<8x16xi32>
    %c0_i32 = arith.constant 0 : i32
    %1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %2 = linalg.matmul ins(%arg0, %arg1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    return %2 : tensor<8x16xi32>
  }
}


// -----// IR Dump Before AutoInputConversionPipeline (iree-auto-input-conversion) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: tensor<8x8xi32>, %arg1: tensor<8x16xi32>) -> tensor<8x16xi32> {
    %0 = tensor.empty() : tensor<8x16xi32>
    %c0_i32 = arith.constant 0 : i32
    %1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %2 = linalg.matmul ins(%arg0, %arg1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    return %2 : tensor<8x16xi32>
  }
}


// -----// IR Dump Before IREEImportPublic (iree-import-public) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: tensor<8x8xi32>, %arg1: tensor<8x16xi32>) -> tensor<8x16xi32> {
    %0 = tensor.empty() : tensor<8x16xi32>
    %c0_i32 = arith.constant 0 : i32
    %1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %2 = linalg.matmul ins(%arg0, %arg1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    return %2 : tensor<8x16xi32>
  }
}


// -----// IR Dump Before ImportMLProgram (iree-import-ml-program) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: tensor<8x8xi32>, %arg1: tensor<8x16xi32>) -> tensor<8x16xi32> {
    %0 = tensor.empty() : tensor<8x16xi32>
    %c0_i32 = arith.constant 0 : i32
    %1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %2 = linalg.matmul ins(%arg0, %arg1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    return %2 : tensor<8x16xi32>
  }
}


// -----// IR Dump Before SanitizeModuleNames (iree-sanitize-module-names) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: tensor<8x8xi32>, %arg1: tensor<8x16xi32>) -> tensor<8x16xi32> {
    %0 = tensor.empty() : tensor<8x16xi32>
    %c0_i32 = arith.constant 0 : i32
    %1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %2 = linalg.matmul ins(%arg0, %arg1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    return %2 : tensor<8x16xi32>
  }
}


// -----// IR Dump Before mlir::iree_compiler::IREE::ABI::ConvertStreamableOpsPass (iree-abi-convert-streamable-ops) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: tensor<8x8xi32>, %arg1: tensor<8x16xi32>) -> tensor<8x16xi32> {
    %0 = tensor.empty() : tensor<8x16xi32>
    %c0_i32 = arith.constant 0 : i32
    %1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %2 = linalg.matmul ins(%arg0, %arg1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    return %2 : tensor<8x16xi32>
  }
}


// -----// IR Dump Before mlir::iree_compiler::IREE::ABI::WrapEntryPointsPass (iree-abi-wrap-entry-points) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: tensor<8x8xi32>, %arg1: tensor<8x16xi32>) -> tensor<8x16xi32> {
    %0 = tensor.empty() : tensor<8x16xi32>
    %c0_i32 = arith.constant 0 : i32
    %1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %2 = linalg.matmul ins(%arg0, %arg1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    return %2 : tensor<8x16xi32>
  }
}


// -----// IR Dump Before Inliner (inline) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = call @_matmul_static(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
  func.func private @_matmul_static(%arg0: tensor<8x8xi32>, %arg1: tensor<8x16xi32>) -> tensor<8x16xi32> {
    %0 = tensor.empty() : tensor<8x16xi32>
    %c0_i32 = arith.constant 0 : i32
    %1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %2 = linalg.matmul ins(%arg0, %arg1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    return %2 : tensor<8x16xi32>
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func private @_matmul_static(%arg0: tensor<8x8xi32>, %arg1: tensor<8x16xi32>) -> tensor<8x16xi32> {
  %0 = tensor.empty() : tensor<8x16xi32>
  %c0_i32 = arith.constant 0 : i32
  %1 = linalg.fill ins(%c0_i32 : i32) outs(%0 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %2 = linalg.matmul ins(%arg0, %arg1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%1 : tensor<8x16xi32>) -> tensor<8x16xi32>
  return %2 : tensor<8x16xi32>
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = call @_matmul_static(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %c0_i32 = arith.constant 0 : i32
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before SymbolDCE (symbol-dce) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before DemoteF64ToF32 (iree-util-demote-f64-to-f32) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before RemoveZeroExtentTensors (iree-global-opt-remove-zero-extent-tensors) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before DetachElementwiseFromNamedOps (iree-global-opt-detach-elementwise-from-named-ops) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before LinalgNamedOpConversion (linalg-named-op-conversion) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before Convert1X1FilterConv2DToMatmul (iree-global-opt-convert-1x1-filter-conv2d-to-matmul) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before EraseUnusedLinalgOperands (iree-global-opt-erase-unused-linalg-operands) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before ExpandTensorShapes (iree-global-opt-expand-tensor-shapes) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before ConvertElementwiseToLinalg (convert-elementwise-to-linalg) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before RaiseSpecialOps (iree-global-opt-raise-special-ops) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before DecomposeConcat (iree-global-opt-decompose-concat) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before GeneralizeLinalgNamedOps (iree-global-opt-generalize-linalg-named-ops) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before FoldUnitExtentDims (iree-flow-fold-unit-extent-dims) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before FuseDequantizationMatmul (iree-global-opt-fuse-dequantization-matmul) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before LiftGenericToTransposeBatchMatmul (iree-global-opt-lift-generic-to-tranpose-batch-matmul) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before SetEncoding (iree-global-opt-set-encoding) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before MaterializeHomogeneousEncodings (iree-global-opt-materialize-homogeneous-encodings) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#map = affine_map<(d0, d1, d2) -> (d0, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d2, d1)>
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
#map3 = affine_map<()[s0, s1] -> (-s1 + (s1 ceildiv s0) * s0)>
#map4 = affine_map<()[s0] -> ((8 ceildiv s0) * s0)>
#map5 = affine_map<()[s0] -> ((16 ceildiv s0) * s0)>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2:2 = iree_linalg_ext.upper_bound_tile_size tensor<8x8xi32, #iree_linalg_ext.encoding<role =  LHS, element_types = [i32, i32, i32], matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>> -> index, index
    %3 = affine.apply #map3()[%2#0, %c8]
    %4 = affine.apply #map3()[%2#1, %c8]
    %padded = tensor.pad %0 low[0, 0] high[%3, %4] {
    ^bb0(%arg2: index, %arg3: index):
      tensor.yield %c0_i32 : i32
    } : tensor<8x8xi32> to tensor<?x?xi32>
    %5 = iree_linalg_ext.set_encoding %padded : tensor<?x?xi32> -> tensor<?x?xi32, #iree_linalg_ext.encoding<role =  LHS, element_types = [i32, i32, i32], original_type = tensor<8x8xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>>
    %6:2 = iree_linalg_ext.upper_bound_tile_size tensor<8x16xi32, #iree_linalg_ext.encoding<role =  RHS, element_types = [i32, i32, i32], matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>> -> index, index
    %7 = affine.apply #map3()[%6#0, %c8]
    %8 = affine.apply #map3()[%6#1, %c16]
    %padded_0 = tensor.pad %1 low[0, 0] high[%7, %8] {
    ^bb0(%arg2: index, %arg3: index):
      tensor.yield %c0_i32 : i32
    } : tensor<8x16xi32> to tensor<?x?xi32>
    %9 = iree_linalg_ext.set_encoding %padded_0 : tensor<?x?xi32> -> tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RHS, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>>
    %10:2 = iree_linalg_ext.upper_bound_tile_size tensor<8x16xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>> -> index, index
    %11 = affine.apply #map4()[%10#0]
    %12 = affine.apply #map5()[%10#1]
    %13 = tensor.empty(%11, %12) : tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>>
    %14 = linalg.fill ins(%c0_i32 : i32) outs(%13 : tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>>) -> tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>>
    %15 = linalg.matmul ins(%5, %9 : tensor<?x?xi32, #iree_linalg_ext.encoding<role =  LHS, element_types = [i32, i32, i32], original_type = tensor<8x8xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>>, tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RHS, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>>) outs(%14 : tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>>) -> tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>>
    %16 = iree_linalg_ext.unset_encoding %15 : tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [#map, #map1, #map2]>> -> tensor<?x?xi32>
    %extracted_slice = tensor.extract_slice %16[0, 0] [8, 16] [1, 1] : tensor<?x?xi32> to tensor<8x16xi32>
    %17 = hal.tensor.export %extracted_slice "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %17 : !hal.buffer_view
  }
}


// -----// IR Dump Before MaterializeEncodingIntoNop (iree-codegen-materialize-encoding-into-nop) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2:2 = iree_linalg_ext.upper_bound_tile_size tensor<8x8xi32, #iree_linalg_ext.encoding<role =  LHS, element_types = [i32, i32, i32], matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>> -> index, index
  %3 = affine.apply affine_map<()[s0, s1] -> (-s1 + (s1 ceildiv s0) * s0)>()[%2#0, %c8]
  %4 = affine.apply affine_map<()[s0, s1] -> (-s1 + (s1 ceildiv s0) * s0)>()[%2#1, %c8]
  %padded = tensor.pad %0 low[0, 0] high[%3, %4] {
  ^bb0(%arg2: index, %arg3: index):
    tensor.yield %c0_i32 : i32
  } : tensor<8x8xi32> to tensor<?x?xi32>
  %5 = iree_linalg_ext.set_encoding %padded : tensor<?x?xi32> -> tensor<?x?xi32, #iree_linalg_ext.encoding<role =  LHS, element_types = [i32, i32, i32], original_type = tensor<8x8xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>
  %6:2 = iree_linalg_ext.upper_bound_tile_size tensor<8x16xi32, #iree_linalg_ext.encoding<role =  RHS, element_types = [i32, i32, i32], matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>> -> index, index
  %7 = affine.apply affine_map<()[s0, s1] -> (-s1 + (s1 ceildiv s0) * s0)>()[%6#0, %c8]
  %8 = affine.apply affine_map<()[s0, s1] -> (-s1 + (s1 ceildiv s0) * s0)>()[%6#1, %c16]
  %padded_0 = tensor.pad %1 low[0, 0] high[%7, %8] {
  ^bb0(%arg2: index, %arg3: index):
    tensor.yield %c0_i32 : i32
  } : tensor<8x16xi32> to tensor<?x?xi32>
  %9 = iree_linalg_ext.set_encoding %padded_0 : tensor<?x?xi32> -> tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RHS, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>
  %10:2 = iree_linalg_ext.upper_bound_tile_size tensor<8x16xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>> -> index, index
  %11 = affine.apply affine_map<()[s0] -> ((8 ceildiv s0) * s0)>()[%10#0]
  %12 = affine.apply affine_map<()[s0] -> ((16 ceildiv s0) * s0)>()[%10#1]
  %13 = tensor.empty(%11, %12) : tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>
  %14 = linalg.fill ins(%c0_i32 : i32) outs(%13 : tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>) -> tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>
  %15 = linalg.matmul ins(%5, %9 : tensor<?x?xi32, #iree_linalg_ext.encoding<role =  LHS, element_types = [i32, i32, i32], original_type = tensor<8x8xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>, tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RHS, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>) outs(%14 : tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>) -> tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>>
  %16 = iree_linalg_ext.unset_encoding %15 : tensor<?x?xi32, #iree_linalg_ext.encoding<role =  RESULT, element_types = [i32, i32, i32], original_type = tensor<8x16xi32>, matmul_narrow_M = 8 : index, user_indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>]>> -> tensor<?x?xi32>
  %extracted_slice = tensor.extract_slice %16[0, 0] [8, 16] [1, 1] : tensor<?x?xi32> to tensor<8x16xi32>
  %17 = hal.tensor.export %extracted_slice "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %17 : !hal.buffer_view
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %c0 = arith.constant 0 : index
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %padded = tensor.pad %0 low[0, 0] high[%c0, %c0] {
  ^bb0(%arg2: index, %arg3: index):
    tensor.yield %c0_i32 : i32
  } : tensor<8x8xi32> to tensor<?x?xi32>
  %padded_0 = tensor.pad %1 low[0, 0] high[%c0, %c0] {
  ^bb0(%arg2: index, %arg3: index):
    tensor.yield %c0_i32 : i32
  } : tensor<8x16xi32> to tensor<?x?xi32>
  %2 = tensor.empty(%c8, %c16) : tensor<?x?xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<?x?xi32>) -> tensor<?x?xi32>
  %4 = linalg.matmul ins(%padded, %padded_0 : tensor<?x?xi32>, tensor<?x?xi32>) outs(%3 : tensor<?x?xi32>) -> tensor<?x?xi32>
  %extracted_slice = tensor.extract_slice %4[0, 0] [8, 16] [1, 1] : tensor<?x?xi32> to tensor<8x16xi32>
  %5 = hal.tensor.export %extracted_slice "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before CSE (cse) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before SimplifyPackUnpack (iree-global-opt-simplify-pack-unpack) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before GeneralizeLinalgNamedOps (iree-global-opt-generalize-linalg-named-ops) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before FixedPointIterator (iree-util-fixed-point-iterator) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before CSE (cse) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before HoistIntoGlobals (iree-util-hoist-into-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before JitGlobals (iree-consteval-jit-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before RaiseSpecialOps (iree-global-opt-raise-special-ops) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before VerifyInputLegality (iree-verify-input-legality) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before TensorPadToTensorInsertSlice (iree-flow-tensor-pad-to-tensor-insert-slice) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = tensor.empty() : tensor<8x16xi32>
    %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %5 : !hal.buffer_view
  }
}


// -----// IR Dump Before InterchangeGenericOps (iree-flow-interchange-generic-ops) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before ResolveShapedTypeResultDims (resolve-shaped-type-result-dims) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before FusionOfTensorOps (iree-flow-fusion-of-tensor-ops) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before SplitReduction (iree-flow-split-reduction-ops) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before InterchangeGenericOps (iree-flow-interchange-generic-ops) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before FormScalarDispatches (iree-flow-form-scalar-dispatches) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before FormDispatchRegions (iree-flow-form-dispatch-regions) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before CloneProducersIntoDispatchRegions (iree-flow-clone-producers-into-dispatch-regions) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = flow.dispatch.region -> (tensor<8x16xi32>) {
    %6 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
    flow.return %6 : tensor<8x16xi32>
  }
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before CollapseDimensions (iree-flow-collapse-dimensions) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = flow.dispatch.region -> (tensor<8x16xi32>) {
    %6 = tensor.empty() : tensor<8x16xi32>
    %c0_i32_0 = arith.constant 0 : i32
    %7 = linalg.fill ins(%c0_i32_0 : i32) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %8 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%7 : tensor<8x16xi32>) -> tensor<8x16xi32>
    flow.return %8 : tensor<8x16xi32>
  }
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before FormDispatchWorkgroups (iree-flow-form-dispatch-workgroups) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = tensor.empty() : tensor<8x16xi32>
  %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %4 = flow.dispatch.region -> (tensor<8x16xi32>) {
    %6 = tensor.empty() : tensor<8x16xi32>
    %c0_i32_0 = arith.constant 0 : i32
    %7 = linalg.fill ins(%c0_i32_0 : i32) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %8 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%7 : tensor<8x16xi32>) -> tensor<8x16xi32>
    flow.return %8 : tensor<8x16xi32>
  }
  %5 = hal.tensor.export %4 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %5 : !hal.buffer_view
}

// -----// IR Dump Before CaptureDispatchDynamicDims (iree-flow-capture-dispatch-dynamic-dims) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch.workgroups(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32> =
      (%arg2: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
    %c0_i32 = arith.constant 0 : i32
    %4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %6 = tensor.empty() : tensor<8x16xi32>
    %7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %8 = linalg.matmul ins(%4, %5 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%7 : tensor<8x16xi32>) -> tensor<8x16xi32>
    flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    flow.return
  } count() -> (index, index, index) {
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    flow.return %x, %y, %z : index, index, index
  }
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch.workgroups(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32> =
      (%arg2: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
    %c0_i32 = arith.constant 0 : i32
    %4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %6 = tensor.empty() : tensor<8x16xi32>
    %7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %8 = linalg.matmul ins(%4, %5 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%7 : tensor<8x16xi32>) -> tensor<8x16xi32>
    flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    flow.return
  } count() -> (index, index, index) {
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    flow.return %x, %y, %z : index, index, index
  }
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch.workgroups(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32> =
      (%arg2: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
    %c0_i32 = arith.constant 0 : i32
    %4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %6 = tensor.empty() : tensor<8x16xi32>
    %7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %8 = linalg.matmul ins(%4, %5 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%7 : tensor<8x16xi32>) -> tensor<8x16xi32>
    flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    flow.return
  } count() -> (index, index, index) {
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    flow.return %x, %y, %z : index, index, index
  }
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before InitializeEmptyTensors (iree-flow-initialize-empty-tensors) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch.workgroups(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32> =
      (%arg2: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
    %c0_i32 = arith.constant 0 : i32
    %4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %6 = tensor.empty() : tensor<8x16xi32>
    %7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %8 = linalg.matmul ins(%4, %5 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%7 : tensor<8x16xi32>) -> tensor<8x16xi32>
    flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    flow.return
  } count() -> (index, index, index) {
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    flow.return %x, %y, %z : index, index, index
  }
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before OutlineDispatchExterns (iree-flow-outline-dispatch-externs) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch.workgroups(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32> =
        (%arg2: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
      %c0_i32 = arith.constant 0 : i32
      %4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
      %5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
      %6 = tensor.empty() : tensor<8x16xi32>
      %7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %8 = linalg.matmul ins(%4, %5 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%7 : tensor<8x16xi32>) -> tensor<8x16xi32>
      flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      flow.return
    } count() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before OutlineDispatchRegions (iree-flow-outline-dispatch-regions) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch.workgroups(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32> =
        (%arg2: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg3: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg4: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
      %c0_i32 = arith.constant 0 : i32
      %4 = flow.dispatch.tensor.load %arg2, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
      %5 = flow.dispatch.tensor.load %arg3, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
      %6 = tensor.empty() : tensor<8x16xi32>
      %7 = linalg.fill ins(%c0_i32 : i32) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %8 = linalg.matmul ins(%4, %5 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%7 : tensor<8x16xi32>) -> tensor<8x16xi32>
      flow.dispatch.tensor.store %8, %arg4, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      flow.return
    } count() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before AnnotateDispatches (iree-flow-annotate-dispatches) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before StripDebugOps (iree-util-strip-debug-ops) //----- //
flow.executable private @matmul_static_dispatch_0 {
  flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    flow.return %x, %y, %z : index, index, index
  }
  builtin.module {
    func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
      %c0_i32 = arith.constant 0 : i32
      %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
      %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
      %2 = tensor.empty() : tensor<8x16xi32>
      %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
      flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      return
    }
  }
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before DeduplicateExecutables (iree-flow-deduplicate-executables) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
flow.executable private @matmul_static_dispatch_0 {
  flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    flow.return %x, %y, %z : index, index, index
  }
  builtin.module {
    func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
      %c0_i32 = arith.constant 0 : i32
      %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
      %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
      %2 = tensor.empty() : tensor<8x16xi32>
      %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
      flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      return
    }
  }
}

// -----// IR Dump Before CSE (cse) //----- //
flow.executable private @matmul_static_dispatch_0 {
  flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    flow.return %x, %y, %z : index, index, index
  }
  builtin.module {
    func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
      %c0_i32 = arith.constant 0 : i32
      %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
      %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
      %2 = tensor.empty() : tensor<8x16xi32>
      %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
      flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      return
    }
  }
}

// -----// IR Dump Before CleanupTensorShapes (iree-flow-cleanup-tensor-shapes) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before SymbolDCE (symbol-dce) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before VerifyInputPass (iree-stream-verify-input) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before OutlineConstants (iree-util-outline-constants) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
  %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
  %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
  %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before ConvertToStreamPass (iree-stream-conversion) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  flow.executable private @matmul_static_dispatch_0 {
    flow.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      flow.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !flow.dispatch.tensor<readonly:tensor<8x8xi32>>, %arg1: !flow.dispatch.tensor<readonly:tensor<8x16xi32>>, %arg2: !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>) {
        %c0_i32 = arith.constant 0 : i32
        %0 = flow.dispatch.tensor.load %arg0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %1 = flow.dispatch.tensor.load %arg1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %2 = tensor.empty() : tensor<8x16xi32>
        %3 = linalg.fill ins(%c0_i32 : i32) outs(%2 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %4 = linalg.matmul ins(%0, %1 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%3 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %4, %arg2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %0 = hal.tensor.import %arg0 "input0" : !hal.buffer_view -> tensor<8x8xi32>
    %1 = hal.tensor.import %arg1 "input1" : !hal.buffer_view -> tensor<8x16xi32>
    %2 = flow.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0, %1) : (tensor<8x8xi32>, tensor<8x16xi32>) -> tensor<8x16xi32>
    %3 = hal.tensor.export %2 "output0" : tensor<8x16xi32> -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before VerifyLoweringToTensorsPass (iree-stream-verify-lowering-to-tensors) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %c0_i32 = arith.constant 0 : i32
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    %c8 = arith.constant 8 : index
    %c8_0 = arith.constant 8 : index
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8_0]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.sizeof tensor<8x8xi32> : index
    %1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%0}
    %2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
    %element_type_i32_1 = hal.element_type<i32> : i32
    %dense_row_major_2 = hal.encoding_type<dense_row_major> : i32
    %c8_3 = arith.constant 8 : index
    %c16 = arith.constant 16 : index
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8_3, %c16]) type(%element_type_i32_1) encoding(%dense_row_major_2)
    %3 = stream.tensor.sizeof tensor<8x16xi32> : index
    %4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%3}
    %5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
    %c0 = arith.constant 0 : index
    %6 = stream.tensor.sizeof tensor<8x16xi32> : index
    %7 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%6}
    %8 = stream.async.transfer %7 : !stream.resource<*>{%6} -> !stream.resource<external>{%6}
    %9 = stream.tensor.export %8 : tensor<8x16xi32> in !stream.resource<external>{%6} -> !hal.buffer_view
    return %9 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  %c8 = arith.constant 8 : index
  %c8_0 = arith.constant 8 : index
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8_0]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.sizeof tensor<8x8xi32> : index
  %1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%0}
  %2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
  %element_type_i32_1 = hal.element_type<i32> : i32
  %dense_row_major_2 = hal.encoding_type<dense_row_major> : i32
  %c8_3 = arith.constant 8 : index
  %c16 = arith.constant 16 : index
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8_3, %c16]) type(%element_type_i32_1) encoding(%dense_row_major_2)
  %3 = stream.tensor.sizeof tensor<8x16xi32> : index
  %4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%3}
  %5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
  %c0 = arith.constant 0 : index
  %6 = stream.tensor.sizeof tensor<8x16xi32> : index
  %7 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%6}
  %8 = stream.async.transfer %7 : !stream.resource<*>{%6} -> !stream.resource<external>{%6}
  %9 = stream.tensor.export %8 : tensor<8x16xi32> in !stream.resource<external>{%6} -> !hal.buffer_view
  return %9 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.sizeof tensor<8x8xi32> : index
  %1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%0}
  %2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
  %element_type_i32_0 = hal.element_type<i32> : i32
  %dense_row_major_1 = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32_0) encoding(%dense_row_major_1)
  %3 = stream.tensor.sizeof tensor<8x16xi32> : index
  %4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%3}
  %5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
  %6 = stream.tensor.sizeof tensor<8x16xi32> : index
  %7 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%6}
  %8 = stream.async.transfer %7 : !stream.resource<*>{%6} -> !stream.resource<external>{%6}
  %9 = stream.tensor.export %8 : tensor<8x16xi32> in !stream.resource<external>{%6} -> !hal.buffer_view
  return %9 : !hal.buffer_view
}

// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.sizeof tensor<8x8xi32> : index
  %1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%0}
  %2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %3 = stream.tensor.sizeof tensor<8x16xi32> : index
  %4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%3}
  %5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
  %6 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%3}
  %7 = stream.async.transfer %6 : !stream.resource<*>{%3} -> !stream.resource<external>{%3}
  %8 = stream.tensor.export %7 : tensor<8x16xi32> in !stream.resource<external>{%3} -> !hal.buffer_view
  return %8 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %c0_i32 = arith.constant 0 : i32
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.sizeof tensor<8x8xi32> : index
    %1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%0}
    %2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %3 = stream.tensor.sizeof tensor<8x16xi32> : index
    %4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%3}
    %5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
    %6 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%3}
    %7 = stream.async.transfer %6 : !stream.resource<*>{%3} -> !stream.resource<external>{%3}
    %8 = stream.tensor.export %7 : tensor<8x16xi32> in !stream.resource<external>{%3} -> !hal.buffer_view
    return %8 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.sizeof tensor<8x8xi32> : index
    %1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%0}
    %2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %3 = stream.tensor.sizeof tensor<8x16xi32> : index
    %4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%3}
    %5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
    %6 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%3}
    %7 = stream.async.transfer %6 : !stream.resource<*>{%3} -> !stream.resource<external>{%3}
    %8 = stream.tensor.export %7 : tensor<8x16xi32> in !stream.resource<external>{%3} -> !hal.buffer_view
    return %8 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.sizeof tensor<8x8xi32> : index
    %1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%0}
    %2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %3 = stream.tensor.sizeof tensor<8x16xi32> : index
    %4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%3}
    %5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
    %6 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%3}
    %7 = stream.async.transfer %6 : !stream.resource<*>{%3} -> !stream.resource<external>{%3}
    %8 = stream.tensor.export %7 : tensor<8x16xi32> in !stream.resource<external>{%3} -> !hal.buffer_view
    return %8 : !hal.buffer_view
  }
}


// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.sizeof tensor<8x8xi32> : index
    %1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%0}
    %2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %3 = stream.tensor.sizeof tensor<8x16xi32> : index
    %4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%3}
    %5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
    %6 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%3}
    %7 = stream.async.transfer %6 : !stream.resource<*>{%3} -> !stream.resource<external>{%3}
    %8 = stream.tensor.export %7 : tensor<8x16xi32> in !stream.resource<external>{%3} -> !hal.buffer_view
    return %8 : !hal.buffer_view
  }
}


// -----// IR Dump Before CombineInitializers (iree-util-combine-initializers) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.sizeof tensor<8x8xi32> : index
    %1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%0}
    %2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %3 = stream.tensor.sizeof tensor<8x16xi32> : index
    %4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%3}
    %5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
    %6 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%3}
    %7 = stream.async.transfer %6 : !stream.resource<*>{%3} -> !stream.resource<external>{%3}
    %8 = stream.tensor.export %7 : tensor<8x16xi32> in !stream.resource<external>{%3} -> !hal.buffer_view
    return %8 : !hal.buffer_view
  }
}


// -----// IR Dump Before EncodeDeviceTensorsPass (iree-stream-encode-device-tensors) //----- //
stream.executable private @matmul_static_dispatch_0 {
  stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    stream.return %x, %y, %z : index, index, index
  }
  builtin.module {
    func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
      %c0_i32 = arith.constant 0 : i32
      %c0 = arith.constant 0 : index
      %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
      %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
      %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
      %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
      %5 = tensor.empty() : tensor<8x16xi32>
      %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
      flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      return
    }
  }
}

// -----// IR Dump Before EncodeHostTensorsPass (iree-stream-encode-host-tensors) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.sizeof tensor<8x8xi32> : index
  %1 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%0}
  %2 = stream.async.transfer %1 : !stream.resource<external>{%0} -> !stream.resource<*>{%0}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %3 = stream.tensor.sizeof tensor<8x16xi32> : index
  %4 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%3}
  %5 = stream.async.transfer %4 : !stream.resource<external>{%3} -> !stream.resource<*>{%3}
  %6 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%2[%c0 to %0 for %0], %5[%c0 to %3 for %3]) : (!stream.resource<*>{%0}, !stream.resource<*>{%3}) -> !stream.resource<*>{%3}
  %7 = stream.async.transfer %6 : !stream.resource<*>{%3} -> !stream.resource<external>{%3}
  %8 = stream.tensor.export %7 : tensor<8x16xi32> in !stream.resource<external>{%3} -> !hal.buffer_view
  return %8 : !hal.buffer_view
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  %1 = stream.async.transfer %0 : !stream.resource<external>{%c256} -> !stream.resource<*>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %3 = stream.async.transfer %2 : !stream.resource<external>{%c512} -> !stream.resource<*>{%c512}
  %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%1[%c0 to %c256 for %c256], %3[%c0 to %c512 for %c512]) : (!stream.resource<*>{%c256}, !stream.resource<*>{%c512}) -> !stream.resource<*>{%c512}
  %5 = stream.async.transfer %4 : !stream.resource<*>{%c512} -> !stream.resource<external>{%c512}
  %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %6 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  %1 = stream.async.transfer %0 : !stream.resource<external>{%c256} -> !stream.resource<*>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %3 = stream.async.transfer %2 : !stream.resource<external>{%c512} -> !stream.resource<*>{%c512}
  %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%1[%c0 to %c256 for %c256], %3[%c0 to %c512 for %c512]) : (!stream.resource<*>{%c256}, !stream.resource<*>{%c512}) -> !stream.resource<*>{%c512}
  %5 = stream.async.transfer %4 : !stream.resource<*>{%c512} -> !stream.resource<external>{%c512}
  %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %6 : !hal.buffer_view
}

// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  %1 = stream.async.transfer %0 : !stream.resource<external>{%c256} -> !stream.resource<*>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %3 = stream.async.transfer %2 : !stream.resource<external>{%c512} -> !stream.resource<*>{%c512}
  %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%1[%c0 to %c256 for %c256], %3[%c0 to %c512 for %c512]) : (!stream.resource<*>{%c256}, !stream.resource<*>{%c512}) -> !stream.resource<*>{%c512}
  %5 = stream.async.transfer %4 : !stream.resource<*>{%c512} -> !stream.resource<external>{%c512}
  %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %6 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    %1 = stream.async.transfer %0 : !stream.resource<external>{%c256} -> !stream.resource<*>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %3 = stream.async.transfer %2 : !stream.resource<external>{%c512} -> !stream.resource<*>{%c512}
    %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%1[%c0 to %c256 for %c256], %3[%c0 to %c512 for %c512]) : (!stream.resource<*>{%c256}, !stream.resource<*>{%c512}) -> !stream.resource<*>{%c512}
    %5 = stream.async.transfer %4 : !stream.resource<*>{%c512} -> !stream.resource<external>{%c512}
    %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %6 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    %1 = stream.async.transfer %0 : !stream.resource<external>{%c256} -> !stream.resource<*>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %3 = stream.async.transfer %2 : !stream.resource<external>{%c512} -> !stream.resource<*>{%c512}
    %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%1[%c0 to %c256 for %c256], %3[%c0 to %c512 for %c512]) : (!stream.resource<*>{%c256}, !stream.resource<*>{%c512}) -> !stream.resource<*>{%c512}
    %5 = stream.async.transfer %4 : !stream.resource<*>{%c512} -> !stream.resource<external>{%c512}
    %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %6 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    %1 = stream.async.transfer %0 : !stream.resource<external>{%c256} -> !stream.resource<*>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %3 = stream.async.transfer %2 : !stream.resource<external>{%c512} -> !stream.resource<*>{%c512}
    %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%1[%c0 to %c256 for %c256], %3[%c0 to %c512 for %c512]) : (!stream.resource<*>{%c256}, !stream.resource<*>{%c512}) -> !stream.resource<*>{%c512}
    %5 = stream.async.transfer %4 : !stream.resource<*>{%c512} -> !stream.resource<external>{%c512}
    %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %6 : !hal.buffer_view
  }
}


// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    %1 = stream.async.transfer %0 : !stream.resource<external>{%c256} -> !stream.resource<*>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %3 = stream.async.transfer %2 : !stream.resource<external>{%c512} -> !stream.resource<*>{%c512}
    %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%1[%c0 to %c256 for %c256], %3[%c0 to %c512 for %c512]) : (!stream.resource<*>{%c256}, !stream.resource<*>{%c512}) -> !stream.resource<*>{%c512}
    %5 = stream.async.transfer %4 : !stream.resource<*>{%c512} -> !stream.resource<external>{%c512}
    %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %6 : !hal.buffer_view
  }
}


// -----// IR Dump Before MaterializeCopyOnWritePass (iree-stream-materialize-copy-on-write) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  %1 = stream.async.transfer %0 : !stream.resource<external>{%c256} -> !stream.resource<*>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %3 = stream.async.transfer %2 : !stream.resource<external>{%c512} -> !stream.resource<*>{%c512}
  %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%1[%c0 to %c256 for %c256], %3[%c0 to %c512 for %c512]) : (!stream.resource<*>{%c256}, !stream.resource<*>{%c512}) -> !stream.resource<*>{%c512}
  %5 = stream.async.transfer %4 : !stream.resource<*>{%c512} -> !stream.resource<external>{%c512}
  %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %6 : !hal.buffer_view
}

// -----// IR Dump Before ElideAsyncCopiesPass (iree-stream-elide-async-copies) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    %1 = stream.async.transfer %0 : !stream.resource<external>{%c256} -> !stream.resource<*>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %3 = stream.async.transfer %2 : !stream.resource<external>{%c512} -> !stream.resource<*>{%c512}
    %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%1[%c0 to %c256 for %c256], %3[%c0 to %c512 for %c512]) : (!stream.resource<*>{%c256}, !stream.resource<*>{%c512}) -> !stream.resource<*>{%c512}
    %5 = stream.async.transfer %4 : !stream.resource<*>{%c512} -> !stream.resource<external>{%c512}
    %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %6 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  %1 = stream.async.transfer %0 : !stream.resource<external>{%c256} -> !stream.resource<*>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %3 = stream.async.transfer %2 : !stream.resource<external>{%c512} -> !stream.resource<*>{%c512}
  %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%1[%c0 to %c256 for %c256], %3[%c0 to %c512 for %c512]) : (!stream.resource<*>{%c256}, !stream.resource<*>{%c512}) -> !stream.resource<*>{%c512}
  %5 = stream.async.transfer %4 : !stream.resource<*>{%c512} -> !stream.resource<external>{%c512}
  %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %6 : !hal.buffer_view
}

// -----// IR Dump Before EmplaceAllocationsPass (iree-stream-emplace-allocations) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  %1 = stream.async.transfer %0 : !stream.resource<external>{%c256} -> !stream.resource<*>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %3 = stream.async.transfer %2 : !stream.resource<external>{%c512} -> !stream.resource<*>{%c512}
  %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%1[%c0 to %c256 for %c256], %3[%c0 to %c512 for %c512]) : (!stream.resource<*>{%c256}, !stream.resource<*>{%c512}) -> !stream.resource<*>{%c512}
  %5 = stream.async.transfer %4 : !stream.resource<*>{%c512} -> !stream.resource<external>{%c512}
  %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %6 : !hal.buffer_view
}

// -----// IR Dump Before RefineUsagePass (iree-stream-refine-usage) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    %1 = stream.async.transfer %0 : !stream.resource<external>{%c256} -> !stream.resource<*>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %2 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %3 = stream.async.transfer %2 : !stream.resource<external>{%c512} -> !stream.resource<*>{%c512}
    %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%1[%c0 to %c256 for %c256], %3[%c0 to %c512 for %c512]) : (!stream.resource<*>{%c256}, !stream.resource<*>{%c512}) -> !stream.resource<*>{%c512}
    %5 = stream.async.transfer %4 : !stream.resource<*>{%c512} -> !stream.resource<external>{%c512}
    %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %6 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %2 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0[%c0 to %c256 for %c256], %1[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
  %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %2 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0[%c0 to %c256 for %c256], %1[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
  %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %2 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0[%c0 to %c256 for %c256], %1[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
  %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %2 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0[%c0 to %c256 for %c256], %1[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
    %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %2 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0[%c0 to %c256 for %c256], %1[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
    %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %2 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0[%c0 to %c256 for %c256], %1[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
    %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %2 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0[%c0 to %c256 for %c256], %1[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
    %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before VerifyAsyncAccessRangesPass (iree-stream-verify-async-access-ranges) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %2 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0[%c0 to %c256 for %c256], %1[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
    %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before ScheduleExecutionPass (iree-stream-schedule-execution) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %2 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%0[%c0 to %c256 for %c256], %1[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
  %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before ScheduleConcurrencyPass (iree-stream-schedule-concurrency) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512} {
    %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%arg2[%c0 to %c256 for %c256], %arg3[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
    stream.yield %4 : !stream.resource<external>{%c512}
  } => !stream.timepoint
  %2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c512}
  %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before PropagateTimepointsPass (iree-stream-propagate-timepoints) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512} {
      %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%arg2[%c0 to %c256 for %c256], %arg3[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
      stream.yield %4 : !stream.resource<external>{%c512}
    } => !stream.timepoint
    %2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c512}
    %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before MaterializeBuiltinsPass (iree-stream-materialize-builtins) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %2 = stream.timepoint.immediate => !stream.timepoint
    %3 = stream.timepoint.immediate => !stream.timepoint
    %4 = stream.timepoint.join max(%2, %3) => !stream.timepoint
    %results, %result_timepoint = stream.async.execute await(%4) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512} {
      %7 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%arg2[%c0 to %c256 for %c256], %arg3[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
      stream.yield %7 : !stream.resource<external>{%c512}
    } => !stream.timepoint
    %5 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c512}
    %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %6 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %2 = stream.timepoint.immediate => !stream.timepoint
  %3 = stream.timepoint.immediate => !stream.timepoint
  %4 = stream.timepoint.join max(%2, %3) => !stream.timepoint
  %results, %result_timepoint = stream.async.execute await(%4) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512} {
    %7 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%arg2[%c0 to %c256 for %c256], %arg3[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
    stream.yield %7 : !stream.resource<external>{%c512}
  } => !stream.timepoint
  %5 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c512}
  %6 = stream.tensor.export %5 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %6 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512} {
    %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%arg2[%c0 to %c256 for %c256], %arg3[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
    stream.yield %4 : !stream.resource<external>{%c512}
  } => !stream.timepoint
  %2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c512}
  %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512} {
    %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%arg2[%c0 to %c256 for %c256], %arg3[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
    stream.yield %4 : !stream.resource<external>{%c512}
  } => !stream.timepoint
  %2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c512}
  %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %3 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512} {
      %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%arg2[%c0 to %c256 for %c256], %arg3[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
      stream.yield %4 : !stream.resource<external>{%c512}
    } => !stream.timepoint
    %2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c512}
    %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512} {
      %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%arg2[%c0 to %c256 for %c256], %arg3[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
      stream.yield %4 : !stream.resource<external>{%c512}
    } => !stream.timepoint
    %2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c512}
    %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512} {
      %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%arg2[%c0 to %c256 for %c256], %arg3[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
      stream.yield %4 : !stream.resource<external>{%c512}
    } => !stream.timepoint
    %2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c512}
    %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512} {
      %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%arg2[%c0 to %c256 for %c256], %arg3[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
      stream.yield %4 : !stream.resource<external>{%c512}
    } => !stream.timepoint
    %2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c512}
    %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before VerifyLoweringToAsyncPass (iree-stream-verify-lowering-to-async) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512} {
      %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%arg2[%c0 to %c256 for %c256], %arg3[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
      stream.yield %4 : !stream.resource<external>{%c512}
    } => !stream.timepoint
    %2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c512}
    %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before ScheduleAllocationPass (iree-stream-schedule-allocation) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %results, %result_timepoint = stream.async.execute with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512} {
      %4 = stream.async.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%arg2[%c0 to %c256 for %c256], %arg3[%c0 to %c512 for %c512]) : (!stream.resource<external>{%c256}, !stream.resource<external>{%c512}) -> !stream.resource<external>{%c512}
      stream.yield %4 : !stream.resource<external>{%c512}
    } => !stream.timepoint
    %2 = stream.timepoint.await %result_timepoint => %results : !stream.resource<external>{%c512}
    %3 = stream.tensor.export %2 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %3 : !hal.buffer_view
  }
}


// -----// IR Dump Before PackConstantsPass (iree-stream-pack-constants) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %c0_0 = arith.constant 0 : index
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0_0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before LayoutSlicesPass (iree-stream-layout-slices) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %c0_0 = arith.constant 0 : index
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0_0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before PropagateSubranges (iree-util-propagate-subranges) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %c0_0 = arith.constant 0 : index
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0_0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %c0_0 = arith.constant 0 : index
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0_0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before VerifyLoweringToCmdPass (iree-stream-verify-lowering-to-cmd) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before SCFToControlFlow (convert-scf-to-cf) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before FixedPointIterator (iree-util-fixed-point-iterator) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before ElideTimepointsPass (iree-stream-elide-timepoints) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie], iree.fixedpoint.iteration = 0 : index} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseDispatchBindingsPass (iree-stream-fuse-dispatch-bindings) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before AnnotateDispatchArgumentsPass (iree-stream-annotate-dispatch-arguments) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding, %arg1: !stream.binding, %arg2: !stream.binding, %arg3: index, %arg4: index, %arg5: index) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%arg3] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%arg4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%arg5] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %c0_0 = arith.constant 0 : index
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%c0, %c0, %c0 : index, index, index) {
        ro %arg2[%c0_0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0_0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0_0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before PackDispatchOperandsPass (iree-stream-pack-dispatch-operands) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: index {stream.values = [0 : index]}, %arg4: index {stream.values = [0 : index]}, %arg5: index {stream.values = [0 : index]}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%arg3] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%arg4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%arg5] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %c0_0 = arith.constant 0 : index
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%c0, %c0, %c0 : index, index, index) {
        ro %arg2[%c0_0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0_0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0_0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %c0_0 = arith.constant 0 : index
  %c0_i64 = arith.constant 0 : i64
  %c0_i32 = arith.constant 0 : i32
  %c32_i64 = arith.constant 32 : i64
  %c0_i64_1 = arith.constant 0 : i64
  %c0_i32_2 = arith.constant 0 : i32
  %c0_i64_3 = arith.constant 0 : i64
  %c0_i32_4 = arith.constant 0 : i32
  %c32_i64_5 = arith.constant 32 : i64
  %c0_i64_6 = arith.constant 0 : i64
  %c0_i32_7 = arith.constant 0 : i32
  %c0_i64_8 = arith.constant 0 : i64
  %c0_i32_9 = arith.constant 0 : i32
  %c32_i64_10 = arith.constant 32 : i64
  %c0_i64_11 = arith.constant 0 : i64
  %c0_i32_12 = arith.constant 0 : i32
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%c0_i32, %c0_i32_2, %c0_i32_4, %c0_i32_7, %c0_i32_9, %c0_i32_12 : i32, i32, i32, i32, i32, i32) {
      ro %arg2[%c0_0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0_0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0_0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
        %0 = arith.extui %arg3 : i32 to i64
        %1 = arith.extui %arg4 : i32 to i64
        %c32_i64 = arith.constant 32 : i64
        %2 = arith.shli %1, %c32_i64 : i64
        %3 = arith.ori %0, %2 : i64
        %4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
        %5 = arith.extui %arg5 : i32 to i64
        %6 = arith.extui %arg6 : i32 to i64
        %c32_i64_0 = arith.constant 32 : i64
        %7 = arith.shli %6, %c32_i64_0 : i64
        %8 = arith.ori %5, %7 : i64
        %9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
        %10 = arith.extui %arg7 : i32 to i64
        %11 = arith.extui %arg8 : i32 to i64
        %c32_i64_1 = arith.constant 32 : i64
        %12 = arith.shli %11, %c32_i64_1 : i64
        %13 = arith.ori %10, %12 : i64
        %14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %20 = tensor.empty() : tensor<8x16xi32>
        %21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %22 = linalg.matmul ins(%18, %19 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%21 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
        %c0_i32 = arith.constant 0 : i32
        %c32_i64 = arith.constant 32 : i64
        %0 = arith.extui %arg3 : i32 to i64
        %1 = arith.extui %arg4 : i32 to i64
        %2 = arith.shli %1, %c32_i64 : i64
        %3 = arith.ori %0, %2 : i64
        %4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
        %5 = arith.extui %arg5 : i32 to i64
        %6 = arith.extui %arg6 : i32 to i64
        %7 = arith.shli %6, %c32_i64 : i64
        %8 = arith.ori %5, %7 : i64
        %9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
        %10 = arith.extui %arg7 : i32 to i64
        %11 = arith.extui %arg8 : i32 to i64
        %12 = arith.shli %11, %c32_i64 : i64
        %13 = arith.ori %10, %12 : i64
        %14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
        %15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %20 = tensor.empty() : tensor<8x16xi32>
        %21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %22 = linalg.matmul ins(%18, %19 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%21 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
        %c0_i32 = arith.constant 0 : i32
        %c32_i64 = arith.constant 32 : i64
        %0 = arith.extui %arg3 : i32 to i64
        %1 = arith.extui %arg4 : i32 to i64
        %2 = arith.shli %1, %c32_i64 : i64
        %3 = arith.ori %0, %2 : i64
        %4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
        %5 = arith.extui %arg5 : i32 to i64
        %6 = arith.extui %arg6 : i32 to i64
        %7 = arith.shli %6, %c32_i64 : i64
        %8 = arith.ori %5, %7 : i64
        %9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
        %10 = arith.extui %arg7 : i32 to i64
        %11 = arith.extui %arg8 : i32 to i64
        %12 = arith.shli %11, %c32_i64 : i64
        %13 = arith.ori %10, %12 : i64
        %14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
        %15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %20 = tensor.empty() : tensor<8x16xi32>
        %21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %22 = linalg.matmul ins(%18, %19 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%21 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
        %c0_i32 = arith.constant 0 : i32
        %c32_i64 = arith.constant 32 : i64
        %0 = arith.extui %arg3 : i32 to i64
        %1 = arith.extui %arg4 : i32 to i64
        %2 = arith.shli %1, %c32_i64 : i64
        %3 = arith.ori %0, %2 : i64
        %4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
        %5 = arith.extui %arg5 : i32 to i64
        %6 = arith.extui %arg6 : i32 to i64
        %7 = arith.shli %6, %c32_i64 : i64
        %8 = arith.ori %5, %7 : i64
        %9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
        %10 = arith.extui %arg7 : i32 to i64
        %11 = arith.extui %arg8 : i32 to i64
        %12 = arith.shli %11, %c32_i64 : i64
        %13 = arith.ori %10, %12 : i64
        %14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
        %15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %20 = tensor.empty() : tensor<8x16xi32>
        %21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %22 = linalg.matmul ins(%18, %19 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%21 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldUniformOperandsPass (iree-stream-fold-uniform-operands) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}, %arg3: i32, %arg4: i32, %arg5: i32, %arg6: i32, %arg7: i32, %arg8: i32) {
        %c0_i32 = arith.constant 0 : i32
        %c32_i64 = arith.constant 32 : i64
        %0 = arith.extui %arg3 : i32 to i64
        %1 = arith.extui %arg4 : i32 to i64
        %2 = arith.shli %1, %c32_i64 : i64
        %3 = arith.ori %0, %2 : i64
        %4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
        %5 = arith.extui %arg5 : i32 to i64
        %6 = arith.extui %arg6 : i32 to i64
        %7 = arith.shli %6, %c32_i64 : i64
        %8 = arith.ori %5, %7 : i64
        %9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
        %10 = arith.extui %arg7 : i32 to i64
        %11 = arith.extui %arg8 : i32 to i64
        %12 = arith.shli %11, %c32_i64 : i64
        %13 = arith.ori %10, %12 : i64
        %14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
        %15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %20 = tensor.empty() : tensor<8x16xi32>
        %21 = linalg.fill ins(%c0_i32 : i32) outs(%20 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %22 = linalg.matmul ins(%18, %19 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%21 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c0_i32 = arith.constant 0 : i32
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32(%c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32, %c0_i32 : i32, i32, i32, i32, i32, i32) {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c0_i32 = arith.constant 0 : i32
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0_i32_0 = arith.constant 0 : i32
        %c32_i64 = arith.constant 32 : i64
        %0 = arith.extui %c0_i32 : i32 to i64
        %1 = arith.extui %c0_i32 : i32 to i64
        %2 = arith.shli %1, %c32_i64 : i64
        %3 = arith.ori %0, %2 : i64
        %4 = arith.index_castui %3 {stream.values = [0 : index]} : i64 to index
        %5 = arith.extui %c0_i32 : i32 to i64
        %6 = arith.extui %c0_i32 : i32 to i64
        %7 = arith.shli %6, %c32_i64 : i64
        %8 = arith.ori %5, %7 : i64
        %9 = arith.index_castui %8 {stream.values = [0 : index]} : i64 to index
        %10 = arith.extui %c0_i32 : i32 to i64
        %11 = arith.extui %c0_i32 : i32 to i64
        %12 = arith.shli %11, %c32_i64 : i64
        %13 = arith.ori %10, %12 : i64
        %14 = arith.index_castui %13 {stream.values = [0 : index]} : i64 to index
        %15 = stream.binding.subspan %arg0[%4] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %16 = stream.binding.subspan %arg1[%9] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %17 = stream.binding.subspan %arg2[%14] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %18 = flow.dispatch.tensor.load %15, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %19 = flow.dispatch.tensor.load %16, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %20 = tensor.empty() : tensor<8x16xi32>
        %21 = linalg.fill ins(%c0_i32_0 : i32) outs(%20 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %22 = linalg.matmul ins(%18, %19 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%21 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %22, %17, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before IPO (iree-util-ipo) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before SymbolDCE (symbol-dce) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before CSE (cse) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before CSE (cse) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before SimplifyGlobalAccesses (iree-util-simplify-global-accesses) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    }
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before ApplyPatterns (iree-util-apply-patterns) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FoldGlobals (iree-util-fold-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before FuseGlobals (iree-util-fuse-globals) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before AssignTargetDevicesPass (iree-hal-assign-target-devices) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before VerifyTargetEnvironmentPass (iree-hal-verify-target-environment) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before MaterializeInterfacesPass (iree-hal-materialize-interfaces) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  stream.executable private @matmul_static_dispatch_0 {
    stream.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 workgroups() -> (index, index, index) {
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      stream.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32(%arg0: !stream.binding {stream.alignment = 64 : index}, %arg1: !stream.binding {stream.alignment = 64 : index}, %arg2: !stream.binding {stream.alignment = 64 : index}) {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = stream.binding.subspan %arg0[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = stream.binding.subspan %arg1[%c0] : !stream.binding -> !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = stream.binding.subspan %arg2[%c0] : !stream.binding -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      }
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before DumpExecutableSourcesPass (iree-hal-dump-executable-sources) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  hal.executable private @matmul_static_dispatch_0 {
    hal.executable.variant public @amdaie_xclbin_fb target(#executable_target_amdaie_xclbin_fb) {
      hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#pipeline_layout) {
      ^bb0(%arg0: !hal.device):
        %x, %y, %z = flow.dispatch.workgroup_count_from_slice
        hal.return %x, %y, %z : index, index, index
      }
      builtin.module {
        func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
          %c0_i32 = arith.constant 0 : i32
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
          %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
          %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
          %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
          %5 = tensor.empty() : tensor<8x16xi32>
          %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
          %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
          flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
          return
        }
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@amdaie_xclbin_fb::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>, #hal.interface.binding<0, 2>]}
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before ConfigureExecutablesPass (iree-hal-configure-executables) //----- //
hal.executable private @matmul_static_dispatch_0 {
  hal.executable.variant public @amdaie_xclbin_fb target(<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>) {
    hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>) {
    ^bb0(%arg0: !hal.device):
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      hal.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
}

// -----// IR Dump Before ConfigureTargetExecutableVariantsPass (iree-hal-configure-target-executable-variants) //----- //
hal.executable.variant public @amdaie_xclbin_fb target(<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>) {
  hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>) {
  ^bb0(%arg0: !hal.device):
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    hal.return %x, %y, %z : index, index, index
  }
  builtin.module {
    func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
      %c0_i32 = arith.constant 0 : i32
      %c0 = arith.constant 0 : index
      %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
      %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
      %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
      %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
      %5 = tensor.empty() : tensor<8x16xi32>
      %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
      flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      return
    }
  }
}

// -----// IR Dump Before CPUMaterializeUpperBoundTileSize (iree-codegen-cpu-materialize-upper-bound-tile-size) //----- //
func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
  %c512 = arith.constant 512 : index
  %c256 = arith.constant 256 : index
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %c8 = arith.constant 8 : index
  %element_type_i32 = hal.element_type<i32> : i32
  %dense_row_major = hal.encoding_type<dense_row_major> : i32
  hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
  %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
  hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
  %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
  %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
  %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
    stream.cmd.dispatch @matmul_static_dispatch_0::@amdaie_xclbin_fb::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
      ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
      ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
      wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
    } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>, #hal.interface.binding<0, 2>]}
  } => !stream.timepoint
  %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
  %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
  return %4 : !hal.buffer_view
}

// -----// IR Dump Before DumpExecutableSourcesPass (iree-hal-dump-executable-sources) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  hal.executable private @matmul_static_dispatch_0 {
    hal.executable.variant public @amdaie_xclbin_fb target(#executable_target_amdaie_xclbin_fb) {
      hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#pipeline_layout) {
      ^bb0(%arg0: !hal.device):
        %x, %y, %z = flow.dispatch.workgroup_count_from_slice
        hal.return %x, %y, %z : index, index, index
      }
      builtin.module {
        func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
          %c0_i32 = arith.constant 0 : i32
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
          %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
          %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
          %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
          %5 = tensor.empty() : tensor<8x16xi32>
          %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
          %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
          flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
          return
        }
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@amdaie_xclbin_fb::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>, #hal.interface.binding<0, 2>]}
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before DumpExecutableBenchmarksPass (iree-hal-dump-executable-benchmarks) //----- //
#executable_target_amdaie_xclbin_fb = #hal.executable.target<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>
#pipeline_layout = #hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>
#device_target_amd_aie = #hal.device.target<"amd-aie", {executable_targets = [#executable_target_amdaie_xclbin_fb], legacy_sync}>
module attributes {hal.device.targets = [#device_target_amd_aie]} {
  hal.executable private @matmul_static_dispatch_0 {
    hal.executable.variant public @amdaie_xclbin_fb target(#executable_target_amdaie_xclbin_fb) {
      hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#pipeline_layout) {
      ^bb0(%arg0: !hal.device):
        %x, %y, %z = flow.dispatch.workgroup_count_from_slice
        hal.return %x, %y, %z : index, index, index
      }
      builtin.module {
        func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
          %c0_i32 = arith.constant 0 : i32
          %c0 = arith.constant 0 : index
          %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
          %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
          %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
          %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
          %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
          %5 = tensor.empty() : tensor<8x16xi32>
          %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
          %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
          flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
          return
        }
      }
    }
  }
  func.func @matmul_static(%arg0: !hal.buffer_view, %arg1: !hal.buffer_view) -> !hal.buffer_view attributes {iree.abi.stub, iree.reflection = {iree.abi.declaration = "sync func @matmul_static(%input0: tensor<8x8xi32>, %input1: tensor<8x16xi32>) -> (%output0: tensor<8x16xi32>)"}} {
    %c512 = arith.constant 512 : index
    %c256 = arith.constant 256 : index
    %c0 = arith.constant 0 : index
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %element_type_i32 = hal.element_type<i32> : i32
    %dense_row_major = hal.encoding_type<dense_row_major> : i32
    hal.buffer_view.assert<%arg0 : !hal.buffer_view> message("input0") shape([%c8, %c8]) type(%element_type_i32) encoding(%dense_row_major)
    %0 = stream.tensor.import %arg0 : !hal.buffer_view -> tensor<8x8xi32> in !stream.resource<external>{%c256}
    hal.buffer_view.assert<%arg1 : !hal.buffer_view> message("input1") shape([%c8, %c16]) type(%element_type_i32) encoding(%dense_row_major)
    %1 = stream.tensor.import %arg1 : !hal.buffer_view -> tensor<8x16xi32> in !stream.resource<external>{%c512}
    %result, %result_timepoint = stream.resource.alloca uninitialized : !stream.resource<external>{%c512} => !stream.timepoint
    %2 = stream.cmd.execute await(%result_timepoint) => with(%0 as %arg2: !stream.resource<external>{%c256}, %1 as %arg3: !stream.resource<external>{%c512}, %result as %arg4: !stream.resource<external>{%c512}) {
      stream.cmd.dispatch @matmul_static_dispatch_0::@amdaie_xclbin_fb::@matmul_static_dispatch_0_matmul_8x16x8_i32 {
        ro %arg2[%c0 for %c256] : !stream.resource<external>{%c256},
        ro %arg3[%c0 for %c512] : !stream.resource<external>{%c512},
        wo %arg4[%c0 for %c512] : !stream.resource<external>{%c512}
      } attributes {hal.interface.bindings = [#hal.interface.binding<0, 0>, #hal.interface.binding<0, 1>, #hal.interface.binding<0, 2>]}
    } => !stream.timepoint
    %3 = stream.timepoint.await %2 => %result : !stream.resource<external>{%c512}
    %4 = stream.tensor.export %3 : tensor<8x16xi32> in !stream.resource<external>{%c512} -> !hal.buffer_view
    return %4 : !hal.buffer_view
  }
}


// -----// IR Dump Before TranslateExecutablesPass (iree-hal-translate-executables) //----- //
hal.executable private @matmul_static_dispatch_0 {
  hal.executable.variant public @amdaie_xclbin_fb target(<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>) {
    hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>) {
    ^bb0(%arg0: !hal.device):
      %x, %y, %z = flow.dispatch.workgroup_count_from_slice
      hal.return %x, %y, %z : index, index, index
    }
    builtin.module {
      func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
        %c0_i32 = arith.constant 0 : i32
        %c0 = arith.constant 0 : index
        %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
        %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
        %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
        %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
        %5 = tensor.empty() : tensor<8x16xi32>
        %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
        %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
        flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
        return
      }
    }
  }
}

// -----// IR Dump Before TranslateTargetExecutableVariantsPass (iree-hal-translate-target-executable-variants) //----- //
hal.executable.variant public @amdaie_xclbin_fb target(<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>) {
  hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>) {
  ^bb0(%arg0: !hal.device):
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    hal.return %x, %y, %z : index, index, index
  }
  builtin.module {
    func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
      %c0_i32 = arith.constant 0 : i32
      %c0 = arith.constant 0 : index
      %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
      %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
      %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
      %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
      %5 = tensor.empty() : tensor<8x16xi32>
      %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
      flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      return
    }
  }
}

// -----// IR Dump Before TypePropagation (iree-codegen-type-propagation) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
  flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before BubbleUpOrdinalOps (iree-codegen-bubble-up-ordinal-ops) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = tensor.empty() : tensor<8x16xi32>
    %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
    flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before BufferizeCopyOnlyDispatches (iree-codegen-bufferize-copy-only-dispatches) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = tensor.empty() : tensor<8x16xi32>
    %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
    flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before DecomposeSoftmax (iree-codegen-decompose-softmax) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
  flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before MaterializeUserConfigs (iree-codegen-materialize-user-configs) //----- //
hal.executable.variant public @amdaie_xclbin_fb target(<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>) {
  hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>) {
  ^bb0(%arg0: !hal.device):
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    hal.return %x, %y, %z : index, index, index
  }
  builtin.module {
    func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
      %c0_i32 = arith.constant 0 : i32
      %c0 = arith.constant 0 : index
      %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
      %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
      %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
      %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
      %5 = tensor.empty() : tensor<8x16xi32>
      %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
      flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      return
    }
  }
}

// -----// IR Dump Before AMDAIELoweringStrategy (iree-amdaie-lowering-strategy) //----- //
hal.executable.variant public @amdaie_xclbin_fb target(<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>) {
  hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>) {
  ^bb0(%arg0: !hal.device):
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    hal.return %x, %y, %z : index, index, index
  }
  builtin.module {
    func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
      %c0_i32 = arith.constant 0 : i32
      %c0 = arith.constant 0 : index
      %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
      %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
      %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
      %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
      %5 = tensor.empty() : tensor<8x16xi32>
      %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %7 = linalg.matmul ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
      flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      return
    }
  }
}

// -----// IR Dump Before AMDAIELowerExecutableTarget (iree-amdaie-lower-executable-target) //----- //
hal.executable.variant public @amdaie_xclbin_fb target(<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>) {
  hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>) attributes {translation_info = #iree_codegen.translation_info<None>} {
  ^bb0(%arg0: !hal.device):
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    hal.return %x, %y, %z : index, index, index
  }
  builtin.module {
    func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
      %c0_i32 = arith.constant 0 : i32
      %c0 = arith.constant 0 : index
      %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
      %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
      %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
      %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
      %5 = tensor.empty() : tensor<8x16xi32>
      %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %7 = linalg.matmul {lowering_config = #iree_codegen.lowering_config<tile_sizes = [[8, 16], [1, 1], [0, 0, 1]]>} ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
      flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
      return
    }
  }
}

// -----// IR Dump Before AMDAIECleanup (iree-amdaie-cleanup) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %7 = linalg.matmul {lowering_config = #iree_codegen.lowering_config<tile_sizes = [[8, 16], [1, 1], [0, 0, 1]]>} ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
  flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before AMDAIETileAndFuse (iree-amdaie-tile-and-fuse) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %7 = linalg.matmul {lowering_config = #iree_codegen.lowering_config<tile_sizes = [[8, 16], [1, 1], [0, 0, 1]]>} ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
  flow.dispatch.tensor.store %7, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before AMDAIECleanup (iree-amdaie-cleanup) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = linalg.fill ins(%c0_i32 : i32) outs(%5 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %7 = linalg.matmul {lowering_config = #iree_codegen.lowering_config<tile_sizes = [[8, 16], [1, 1], [0, 0, 1]]>} ins(%3, %4 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%6 : tensor<8x16xi32>) -> tensor<8x16xi32>
  %8 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
    %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
    %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %9 = linalg.fill ins(%c0_i32 : i32) outs(%extracted_slice_1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %extracted_slice_2 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %10 = linalg.matmul {lowering_config = #iree_codegen.lowering_config<tile_sizes = [[8, 16], [1, 1], [0, 0, 1]]>} ins(%extracted_slice, %extracted_slice_0 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%9 : tensor<8x16xi32>) -> tensor<8x16xi32>
    scf.forall.in_parallel {
      tensor.parallel_insert_slice %10 into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  flow.dispatch.tensor.store %8, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = tensor.empty() : tensor<8x16xi32>
    %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
      %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
      %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %7 = linalg.fill ins(%c0_i32 : i32) outs(%extracted_slice_1 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %8 = linalg.matmul {lowering_config = #iree_codegen.lowering_config<tile_sizes = [[8, 16], [1, 1], [0, 0, 1]]>} ins(%extracted_slice, %extracted_slice_0 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%7 : tensor<8x16xi32>) -> tensor<8x16xi32>
      scf.forall.in_parallel {
        tensor.parallel_insert_slice %8 into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
      }
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before CSE (cse) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = tensor.empty() : tensor<8x16xi32>
    %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
      %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
      %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %7 = linalg.fill ins(%c0_i32 : i32) outs(%extracted_slice_1 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %8 = linalg.matmul {lowering_config = #iree_codegen.lowering_config<tile_sizes = [[8, 16], [1, 1], [0, 0, 1]]>} ins(%extracted_slice, %extracted_slice_0 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%7 : tensor<8x16xi32>) -> tensor<8x16xi32>
      scf.forall.in_parallel {
        tensor.parallel_insert_slice %8 into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
      }
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before AMDAIEPackAndTranspose (iree-amdaie-pack-and-transpose) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
    %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
    %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %7 = linalg.fill ins(%c0_i32 : i32) outs(%extracted_slice_1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %8 = linalg.matmul {lowering_config = #iree_codegen.lowering_config<tile_sizes = [[8, 16], [1, 1], [0, 0, 1]]>} ins(%extracted_slice, %extracted_slice_0 : tensor<8x8xi32>, tensor<8x16xi32>) outs(%7 : tensor<8x16xi32>) -> tensor<8x16xi32>
    scf.forall.in_parallel {
      tensor.parallel_insert_slice %8 into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before AMDAIEBufferizeToAllocation (iree-amdaie-bufferize-to-allocation) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
    %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
    %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %7 = linalg.fill ins(%c0_i32 : i32) outs(%extracted_slice_1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %8 = tensor.empty() : tensor<1x1x8x16xi32>
    %c0_i32_2 = arith.constant 0 : i32
    %pack = tensor.pack %extracted_slice padding_value(%c0_i32_2 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %8 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
    %9 = tensor.empty() : tensor<1x1x16x16xi32>
    %c0_i32_3 = arith.constant 0 : i32
    %10 = tensor.empty() : tensor<1x1x16x16xi32>
    %pack_4 = tensor.pack %extracted_slice_0 padding_value(%c0_i32_3 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %10 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
    %11 = tensor.empty() : tensor<1x1x8x16xi32>
    %pack_5 = tensor.pack %7 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %11 : tensor<8x16xi32> -> tensor<1x1x8x16xi32>
    %12 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack, %pack_4 : tensor<1x1x8x16xi32>, tensor<1x1x16x16xi32>) outs(%pack_5 : tensor<1x1x8x16xi32>) {
    ^bb0(%in: i32, %in_6: i32, %out: i32):
      %13 = arith.muli %in, %in_6 : i32
      %14 = arith.addi %out, %13 : i32
      linalg.yield %14 : i32
    } -> tensor<1x1x8x16xi32>
    %unpack = tensor.unpack %12 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
    scf.forall.in_parallel {
      tensor.parallel_insert_slice %unpack into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before AMDAIETileAndFuse (iree-amdaie-tile-and-fuse) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
    %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
    %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %7 = linalg.fill ins(%c0_i32 : i32) outs(%extracted_slice_1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %8 = tensor.empty() : tensor<1x1x8x16xi32>
    %c0_i32_2 = arith.constant 0 : i32
    %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %9 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %pack = tensor.pack %extracted_slice padding_value(%c0_i32_2 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %9 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
    %10 = tensor.empty() : tensor<1x1x16x16xi32>
    %c0_i32_3 = arith.constant 0 : i32
    %11 = tensor.empty() : tensor<1x1x16x16xi32>
    %alloc_4 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
    %12 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x16x16xi32, 1 : i32>
    %pack_5 = tensor.pack %extracted_slice_0 padding_value(%c0_i32_3 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %12 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
    %13 = tensor.empty() : tensor<1x1x8x16xi32>
    %alloc_6 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %14 = bufferization.to_tensor %alloc_6 restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %pack_7 = tensor.pack %7 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %14 : tensor<8x16xi32> -> tensor<1x1x8x16xi32>
    %15 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack, %pack_5 : tensor<1x1x8x16xi32>, tensor<1x1x16x16xi32>) outs(%pack_7 : tensor<1x1x8x16xi32>) {
    ^bb0(%in: i32, %in_8: i32, %out: i32):
      %16 = arith.muli %in, %in_8 : i32
      %17 = arith.addi %out, %16 : i32
      linalg.yield %17 : i32
    } -> tensor<1x1x8x16xi32>
    %unpack = tensor.unpack %15 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
    memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_4 : memref<1x1x16x16xi32, 1 : i32>
    memref.dealloc %alloc_6 : memref<1x1x8x16xi32, 1 : i32>
    scf.forall.in_parallel {
      tensor.parallel_insert_slice %unpack into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before AMDAIECleanup (iree-amdaie-cleanup) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
    %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
    %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %7 = linalg.fill ins(%c0_i32 : i32) outs(%extracted_slice_1 : tensor<8x16xi32>) -> tensor<8x16xi32>
    %8 = tensor.empty() : tensor<1x1x8x16xi32>
    %c0_i32_2 = arith.constant 0 : i32
    %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %9 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %pack = tensor.pack %extracted_slice padding_value(%c0_i32_2 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %9 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
    %10 = tensor.empty() : tensor<1x1x16x16xi32>
    %c0_i32_3 = arith.constant 0 : i32
    %11 = tensor.empty() : tensor<1x1x16x16xi32>
    %alloc_4 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
    %12 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x16x16xi32, 1 : i32>
    %pack_5 = tensor.pack %extracted_slice_0 padding_value(%c0_i32_3 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %12 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
    %13 = tensor.empty() : tensor<1x1x8x16xi32>
    %alloc_6 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %14 = bufferization.to_tensor %alloc_6 restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %pack_7 = tensor.pack %7 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %14 : tensor<8x16xi32> -> tensor<1x1x8x16xi32>
    %15 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack, %pack_5 : tensor<1x1x8x16xi32>, tensor<1x1x16x16xi32>) outs(%pack_7 : tensor<1x1x8x16xi32>) {
    ^bb0(%in: i32, %in_8: i32, %out: i32):
      %16 = arith.muli %in, %in_8 : i32
      %17 = arith.addi %out, %16 : i32
      linalg.yield %17 : i32
    } -> tensor<1x1x8x16xi32>
    %unpack = tensor.unpack %15 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
    memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_4 : memref<1x1x16x16xi32, 1 : i32>
    memref.dealloc %alloc_6 : memref<1x1x8x16xi32, 1 : i32>
    scf.forall.in_parallel {
      tensor.parallel_insert_slice %unpack into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = tensor.empty() : tensor<8x16xi32>
    %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
      %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
      %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %7 = linalg.fill ins(%c0_i32 : i32) outs(%extracted_slice_1 : tensor<8x16xi32>) -> tensor<8x16xi32>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %8 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %8 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      %9 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
      %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %9 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
      %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %10 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %11 = linalg.fill ins(%c0_i32 : i32) outs(%10 : tensor<1x1x8x16xi32>) -> tensor<1x1x8x16xi32>
      %12 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack, %pack_3 : tensor<1x1x8x16xi32>, tensor<1x1x16x16xi32>) outs(%11 : tensor<1x1x8x16xi32>) {
      ^bb0(%in: i32, %in_5: i32, %out: i32):
        %13 = arith.muli %in, %in_5 : i32
        %14 = arith.addi %out, %13 : i32
        linalg.yield %14 : i32
      } -> tensor<1x1x8x16xi32>
      %unpack = tensor.unpack %12 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
      scf.forall.in_parallel {
        tensor.parallel_insert_slice %unpack into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
      }
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before CSE (cse) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = tensor.empty() : tensor<8x16xi32>
    %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
      %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
      %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
      %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
      %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %10 = linalg.fill ins(%c0_i32 : i32) outs(%9 : tensor<1x1x8x16xi32>) -> tensor<1x1x8x16xi32>
      %11 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack, %pack_3 : tensor<1x1x8x16xi32>, tensor<1x1x16x16xi32>) outs(%10 : tensor<1x1x8x16xi32>) {
      ^bb0(%in: i32, %in_5: i32, %out: i32):
        %12 = arith.muli %in, %in_5 : i32
        %13 = arith.addi %out, %12 : i32
        linalg.yield %13 : i32
      } -> tensor<1x1x8x16xi32>
      %unpack = tensor.unpack %11 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
      scf.forall.in_parallel {
        tensor.parallel_insert_slice %unpack into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
      }
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before AMDAIEFuseFillIntoForall (iree-amdaie-fuse-fill-into-forall) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
    %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
    %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
    %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
    %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
    %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
    %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %10 = linalg.fill ins(%c0_i32 : i32) outs(%9 : tensor<1x1x8x16xi32>) -> tensor<1x1x8x16xi32>
    %11 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack, %pack_3 : tensor<1x1x8x16xi32>, tensor<1x1x16x16xi32>) outs(%10 : tensor<1x1x8x16xi32>) {
    ^bb0(%in: i32, %in_5: i32, %out: i32):
      %12 = arith.muli %in, %in_5 : i32
      %13 = arith.addi %out, %12 : i32
      linalg.yield %13 : i32
    } -> tensor<1x1x8x16xi32>
    %unpack = tensor.unpack %11 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
    memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
    memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
    scf.forall.in_parallel {
      tensor.parallel_insert_slice %unpack into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before AMDAIECleanup (iree-amdaie-cleanup) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
    %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
    %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
    %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
    %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
    %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
    %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %10 = linalg.fill ins(%c0_i32 : i32) outs(%9 : tensor<1x1x8x16xi32>) -> tensor<1x1x8x16xi32>
    %11 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack, %pack_3 : tensor<1x1x8x16xi32>, tensor<1x1x16x16xi32>) outs(%10 : tensor<1x1x8x16xi32>) {
    ^bb0(%in: i32, %in_5: i32, %out: i32):
      %12 = arith.muli %in, %in_5 : i32
      %13 = arith.addi %out, %12 : i32
      linalg.yield %13 : i32
    } -> tensor<1x1x8x16xi32>
    %unpack = tensor.unpack %11 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
    memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
    memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
    scf.forall.in_parallel {
      tensor.parallel_insert_slice %unpack into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = tensor.empty() : tensor<8x16xi32>
    %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
      %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
      %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
      %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
      %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %10 = linalg.fill ins(%c0_i32 : i32) outs(%9 : tensor<1x1x8x16xi32>) -> tensor<1x1x8x16xi32>
      %11 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack, %pack_3 : tensor<1x1x8x16xi32>, tensor<1x1x16x16xi32>) outs(%10 : tensor<1x1x8x16xi32>) {
      ^bb0(%in: i32, %in_5: i32, %out: i32):
        %12 = arith.muli %in, %in_5 : i32
        %13 = arith.addi %out, %12 : i32
        linalg.yield %13 : i32
      } -> tensor<1x1x8x16xi32>
      %unpack = tensor.unpack %11 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
      scf.forall.in_parallel {
        tensor.parallel_insert_slice %unpack into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
      }
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before CSE (cse) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = tensor.empty() : tensor<8x16xi32>
    %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
      %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
      %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
      %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
      %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %10 = linalg.fill ins(%c0_i32 : i32) outs(%9 : tensor<1x1x8x16xi32>) -> tensor<1x1x8x16xi32>
      %11 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack, %pack_3 : tensor<1x1x8x16xi32>, tensor<1x1x16x16xi32>) outs(%10 : tensor<1x1x8x16xi32>) {
      ^bb0(%in: i32, %in_5: i32, %out: i32):
        %12 = arith.muli %in, %in_5 : i32
        %13 = arith.addi %out, %12 : i32
        linalg.yield %13 : i32
      } -> tensor<1x1x8x16xi32>
      %unpack = tensor.unpack %11 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
      scf.forall.in_parallel {
        tensor.parallel_insert_slice %unpack into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
      }
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before AMDAIEPackAndTranspose (iree-amdaie-pack-and-transpose) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
    %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
    %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
    %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
    %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
    %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
    %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %10 = linalg.fill ins(%c0_i32 : i32) outs(%9 : tensor<1x1x8x16xi32>) -> tensor<1x1x8x16xi32>
    %11 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)>, affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack, %pack_3 : tensor<1x1x8x16xi32>, tensor<1x1x16x16xi32>) outs(%10 : tensor<1x1x8x16xi32>) {
    ^bb0(%in: i32, %in_5: i32, %out: i32):
      %12 = arith.muli %in, %in_5 : i32
      %13 = arith.addi %out, %12 : i32
      linalg.yield %13 : i32
    } -> tensor<1x1x8x16xi32>
    %unpack = tensor.unpack %11 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
    memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
    memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
    scf.forall.in_parallel {
      tensor.parallel_insert_slice %unpack into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before AMDAIEBufferizeToAllocation (iree-amdaie-bufferize-to-allocation) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
    %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
    %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
    %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
    %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
    %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
    %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %10 = linalg.fill ins(%c0_i32 : i32) outs(%9 : tensor<1x1x8x16xi32>) -> tensor<1x1x8x16xi32>
    %11 = tensor.empty() : tensor<1x1x2x2x4x8xi32>
    %12 = tensor.empty() : tensor<1x1x2x2x4x8xi32>
    %pack_5 = tensor.pack %pack outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %12 : tensor<1x1x8x16xi32> -> tensor<1x1x2x2x4x8xi32>
    %13 = tensor.empty() : tensor<1x1x2x2x8x8xi32>
    %14 = tensor.empty() : tensor<1x1x2x2x8x8xi32>
    %pack_6 = tensor.pack %pack_3 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %14 : tensor<1x1x16x16xi32> -> tensor<1x1x2x2x8x8xi32>
    %15 = tensor.empty() : tensor<1x1x2x2x4x8xi32>
    %16 = tensor.empty() : tensor<1x1x2x2x4x8xi32>
    %pack_7 = tensor.pack %10 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %16 : tensor<1x1x8x16xi32> -> tensor<1x1x2x2x4x8xi32>
    %17 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack_5, %pack_6 : tensor<1x1x2x2x4x8xi32>, tensor<1x1x2x2x8x8xi32>) outs(%pack_7 : tensor<1x1x2x2x4x8xi32>) {
    ^bb0(%in: i32, %in_9: i32, %out: i32):
      %18 = arith.muli %in, %in_9 : i32
      %19 = arith.addi %out, %18 : i32
      linalg.yield %19 : i32
    } -> tensor<1x1x2x2x4x8xi32>
    %unpack = tensor.unpack %17 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %10 : tensor<1x1x2x2x4x8xi32> -> tensor<1x1x8x16xi32>
    %unpack_8 = tensor.unpack %unpack inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
    memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
    memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
    scf.forall.in_parallel {
      tensor.parallel_insert_slice %unpack_8 into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before AMDAIETileAndFuse (iree-amdaie-tile-and-fuse) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
    %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
    %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
    %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
    %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
    %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
    %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %10 = linalg.fill ins(%c0_i32 : i32) outs(%9 : tensor<1x1x8x16xi32>) -> tensor<1x1x8x16xi32>
    %11 = tensor.empty() : tensor<1x1x2x2x4x8xi32>
    %12 = tensor.empty() : tensor<1x1x2x2x4x8xi32>
    %alloc_5 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
    %13 = bufferization.to_tensor %alloc_5 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
    %pack_6 = tensor.pack %pack outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %13 : tensor<1x1x8x16xi32> -> tensor<1x1x2x2x4x8xi32>
    %14 = tensor.empty() : tensor<1x1x2x2x8x8xi32>
    %15 = tensor.empty() : tensor<1x1x2x2x8x8xi32>
    %alloc_7 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
    %16 = bufferization.to_tensor %alloc_7 restrict writable : memref<1x1x2x2x8x8xi32, 2 : i32>
    %pack_8 = tensor.pack %pack_3 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %16 : tensor<1x1x16x16xi32> -> tensor<1x1x2x2x8x8xi32>
    %17 = tensor.empty() : tensor<1x1x2x2x4x8xi32>
    %18 = tensor.empty() : tensor<1x1x2x2x4x8xi32>
    %alloc_9 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
    %19 = bufferization.to_tensor %alloc_9 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
    %pack_10 = tensor.pack %10 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %19 : tensor<1x1x8x16xi32> -> tensor<1x1x2x2x4x8xi32>
    %20 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack_6, %pack_8 : tensor<1x1x2x2x4x8xi32>, tensor<1x1x2x2x8x8xi32>) outs(%pack_10 : tensor<1x1x2x2x4x8xi32>) {
    ^bb0(%in: i32, %in_12: i32, %out: i32):
      %21 = arith.muli %in, %in_12 : i32
      %22 = arith.addi %out, %21 : i32
      linalg.yield %22 : i32
    } -> tensor<1x1x2x2x4x8xi32>
    %unpack = tensor.unpack %20 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %10 : tensor<1x1x2x2x4x8xi32> -> tensor<1x1x8x16xi32>
    %unpack_11 = tensor.unpack %unpack inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
    memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
    memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>
    memref.dealloc %alloc_7 : memref<1x1x2x2x8x8xi32, 2 : i32>
    memref.dealloc %alloc_9 : memref<1x1x2x2x4x8xi32, 2 : i32>
    scf.forall.in_parallel {
      tensor.parallel_insert_slice %unpack_11 into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before AMDAIECleanup (iree-amdaie-cleanup) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
  %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
  %5 = tensor.empty() : tensor<8x16xi32>
  %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
    %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
    %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
    %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
    %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
    %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
    %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
    %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
    %10 = linalg.fill ins(%c0_i32 : i32) outs(%9 : tensor<1x1x8x16xi32>) -> tensor<1x1x8x16xi32>
    %11 = tensor.empty() : tensor<1x1x2x2x4x8xi32>
    %12 = tensor.empty() : tensor<1x1x2x2x4x8xi32>
    %alloc_5 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
    %13 = bufferization.to_tensor %alloc_5 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
    %pack_6 = tensor.pack %pack outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %13 : tensor<1x1x8x16xi32> -> tensor<1x1x2x2x4x8xi32>
    %14 = tensor.empty() : tensor<1x1x2x2x8x8xi32>
    %15 = tensor.empty() : tensor<1x1x2x2x8x8xi32>
    %alloc_7 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
    %16 = bufferization.to_tensor %alloc_7 restrict writable : memref<1x1x2x2x8x8xi32, 2 : i32>
    %pack_8 = tensor.pack %pack_3 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %16 : tensor<1x1x16x16xi32> -> tensor<1x1x2x2x8x8xi32>
    %17 = tensor.empty() : tensor<1x1x2x2x4x8xi32>
    %18 = tensor.empty() : tensor<1x1x2x2x4x8xi32>
    %alloc_9 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
    %19 = bufferization.to_tensor %alloc_9 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
    %pack_10 = tensor.pack %10 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %19 : tensor<1x1x8x16xi32> -> tensor<1x1x2x2x4x8xi32>
    %20 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack_6, %pack_8 : tensor<1x1x2x2x4x8xi32>, tensor<1x1x2x2x8x8xi32>) outs(%pack_10 : tensor<1x1x2x2x4x8xi32>) {
    ^bb0(%in: i32, %in_12: i32, %out: i32):
      %21 = arith.muli %in, %in_12 : i32
      %22 = arith.addi %out, %21 : i32
      linalg.yield %22 : i32
    } -> tensor<1x1x2x2x4x8xi32>
    %unpack = tensor.unpack %20 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %10 : tensor<1x1x2x2x4x8xi32> -> tensor<1x1x8x16xi32>
    %unpack_11 = tensor.unpack %unpack inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
    memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
    memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>
    memref.dealloc %alloc_7 : memref<1x1x2x2x8x8xi32, 2 : i32>
    memref.dealloc %alloc_9 : memref<1x1x2x2x4x8xi32, 2 : i32>
    scf.forall.in_parallel {
      tensor.parallel_insert_slice %unpack_11 into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
  return
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = tensor.empty() : tensor<8x16xi32>
    %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
      %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
      %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
      %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
      %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %10 = linalg.fill ins(%c0_i32 : i32) outs(%9 : tensor<1x1x8x16xi32>) -> tensor<1x1x8x16xi32>
      %alloc_5 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      %11 = bufferization.to_tensor %alloc_5 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
      %pack_6 = tensor.pack %pack outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %11 : tensor<1x1x8x16xi32> -> tensor<1x1x2x2x4x8xi32>
      %alloc_7 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
      %12 = bufferization.to_tensor %alloc_7 restrict writable : memref<1x1x2x2x8x8xi32, 2 : i32>
      %pack_8 = tensor.pack %pack_3 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %12 : tensor<1x1x16x16xi32> -> tensor<1x1x2x2x8x8xi32>
      %alloc_9 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      %13 = bufferization.to_tensor %alloc_9 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
      %14 = linalg.fill ins(%c0_i32 : i32) outs(%13 : tensor<1x1x2x2x4x8xi32>) -> tensor<1x1x2x2x4x8xi32>
      %15 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack_6, %pack_8 : tensor<1x1x2x2x4x8xi32>, tensor<1x1x2x2x8x8xi32>) outs(%14 : tensor<1x1x2x2x4x8xi32>) {
      ^bb0(%in: i32, %in_11: i32, %out: i32):
        %16 = arith.muli %in, %in_11 : i32
        %17 = arith.addi %out, %16 : i32
        linalg.yield %17 : i32
      } -> tensor<1x1x2x2x4x8xi32>
      %unpack = tensor.unpack %15 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %10 : tensor<1x1x2x2x4x8xi32> -> tensor<1x1x8x16xi32>
      %unpack_10 = tensor.unpack %unpack inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>
      memref.dealloc %alloc_7 : memref<1x1x2x2x8x8xi32, 2 : i32>
      memref.dealloc %alloc_9 : memref<1x1x2x2x4x8xi32, 2 : i32>
      scf.forall.in_parallel {
        tensor.parallel_insert_slice %unpack_10 into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
      }
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before CSE (cse) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = tensor.empty() : tensor<8x16xi32>
    %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
      %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
      %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
      %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
      %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %alloc_5 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      %10 = bufferization.to_tensor %alloc_5 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
      %pack_6 = tensor.pack %pack outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %10 : tensor<1x1x8x16xi32> -> tensor<1x1x2x2x4x8xi32>
      %alloc_7 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
      %11 = bufferization.to_tensor %alloc_7 restrict writable : memref<1x1x2x2x8x8xi32, 2 : i32>
      %pack_8 = tensor.pack %pack_3 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %11 : tensor<1x1x16x16xi32> -> tensor<1x1x2x2x8x8xi32>
      %alloc_9 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      %12 = bufferization.to_tensor %alloc_9 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
      %13 = linalg.fill ins(%c0_i32 : i32) outs(%12 : tensor<1x1x2x2x4x8xi32>) -> tensor<1x1x2x2x4x8xi32>
      %14 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack_6, %pack_8 : tensor<1x1x2x2x4x8xi32>, tensor<1x1x2x2x8x8xi32>) outs(%13 : tensor<1x1x2x2x4x8xi32>) {
      ^bb0(%in: i32, %in_11: i32, %out: i32):
        %15 = arith.muli %in, %in_11 : i32
        %16 = arith.addi %out, %15 : i32
        linalg.yield %16 : i32
      } -> tensor<1x1x2x2x4x8xi32>
      %unpack = tensor.unpack %14 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %9 : tensor<1x1x2x2x4x8xi32> -> tensor<1x1x8x16xi32>
      %unpack_10 = tensor.unpack %unpack inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>
      memref.dealloc %alloc_7 : memref<1x1x2x2x8x8xi32, 2 : i32>
      memref.dealloc %alloc_9 : memref<1x1x2x2x4x8xi32, 2 : i32>
      scf.forall.in_parallel {
        tensor.parallel_insert_slice %unpack_10 into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
      }
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before EliminateEmptyTensors (iree-eliminate-empty-tensors) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = tensor.empty() : tensor<8x16xi32>
    %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
      %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
      %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
      %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
      %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %alloc_5 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      %10 = bufferization.to_tensor %alloc_5 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
      %pack_6 = tensor.pack %pack outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %10 : tensor<1x1x8x16xi32> -> tensor<1x1x2x2x4x8xi32>
      %alloc_7 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
      %11 = bufferization.to_tensor %alloc_7 restrict writable : memref<1x1x2x2x8x8xi32, 2 : i32>
      %pack_8 = tensor.pack %pack_3 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %11 : tensor<1x1x16x16xi32> -> tensor<1x1x2x2x8x8xi32>
      %alloc_9 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      %12 = bufferization.to_tensor %alloc_9 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
      %13 = linalg.fill ins(%c0_i32 : i32) outs(%12 : tensor<1x1x2x2x4x8xi32>) -> tensor<1x1x2x2x4x8xi32>
      %14 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack_6, %pack_8 : tensor<1x1x2x2x4x8xi32>, tensor<1x1x2x2x8x8xi32>) outs(%13 : tensor<1x1x2x2x4x8xi32>) {
      ^bb0(%in: i32, %in_11: i32, %out: i32):
        %15 = arith.muli %in, %in_11 : i32
        %16 = arith.addi %out, %15 : i32
        linalg.yield %16 : i32
      } -> tensor<1x1x2x2x4x8xi32>
      %unpack = tensor.unpack %14 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %9 : tensor<1x1x2x2x4x8xi32> -> tensor<1x1x8x16xi32>
      %unpack_10 = tensor.unpack %unpack inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>
      memref.dealloc %alloc_7 : memref<1x1x2x2x8x8xi32, 2 : i32>
      memref.dealloc %alloc_9 : memref<1x1x2x2x4x8xi32, 2 : i32>
      scf.forall.in_parallel {
        tensor.parallel_insert_slice %unpack_10 into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
      }
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before EmptyTensorToAllocTensor (empty-tensor-to-alloc-tensor) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = flow.dispatch.tensor.load %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
      %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
      %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
      %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
      %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %alloc_5 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      %10 = bufferization.to_tensor %alloc_5 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
      %pack_6 = tensor.pack %pack outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %10 : tensor<1x1x8x16xi32> -> tensor<1x1x2x2x4x8xi32>
      %alloc_7 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
      %11 = bufferization.to_tensor %alloc_7 restrict writable : memref<1x1x2x2x8x8xi32, 2 : i32>
      %pack_8 = tensor.pack %pack_3 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %11 : tensor<1x1x16x16xi32> -> tensor<1x1x2x2x8x8xi32>
      %alloc_9 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      %12 = bufferization.to_tensor %alloc_9 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
      %13 = linalg.fill ins(%c0_i32 : i32) outs(%12 : tensor<1x1x2x2x4x8xi32>) -> tensor<1x1x2x2x4x8xi32>
      %14 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack_6, %pack_8 : tensor<1x1x2x2x4x8xi32>, tensor<1x1x2x2x8x8xi32>) outs(%13 : tensor<1x1x2x2x4x8xi32>) {
      ^bb0(%in: i32, %in_11: i32, %out: i32):
        %15 = arith.muli %in, %in_11 : i32
        %16 = arith.addi %out, %15 : i32
        linalg.yield %16 : i32
      } -> tensor<1x1x2x2x4x8xi32>
      %unpack = tensor.unpack %14 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %9 : tensor<1x1x2x2x4x8xi32> -> tensor<1x1x8x16xi32>
      %unpack_10 = tensor.unpack %unpack inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>
      memref.dealloc %alloc_7 : memref<1x1x2x2x8x8xi32, 2 : i32>
      memref.dealloc %alloc_9 : memref<1x1x2x2x4x8xi32, 2 : i32>
      scf.forall.in_parallel {
        tensor.parallel_insert_slice %unpack_10 into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
      }
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before IREEComprehensiveBufferize (iree-codegen-iree-comprehensive-bufferize) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x8xi32>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<8x16xi32>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    %3 = flow.dispatch.tensor.load %0, offsets = [0, 0], sizes = [8, 8], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x8xi32>> -> tensor<8x8xi32>
    %4 = flow.dispatch.tensor.load %1, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<readonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %5 = flow.dispatch.tensor.load %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : !flow.dispatch.tensor<writeonly:tensor<8x16xi32>> -> tensor<8x16xi32>
    %6 = scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) shared_outs(%arg2 = %5) -> (tensor<8x16xi32>) {
      %extracted_slice = tensor.extract_slice %3[%arg0, 0] [8, 8] [1, 1] : tensor<8x8xi32> to tensor<8x8xi32>
      %extracted_slice_0 = tensor.extract_slice %4[0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %extracted_slice_1 = tensor.extract_slice %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> to tensor<8x16xi32>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %7 = bufferization.to_tensor %alloc restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %pack = tensor.pack %extracted_slice padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %7 : tensor<8x8xi32> -> tensor<1x1x8x16xi32>
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      %8 = bufferization.to_tensor %alloc_2 restrict writable : memref<1x1x16x16xi32, 1 : i32>
      %pack_3 = tensor.pack %extracted_slice_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %8 : tensor<8x16xi32> -> tensor<1x1x16x16xi32>
      %alloc_4 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %9 = bufferization.to_tensor %alloc_4 restrict writable : memref<1x1x8x16xi32, 1 : i32>
      %alloc_5 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      %10 = bufferization.to_tensor %alloc_5 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
      %pack_6 = tensor.pack %pack outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %10 : tensor<1x1x8x16xi32> -> tensor<1x1x2x2x4x8xi32>
      %alloc_7 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
      %11 = bufferization.to_tensor %alloc_7 restrict writable : memref<1x1x2x2x8x8xi32, 2 : i32>
      %pack_8 = tensor.pack %pack_3 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %11 : tensor<1x1x16x16xi32> -> tensor<1x1x2x2x8x8xi32>
      %alloc_9 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      %12 = bufferization.to_tensor %alloc_9 restrict writable : memref<1x1x2x2x4x8xi32, 2 : i32>
      %13 = linalg.fill ins(%c0_i32 : i32) outs(%12 : tensor<1x1x2x2x4x8xi32>) -> tensor<1x1x2x2x4x8xi32>
      %14 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%pack_6, %pack_8 : tensor<1x1x2x2x4x8xi32>, tensor<1x1x2x2x8x8xi32>) outs(%13 : tensor<1x1x2x2x4x8xi32>) {
      ^bb0(%in: i32, %in_11: i32, %out: i32):
        %15 = arith.muli %in, %in_11 : i32
        %16 = arith.addi %out, %15 : i32
        linalg.yield %16 : i32
      } -> tensor<1x1x2x2x4x8xi32>
      %unpack = tensor.unpack %14 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %9 : tensor<1x1x2x2x4x8xi32> -> tensor<1x1x8x16xi32>
      %unpack_10 = tensor.unpack %unpack inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %extracted_slice_1 : tensor<1x1x8x16xi32> -> tensor<8x16xi32>
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>
      memref.dealloc %alloc_7 : memref<1x1x2x2x8x8xi32, 2 : i32>
      memref.dealloc %alloc_9 : memref<1x1x2x2x4x8xi32, 2 : i32>
      scf.forall.in_parallel {
        tensor.parallel_insert_slice %unpack_10 into %arg2[%arg0, %arg1] [8, 16] [1, 1] : tensor<8x16xi32> into tensor<8x16xi32>
      }
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    flow.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : tensor<8x16xi32> -> !flow.dispatch.tensor<writeonly:tensor<8x16xi32>>
    return
  }
}

// -----// IR Dump Before ResolveShapedTypeResultDims (resolve-shaped-type-result-dims) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
    memref.assume_alignment %0, 64 : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
    memref.assume_alignment %1, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
    memref.assume_alignment %2, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
    scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) {
      %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32, #hal.descriptor_type<storage_buffer>> to memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
      %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
      %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      iree_linalg_ext.pack %subview padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %alloc : (memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x8x16xi32, 1 : i32>)
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      iree_linalg_ext.pack %subview_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %alloc_2 : (memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x16x16xi32, 1 : i32>)
      %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      iree_linalg_ext.pack %alloc outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_4 : (memref<1x1x8x16xi32, 1 : i32> memref<1x1x2x2x4x8xi32, 2 : i32>)
      %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
      iree_linalg_ext.pack %alloc_2 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %alloc_5 : (memref<1x1x16x16xi32, 1 : i32> memref<1x1x2x2x8x8xi32, 2 : i32>)
      %alloc_6 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      linalg.fill ins(%c0_i32 : i32) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>)
      linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
      ^bb0(%in: i32, %in_8: i32, %out: i32):
        %3 = arith.muli %in, %in_8 : i32
        %4 = arith.addi %out, %3 : i32
        linalg.yield %4 : i32
      }
      iree_linalg_ext.unpack %alloc_6 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_3 : (memref<1x1x2x2x4x8xi32, 2 : i32> memref<1x1x8x16xi32, 1 : i32>)
      iree_linalg_ext.unpack %alloc_3 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %subview_1 : (memref<1x1x8x16xi32, 1 : i32> memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>)
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
      memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
      memref.dealloc %alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>
      %subview_7 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
      linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0, d1)>], iterator_types = ["parallel", "parallel"]} ins(%subview_1 : memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>) outs(%subview_7 : memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>) {
      ^bb0(%in: i32, %out: i32):
        linalg.yield %in : i32
      }
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0, d1)>], iterator_types = ["parallel", "parallel"]} ins(%2 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>) outs(%2 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>) {
    ^bb0(%in: i32, %out: i32):
      linalg.yield %in : i32
    }
    return
  }
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
  memref.assume_alignment %0, 64 : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  memref.assume_alignment %1, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  memref.assume_alignment %2, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) {
    %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32, #hal.descriptor_type<storage_buffer>> to memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    iree_linalg_ext.pack %subview padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %alloc : (memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x8x16xi32, 1 : i32>)
    %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
    iree_linalg_ext.pack %subview_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %alloc_2 : (memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x16x16xi32, 1 : i32>)
    %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
    iree_linalg_ext.pack %alloc outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_4 : (memref<1x1x8x16xi32, 1 : i32> memref<1x1x2x2x4x8xi32, 2 : i32>)
    %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
    iree_linalg_ext.pack %alloc_2 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %alloc_5 : (memref<1x1x16x16xi32, 1 : i32> memref<1x1x2x2x8x8xi32, 2 : i32>)
    %alloc_6 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
    linalg.fill ins(%c0_i32 : i32) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>)
    linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
    ^bb0(%in: i32, %in_8: i32, %out: i32):
      %3 = arith.muli %in, %in_8 : i32
      %4 = arith.addi %out, %3 : i32
      linalg.yield %4 : i32
    }
    iree_linalg_ext.unpack %alloc_6 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_3 : (memref<1x1x2x2x4x8xi32, 2 : i32> memref<1x1x8x16xi32, 1 : i32>)
    iree_linalg_ext.unpack %alloc_3 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %subview_1 : (memref<1x1x8x16xi32, 1 : i32> memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>)
    memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
    memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
    memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
    memref.dealloc %alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>
    %subview_7 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0, d1)>], iterator_types = ["parallel", "parallel"]} ins(%subview_1 : memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>) outs(%subview_7 : memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>) {
    ^bb0(%in: i32, %out: i32):
      linalg.yield %in : i32
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0, d1)>], iterator_types = ["parallel", "parallel"]} ins(%2 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>) outs(%2 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>) {
  ^bb0(%in: i32, %out: i32):
    linalg.yield %in : i32
  }
  return
}

// -----// IR Dump Before CSE (cse) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
  memref.assume_alignment %0, 64 : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  memref.assume_alignment %1, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  memref.assume_alignment %2, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) {
    %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32, #hal.descriptor_type<storage_buffer>> to memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    iree_linalg_ext.pack %subview padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %alloc : (memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x8x16xi32, 1 : i32>)
    %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
    iree_linalg_ext.pack %subview_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %alloc_2 : (memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x16x16xi32, 1 : i32>)
    %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
    iree_linalg_ext.pack %alloc outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_4 : (memref<1x1x8x16xi32, 1 : i32> memref<1x1x2x2x4x8xi32, 2 : i32>)
    %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
    iree_linalg_ext.pack %alloc_2 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %alloc_5 : (memref<1x1x16x16xi32, 1 : i32> memref<1x1x2x2x8x8xi32, 2 : i32>)
    %alloc_6 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
    linalg.fill ins(%c0_i32 : i32) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>)
    linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
    ^bb0(%in: i32, %in_8: i32, %out: i32):
      %3 = arith.muli %in, %in_8 : i32
      %4 = arith.addi %out, %3 : i32
      linalg.yield %4 : i32
    }
    iree_linalg_ext.unpack %alloc_6 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_3 : (memref<1x1x2x2x4x8xi32, 2 : i32> memref<1x1x8x16xi32, 1 : i32>)
    iree_linalg_ext.unpack %alloc_3 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %subview_1 : (memref<1x1x8x16xi32, 1 : i32> memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>)
    memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
    memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
    memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
    memref.dealloc %alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>
    %subview_7 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0, d1)>], iterator_types = ["parallel", "parallel"]} ins(%subview_1 : memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>) outs(%subview_7 : memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>) {
    ^bb0(%in: i32, %out: i32):
      linalg.yield %in : i32
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  return
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
  memref.assume_alignment %0, 64 : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  memref.assume_alignment %1, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  memref.assume_alignment %2, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) {
    %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32, #hal.descriptor_type<storage_buffer>> to memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    iree_linalg_ext.pack %subview padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %alloc : (memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x8x16xi32, 1 : i32>)
    %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
    iree_linalg_ext.pack %subview_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %alloc_2 : (memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x16x16xi32, 1 : i32>)
    %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
    iree_linalg_ext.pack %alloc outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_4 : (memref<1x1x8x16xi32, 1 : i32> memref<1x1x2x2x4x8xi32, 2 : i32>)
    %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
    iree_linalg_ext.pack %alloc_2 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %alloc_5 : (memref<1x1x16x16xi32, 1 : i32> memref<1x1x2x2x8x8xi32, 2 : i32>)
    %alloc_6 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
    linalg.fill ins(%c0_i32 : i32) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>)
    linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
    ^bb0(%in: i32, %in_7: i32, %out: i32):
      %3 = arith.muli %in, %in_7 : i32
      %4 = arith.addi %out, %3 : i32
      linalg.yield %4 : i32
    }
    iree_linalg_ext.unpack %alloc_6 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_3 : (memref<1x1x2x2x4x8xi32, 2 : i32> memref<1x1x8x16xi32, 1 : i32>)
    iree_linalg_ext.unpack %alloc_3 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %subview_1 : (memref<1x1x8x16xi32, 1 : i32> memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>)
    memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
    memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
    memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
    memref.dealloc %alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>
    linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, affine_map<(d0, d1) -> (d0, d1)>], iterator_types = ["parallel", "parallel"]} ins(%subview_1 : memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>) outs(%subview_1 : memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>) {
    ^bb0(%in: i32, %out: i32):
      linalg.yield %in : i32
    }
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  return
}

// -----// IR Dump Before CleanupBufferAllocView (iree-codegen-cleanup-buffer-alloc-view) //----- //
func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
  %c0_i32 = arith.constant 0 : i32
  %c0 = arith.constant 0 : index
  %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
  memref.assume_alignment %0, 64 : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
  %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  memref.assume_alignment %1, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  memref.assume_alignment %2, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
  scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) {
    %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32, #hal.descriptor_type<storage_buffer>> to memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
    %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    iree_linalg_ext.pack %subview padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %alloc : (memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x8x16xi32, 1 : i32>)
    %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
    iree_linalg_ext.pack %subview_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %alloc_2 : (memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x16x16xi32, 1 : i32>)
    %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
    %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
    iree_linalg_ext.pack %alloc outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_4 : (memref<1x1x8x16xi32, 1 : i32> memref<1x1x2x2x4x8xi32, 2 : i32>)
    %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
    iree_linalg_ext.pack %alloc_2 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %alloc_5 : (memref<1x1x16x16xi32, 1 : i32> memref<1x1x2x2x8x8xi32, 2 : i32>)
    %alloc_6 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
    linalg.fill ins(%c0_i32 : i32) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>)
    linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
    ^bb0(%in: i32, %in_7: i32, %out: i32):
      %3 = arith.muli %in, %in_7 : i32
      %4 = arith.addi %out, %3 : i32
      linalg.yield %4 : i32
    }
    iree_linalg_ext.unpack %alloc_6 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_3 : (memref<1x1x2x2x4x8xi32, 2 : i32> memref<1x1x8x16xi32, 1 : i32>)
    iree_linalg_ext.unpack %alloc_3 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %subview_1 : (memref<1x1x8x16xi32, 1 : i32> memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>)
    memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
    memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
    memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
    memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
    memref.dealloc %alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>
  } {mapping = [#gpu.block<y>, #gpu.block<x>]}
  return
}

// -----// IR Dump Before Canonicalizer (canonicalize) //----- //
hal.executable.variant public @amdaie_xclbin_fb target(<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>) {
  hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>) attributes {translation_info = #iree_codegen.translation_info<None>} {
  ^bb0(%arg0: !hal.device):
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    hal.return %x, %y, %z : index, index, index
  }
  builtin.module {
    func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
      %c0_i32 = arith.constant 0 : i32
      %c0 = arith.constant 0 : index
      %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
      memref.assume_alignment %0, 64 : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
      %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
      memref.assume_alignment %1, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
      %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
      memref.assume_alignment %2, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
      scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) {
        %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32, #hal.descriptor_type<storage_buffer>> to memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
        %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
        %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
        %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
        iree_linalg_ext.pack %subview padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %alloc : (memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x8x16xi32, 1 : i32>)
        %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
        iree_linalg_ext.pack %subview_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %alloc_2 : (memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x16x16xi32, 1 : i32>)
        %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
        %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
        iree_linalg_ext.pack %alloc outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_4 : (memref<1x1x8x16xi32, 1 : i32> memref<1x1x2x2x4x8xi32, 2 : i32>)
        %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
        iree_linalg_ext.pack %alloc_2 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %alloc_5 : (memref<1x1x16x16xi32, 1 : i32> memref<1x1x2x2x8x8xi32, 2 : i32>)
        %alloc_6 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
        linalg.fill ins(%c0_i32 : i32) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>)
        linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
        ^bb0(%in: i32, %in_7: i32, %out: i32):
          %3 = arith.muli %in, %in_7 : i32
          %4 = arith.addi %out, %3 : i32
          linalg.yield %4 : i32
        }
        iree_linalg_ext.unpack %alloc_6 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_3 : (memref<1x1x2x2x4x8xi32, 2 : i32> memref<1x1x8x16xi32, 1 : i32>)
        iree_linalg_ext.unpack %alloc_3 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %subview_1 : (memref<1x1x8x16xi32, 1 : i32> memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>)
        memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
        memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
        memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
        memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
        memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
        memref.dealloc %alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>
      } {mapping = [#gpu.block<y>, #gpu.block<x>]}
      return
    }
  }
}

// -----// IR Dump Before CSE (cse) //----- //
hal.executable.variant public @amdaie_xclbin_fb target(<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>) {
  hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>) attributes {translation_info = #iree_codegen.translation_info<None>} {
  ^bb0(%arg0: !hal.device):
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    hal.return %x, %y, %z : index, index, index
  }
  builtin.module {
    func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
      %c0_i32 = arith.constant 0 : i32
      %c0 = arith.constant 0 : index
      %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
      memref.assume_alignment %0, 64 : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
      %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
      memref.assume_alignment %1, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
      %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
      memref.assume_alignment %2, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
      scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) {
        %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32, #hal.descriptor_type<storage_buffer>> to memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
        %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
        %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
        %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
        iree_linalg_ext.pack %subview padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %alloc : (memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x8x16xi32, 1 : i32>)
        %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
        iree_linalg_ext.pack %subview_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %alloc_2 : (memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x16x16xi32, 1 : i32>)
        %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
        %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
        iree_linalg_ext.pack %alloc outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_4 : (memref<1x1x8x16xi32, 1 : i32> memref<1x1x2x2x4x8xi32, 2 : i32>)
        %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
        iree_linalg_ext.pack %alloc_2 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %alloc_5 : (memref<1x1x16x16xi32, 1 : i32> memref<1x1x2x2x8x8xi32, 2 : i32>)
        %alloc_6 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
        linalg.fill ins(%c0_i32 : i32) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>)
        linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
        ^bb0(%in: i32, %in_7: i32, %out: i32):
          %3 = arith.muli %in, %in_7 : i32
          %4 = arith.addi %out, %3 : i32
          linalg.yield %4 : i32
        }
        iree_linalg_ext.unpack %alloc_6 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_3 : (memref<1x1x2x2x4x8xi32, 2 : i32> memref<1x1x8x16xi32, 1 : i32>)
        iree_linalg_ext.unpack %alloc_3 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %subview_1 : (memref<1x1x8x16xi32, 1 : i32> memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>)
        memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
        memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
        memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
        memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
        memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
        memref.dealloc %alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>
      } {mapping = [#gpu.block<y>, #gpu.block<x>]}
      return
    }
  }
}

// -----// IR Dump Before AMDAIELowerWorkgroupCount (iree-amdaie-lower-workgroup-count) //----- //
hal.executable.variant public @amdaie_xclbin_fb target(<"amd-aie", "amdaie-xclbin-fb", {target_arch = "chip-tbd"}>) {
  hal.executable.export public @matmul_static_dispatch_0_matmul_8x16x8_i32 ordinal(0) layout(#hal.pipeline.layout<push_constants = 0, sets = [<0, bindings = [<0, storage_buffer, ReadOnly>, <1, storage_buffer, ReadOnly>, <2, storage_buffer>]>]>) attributes {translation_info = #iree_codegen.translation_info<None>} {
  ^bb0(%arg0: !hal.device):
    %x, %y, %z = flow.dispatch.workgroup_count_from_slice
    hal.return %x, %y, %z : index, index, index
  }
  builtin.module {
    func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
      %c0_i32 = arith.constant 0 : i32
      %c0 = arith.constant 0 : index
      %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
      memref.assume_alignment %0, 64 : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
      %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
      memref.assume_alignment %1, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
      %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
      memref.assume_alignment %2, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
      scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) {
        %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32, #hal.descriptor_type<storage_buffer>> to memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
        %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
        %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
        %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
        iree_linalg_ext.pack %subview padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %alloc : (memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x8x16xi32, 1 : i32>)
        %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
        iree_linalg_ext.pack %subview_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %alloc_2 : (memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x16x16xi32, 1 : i32>)
        %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
        %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
        iree_linalg_ext.pack %alloc outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_4 : (memref<1x1x8x16xi32, 1 : i32> memref<1x1x2x2x4x8xi32, 2 : i32>)
        %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
        iree_linalg_ext.pack %alloc_2 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %alloc_5 : (memref<1x1x16x16xi32, 1 : i32> memref<1x1x2x2x8x8xi32, 2 : i32>)
        %alloc_6 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
        linalg.fill ins(%c0_i32 : i32) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>)
        linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
        ^bb0(%in: i32, %in_7: i32, %out: i32):
          %3 = arith.muli %in, %in_7 : i32
          %4 = arith.addi %out, %3 : i32
          linalg.yield %4 : i32
        }
        iree_linalg_ext.unpack %alloc_6 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_3 : (memref<1x1x2x2x4x8xi32, 2 : i32> memref<1x1x8x16xi32, 1 : i32>)
        iree_linalg_ext.unpack %alloc_3 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %subview_1 : (memref<1x1x8x16xi32, 1 : i32> memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>)
        memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
        memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
        memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
        memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
        memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
        memref.dealloc %alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>
      } {mapping = [#gpu.block<y>, #gpu.block<x>]}
      return
    }
  }
}

// -----// IR Dump Before EraseHALDescriptorTypeFromMemRef (iree-codegen-erase-hal-descriptor-type-from-memref) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
    memref.assume_alignment %0, 64 : memref<8x8xi32, #hal.descriptor_type<storage_buffer>>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
    memref.assume_alignment %1, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
    memref.assume_alignment %2, 64 : memref<8x16xi32, #hal.descriptor_type<storage_buffer>>
    scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) {
      %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32, #hal.descriptor_type<storage_buffer>> to memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
      %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
      %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32, #hal.descriptor_type<storage_buffer>> to memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      iree_linalg_ext.pack %subview padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %alloc : (memref<8x8xi32, strided<[8, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x8x16xi32, 1 : i32>)
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      iree_linalg_ext.pack %subview_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %alloc_2 : (memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>> memref<1x1x16x16xi32, 1 : i32>)
      %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      iree_linalg_ext.pack %alloc outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_4 : (memref<1x1x8x16xi32, 1 : i32> memref<1x1x2x2x4x8xi32, 2 : i32>)
      %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
      iree_linalg_ext.pack %alloc_2 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %alloc_5 : (memref<1x1x16x16xi32, 1 : i32> memref<1x1x2x2x8x8xi32, 2 : i32>)
      %alloc_6 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      linalg.fill ins(%c0_i32 : i32) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>)
      linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
      ^bb0(%in: i32, %in_7: i32, %out: i32):
        %3 = arith.muli %in, %in_7 : i32
        %4 = arith.addi %out, %3 : i32
        linalg.yield %4 : i32
      }
      iree_linalg_ext.unpack %alloc_6 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_3 : (memref<1x1x2x2x4x8xi32, 2 : i32> memref<1x1x8x16xi32, 1 : i32>)
      iree_linalg_ext.unpack %alloc_3 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %subview_1 : (memref<1x1x8x16xi32, 1 : i32> memref<8x16xi32, strided<[16, 1], offset: ?>, #hal.descriptor_type<storage_buffer>>)
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
      memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
      memref.dealloc %alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    return
  }
}

// -----// IR Dump Before AMDAIEBridgeToAIR (iree-amdaie-bridge-to-air) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32>
    memref.assume_alignment %0, 64 : memref<8x8xi32>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32>
    memref.assume_alignment %1, 64 : memref<8x16xi32>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32>
    memref.assume_alignment %2, 64 : memref<8x16xi32>
    scf.forall (%arg0, %arg1) = (0, 0) to (8, 16) step (8, 16) {
      %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32> to memref<8x8xi32, strided<[8, 1], offset: ?>>
      %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32> to memref<8x16xi32, strided<[16, 1], offset: ?>>
      %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32> to memref<8x16xi32, strided<[16, 1], offset: ?>>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      iree_linalg_ext.pack %subview padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %alloc : (memref<8x8xi32, strided<[8, 1], offset: ?>> memref<1x1x8x16xi32, 1 : i32>)
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      iree_linalg_ext.pack %subview_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %alloc_2 : (memref<8x16xi32, strided<[16, 1], offset: ?>> memref<1x1x16x16xi32, 1 : i32>)
      %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      iree_linalg_ext.pack %alloc outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_4 : (memref<1x1x8x16xi32, 1 : i32> memref<1x1x2x2x4x8xi32, 2 : i32>)
      %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
      iree_linalg_ext.pack %alloc_2 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %alloc_5 : (memref<1x1x16x16xi32, 1 : i32> memref<1x1x2x2x8x8xi32, 2 : i32>)
      %alloc_6 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      linalg.fill ins(%c0_i32 : i32) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>)
      linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
      ^bb0(%in: i32, %in_7: i32, %out: i32):
        %3 = arith.muli %in, %in_7 : i32
        %4 = arith.addi %out, %3 : i32
        linalg.yield %4 : i32
      }
      iree_linalg_ext.unpack %alloc_6 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_3 : (memref<1x1x2x2x4x8xi32, 2 : i32> memref<1x1x8x16xi32, 1 : i32>)
      iree_linalg_ext.unpack %alloc_3 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %subview_1 : (memref<1x1x8x16xi32, 1 : i32> memref<8x16xi32, strided<[16, 1], offset: ?>>)
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
      memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
      memref.dealloc %alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>
    } {mapping = [#gpu.block<y>, #gpu.block<x>]}
    return
  }
}

// -----// IR Dump Before FoldMemRefAliasOps (fold-memref-alias-ops) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32>
    memref.assume_alignment %0, 64 : memref<8x8xi32>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32>
    memref.assume_alignment %1, 64 : memref<8x16xi32>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32>
    memref.assume_alignment %2, 64 : memref<8x16xi32>
    scf.parallel (%arg0, %arg1) = (%c0, %c0) to (%c8, %c16) step (%c8, %c16) {
      %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32> to memref<8x8xi32, strided<[8, 1], offset: ?>>
      %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32> to memref<8x16xi32, strided<[16, 1], offset: ?>>
      %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32> to memref<8x16xi32, strided<[16, 1], offset: ?>>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      iree_linalg_ext.pack %subview padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %alloc : (memref<8x8xi32, strided<[8, 1], offset: ?>> memref<1x1x8x16xi32, 1 : i32>)
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      iree_linalg_ext.pack %subview_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %alloc_2 : (memref<8x16xi32, strided<[16, 1], offset: ?>> memref<1x1x16x16xi32, 1 : i32>)
      %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      iree_linalg_ext.pack %alloc outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_4 : (memref<1x1x8x16xi32, 1 : i32> memref<1x1x2x2x4x8xi32, 2 : i32>)
      %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
      iree_linalg_ext.pack %alloc_2 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %alloc_5 : (memref<1x1x16x16xi32, 1 : i32> memref<1x1x2x2x8x8xi32, 2 : i32>)
      %alloc_6 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      linalg.fill ins(%c0_i32 : i32) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>)
      linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
      ^bb0(%in: i32, %in_7: i32, %out: i32):
        %3 = arith.muli %in, %in_7 : i32
        %4 = arith.addi %out, %3 : i32
        linalg.yield %4 : i32
      }
      iree_linalg_ext.unpack %alloc_6 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_3 : (memref<1x1x2x2x4x8xi32, 2 : i32> memref<1x1x8x16xi32, 1 : i32>)
      iree_linalg_ext.unpack %alloc_3 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %subview_1 : (memref<1x1x8x16xi32, 1 : i32> memref<8x16xi32, strided<[16, 1], offset: ?>>)
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
      memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
      memref.dealloc %alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>
      scf.reduce
    }
    return
  }
}

// -----// IR Dump Before AMDAIEDecomposeLinalgExtPackUnPackToAIR (iree-amdaie-decompose-pack-unpack-to-air) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32>
    memref.assume_alignment %0, 64 : memref<8x8xi32>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32>
    memref.assume_alignment %1, 64 : memref<8x16xi32>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32>
    memref.assume_alignment %2, 64 : memref<8x16xi32>
    scf.parallel (%arg0, %arg1) = (%c0, %c0) to (%c8, %c16) step (%c8, %c16) {
      %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32> to memref<8x8xi32, strided<[8, 1], offset: ?>>
      %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32> to memref<8x16xi32, strided<[16, 1], offset: ?>>
      %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32> to memref<8x16xi32, strided<[16, 1], offset: ?>>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      iree_linalg_ext.pack %subview padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %alloc : (memref<8x8xi32, strided<[8, 1], offset: ?>> memref<1x1x8x16xi32, 1 : i32>)
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      iree_linalg_ext.pack %subview_0 padding_value(%c0_i32 : i32) outer_dims_perm = [0, 1] inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %alloc_2 : (memref<8x16xi32, strided<[16, 1], offset: ?>> memref<1x1x16x16xi32, 1 : i32>)
      %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      iree_linalg_ext.pack %alloc outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_4 : (memref<1x1x8x16xi32, 1 : i32> memref<1x1x2x2x4x8xi32, 2 : i32>)
      %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
      iree_linalg_ext.pack %alloc_2 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [8, 8] into %alloc_5 : (memref<1x1x16x16xi32, 1 : i32> memref<1x1x2x2x8x8xi32, 2 : i32>)
      %alloc_6 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      linalg.fill ins(%c0_i32 : i32) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>)
      linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
      ^bb0(%in: i32, %in_7: i32, %out: i32):
        %3 = arith.muli %in, %in_7 : i32
        %4 = arith.addi %out, %3 : i32
        linalg.yield %4 : i32
      }
      iree_linalg_ext.unpack %alloc_6 outer_dims_perm = [0, 1, 3, 2] inner_dims_pos = [2, 3] inner_tiles = [4, 8] into %alloc_3 : (memref<1x1x2x2x4x8xi32, 2 : i32> memref<1x1x8x16xi32, 1 : i32>)
      iree_linalg_ext.unpack %alloc_3 inner_dims_pos = [0, 1] inner_tiles = [8, 16] into %subview_1 : (memref<1x1x8x16xi32, 1 : i32> memref<8x16xi32, strided<[16, 1], offset: ?>>)
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
      memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
      memref.dealloc %alloc_6 : memref<1x1x2x2x4x8xi32, 2 : i32>
      scf.reduce
    }
    return
  }
}

// -----// IR Dump Before ParallelToHerd (air-par-to-herd) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32>
    memref.assume_alignment %0, 64 : memref<8x8xi32>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32>
    memref.assume_alignment %1, 64 : memref<8x16xi32>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32>
    memref.assume_alignment %2, 64 : memref<8x16xi32>
    scf.parallel (%arg0, %arg1) = (%c0, %c0) to (%c8, %c16) step (%c8, %c16) {
      %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32> to memref<8x8xi32, strided<[8, 1], offset: ?>>
      %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32> to memref<8x16xi32, strided<[16, 1], offset: ?>>
      %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32> to memref<8x16xi32, strided<[16, 1], offset: ?>>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      air.dma_memcpy_nd (%alloc[] [] [], %subview[] [] []) : (memref<1x1x8x16xi32, 1 : i32>, memref<8x8xi32, strided<[8, 1], offset: ?>>)
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      air.dma_memcpy_nd (%alloc_2[] [] [], %subview_0[] [] []) : (memref<1x1x16x16xi32, 1 : i32>, memref<8x16xi32, strided<[16, 1], offset: ?>>)
      %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      %expand_shape = memref.expand_shape %alloc [[0], [1], [2, 3], [4, 5]] : memref<1x1x8x16xi32, 1 : i32> into memref<1x1x2x4x2x8xi32, 1 : i32>
      %transpose = memref.transpose %expand_shape (d0, d1, d2, d3, d4, d5) -> (d0, d1, d4, d2, d3, d5) : memref<1x1x2x4x2x8xi32, 1 : i32> to memref<1x1x2x2x4x8xi32, strided<[128, 128, 8, 64, 16, 1]>, 1 : i32>
      air.dma_memcpy_nd (%alloc_4[] [] [], %transpose[] [] []) : (memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x4x8xi32, strided<[128, 128, 8, 64, 16, 1]>, 1 : i32>)
      %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
      %expand_shape_6 = memref.expand_shape %alloc_2 [[0], [1], [2, 3], [4, 5]] : memref<1x1x16x16xi32, 1 : i32> into memref<1x1x2x8x2x8xi32, 1 : i32>
      %transpose_7 = memref.transpose %expand_shape_6 (d0, d1, d2, d3, d4, d5) -> (d0, d1, d4, d2, d3, d5) : memref<1x1x2x8x2x8xi32, 1 : i32> to memref<1x1x2x2x8x8xi32, strided<[256, 256, 8, 128, 16, 1]>, 1 : i32>
      air.dma_memcpy_nd (%alloc_5[] [] [], %transpose_7[] [] []) : (memref<1x1x2x2x8x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, strided<[256, 256, 8, 128, 16, 1]>, 1 : i32>)
      %alloc_8 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      linalg.fill ins(%c0_i32 : i32) outs(%alloc_8 : memref<1x1x2x2x4x8xi32, 2 : i32>)
      linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_8 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
      ^bb0(%in: i32, %in_12: i32, %out: i32):
        %3 = arith.muli %in, %in_12 : i32
        %4 = arith.addi %out, %3 : i32
        linalg.yield %4 : i32
      }
      %transpose_9 = memref.transpose %alloc_8 (d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4, d2, d5) : memref<1x1x2x2x4x8xi32, 2 : i32> to memref<1x1x2x4x2x8xi32, strided<[128, 128, 32, 8, 64, 1]>, 2 : i32>
      air.dma_memcpy_nd (%alloc_3[] [] [], %transpose_9[] [] []) : (memref<1x1x8x16xi32, 1 : i32>, memref<1x1x2x4x2x8xi32, strided<[128, 128, 32, 8, 64, 1]>, 2 : i32>)
      %subview_10 = memref.subview %alloc_3[0, 0, 0, 0] [1, 1, 8, 16] [1, 1, 1, 1] : memref<1x1x8x16xi32, 1 : i32> to memref<8x16xi32, 1 : i32>
      %transpose_11 = memref.transpose %subview_10 (d0, d1) -> (d0, d1) : memref<8x16xi32, 1 : i32> to memref<8x16xi32, strided<[16, 1]>, 1 : i32>
      air.dma_memcpy_nd (%subview_1[] [] [], %transpose_11[] [] []) : (memref<8x16xi32, strided<[16, 1], offset: ?>>, memref<8x16xi32, strided<[16, 1]>, 1 : i32>)
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
      memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
      memref.dealloc %alloc_8 : memref<1x1x2x2x4x8xi32, 2 : i32>
      scf.reduce
    }
    return
  }
}

// -----// IR Dump Before ParallelToLaunch (air-par-to-launch) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32>
    memref.assume_alignment %0, 64 : memref<8x8xi32>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32>
    memref.assume_alignment %1, 64 : memref<8x16xi32>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32>
    memref.assume_alignment %2, 64 : memref<8x16xi32>
    scf.parallel (%arg0, %arg1) = (%c0, %c0) to (%c8, %c16) step (%c8, %c16) {
      %subview = memref.subview %0[%arg0, 0] [8, 8] [1, 1] : memref<8x8xi32> to memref<8x8xi32, strided<[8, 1], offset: ?>>
      %subview_0 = memref.subview %1[0, %arg1] [8, 16] [1, 1] : memref<8x16xi32> to memref<8x16xi32, strided<[16, 1], offset: ?>>
      %subview_1 = memref.subview %2[%arg0, %arg1] [8, 16] [1, 1] : memref<8x16xi32> to memref<8x16xi32, strided<[16, 1], offset: ?>>
      %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      air.dma_memcpy_nd (%alloc[] [] [], %subview[] [] []) : (memref<1x1x8x16xi32, 1 : i32>, memref<8x8xi32, strided<[8, 1], offset: ?>>)
      %alloc_2 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
      air.dma_memcpy_nd (%alloc_2[] [] [], %subview_0[] [] []) : (memref<1x1x16x16xi32, 1 : i32>, memref<8x16xi32, strided<[16, 1], offset: ?>>)
      %alloc_3 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
      %alloc_4 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      %expand_shape = memref.expand_shape %alloc [[0], [1], [2, 3], [4, 5]] : memref<1x1x8x16xi32, 1 : i32> into memref<1x1x2x4x2x8xi32, 1 : i32>
      %transpose = memref.transpose %expand_shape (d0, d1, d2, d3, d4, d5) -> (d0, d1, d4, d2, d3, d5) : memref<1x1x2x4x2x8xi32, 1 : i32> to memref<1x1x2x2x4x8xi32, strided<[128, 128, 8, 64, 16, 1]>, 1 : i32>
      air.dma_memcpy_nd (%alloc_4[] [] [], %transpose[] [] []) : (memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x4x8xi32, strided<[128, 128, 8, 64, 16, 1]>, 1 : i32>)
      %alloc_5 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
      %expand_shape_6 = memref.expand_shape %alloc_2 [[0], [1], [2, 3], [4, 5]] : memref<1x1x16x16xi32, 1 : i32> into memref<1x1x2x8x2x8xi32, 1 : i32>
      %transpose_7 = memref.transpose %expand_shape_6 (d0, d1, d2, d3, d4, d5) -> (d0, d1, d4, d2, d3, d5) : memref<1x1x2x8x2x8xi32, 1 : i32> to memref<1x1x2x2x8x8xi32, strided<[256, 256, 8, 128, 16, 1]>, 1 : i32>
      air.dma_memcpy_nd (%alloc_5[] [] [], %transpose_7[] [] []) : (memref<1x1x2x2x8x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, strided<[256, 256, 8, 128, 16, 1]>, 1 : i32>)
      %alloc_8 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
      linalg.fill ins(%c0_i32 : i32) outs(%alloc_8 : memref<1x1x2x2x4x8xi32, 2 : i32>)
      linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_4, %alloc_5 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_8 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
      ^bb0(%in: i32, %in_12: i32, %out: i32):
        %3 = arith.muli %in, %in_12 : i32
        %4 = arith.addi %out, %3 : i32
        linalg.yield %4 : i32
      }
      %transpose_9 = memref.transpose %alloc_8 (d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4, d2, d5) : memref<1x1x2x2x4x8xi32, 2 : i32> to memref<1x1x2x4x2x8xi32, strided<[128, 128, 32, 8, 64, 1]>, 2 : i32>
      air.dma_memcpy_nd (%alloc_3[] [] [], %transpose_9[] [] []) : (memref<1x1x8x16xi32, 1 : i32>, memref<1x1x2x4x2x8xi32, strided<[128, 128, 32, 8, 64, 1]>, 2 : i32>)
      %subview_10 = memref.subview %alloc_3[0, 0, 0, 0] [1, 1, 8, 16] [1, 1, 1, 1] : memref<1x1x8x16xi32, 1 : i32> to memref<8x16xi32, 1 : i32>
      %transpose_11 = memref.transpose %subview_10 (d0, d1) -> (d0, d1) : memref<8x16xi32, 1 : i32> to memref<8x16xi32, strided<[16, 1]>, 1 : i32>
      air.dma_memcpy_nd (%subview_1[] [] [], %transpose_11[] [] []) : (memref<8x16xi32, strided<[16, 1], offset: ?>>, memref<8x16xi32, strided<[16, 1]>, 1 : i32>)
      memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_2 : memref<1x1x16x16xi32, 1 : i32>
      memref.dealloc %alloc_3 : memref<1x1x8x16xi32, 1 : i32>
      memref.dealloc %alloc_4 : memref<1x1x2x2x4x8xi32, 2 : i32>
      memref.dealloc %alloc_5 : memref<1x1x2x2x8x8xi32, 2 : i32>
      memref.dealloc %alloc_8 : memref<1x1x2x2x4x8xi32, 2 : i32>
      scf.reduce
    }
    return
  }
}

// -----// IR Dump Before CopyToDma (air-copy-to-dma) //----- //
module {
  func.func @matmul_static_dispatch_0_matmul_8x16x8_i32() {
    %c16 = arith.constant 16 : index
    %c8 = arith.constant 8 : index
    %c0_i32 = arith.constant 0 : i32
    %c0 = arith.constant 0 : index
    %0 = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x8xi32>
    memref.assume_alignment %0, 64 : memref<8x8xi32>
    %1 = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) alignment(64) offset(%c0) flags(ReadOnly) : memref<8x16xi32>
    memref.assume_alignment %1, 64 : memref<8x16xi32>
    %2 = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) alignment(64) offset(%c0) : memref<8x16xi32>
    memref.assume_alignment %2, 64 : memref<8x16xi32>
    %c1 = arith.constant 1 : index
    %c0_0 = arith.constant 0 : index
    %c1_1 = arith.constant 1 : index
    %c1_2 = arith.constant 1 : index
    %c0_3 = arith.constant 0 : index
    %c1_4 = arith.constant 1 : index
    %c1_5 = arith.constant 1 : index
    %c1_6 = arith.constant 1 : index
    air.launch (%arg0, %arg1) in (%arg2=%c1_5, %arg3=%c1_6) args(%arg4=%0, %arg5=%1, %arg6=%2) : memref<8x8xi32>, memref<8x16xi32>, memref<8x16xi32> {
      air.segment @segment_0  args(%arg7=%arg0, %arg8=%arg1, %arg9=%arg2, %arg10=%arg3, %arg11=%arg4, %arg12=%arg5, %arg13=%arg6) : index, index, index, index, memref<8x8xi32>, memref<8x16xi32>, memref<8x16xi32> {
        %c0_i32_7 = arith.constant 0 : i32
        %3 = affine.apply affine_map<(d0) -> (d0 * 8)>(%arg7)
        %4 = affine.apply affine_map<(d0) -> (d0 * 16)>(%arg8)
        %subview = memref.subview %arg11[%3, 0] [8, 8] [1, 1] : memref<8x8xi32> to memref<8x8xi32, strided<[8, 1], offset: ?>>
        %subview_8 = memref.subview %arg12[0, %4] [8, 16] [1, 1] : memref<8x16xi32> to memref<8x16xi32, strided<[16, 1], offset: ?>>
        %subview_9 = memref.subview %arg13[%3, %4] [8, 16] [1, 1] : memref<8x16xi32> to memref<8x16xi32, strided<[16, 1], offset: ?>>
        %alloc = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
        air.dma_memcpy_nd (%alloc[] [] [], %subview[] [] []) : (memref<1x1x8x16xi32, 1 : i32>, memref<8x8xi32, strided<[8, 1], offset: ?>>)
        %alloc_10 = memref.alloc() : memref<1x1x16x16xi32, 1 : i32>
        air.dma_memcpy_nd (%alloc_10[] [] [], %subview_8[] [] []) : (memref<1x1x16x16xi32, 1 : i32>, memref<8x16xi32, strided<[16, 1], offset: ?>>)
        %alloc_11 = memref.alloc() : memref<1x1x8x16xi32, 1 : i32>
        %alloc_12 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
        %expand_shape = memref.expand_shape %alloc [[0], [1], [2, 3], [4, 5]] : memref<1x1x8x16xi32, 1 : i32> into memref<1x1x2x4x2x8xi32, 1 : i32>
        %transpose = memref.transpose %expand_shape (d0, d1, d2, d3, d4, d5) -> (d0, d1, d4, d2, d3, d5) : memref<1x1x2x4x2x8xi32, 1 : i32> to memref<1x1x2x2x4x8xi32, strided<[128, 128, 8, 64, 16, 1]>, 1 : i32>
        air.dma_memcpy_nd (%alloc_12[] [] [], %transpose[] [] []) : (memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x4x8xi32, strided<[128, 128, 8, 64, 16, 1]>, 1 : i32>)
        %alloc_13 = memref.alloc() : memref<1x1x2x2x8x8xi32, 2 : i32>
        %expand_shape_14 = memref.expand_shape %alloc_10 [[0], [1], [2, 3], [4, 5]] : memref<1x1x16x16xi32, 1 : i32> into memref<1x1x2x8x2x8xi32, 1 : i32>
        %transpose_15 = memref.transpose %expand_shape_14 (d0, d1, d2, d3, d4, d5) -> (d0, d1, d4, d2, d3, d5) : memref<1x1x2x8x2x8xi32, 1 : i32> to memref<1x1x2x2x8x8xi32, strided<[256, 256, 8, 128, 16, 1]>, 1 : i32>
        air.dma_memcpy_nd (%alloc_13[] [] [], %transpose_15[] [] []) : (memref<1x1x2x2x8x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, strided<[256, 256, 8, 128, 16, 1]>, 1 : i32>)
        %alloc_16 = memref.alloc() : memref<1x1x2x2x4x8xi32, 2 : i32>
        linalg.fill ins(%c0_i32_7 : i32) outs(%alloc_16 : memref<1x1x2x2x4x8xi32, 2 : i32>)
        linalg.generic {indexing_maps = [affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d2, d5, d3, d6, d8)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d2, d1, d4, d5, d8, d7)>, affine_map<(d0, d1, d2, d3, d4, d5, d6, d7, d8) -> (d0, d1, d4, d3, d6, d7)>], iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction", "parallel", "parallel", "reduction"]} ins(%alloc_12, %alloc_13 : memref<1x1x2x2x4x8xi32, 2 : i32>, memref<1x1x2x2x8x8xi32, 2 : i32>) outs(%alloc_16 : memref<1x1x2x2x4x8xi32, 2 : i32>) {
        ^bb0(%in: i32, %in_20: i32, %out: i32):
          %5 = arith.muli %in, %in_20 : i32
          %6 = arith.addi %out, %5 : i32
          linalg.yield %6 : i32
        }
        %transpose_17 = memref.transpose %alloc_16 (d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4, d2, d5) : memref<1x1x2x2x4x8xi32, 2 : i32> to memref<1x1x2x4x2x8xi32, strided<[128, 128, 32, 8, 64, 1]>, 2 : i32>
        air.dma_memcpy_nd (%alloc_11[] [] [], %transpose_17[] [] []) : (memref<1x1x8x16xi32, 1 : i32>, memref<1x1x2x4x2x8xi32, strided<[128, 128, 32, 8, 64, 1]>, 2 : i32>)
        %subview_18 = memref.subview %alloc_11[0, 0, 0, 0] [1, 1, 8, 16] [1, 1, 1, 1] : memref<1x1x8x16xi32, 1 : i32> to memref<8x16xi32, 1 : i32>
        %transpose_19 = memref.transpose %subview_18 (d0, d1) -> (d0, d1) : memref<8x16xi32, 1 : i32> to memref<8x16xi32, strided<[16, 1]>, 1 : i32>
        air.dma_memcpy_nd (%subview_9[] [] [], %transpose_19[] [] []) : (memref<8x16xi32, strided<[16, 1], offset: ?>>, memref<8x16xi32, strided<[16, 1]>, 1 : i32>)
        memref.dealloc %alloc : memref<1x1x8x16xi32, 1 : i32>
        memref.dealloc %alloc_10 : memref<1x1x16x16xi32, 1 : i32>
        memref.dealloc %alloc_11 : memref<1x1x8x16xi32, 1 : i32>
        memref.dealloc %alloc_12 : memref<1x1x2x2x4x8xi32, 2 : i32>
        memref.dealloc %alloc_13 : memref<1x1x2x2x8x8xi32, 2 : i32>
        memref.dealloc %alloc_16 : memref<1x1x2x2x4x8xi32, 2 : i32>
        air.segment_terminator
      }
      air.launch_terminator
    }
    return
  }
}

Please report issues to https://github.com/openxla/iree/issues and include the crash backtrace.
Stack dump:
0.	Program arguments: /proj/xcohdstaff6/abhvarma/iree/build/tools/iree-compile --mlir-elide-elementsattrs-if-larger=2 --iree-hal-target-backends=amd-aie /proj/xcohdstaff6/abhvarma/all_dispatch/7_dispatch_8_16_8_i32.mlir --iree-amd-aie-peano-install-dir=/proj/xcohdstaff6/erieaton/install --iree-amd-aie-mlir-aie-install-dir=/proj/xcohdstaff6/nmeshram/iree-amd-aie/third_party/mlir-aie/install --iree-amd-aie-vitis-install-dir=/proj/xbuilds/SWIP/2023.2_1013_2256/installs/lin64/Vitis/2023.2 --iree-hal-dump-executable-files-to=/proj/xcohdstaff6/abhvarma/iree/build --iree-amd-aie-show-invoked-commands -o test.vmfb --mlir-print-ir-before-all --mlir-disable-threading
Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var `LLVM_SYMBOLIZER_PATH` to point to it):
0  libIREECompiler.so 0x00007f83f82d22cd llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) + 61
1  libIREECompiler.so 0x00007f83f82d27bb
2  libIREECompiler.so 0x00007f83f82d07e6 llvm::sys::RunSignalHandlers() + 134
3  libIREECompiler.so 0x00007f83f82d2fd5
4  libc.so.6          0x00007f83ec042520
5  libIREECompiler.so 0x00007f83f849e015 mlir::MemRefType::getLayout() const + 21
6  libIREECompiler.so 0x00007f840050c0d8 mlir::memref::ExpandShapeOp::computeExpandedType(mlir::MemRefType, llvm::ArrayRef<long>, llvm::ArrayRef<llvm::SmallVector<long, 2u>>) + 40
7  libIREECompiler.so 0x00007f83faae0369
8  libIREECompiler.so 0x00007f83faadfa02
9  libIREECompiler.so 0x00007f83f87051fb
10 libIREECompiler.so 0x00007f83f8705195
11 libIREECompiler.so 0x00007f83f81e57e9
12 libIREECompiler.so 0x00007f83f87082dd
13 libIREECompiler.so 0x00007f83f87006c3 mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int) + 851
14 libIREECompiler.so 0x00007f83f8700c74 mlir::detail::OpToOpPassAdaptor::runPipeline(mlir::OpPassManager&, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int, mlir::PassInstrumentor*, mlir::PassInstrumentation::PipelineParentInfo const*) + 388
15 libIREECompiler.so 0x00007f83f8701afe mlir::detail::OpToOpPassAdaptor::runOnOperationImpl(bool) + 574
16 libIREECompiler.so 0x00007f83f870139d mlir::detail::OpToOpPassAdaptor::runOnOperation(bool) + 93
17 libIREECompiler.so 0x00007f83f87051e6
18 libIREECompiler.so 0x00007f83f8705195
19 libIREECompiler.so 0x00007f83f81e57e9
20 libIREECompiler.so 0x00007f83f87082dd
21 libIREECompiler.so 0x00007f83f87006c3 mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int) + 851
22 libIREECompiler.so 0x00007f83f8700c74 mlir::detail::OpToOpPassAdaptor::runPipeline(mlir::OpPassManager&, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int, mlir::PassInstrumentor*, mlir::PassInstrumentation::PipelineParentInfo const*) + 388
23 libIREECompiler.so 0x00007f83f8705171
24 libIREECompiler.so 0x00007f83f8704ef2
25 libIREECompiler.so 0x00007f83f8626b11
26 libIREECompiler.so 0x00007f83f861fb05
27 libIREECompiler.so 0x00007f83fb3f2c11
28 libIREECompiler.so 0x00007f83f87051fb
29 libIREECompiler.so 0x00007f83f8705195
30 libIREECompiler.so 0x00007f83f81e57e9
31 libIREECompiler.so 0x00007f83f87082dd
32 libIREECompiler.so 0x00007f83f87006c3 mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int) + 851
33 libIREECompiler.so 0x00007f83f8700c74 mlir::detail::OpToOpPassAdaptor::runPipeline(mlir::OpPassManager&, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int, mlir::PassInstrumentor*, mlir::PassInstrumentation::PipelineParentInfo const*) + 388
34 libIREECompiler.so 0x00007f83f8701afe mlir::detail::OpToOpPassAdaptor::runOnOperationImpl(bool) + 574
35 libIREECompiler.so 0x00007f83f870139d mlir::detail::OpToOpPassAdaptor::runOnOperation(bool) + 93
36 libIREECompiler.so 0x00007f83f87051e6
37 libIREECompiler.so 0x00007f83f8705195
38 libIREECompiler.so 0x00007f83f81e57e9
39 libIREECompiler.so 0x00007f83f87082dd
40 libIREECompiler.so 0x00007f83f87006c3 mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int) + 851
41 libIREECompiler.so 0x00007f83f8700c74 mlir::detail::OpToOpPassAdaptor::runPipeline(mlir::OpPassManager&, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int, mlir::PassInstrumentor*, mlir::PassInstrumentation::PipelineParentInfo const*) + 388
42 libIREECompiler.so 0x00007f83f8705171
43 libIREECompiler.so 0x00007f83f8704ef2
44 libIREECompiler.so 0x00007f83f8626b11
45 libIREECompiler.so 0x00007f83f861fb05
46 libIREECompiler.so 0x00007f83fb3f3bcc
47 libIREECompiler.so 0x00007f83f87051fb
48 libIREECompiler.so 0x00007f83f8705195
49 libIREECompiler.so 0x00007f83f81e57e9
50 libIREECompiler.so 0x00007f83f87082dd
51 libIREECompiler.so 0x00007f83f87006c3 mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int) + 851
52 libIREECompiler.so 0x00007f83f8700c74 mlir::detail::OpToOpPassAdaptor::runPipeline(mlir::OpPassManager&, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int, mlir::PassInstrumentor*, mlir::PassInstrumentation::PipelineParentInfo const*) + 388
53 libIREECompiler.so 0x00007f83f8701afe mlir::detail::OpToOpPassAdaptor::runOnOperationImpl(bool) + 574
54 libIREECompiler.so 0x00007f83f870139d mlir::detail::OpToOpPassAdaptor::runOnOperation(bool) + 93
55 libIREECompiler.so 0x00007f83f87051e6
56 libIREECompiler.so 0x00007f83f8705195
57 libIREECompiler.so 0x00007f83f81e57e9
58 libIREECompiler.so 0x00007f83f87082dd
59 libIREECompiler.so 0x00007f83f87006c3 mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int) + 851
60 libIREECompiler.so 0x00007f83f8700c74 mlir::detail::OpToOpPassAdaptor::runPipeline(mlir::OpPassManager&, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int, mlir::PassInstrumentor*, mlir::PassInstrumentation::PipelineParentInfo const*) + 388
61 libIREECompiler.so 0x00007f83f870275c mlir::PassManager::runPasses(mlir::Operation*, mlir::AnalysisManager) + 108
62 libIREECompiler.so 0x00007f83f870267f mlir::PassManager::run(mlir::Operation*) + 1151
63 libIREECompiler.so 0x00007f83f812e651
64 libIREECompiler.so 0x00007f83f812df73 ireeCompilerInvocationPipeline + 35
65 libIREECompiler.so 0x00007f83f868e150
66 libIREECompiler.so 0x00007f83f868d609
67 libIREECompiler.so 0x00007f83f817b03b ireeCompilerRunMain + 27
68 iree-compile       0x000055a246d297b2
69 libc.so.6          0x00007f83ec029d90
70 libc.so.6          0x00007f83ec029e40 __libc_start_main + 128
71 iree-compile       0x000055a246d296c5
timeout: the monitored command dumped core