Acathla-fr

$: make VexRiscv_Lite.v
sbt compile "runMain vexriscv.GenCoreDefault --iCacheSize 2048 --dCacheSize 0 --mulDiv true --singleCycleShift false --singleCycleMulDiv false  --outputFile VexRiscv_Lite"
[info] Loading settings for project verilog-build from plugins.sbt ...
[info] Loading project definition from /home/fabien/prog/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/project
[info] Loading settings for project root from build.sbt ...
[info] Set current project to VexRiscvOnWishbone (in build file:/home/fabien/prog/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/)
[info] Executing in batch mode. For better performance use sbt's shell
[info] Updating ...
[warn] 	module not found: default#vexriscv_2.11;0.1.0-SNAPSHOT
[warn] ==== local: tried