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@Aflecht
Last active January 18, 2024 10:06
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How to configure STM32F37x ARM Cortex M4 microcontroller to 72 MHz? (using 8 MHz crystal)
//
// Clock STM32F37x to 72 MHz using 8 MHz crystal
//
#include <stm32f37x.h>
/*
AHB = max 72 MHz
APB2 = max 72 MHz
APB1 = max 36 MHz
SysTick = AHB/8 OR AHB (configure from SysTick configuration bits)
Timers = 2x APB to which they are connected.
USART1/2/3 still needs to be configured. (RCC_CFGR3)
*/
void Configure_Clocks()
{
// Flash = two wait states, as 48 < SYSCLK <= 72 MHz
FLASH->ACR |= FLASH_ACR_LATENCY_1;
// Turn HSE on
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY));
// Turn PLL off
RCC->CR &= ~RCC_CR_PLLON;
while (RCC->CR & RCC_CR_PLLRDY);
// Change PLL parameters
RCC->CFGR |= RCC_CFGR_PLLSRC; // Set HSE as PLL clock source
RCC->CFGR |= RCC_CFGR_PLLMULL_0 | // PLL input clock x 9 = 72 MHz
RCC_CFGR_PLLMULL_1 |
RCC_CFGR_PLLMULL_2;
RCC->CFGR |= RCC_CFGR_MCO_PLL; // MCO = PLL clock divided by 2 selected
// Change bus clock prescaler parameters
RCC->CFGR &= ~RCC_CFGR_PPRE2; // APB2 = AHB clock not divided
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; // APB1 = AHB clock divided by 2
RCC->CFGR &= ~RCC_CFGR_HPRE; // AHB = not divided
// Turn PLL back on
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY));
// Switch system clock source to PLL
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
}
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