AliHusseinS

library ieee ;
use ieee.std_logic_1164.all ;
--------------------------------------------------------------
entity finalproject is 
generic (R_width : integer := 24 ; R_addres : integer := 5);
port(clock_50                      : in  std_logic;
     ledr                          : out std_logic_vector(1 downto 0);
	  key                           : in  std_logic_vector(1 downto 0);
	  hex0,hex1,hex2,hex3,hex4,hex5 : out std_logic_vector(0 to 6));
end finalproject ;

AliHusseinS

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all    ;
use ieee.std_logic_unsigned.all;
ENTITY lab4 IS
generic (input5Bit   : integer := 12;
         
         data_size    : integer := 24;
         ram_width    : integer := 24; 
         addres_width : integer := 32);

AliHusseinS

-- 
-- test vector for full_adder.vhdl
-- A testbench has no ports.
entity ftest is
end ftest;
 
architecture behav of ftest is
component FULL_ADDER
  port(A, B, CIN: in  bit;
       SUM, COUT: out bit);

AliHusseinS

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all    ;
use ieee.std_logic_unsigned.all;
ENTITY lab4 IS
generic (input5Bit   : integer := 12;
         data_size    : integer := 24;
         ram_width    : integer := 24; 
         addres_width : integer := 32);
PORT (clock_50                      : in  std_logic                     ;

AliHusseinS

library ieee ;
use ieee.std_logic_1164.all;

entity lab4 is 
port(key0  : in  std_logic ;
    sw   : in  std_logic_vector(1 downto 0);
    ledr : out std_logic_vector(0 downto 0));
end lab4;
architecture b of lab4 is 
type state is (A,B ,C ,D ,E ,F ,G ,H ,I) ;

AliHusseinS

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
--------------------------
ENTITY lab4 IS
PORT (Clock_50 : IN STD_LOGIC;
		sw:in std_logic;
      HEX0:out std_logic_vector(0 to 6));
		
END lab4;

AliHusseinS

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                
ENTITY lab3_vhd_tst IS
END lab3_vhd_tst;
ARCHITECTURE lab3_arch OF lab3_vhd_tst IS
---------------------------------------------
constant clock_cycle :time:=40ns;
---------------------------------------------
SIGNAL clk,Qc,D,NotQa,NotQb,NotQc,Qb,Qa : STD_LOGIC;
COMPONENT lab3

AliHusseinS

library ieee;
use ieee.std_logic_1164.all;
entity lab3 is
  port
    (clk ,D : in std_logic;
     Qa,NotQa ,Qb,NotQb,NotQc,Qc : out std_logic );                
end lab3;
architecture potato of lab3 is
component latch_Base is
port(clk,D: in std_logic ;

AliHusseinS

library ieee;
use ieee.std_logic_1164.all;
entity lab2 is 
		port ( sw : in std_logic_vector ( 8 downto 0); 		--//	8 SWITCHES  ARE USED IN THIS LAB 
		ledr : out std_logic_vector ( 9 downto 0 );    		--//	10 LED RED ARE USED IN THIS LAB
		hex0 , hex1 ,hex2 , hex3   : out std_logic_vector (0 to 6)); --//WE USE only hex0 and hex1 and hex2 and hex3  from LCD 7 SIG that all we need in this lab
end lab2;
architecture structure of lab2 is 
----------------components OF 4XFull_Adder 4bit for each Component------

AliHusseinS

void showArrPtr(double *array, int size)
{
	for (int count = 0; count< size; count++)
		cout << *(array + count) << " ";
	cout << endl;
}

void showAverage(double total, int numscores)
{