Criteria:
groups = ['arith', 'logical', 'conver', 'datamov', 'datamov arith', 'shftrot', 'flgctrl'];
// Excluded because they may trigger faults, so the optimization can't apply to them
excluded_opcodes = [
// May trigger_ud
'0x8C',
// switch_seg may fault
'0x8E',
// mov to/from seg:offset (memory accesses)
'0xA0',
'0xA1',
'0xA2',
'0xA3',
// Unimplemented in v86
'0xD50A',
'0x0F38F0',
'0x0F38F1',
];
// Keywords that indicate a group/instruction which may fault
excluded_row_words = ['fpu', 'simd', 'mmx', 'sse', 'vmx', 'XLAT', 'DIV', 'AMX', 'AAM', 'CLI', 'STI', 'CMPXCHG8B'];
Instructions:
- 0x00 ADD
- 0x01 ADD
- 0x02 ADD
- 0x03 ADD
- 0x04 ADD
- 0x05 ADD
- 0x08 OR
- 0x09 OR
- 0x0A OR
- 0x0B OR
- 0x0C OR
- 0x0D OR
- 0x10 ADC
- 0x11 ADC
- 0x12 ADC
- 0x13 ADC
- 0x14 ADC
- 0x15 ADC
- 0x18 SBB
- 0x19 SBB
- 0x1A SBB
- 0x1B SBB
- 0x1C SBB
- 0x1D SBB
- 0x20 AND
- 0x21 AND
- 0x22 AND
- 0x23 AND
- 0x24 AND
- 0x25 AND
- 0x27 DAA
- 0x28 SUB
- 0x29 SUB
- 0x2A SUB
- 0x2B SUB
- 0x2C SUB
- 0x2D SUB
- 0x2F DAS
- 0x30 XOR
- 0x31 XOR
- 0x32 XOR
- 0x33 XOR
- 0x34 XOR
- 0x35 XOR
- 0x37 AAA
- 0x38 CMP
- 0x39 CMP
- 0x3A CMP
- 0x3B CMP
- 0x3C CMP
- 0x3D CMP
- 0x3F AAS
- 0x40 INC +r (more)
- 0x48 DEC +r (more)
- 0x69 IMUL
- 0x6B IMUL
- 0x80_0 ADD
- 0x80_1 OR
- 0x80_2 ADC
- 0x80_3 SBB
- 0x80_4 AND
- 0x80_5 SUB
- 0x80_6 XOR
- 0x80_7 CMP
- 0x81_0 ADD
- 0x81_1 OR
- 0x81_2 ADC
- 0x81_3 SBB
- 0x81_4 AND
- 0x81_5 SUB
- 0x81_6 XOR
- 0x81_7 CMP
- 0x82_0 ADD alias
- 0x82_1 OR alias
- 0x82_2 ADC alias
- 0x82_3 SBB alias
- 0x82_4 AND alias
- 0x82_5 SUB alias
- 0x82_6 XOR alias
- 0x82_7 CMP alias
- 0x83_0 ADD
- 0x83_1 OR
- 0x83_2 ADC
- 0x83_3 SBB
- 0x83_4 AND
- 0x83_5 SUB
- 0x83_6 XOR
- 0x83_7 CMP
- 0x84 TEST
- 0x85 TEST
- 0x86 XCHG
- 0x87 XCHG
- 0x88 MOV
- 0x89 MOV
- 0x8A MOV
- 0x8B MOV
- 0x8D LEA
- 0x90 XCHG +r (more)
- 0x98 CBW
- 0x98 CWDE
- 0x99 CWD
- 0x99 CDQ
- 0xA8 TEST
- 0xA9 TEST
- 0xB0 MOV +r (more)
- 0xB8 MOV +r (more)
- 0xC0_0 ROL
- 0xC0_1 ROR
- 0xC0_2 RCL
- 0xC0_3 RCR
- 0xC0_4 SHL
- 0xC0_5 SHR
- 0xC0_6 SAL alias
- 0xC0_7 SAR
- 0xC1_0 ROL
- 0xC1_1 ROR
- 0xC1_2 RCL
- 0xC1_3 RCR
- 0xC1_4 SHL
- 0xC1_5 SHR
- 0xC1_6 SAL alias
- 0xC1_7 SAR
- 0xC6_0 MOV
- 0xC7_0 MOV
- 0xD0_0 ROL
- 0xD0_1 ROR
- 0xD0_2 RCL
- 0xD0_3 RCR
- 0xD0_4 SHL
- 0xD0_5 SHR
- 0xD0_6 SAL alias
- 0xD0_7 SAR
- 0xD1_0 ROL
- 0xD1_1 ROR
- 0xD1_2 RCL
- 0xD1_3 RCR
- 0xD1_4 SHL
- 0xD1_5 SHR
- 0xD1_6 SAL alias
- 0xD1_7 SAR
- 0xD2_0 ROL
- 0xD2_1 ROR
- 0xD2_2 RCL
- 0xD2_3 RCR
- 0xD2_4 SHL
- 0xD2_5 SHR
- 0xD2_6 SAL alias
- 0xD2_7 SAR
- 0xD3_0 ROL
- 0xD3_1 ROR
- 0xD3_2 RCL
- 0xD3_3 RCR
- 0xD3_4 SHL
- 0xD3_5 SHR
- 0xD3_6 SAL alias
- 0xD3_7 SAR
- 0xD4 AMX
- 0xD6 SALC
- 0xF5 CMC
- 0xF6_0 TEST
- 0xF6_1 TEST alias
- 0xF6_2 NOT
- 0xF6_3 NEG
- 0xF6_4 MUL
- 0xF6_5 IMUL
- 0xF7_0 TEST
- 0xF7_1 TEST alias
- 0xF7_2 NOT
- 0xF7_3 NEG
- 0xF7_4 MUL
- 0xF7_5 IMUL
- 0xF8 CLC
- 0xF9 STC
- 0xFC CLD
- 0xFD STD
- 0xFE_0 INC
- 0xFE_1 DEC
- 0xFF_0 INC
- 0xFF_1 DEC
- 0x0F40 CMOVO
- 0x0F41 CMOVNO
- 0x0F42 CMOVB
- 0x0F43 CMOVNB
- 0x0F44 CMOVZ
- 0x0F45 CMOVNZ
- 0x0F46 CMOVBE
- 0x0F47 CMOVNBE
- 0x0F48 CMOVS
- 0x0F49 CMOVNS
- 0x0F4A CMOVP
- 0x0F4B CMOVNP
- 0x0F4C CMOVL
- 0x0F4D CMOVNL
- 0x0F4E CMOVLE
- 0x0F4F CMOVNLE
- 0x0F90_0 SETO
- 0x0F91_0 SETNO
- 0x0F92_0 SETB
- 0x0F93_0 SETNB
- 0x0F94_0 SETZ
- 0x0F95_0 SETNZ
- 0x0F96_0 SETBE
- 0x0F97_0 SETNBE
- 0x0F98_0 SETS
- 0x0F99_0 SETNS
- 0x0F9A_0 SETP
- 0x0F9B_0 SETNP
- 0x0F9C_0 SETL
- 0x0F9D_0 SETNL
- 0x0F9E_0 SETLE
- 0x0F9F_0 SETNLE
- 0x0FA4 SHLD
- 0x0FA5 SHLD
- 0x0FAC SHRD
- 0x0FAD SHRD
- 0x0FAF IMUL
- 0x0FB0 CMPXCHG
- 0x0FB1 CMPXCHG
- 0x0FB6 MOVZX
- 0x0FB7 MOVZX
- 0x0FBE MOVSX
- 0x0FBF MOVSX
- 0x0FC0 XADD
- 0x0FC1 XADD
- 0x0FC8 BSWAP +r (more)