Skip to content

Instantly share code, notes, and snippets.

@AndyAyersMS

AndyAyersMS/ex.base.d

Created March 5, 2020 19:03
Show Gist options
  • Save AndyAyersMS/f10d9dae8143ddec55869b718d0f38bd to your computer and use it in GitHub Desktop.
Save AndyAyersMS/f10d9dae8143ddec55869b718d0f38bd to your computer and use it in GitHub Desktop.
Download ZIP
Jit dumps for simple repro case in dotnet/runtime#33098
Raw
ex.base.d
c:\repos\runtime4\artifacts\tests\coreclr\Windows_NT.x86.release\Tests\Core_Root\corerun.exe ex.exe
Compiling 0 CastHelpers::StelemRef, IL size = 86, hash=0x93aaa786 FullOpts
Compiling 1 CastHelpers::LdelemaRef, IL size = 42, hash=0xffd2fc9e FullOpts
Compiling 2 SpanHelpers::IndexOf, IL size = 705, hash=0xdb3370c7 FullOpts
Compiling 3 Utf16Utility::GetPointerToFirstInvalidChar, IL size = 972, hash=0x137a51fe FullOpts
Compiling 4 Vector128::CreateScalarUnsafe, IL size = 21, hash=0xcd46d192 FullOpts
Compiling 5 Vector128::AsUInt32, IL size = 7, hash=0x8f8eda53 FullOpts
Compiling 6 Vector128::AsUInt16, IL size = 7, hash=0x7bc35b55 FullOpts
Compiling 7 Vector128::AsByte, IL size = 7, hash=0x9ea1d9de FullOpts
Compiling 8 Sse41::get_IsSupported, IL size = 6, hash=0x6da8cf37 FullOpts
Compiling 9 ASCIIUtility::NarrowUtf16ToAscii, IL size = 637, hash=0x150d5dc8 FullOpts
Compiling 10 X::Main, IL size = 51, hash=0x17874944 FullOpts
Compiling 11 EmptyArray`1::.cctor, IL size = 12, hash=0xaece4604 Tier-1/FullOpts switched to MinOpts
Compiling 12 Stack`1::Push, IL size = 60, hash=0x3bffc3a2 FullOpts
Compiling 13 Stack`1::PushWithResize, IL size = 80, hash=0xa06e2af2 FullOpts
Compiling 14 Array::Resize, IL size = 66, hash=0x16e8e9e0 FullOpts
****** START compiling Stack`1:Pop():RefAsValueType`1:this (MethodHash=b85a3b29)
Generating code for Windows x86
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
IL to import:
IL_0000 02 ldarg.0
IL_0001 7b 54 02 00 0a ldfld 0xA000254
IL_0006 17 ldc.i4.1
IL_0007 59 sub
IL_0008 0a stloc.0
IL_0009 02 ldarg.0
IL_000a 7b 53 02 00 0a ldfld 0xA000253
IL_000f 0b stloc.1
IL_0010 06 ldloc.0
IL_0011 07 ldloc.1
IL_0012 8e ldlen
IL_0013 69 conv.i4
IL_0014 37 06 blt.un.s 6 (IL_001c)
IL_0016 02 ldarg.0
IL_0017 28 59 02 00 0a call 0xA000259
IL_001c 02 ldarg.0
IL_001d 02 ldarg.0
IL_001e 7b 55 02 00 0a ldfld 0xA000255
IL_0023 17 ldc.i4.1
IL_0024 58 add
IL_0025 7d 55 02 00 0a stfld 0xA000255
IL_002a 02 ldarg.0
IL_002b 06 ldloc.0
IL_002c 7d 54 02 00 0a stfld 0xA000254
IL_0031 07 ldloc.1
IL_0032 06 ldloc.0
IL_0033 a3 11 00 00 1b ldelem 0x1B000011
IL_0038 0c stloc.2
IL_0039 28 0b 00 00 2b call 0x2B00000B
IL_003e 2c 10 brfalse.s 16 (IL_0050)
IL_0040 07 ldloc.1
IL_0041 06 ldloc.0
IL_0042 12 03 ldloca.s 0x3
IL_0044 fe 15 11 00 00 1b initobj 0x1B000011
IL_004a 09 ldloc.3
IL_004b a4 11 00 00 1b stelem 0x1B000011
IL_0050 08 ldloc.2
IL_0051 2a ret
lvaSetClass: setting class for V00 to (0825A8B8) Stack`1
'this' passed in register ecx
lvaSetClass: setting class for V02 to (0825AD18) (null)
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 int
; V02 loc1 ref class-hnd
; V03 loc2 struct ( 4)
; V04 loc3 struct ( 4)
*************** In compInitDebuggingInfo() for Stack`1:Pop():RefAsValueType`1:this
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 5
VarNum LVNum Name Beg End
0: 00h 00h V00 this 000h 052h
1: 01h 01h V01 loc0 000h 052h
2: 02h 02h V02 loc1 000h 052h
3: 03h 03h V03 loc2 000h 052h
4: 04h 04h V04 loc3 000h 052h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Stack`1:Pop():RefAsValueType`1:this
Marked V01 as a single def local
Marked V02 as a single def local
Marked V03 as a single def local
Jump targets:
IL_001c
IL_0050
New Basic Block BB01 [0000] created.
BB01 [000..016)
New Basic Block BB02 [0001] created.
BB02 [016..01C)
New Basic Block BB03 [0002] created.
BB03 [01C..040)
New Basic Block BB04 [0003] created.
BB04 [040..050)
New Basic Block BB05 [0004] created.
BB05 [050..052)
IL Code Size,Instr 82, 38, Basic Block count 5, Local Variable Num,Ref count 5, 19 for method Stack`1:Pop():RefAsValueType`1:this
OPTIONS: opts.MinOpts() == false
Basic block list for 'Stack`1:Pop():RefAsValueType`1:this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond )
BB02 [0001] 1 1 [016..01C)
BB03 [0002] 2 1 [01C..040)-> BB05 ( cond )
BB04 [0003] 1 1 [040..050)
BB05 [0004] 2 1 [050..052) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
Compiling 15 Stack`1::Pop, IL size = 82, hash=0xb85a3b29 FullOpts
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
*************** Starting PHASE Importation
*************** In impImport() for Stack`1:Pop():RefAsValueType`1:this
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Stack`1:Pop():RefAsValueType`1:this'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldfld 0A000254
[ 1] 6 (0x006) ldc.i4.1 1
[ 2] 7 (0x007) sub
[ 1] 8 (0x008) stloc.0
STMT00000 (IL 0x000... ???)
[000005] -A-XG------- * ASG int
[000004] D------N---- +--* LCL_VAR int V01 loc0
[000003] ---XG------- \--* SUB int
[000001] ---XG------- +--* FIELD int _size
[000000] ------------ | \--* LCL_VAR ref V00 this
[000002] ------------ \--* CNS_INT int 1
[ 0] 9 (0x009) ldarg.0
[ 1] 10 (0x00a) ldfld 0A000253
[ 1] 15 (0x00f) stloc.1Querying runtime about current class of field Stack`1._array (declared as (null))
Field's current class not available
STMT00001 (IL 0x009... ???)
[000009] -A-XG------- * ASG ref
[000008] D------N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG------- \--* FIELD ref _array
[000006] ------------ \--* LCL_VAR ref V00 this
[ 0] 16 (0x010) ldloc.0
[ 1] 17 (0x011) ldloc.1
[ 2] 18 (0x012) ldlen
[ 2] 19 (0x013) conv.i4
[ 2] 20 (0x014) blt.un.s
STMT00002 (IL 0x010... ???)
[000014] ---X-------- * JTRUE void
[000013] N--X-----U-- \--* LT int
[000010] ------------ +--* LCL_VAR int V01 loc0
[000012] ---X-------- \--* ARR_LENGTH int
[000011] ------------ \--* LCL_VAR ref V02 loc1
impImportBlockPending for BB02
impImportBlockPending for BB03
Importing BB03 (PC=028) of 'Stack`1:Pop():RefAsValueType`1:this'
[ 0] 28 (0x01c) ldarg.0
[ 1] 29 (0x01d) ldarg.0
[ 2] 30 (0x01e) ldfld 0A000255
[ 2] 35 (0x023) ldc.i4.1 1
[ 3] 36 (0x024) add
[ 2] 37 (0x025) stfld 0A000255
STMT00003 (IL 0x01C... ???)
[000021] -A-XG------- * ASG int
[000020] ---XG--N---- +--* FIELD int _version
[000015] ------------ | \--* LCL_VAR ref V00 this
[000019] ---XG------- \--* ADD int
[000017] ---XG------- +--* FIELD int _version
[000016] ------------ | \--* LCL_VAR ref V00 this
[000018] ------------ \--* CNS_INT int 1
[ 0] 42 (0x02a) ldarg.0
[ 1] 43 (0x02b) ldloc.0
[ 2] 44 (0x02c) stfld 0A000254
STMT00004 (IL 0x02A... ???)
[000025] -A-XG------- * ASG int
[000024] ---XG--N---- +--* FIELD int _size
[000022] ------------ | \--* LCL_VAR ref V00 this
[000023] ------------ \--* LCL_VAR int V01 loc0
[ 0] 49 (0x031) ldloc.1
[ 1] 50 (0x032) ldloc.0
[ 2] 51 (0x033) ldelem 1B000011
[ 1] 56 (0x038) stloc.2
STMT00005 (IL 0x031... ???)
[000033] -A-XG------- * ASG struct (copy)
[000031] D----------- +--* LCL_VAR struct<RefAsValueType`1, 4> V03 loc2
[000030] ---XG------- \--* OBJ struct<RefAsValueType`1, 4>
[000029] ---XG------- \--* ADDR byref
[000028] ---XG------- \--* INDEX struct
[000026] ------------ +--* LCL_VAR ref V02 loc1
[000027] ------------ \--* LCL_VAR int V01 loc0
[ 0] 57 (0x039) call 2B00000B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0
Named Intrinsic System.Runtime.CompilerServices.RuntimeHelpersIsReferenceOrContainsReferences: Not recognized
lvaGrabTemp returning 5 (V05 tmp0) called for impRuntimeLookup slot.
STMT00006 (IL 0x039... ???)
[000038] -A-X-------- * ASG int
[000037] D------N---- +--* LCL_VAR int V05 tmp0
[000036] #--X-------- \--* IND int
[000035] ------------ \--* LCL_VAR ref V00 this
lvaGrabTemp returning 6 (V06 tmp1) called for spilling Runtime Lookup tree.
STMT00007 (IL ???... ???)
[000063] -AC-G------- * ASG int
[000062] D------N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G------- \--* QMARK int
[000051] Q----------- if +--* NE int
[000047] n----------- | +--* IND int
[000046] ------------ | | \--* ADD int
[000044] #----------- | | +--* IND int
[000043] #----------- | | | \--* IND int
[000042] ------------ | | | \--* ADD int
[000040] ------------ | | | +--* LCL_VAR int V05 tmp0
[000041] ------------ | | | \--* CNS_INT int 32
[000045] ------------ | | \--* CNS_INT int 12
[000050] ------------ | \--* CNS_INT int 0
[000060] --C-G------- if \--* COLON int
[000049] --C-G------- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] ------------ arg0 | +--* LCL_VAR int V05 tmp0
[000048] ------------ arg1 | \--* CNS_INT(h) int 0x8283EB8 token
[000052] n----------- then \--* IND int
[000053] ------------ \--* ADD int
[000054] #----------- +--* IND int
[000055] #----------- | \--* IND int
[000056] ------------ | \--* ADD int
[000057] ------------ | +--* LCL_VAR int V05 tmp0
[000058] ------------ | \--* CNS_INT int 32
[000059] ------------ \--* CNS_INT int 12
STMT00008 (IL ???... ???)
[000034] I-C-G------- * CALL int RuntimeHelpers.IsReferenceOrContainsReferences (exactContextHnd=0x0825B810)
[000065] ------------ arg0 \--* RUNTIMELOOKUP int 0x825b854 method
[000064] ------------ \--* LCL_VAR int V06 tmp1
[ 1] 62 (0x03e) brfalse.s
STMT00009 (IL ???... ???)
[000069] --C--------- * JTRUE void
[000068] --C--------- \--* EQ int
[000066] --C--------- +--* RET_EXPR int (inl return from call [000034])
[000067] ------------ \--* CNS_INT int 0
impImportBlockPending for BB04
impImportBlockPending for BB05
Importing BB05 (PC=080) of 'Stack`1:Pop():RefAsValueType`1:this'
[ 0] 80 (0x050) ldloc.2
[ 1] 81 (0x051) ret
impFixupStructReturnType: retyping
[000070] ------------ * LCL_VAR struct<RefAsValueType`1, 4> V03 loc2
impFixupStructReturnType: result of retyping is
[000070] ------------ * LCL_FLD ref V03 loc2 [+0]
STMT00010 (IL 0x050... ???)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_FLD ref V03 loc2 [+0]
Importing BB04 (PC=064) of 'Stack`1:Pop():RefAsValueType`1:this'
[ 0] 64 (0x040) ldloc.1
[ 1] 65 (0x041) ldloc.0
[ 2] 66 (0x042) ldloca.s 3
[ 3] 68 (0x044) initobj 1B000011
STMT00011 (IL 0x040... ???)
[000077] IA---------- * ASG struct (init)
[000074] D------N---- +--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
[000076] ------------ \--* CNS_INT int 0
[ 2] 74 (0x04a) ldloc.3
[ 3] 75 (0x04b) stelem 1B000011
STMT00012 (IL ???... ???)
[000081] -A-XG------- * ASG struct (copy)
[000079] ---XG------- +--* INDEX struct
[000072] ------------ | +--* LCL_VAR ref V02 loc1
[000073] ------------ | \--* LCL_VAR int V01 loc0
[000078] ------------ \--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
impImportBlockPending for BB05
Importing BB02 (PC=022) of 'Stack`1:Pop():RefAsValueType`1:this'
[ 0] 22 (0x016) ldarg.0
[ 1] 23 (0x017) call 0A000259
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
STMT00013 (IL 0x016... ???)
[000083] I-C-G------- * CALL void Stack`1.ThrowForEmptyStack (exactContextHnd=0x0825A8A0)
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
impImportBlockPending for BB03
*************** Finishing PHASE Importation
*************** Starting PHASE Indirect call transform
*************** in fgTransformIndirectCalls(root)
-- no candidates to transform
*************** Finishing PHASE Indirect call transform
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import
*************** Starting PHASE Morph - Init
New BlockSet epoch 1, # of blocks (including unused BB00): 6, bitset array size: 1 (short)
*************** Finishing PHASE Morph - Init
*************** In fgDebugCheckBBlist
*************** Starting PHASE Morph - Inlining
*************** In fgInline()
Querying runtime about current class of field Stack`1._array (declared as (null))
Field's current class not available
Expanding INLINE_CANDIDATE in statement STMT00013 in BB02:
STMT00013 (IL 0x016...0x017)
[000083] I-C-G------- * CALL void Stack`1.ThrowForEmptyStack (exactContextHnd=0x0825A8A0)
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
thisArg: is a local var
[000082] ------------ * LCL_VAR ref V00 this
INLINER: inlineInfo.tokenLookupContextHandle for Stack`1:ThrowForEmptyStack():this set to 0x0825A8A0:
Invoking compiler for the inlinee method Stack`1:ThrowForEmptyStack():this :
IL to import:
IL_0000 28 16 00 00 06 call 0x6000016
IL_0005 73 51 00 00 0a newobj 0xA000051
IL_000a 7a throw
INLINER impTokenLookupContextHandle for Stack`1:ThrowForEmptyStack():this is 0x0825A8A0.
*************** In fgFindBasicBlocks() for Stack`1:ThrowForEmptyStack():this
Jump targets:
none
New Basic Block BB06 [0005] created.
BB06 [000..00B)
Basic block list for 'Stack`1:ThrowForEmptyStack():this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB06 [0005] 1 0 [000..00B) (throw ) rare
-----------------------------------------------------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'Stack`1:Pop():RefAsValueType`1:this' calling 'Stack`1:ThrowForEmptyStack():this'
INLINER: during 'fgInline' result 'failed this callee' reason 'does not return'
Expanding INLINE_CANDIDATE in statement STMT00008 in BB03:
STMT00008 (IL ???... ???)
[000034] I-C-G------- * CALL int RuntimeHelpers.IsReferenceOrContainsReferences (exactContextHnd=0x0825B810)
[000065] ------------ arg0 \--* RUNTIMELOOKUP int 0x825b854 method
[000064] ------------ \--* LCL_VAR int V06 tmp1
INLINER: inlineInfo.tokenLookupContextHandle for RuntimeHelpers:IsReferenceOrContainsReferences():bool set to 0x0825B810:
Invoking compiler for the inlinee method RuntimeHelpers:IsReferenceOrContainsReferences():bool :
IL to import:
IL_0000 17 ldc.i4.1
IL_0001 2a ret
INLINER impTokenLookupContextHandle for RuntimeHelpers:IsReferenceOrContainsReferences():bool is 0x0825B810.
*************** In fgFindBasicBlocks() for RuntimeHelpers:IsReferenceOrContainsReferences():bool
Jump targets:
none
New Basic Block BB07 [0005] created.
BB07 [000..002)
Basic block list for 'RuntimeHelpers:IsReferenceOrContainsReferences():bool'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB07 [0005] 1 1 [000..002) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Inline @[000034] Starting PHASE Pre-import
*************** Inline @[000034] Finishing PHASE Pre-import
*************** Inline @[000034] Starting PHASE Importation
*************** In impImport() for RuntimeHelpers:IsReferenceOrContainsReferences():bool
impImportBlockPending for BB07
Importing BB07 (PC=000) of 'RuntimeHelpers:IsReferenceOrContainsReferences():bool'
[ 0] 0 (0x000) ldc.i4.1 1
[ 1] 1 (0x001) ret
Inlinee Return expression (before normalization) =>
[000084] ------------ * CNS_INT int 1
Inlinee Return expression (after normalization) =>
[000085] ------------ * CAST int <- bool <- int
[000084] ------------ \--* CNS_INT int 1
** Note: inlinee IL was partially imported -- imported 0 of 2 bytes of method IL
*************** Inline @[000034] Finishing PHASE Importation
*************** Inline @[000034] Starting PHASE Indirect call transform
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
*************** Inline @[000034] Finishing PHASE Indirect call transform
*************** Inline @[000034] Starting PHASE Post-import
*************** Inline @[000034] Finishing PHASE Post-import
----------- Statements (and blocks) added due to the inlining of call [000034] -----------
Inlinee method body:Inlinee ignores runtime lookup generics context
fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000034] is
[000085] ------------ * CAST int <- bool <- int
[000084] ------------ \--* CNS_INT int 1
Successfully inlined RuntimeHelpers:IsReferenceOrContainsReferences():bool (2 IL bytes) (depth 1) [below ALWAYS_INLINE size]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Stack`1:Pop():RefAsValueType`1:this' calling 'RuntimeHelpers:IsReferenceOrContainsReferences():bool'
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size'
Folding operator with constant nodes into a constant:
[000085] ------------ * CAST int <- bool <- int
[000084] ------------ \--* CNS_INT int 1
Bashed to int constant:
[000085] ------------ * CNS_INT int 1
Replacing the return expression placeholder [000066] with [000085]
[000066] --C--------- * RET_EXPR int (inl return from call [000085])
Inserting the inline return expression
[000085] ------------ * CNS_INT int 1
Folding operator with constant nodes into a constant:
[000068] --C--------- * EQ int
[000085] ------------ +--* CNS_INT int 1
[000067] ------------ \--* CNS_INT int 0
Bashed to int constant:
[000068] ------------ * CNS_INT int 0
... found foldable jtrue at [000069] in BB03
*************** After fgInline()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i idxlen
BB02 [0001] 1 1 [016..01C) i
BB03 [0002] 2 1 [01C..040) i idxlen
BB04 [0003] 1 1 [040..050) i idxlen
BB05 [0004] 1 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01
STMT00000 (IL 0x000...0x008)
[000005] -A-XG------- * ASG int
[000004] D------N---- +--* LCL_VAR int V01 loc0
[000003] ---XG------- \--* SUB int
[000001] ---XG------- +--* FIELD int _size
[000000] ------------ | \--* LCL_VAR ref V00 this
[000002] ------------ \--* CNS_INT int 1
***** BB01
STMT00001 (IL 0x009...0x00F)
[000009] -A-XG------- * ASG ref
[000008] D------N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG------- \--* FIELD ref _array
[000006] ------------ \--* LCL_VAR ref V00 this
***** BB01
STMT00002 (IL 0x010...0x014)
[000014] ---X-------- * JTRUE void
[000013] N--X-----U-- \--* LT int
[000010] ------------ +--* LCL_VAR int V01 loc0
[000012] ---X-------- \--* ARR_LENGTH int
[000011] ------------ \--* LCL_VAR ref V02 loc1
------------ BB02 [016..01C), preds={} succs={BB03}
***** BB02
STMT00013 (IL 0x016...0x017)
[000083] --C-G------- * CALL void Stack`1.ThrowForEmptyStack
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
------------ BB03 [01C..040), preds={} succs={BB04}
***** BB03
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG------- * ASG int
[000020] ---XG--N---- +--* FIELD int _version
[000015] ------------ | \--* LCL_VAR ref V00 this
[000019] ---XG------- \--* ADD int
[000017] ---XG------- +--* FIELD int _version
[000016] ------------ | \--* LCL_VAR ref V00 this
[000018] ------------ \--* CNS_INT int 1
***** BB03
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG------- * ASG int
[000024] ---XG--N---- +--* FIELD int _size
[000022] ------------ | \--* LCL_VAR ref V00 this
[000023] ------------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00005 (IL 0x031...0x038)
[000033] -A-XG------- * ASG struct (copy)
[000031] D----------- +--* LCL_VAR struct<RefAsValueType`1, 4> V03 loc2
[000030] ---XG------- \--* OBJ struct<RefAsValueType`1, 4>
[000029] ---XG------- \--* ADDR byref
[000028] ---XG------- \--* INDEX struct
[000026] ------------ +--* LCL_VAR ref V02 loc1
[000027] ------------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00006 (IL 0x039...0x03E)
[000038] -A-X-------- * ASG int
[000037] D------N---- +--* LCL_VAR int V05 tmp0
[000036] #--X-------- \--* IND int
[000035] ------------ \--* LCL_VAR ref V00 this
***** BB03
STMT00007 (IL ???... ???)
[000063] -AC-G------- * ASG int
[000062] D------N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G------- \--* QMARK int
[000051] Q----------- if +--* NE int
[000047] n----------- | +--* IND int
[000046] ------------ | | \--* ADD int
[000044] #----------- | | +--* IND int
[000043] #----------- | | | \--* IND int
[000042] ------------ | | | \--* ADD int
[000040] ------------ | | | +--* LCL_VAR int V05 tmp0
[000041] ------------ | | | \--* CNS_INT int 32
[000045] ------------ | | \--* CNS_INT int 12
[000050] ------------ | \--* CNS_INT int 0
[000060] --C-G------- if \--* COLON int
[000049] --C-G------- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] ------------ arg0 | +--* LCL_VAR int V05 tmp0
[000048] ------------ arg1 | \--* CNS_INT(h) int 0x8283EB8 token
[000052] n----------- then \--* IND int
[000053] ------------ \--* ADD int
[000054] #----------- +--* IND int
[000055] #----------- | \--* IND int
[000056] ------------ | \--* ADD int
[000057] ------------ | +--* LCL_VAR int V05 tmp0
[000058] ------------ | \--* CNS_INT int 32
[000059] ------------ \--* CNS_INT int 12
***** BB03
STMT00009 (IL ???... ???)
[000069] ------------ * NOP void
------------ BB04 [040..050), preds={} succs={BB05}
***** BB04
STMT00011 (IL 0x040...0x045)
[000077] IA---------- * ASG struct (init)
[000074] D------N---- +--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
[000076] ------------ \--* CNS_INT int 0
***** BB04
STMT00012 (IL ???...0x04B)
[000081] -A-XG------- * ASG struct (copy)
[000079] ---XG------- +--* INDEX struct
[000072] ------------ | +--* LCL_VAR ref V02 loc1
[000073] ------------ | \--* LCL_VAR int V01 loc0
[000078] ------------ \--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
------------ BB05 [050..052) (return), preds={} succs={}
***** BB05
STMT00010 (IL 0x050...0x051)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_FLD ref V03 loc2 [+0]
-------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
**************** Inline Tree
Inlines into 0600029B Stack`1:Pop():RefAsValueType`1:this
[0 IL=0023 TR=000083 060002A0] [FAILED: does not return] Stack`1:ThrowForEmptyStack():this
[1 IL=0057 TR=000034 06003C89] [below ALWAYS_INLINE size] RuntimeHelpers:IsReferenceOrContainsReferences():bool
Budget: initialTime=306, finalTime=292, initialBudget=3060, currentBudget=3060
Budget: initialSize=2000, finalSize=2000
*************** Finishing PHASE Morph - Inlining
Trees before Allocate Objects
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i idxlen
BB02 [0001] 1 1 [016..01C) i
BB03 [0002] 2 1 [01C..040) i idxlen
BB04 [0003] 1 1 [040..050) i idxlen
BB05 [0004] 1 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01
STMT00000 (IL 0x000...0x008)
[000005] -A-XG------- * ASG int
[000004] D------N---- +--* LCL_VAR int V01 loc0
[000003] ---XG------- \--* SUB int
[000001] ---XG------- +--* FIELD int _size
[000000] ------------ | \--* LCL_VAR ref V00 this
[000002] ------------ \--* CNS_INT int 1
***** BB01
STMT00001 (IL 0x009...0x00F)
[000009] -A-XG------- * ASG ref
[000008] D------N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG------- \--* FIELD ref _array
[000006] ------------ \--* LCL_VAR ref V00 this
***** BB01
STMT00002 (IL 0x010...0x014)
[000014] ---X-------- * JTRUE void
[000013] N--X-----U-- \--* LT int
[000010] ------------ +--* LCL_VAR int V01 loc0
[000012] ---X-------- \--* ARR_LENGTH int
[000011] ------------ \--* LCL_VAR ref V02 loc1
------------ BB02 [016..01C), preds={} succs={BB03}
***** BB02
STMT00013 (IL 0x016...0x017)
[000083] --C-G------- * CALL void Stack`1.ThrowForEmptyStack
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
------------ BB03 [01C..040), preds={} succs={BB04}
***** BB03
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG------- * ASG int
[000020] ---XG--N---- +--* FIELD int _version
[000015] ------------ | \--* LCL_VAR ref V00 this
[000019] ---XG------- \--* ADD int
[000017] ---XG------- +--* FIELD int _version
[000016] ------------ | \--* LCL_VAR ref V00 this
[000018] ------------ \--* CNS_INT int 1
***** BB03
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG------- * ASG int
[000024] ---XG--N---- +--* FIELD int _size
[000022] ------------ | \--* LCL_VAR ref V00 this
[000023] ------------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00005 (IL 0x031...0x038)
[000033] -A-XG------- * ASG struct (copy)
[000031] D----------- +--* LCL_VAR struct<RefAsValueType`1, 4> V03 loc2
[000030] ---XG------- \--* OBJ struct<RefAsValueType`1, 4>
[000029] ---XG------- \--* ADDR byref
[000028] ---XG------- \--* INDEX struct
[000026] ------------ +--* LCL_VAR ref V02 loc1
[000027] ------------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00006 (IL 0x039...0x03E)
[000038] -A-X-------- * ASG int
[000037] D------N---- +--* LCL_VAR int V05 tmp0
[000036] #--X-------- \--* IND int
[000035] ------------ \--* LCL_VAR ref V00 this
***** BB03
STMT00007 (IL ???... ???)
[000063] -AC-G------- * ASG int
[000062] D------N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G------- \--* QMARK int
[000051] Q----------- if +--* NE int
[000047] n----------- | +--* IND int
[000046] ------------ | | \--* ADD int
[000044] #----------- | | +--* IND int
[000043] #----------- | | | \--* IND int
[000042] ------------ | | | \--* ADD int
[000040] ------------ | | | +--* LCL_VAR int V05 tmp0
[000041] ------------ | | | \--* CNS_INT int 32
[000045] ------------ | | \--* CNS_INT int 12
[000050] ------------ | \--* CNS_INT int 0
[000060] --C-G------- if \--* COLON int
[000049] --C-G------- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] ------------ arg0 | +--* LCL_VAR int V05 tmp0
[000048] ------------ arg1 | \--* CNS_INT(h) int 0x8283EB8 token
[000052] n----------- then \--* IND int
[000053] ------------ \--* ADD int
[000054] #----------- +--* IND int
[000055] #----------- | \--* IND int
[000056] ------------ | \--* ADD int
[000057] ------------ | +--* LCL_VAR int V05 tmp0
[000058] ------------ | \--* CNS_INT int 32
[000059] ------------ \--* CNS_INT int 12
***** BB03
STMT00009 (IL ???... ???)
[000069] ------------ * NOP void
------------ BB04 [040..050), preds={} succs={BB05}
***** BB04
STMT00011 (IL 0x040...0x045)
[000077] IA---------- * ASG struct (init)
[000074] D------N---- +--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
[000076] ------------ \--* CNS_INT int 0
***** BB04
STMT00012 (IL ???...0x04B)
[000081] -A-XG------- * ASG struct (copy)
[000079] ---XG------- +--* INDEX struct
[000072] ------------ | +--* LCL_VAR ref V02 loc1
[000073] ------------ | \--* LCL_VAR int V01 loc0
[000078] ------------ \--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
------------ BB05 [050..052) (return), preds={} succs={}
***** BB05
STMT00010 (IL 0x050...0x051)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_FLD ref V03 loc2 [+0]
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Allocate Objects
*** ObjectAllocationPhase: no newobjs in this method; punting
*************** Finishing PHASE Allocate Objects
Trees after Allocate Objects
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i idxlen
BB02 [0001] 1 1 [016..01C) i
BB03 [0002] 2 1 [01C..040) i idxlen
BB04 [0003] 1 1 [040..050) i idxlen
BB05 [0004] 1 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01
STMT00000 (IL 0x000...0x008)
[000005] -A-XG------- * ASG int
[000004] D------N---- +--* LCL_VAR int V01 loc0
[000003] ---XG------- \--* SUB int
[000001] ---XG------- +--* FIELD int _size
[000000] ------------ | \--* LCL_VAR ref V00 this
[000002] ------------ \--* CNS_INT int 1
***** BB01
STMT00001 (IL 0x009...0x00F)
[000009] -A-XG------- * ASG ref
[000008] D------N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG------- \--* FIELD ref _array
[000006] ------------ \--* LCL_VAR ref V00 this
***** BB01
STMT00002 (IL 0x010...0x014)
[000014] ---X-------- * JTRUE void
[000013] N--X-----U-- \--* LT int
[000010] ------------ +--* LCL_VAR int V01 loc0
[000012] ---X-------- \--* ARR_LENGTH int
[000011] ------------ \--* LCL_VAR ref V02 loc1
------------ BB02 [016..01C), preds={} succs={BB03}
***** BB02
STMT00013 (IL 0x016...0x017)
[000083] --C-G------- * CALL void Stack`1.ThrowForEmptyStack
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
------------ BB03 [01C..040), preds={} succs={BB04}
***** BB03
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG------- * ASG int
[000020] ---XG--N---- +--* FIELD int _version
[000015] ------------ | \--* LCL_VAR ref V00 this
[000019] ---XG------- \--* ADD int
[000017] ---XG------- +--* FIELD int _version
[000016] ------------ | \--* LCL_VAR ref V00 this
[000018] ------------ \--* CNS_INT int 1
***** BB03
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG------- * ASG int
[000024] ---XG--N---- +--* FIELD int _size
[000022] ------------ | \--* LCL_VAR ref V00 this
[000023] ------------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00005 (IL 0x031...0x038)
[000033] -A-XG------- * ASG struct (copy)
[000031] D----------- +--* LCL_VAR struct<RefAsValueType`1, 4> V03 loc2
[000030] ---XG------- \--* OBJ struct<RefAsValueType`1, 4>
[000029] ---XG------- \--* ADDR byref
[000028] ---XG------- \--* INDEX struct
[000026] ------------ +--* LCL_VAR ref V02 loc1
[000027] ------------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00006 (IL 0x039...0x03E)
[000038] -A-X-------- * ASG int
[000037] D------N---- +--* LCL_VAR int V05 tmp0
[000036] #--X-------- \--* IND int
[000035] ------------ \--* LCL_VAR ref V00 this
***** BB03
STMT00007 (IL ???... ???)
[000063] -AC-G------- * ASG int
[000062] D------N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G------- \--* QMARK int
[000051] Q----------- if +--* NE int
[000047] n----------- | +--* IND int
[000046] ------------ | | \--* ADD int
[000044] #----------- | | +--* IND int
[000043] #----------- | | | \--* IND int
[000042] ------------ | | | \--* ADD int
[000040] ------------ | | | +--* LCL_VAR int V05 tmp0
[000041] ------------ | | | \--* CNS_INT int 32
[000045] ------------ | | \--* CNS_INT int 12
[000050] ------------ | \--* CNS_INT int 0
[000060] --C-G------- if \--* COLON int
[000049] --C-G------- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] ------------ arg0 | +--* LCL_VAR int V05 tmp0
[000048] ------------ arg1 | \--* CNS_INT(h) int 0x8283EB8 token
[000052] n----------- then \--* IND int
[000053] ------------ \--* ADD int
[000054] #----------- +--* IND int
[000055] #----------- | \--* IND int
[000056] ------------ | \--* ADD int
[000057] ------------ | +--* LCL_VAR int V05 tmp0
[000058] ------------ | \--* CNS_INT int 32
[000059] ------------ \--* CNS_INT int 12
***** BB03
STMT00009 (IL ???... ???)
[000069] ------------ * NOP void
------------ BB04 [040..050), preds={} succs={BB05}
***** BB04
STMT00011 (IL 0x040...0x045)
[000077] IA---------- * ASG struct (init)
[000074] D------N---- +--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
[000076] ------------ \--* CNS_INT int 0
***** BB04
STMT00012 (IL ???...0x04B)
[000081] -A-XG------- * ASG struct (copy)
[000079] ---XG------- +--* INDEX struct
[000072] ------------ | +--* LCL_VAR ref V02 loc1
[000073] ------------ | \--* LCL_VAR int V01 loc0
[000078] ------------ \--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
------------ BB05 [050..052) (return), preds={} succs={}
***** BB05
STMT00010 (IL 0x050...0x051)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_FLD ref V03 loc2 [+0]
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i idxlen
BB02 [0001] 1 1 [016..01C) i
BB03 [0002] 2 1 [01C..040) i idxlen
BB04 [0003] 1 1 [040..050) i idxlen
BB05 [0004] 1 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try
*************** Starting PHASE Remove empty finally
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally
*************** Starting PHASE Merge callfinally chains
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains
*************** Starting PHASE Clone finally
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally
*************** Starting PHASE Compute preds
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i idxlen
BB02 [0001] 1 1 [016..01C) i
BB03 [0002] 2 1 [01C..040) i idxlen
BB04 [0003] 1 1 [040..050) i idxlen
BB05 [0004] 1 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
New BlockSet epoch 2, # of blocks (including unused BB00): 6, bitset array size: 1 (short)
*************** In fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i idxlen
BB02 [0001] 1 1 [016..01C) i
BB03 [0002] 2 1 [01C..040) i idxlen
BB04 [0003] 1 1 [040..050) i idxlen
BB05 [0004] 1 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 1 [016..01C) i
BB03 [0002] 2 BB01,BB02 1 [01C..040) i label target idxlen
BB04 [0003] 1 BB03 1 [040..050) i idxlen
BB05 [0004] 1 BB04 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Compute preds
*************** Starting PHASE Update flow graph early pass
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 1 [016..01C) i
BB03 [0002] 2 BB01,BB02 1 [01C..040) i label target idxlen
BB04 [0003] 1 BB03 1 [040..050) i idxlen
BB05 [0004] 1 BB04 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
Compacting blocks BB03 and BB04:
*************** In fgDebugCheckBBlist
Compacting blocks BB03 and BB05:
*************** In fgDebugCheckBBlist
After updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 1 [016..01C) i
BB03 [0002] 2 BB01,BB02 1 [01C..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Update flow graph early pass
*************** Starting PHASE Morph - Promote Structs
*************** In fgPromoteStructs()
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 int
; V02 loc1 ref class-hnd
; V03 loc2 struct ( 4)
; V04 loc3 struct ( 4) ld-addr-op
; V05 tmp0 int "impRuntimeLookup slot"
; V06 tmp1 int "spilling Runtime Lookup tree"
Promoting struct local V03 (RefAsValueType`1):
lvaGrabTemp returning 7 (V07 tmp2) (a long lifetime temp) called for field V03.Value (fldOffset=0x0).
Promoting struct local V04 (RefAsValueType`1):
lvaGrabTemp returning 8 (V08 tmp3) (a long lifetime temp) called for field V04.Value (fldOffset=0x0).
lvaTable after fgPromoteStructs
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 int
; V02 loc1 ref class-hnd
; V03 loc2 struct ( 4)
; V04 loc3 struct ( 4) ld-addr-op
; V05 tmp0 int "impRuntimeLookup slot"
; V06 tmp1 int "spilling Runtime Lookup tree"
; V07 tmp2 ref V03.Value(offs=0x00) P-INDEP "field V03.Value (fldOffset=0x0)"
; V08 tmp3 ref V04.Value(offs=0x00) P-INDEP "field V04.Value (fldOffset=0x0)"
*************** Finishing PHASE Morph - Promote Structs
*************** Starting PHASE Morph - Structs/AddrExp
*************** In fgMarkAddressExposedLocals()
LocalAddressVisitor visiting statement:
STMT00000 (IL 0x000...0x008)
[000005] -A-XG------- * ASG int
[000004] D------N---- +--* LCL_VAR int V01 loc0
[000003] ---XG------- \--* SUB int
[000001] ---XG------- +--* FIELD int _size
[000000] ------------ | \--* LCL_VAR ref V00 this
[000002] ------------ \--* CNS_INT int 1
LocalAddressVisitor visiting statement:
STMT00001 (IL 0x009...0x00F)
[000009] -A-XG------- * ASG ref
[000008] D------N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG------- \--* FIELD ref _array
[000006] ------------ \--* LCL_VAR ref V00 this
LocalAddressVisitor visiting statement:
STMT00002 (IL 0x010...0x014)
[000014] ---X-------- * JTRUE void
[000013] N--X-----U-- \--* LT int
[000010] ------------ +--* LCL_VAR int V01 loc0
[000012] ---X-------- \--* ARR_LENGTH int
[000011] ------------ \--* LCL_VAR ref V02 loc1
LocalAddressVisitor visiting statement:
STMT00013 (IL 0x016...0x017)
[000083] --C-G------- * CALL void Stack`1.ThrowForEmptyStack
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
LocalAddressVisitor visiting statement:
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG------- * ASG int
[000020] ---XG--N---- +--* FIELD int _version
[000015] ------------ | \--* LCL_VAR ref V00 this
[000019] ---XG------- \--* ADD int
[000017] ---XG------- +--* FIELD int _version
[000016] ------------ | \--* LCL_VAR ref V00 this
[000018] ------------ \--* CNS_INT int 1
LocalAddressVisitor visiting statement:
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG------- * ASG int
[000024] ---XG--N---- +--* FIELD int _size
[000022] ------------ | \--* LCL_VAR ref V00 this
[000023] ------------ \--* LCL_VAR int V01 loc0
LocalAddressVisitor visiting statement:
STMT00005 (IL 0x031...0x038)
[000033] -A-XG------- * ASG struct (copy)
[000031] D----------- +--* LCL_VAR struct<RefAsValueType`1, 4>(P) V03 loc2
+--* ref V03.Value (offs=0x00) -> V07 tmp2
[000030] ---XG------- \--* OBJ struct<RefAsValueType`1, 4>
[000029] ---XG------- \--* ADDR byref
[000028] ---XG------- \--* INDEX struct
[000026] ------------ +--* LCL_VAR ref V02 loc1
[000027] ------------ \--* LCL_VAR int V01 loc0
LocalAddressVisitor visiting statement:
STMT00006 (IL 0x039...0x03E)
[000038] -A-X-------- * ASG int
[000037] D------N---- +--* LCL_VAR int V05 tmp0
[000036] #--X-------- \--* IND int
[000035] ------------ \--* LCL_VAR ref V00 this
LocalAddressVisitor visiting statement:
STMT00007 (IL ???... ???)
[000063] -AC-G------- * ASG int
[000062] D------N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G------- \--* QMARK int
[000051] Q----------- if +--* NE int
[000047] n----------- | +--* IND int
[000046] ------------ | | \--* ADD int
[000044] #----------- | | +--* IND int
[000043] #----------- | | | \--* IND int
[000042] ------------ | | | \--* ADD int
[000040] ------------ | | | +--* LCL_VAR int V05 tmp0
[000041] ------------ | | | \--* CNS_INT int 32
[000045] ------------ | | \--* CNS_INT int 12
[000050] ------------ | \--* CNS_INT int 0
[000060] --C-G------- if \--* COLON int
[000049] --C-G------- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] ------------ arg0 | +--* LCL_VAR int V05 tmp0
[000048] ------------ arg1 | \--* CNS_INT(h) int 0x8283EB8 token
[000052] n----------- then \--* IND int
[000053] ------------ \--* ADD int
[000054] #----------- +--* IND int
[000055] #----------- | \--* IND int
[000056] ------------ | \--* ADD int
[000057] ------------ | +--* LCL_VAR int V05 tmp0
[000058] ------------ | \--* CNS_INT int 32
[000059] ------------ \--* CNS_INT int 12
LocalAddressVisitor visiting statement:
STMT00009 (IL ???... ???)
[000069] ------------ * NOP void
LocalAddressVisitor visiting statement:
STMT00011 (IL 0x040...0x045)
[000077] IA---------- * ASG struct (init)
[000074] D------N---- +--* LCL_VAR struct<RefAsValueType`1, 4>(P) V04 loc3
+--* ref V04.Value (offs=0x00) -> V08 tmp3
[000076] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00012 (IL ???...0x04B)
[000081] -A-XG------- * ASG struct (copy)
[000079] ---XG------- +--* INDEX struct
[000072] ------------ | +--* LCL_VAR ref V02 loc1
[000073] ------------ | \--* LCL_VAR int V01 loc0
[000078] ------------ \--* LCL_VAR struct<RefAsValueType`1, 4>(P) V04 loc3
\--* ref V04.Value (offs=0x00) -> V08 tmp3
LocalAddressVisitor visiting statement:
STMT00010 (IL 0x050...0x051)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_FLD ref V03 loc2 [+0]
\--* ref V03.Value (offs=0x00) -> V07 tmp2
Replacing the GT_LCL_FLD in promoted struct with local var V07
LocalAddressVisitor modified statement:
STMT00010 (IL 0x050...0x051)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_VAR ref V07 tmp2
*************** Finishing PHASE Morph - Structs/AddrExp
*************** Starting PHASE Morph - ByRefs
*************** Finishing PHASE Morph - ByRefs
*************** Starting PHASE Morph - Global
*************** In fgMorphBlocks()
Morphing BB01 of 'Stack`1:Pop():RefAsValueType`1:this'
fgMorphTree BB01, STMT00000 (before)
[000005] -A-XG------- * ASG int
[000004] D------N---- +--* LCL_VAR int V01 loc0
[000003] ---XG------- \--* SUB int
[000001] ---XG------- +--* FIELD int _size
[000000] ------------ | \--* LCL_VAR ref V00 this
[000002] ------------ \--* CNS_INT int 1
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000001] ---XG------- * IND int
[000088] -----+------ \--* ADD byref
[000000] -----+------ +--* LCL_VAR ref V00 this
[000087] -----+------ \--* CNS_INT int 8 field offset Fseq[_size]
GenTreeNode creates assertion:
[000001] ---XG------- * IND int
In BB01 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001
fgMorphTree BB01, STMT00000 (after)
[000005] -A-XG+------ * ASG int
[000004] D----+-N---- +--* LCL_VAR int V01 loc0
[000003] ---XG+------ \--* ADD int
[000001] ---XG+------ +--* IND int
[000088] -----+------ | \--* ADD byref
[000000] -----+------ | +--* LCL_VAR ref V00 this
[000087] -----+------ | \--* CNS_INT int 8 field offset Fseq[_size]
[000002] -----+------ \--* CNS_INT int -1
fgMorphTree BB01, STMT00001 (before)
[000009] -A-XG------- * ASG ref
[000008] D------N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG------- \--* FIELD ref _array
[000006] ------------ \--* LCL_VAR ref V00 this
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000007] ---XG------- * IND ref
[000090] -----+------ \--* ADD byref
[000006] -----+------ +--* LCL_VAR ref V00 this
[000089] -----+------ \--* CNS_INT int 4 field offset Fseq[_array]
fgMorphTree BB01, STMT00001 (after)
[000009] -A-XG+------ * ASG ref
[000008] D----+-N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG+------ \--* IND ref
[000090] -----+------ \--* ADD byref
[000006] -----+------ +--* LCL_VAR ref V00 this
[000089] -----+------ \--* CNS_INT int 4 field offset Fseq[_array]
fgMorphTree BB01, STMT00002 (before)
[000014] ---X-------- * JTRUE void
[000013] N--X-----U-- \--* LT int
[000010] ------------ +--* LCL_VAR int V01 loc0
[000012] ---X-------- \--* ARR_LENGTH int
[000011] ------------ \--* LCL_VAR ref V02 loc1
GenTreeNode creates assertion:
[000012] ---X-------- * ARR_LENGTH int
In BB01 New Local Constant Assertion: V02 != null index=#02, mask=0000000000000002
Morphing BB02 of 'Stack`1:Pop():RefAsValueType`1:this'
fgMorphTree BB02, STMT00013 (before)
[000083] --C-G------- * CALL void Stack`1.ThrowForEmptyStack
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
Initializing arg info for 83.CALL:
ArgTable for 83.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 82.LCL_VAR ref, 1 reg: ecx, align=1]
Morphing args for 83.CALL:
Sorting the arguments:
Deferred argument ('ecx'):
[000082] -----+------ * LCL_VAR ref V00 this
Replaced with placeholder node:
[000091] ----------L- * ARGPLACE ref
Shuffled argument table: ecx
ArgTable for 83.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 82.LCL_VAR ref, 1 reg: ecx, align=1, lateArgInx=0, processed]
fgMorphTree BB02, STMT00013 (after)
[000083] --CXG+------ * CALL void Stack`1.ThrowForEmptyStack
[000082] -----+------ this in ecx \--* LCL_VAR ref V00 this
Converting BB02 to BBJ_THROW
Morphing BB03 of 'Stack`1:Pop():RefAsValueType`1:this'
fgMorphTree BB03, STMT00003 (before)
[000021] -A-XG------- * ASG int
[000020] ---XG--N---- +--* FIELD int _version
[000015] ------------ | \--* LCL_VAR ref V00 this
[000019] ---XG------- \--* ADD int
[000017] ---XG------- +--* FIELD int _version
[000016] ------------ | \--* LCL_VAR ref V00 this
[000018] ------------ \--* CNS_INT int 1
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000020] ---XG--N---- * IND int
[000093] -----+------ \--* ADD byref
[000015] -----+------ +--* LCL_VAR ref V00 this
[000092] -----+------ \--* CNS_INT int 12 field offset Fseq[_version]
GenTreeNode creates assertion:
[000020] ---XG--N---- * IND int
In BB03 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000017] ---XG------- * IND int
[000095] -----+------ \--* ADD byref
[000016] -----+------ +--* LCL_VAR ref V00 this
[000094] -----+------ \--* CNS_INT int 12 field offset Fseq[_version]
fgMorphTree BB03, STMT00003 (after)
[000021] -A-XG+------ * ASG int
[000020] ---XG+-N---- +--* IND int
[000093] -----+------ | \--* ADD byref
[000015] -----+------ | +--* LCL_VAR ref V00 this
[000092] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000019] ---XG+------ \--* ADD int
[000017] ---XG+------ +--* IND int
[000095] -----+------ | \--* ADD byref
[000016] -----+------ | +--* LCL_VAR ref V00 this
[000094] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000018] -----+------ \--* CNS_INT int 1
fgMorphTree BB03, STMT00004 (before)
[000025] -A-XG------- * ASG int
[000024] ---XG--N---- +--* FIELD int _size
[000022] ------------ | \--* LCL_VAR ref V00 this
[000023] ------------ \--* LCL_VAR int V01 loc0
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000024] ---XG--N---- * IND int
[000097] -----+------ \--* ADD byref
[000022] -----+------ +--* LCL_VAR ref V00 this
[000096] -----+------ \--* CNS_INT int 8 field offset Fseq[_size]
fgMorphTree BB03, STMT00004 (after)
[000025] -A-XG+------ * ASG int
[000024] ---XG+-N---- +--* IND int
[000097] -----+------ | \--* ADD byref
[000022] -----+------ | +--* LCL_VAR ref V00 this
[000096] -----+------ | \--* CNS_INT int 8 field offset Fseq[_size]
[000023] -----+------ \--* LCL_VAR int V01 loc0
fgMorphTree BB03, STMT00005 (before)
[000033] -A-XG------- * ASG struct (copy)
[000031] D----------- +--* LCL_VAR struct<RefAsValueType`1, 4>(P) V03 loc2
+--* ref V03.Value (offs=0x00) -> V07 tmp2
[000030] ---XG------- \--* OBJ struct<RefAsValueType`1, 4>
[000029] ---XG------- \--* ADDR byref
[000028] ---XG------- \--* INDEX struct
[000026] ------------ +--* LCL_VAR ref V02 loc1
[000027] ------------ \--* LCL_VAR int V01 loc0
GenTreeNode creates assertion:
[000100] ---X-------- * ARR_LENGTH int
In BB03 New Local Constant Assertion: V02 != null index=#02, mask=0000000000000002
fgMorphCopyBlock:block assignment to morph:
[000033] -A-XG------- * ASG struct (copy)
[000031] D----+-N---- +--* LCL_VAR struct<RefAsValueType`1, 4>(P) V03 loc2
+--* ref V03.Value (offs=0x00) -> V07 tmp2
[000030] ---XG+------ \--* OBJ struct<RefAsValueType`1, 4>
[000107] ---XG+------ \--* COMMA byref
[000101] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void
[000027] -----+------ | +--* LCL_VAR int V01 loc0
[000100] ---X-+------ | \--* ARR_LENGTH int
[000026] -----+------ | \--* LCL_VAR ref V02 loc1
[000108] ----G------- \--* ADDR byref
[000028] a---G+-N---- \--* IND struct
[000106] -----+------ \--* ADD byref
[000098] -----+------ +--* LCL_VAR ref V02 loc1
[000105] -----+------ \--* ADD int
[000103] -----+------ +--* LSH int
[000099] i----+------ | +--* LCL_VAR int V01 loc0
[000102] -----+-N---- | \--* CNS_INT int 2
[000104] -----+------ \--* CNS_INT int 8 Fseq[#FirstElem]
(destDoFldAsg=true) using field by field assignments.
fgAddFieldSeqForZeroOffset for Fseq[Value]
addr (Before)
[000110] ---XG------- COMMA byref
(After)
[000110] ---XG------- COMMA byref Zero Fseq[Value]
fgMorphCopyBlock (after):
[000125] -A-XG+------ * ASG ref
[000109] D------N---- +--* LCL_VAR ref V07 tmp2
[000124] ---XG------- \--* IND ref
[000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
[000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
[000113] ------------ | +--* LCL_VAR int V01 loc0
[000111] ---X-------- | \--* ARR_LENGTH int
[000112] ------------ | \--* LCL_VAR ref V02 loc1
[000115] ----G------- \--* ADDR byref
[000116] a---G--N---- \--* IND struct
[000117] ------------ \--* ADD byref
[000118] ------------ +--* LCL_VAR ref V02 loc1
[000119] ------------ \--* ADD int
[000120] ------------ +--* LSH int
[000121] i----------- | +--* LCL_VAR int V01 loc0
[000122] -------N---- | \--* CNS_INT int 2
[000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
fgMorphTree BB03, STMT00005 (after)
[000125] -A-XG+------ * ASG ref
[000109] D------N---- +--* LCL_VAR ref V07 tmp2
[000124] ---XG------- \--* IND ref
[000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
[000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
[000113] ------------ | +--* LCL_VAR int V01 loc0
[000111] ---X-------- | \--* ARR_LENGTH int
[000112] ------------ | \--* LCL_VAR ref V02 loc1
[000115] ----G------- \--* ADDR byref
[000116] a---G--N---- \--* IND struct
[000117] ------------ \--* ADD byref
[000118] ------------ +--* LCL_VAR ref V02 loc1
[000119] ------------ \--* ADD int
[000120] ------------ +--* LSH int
[000121] i----------- | +--* LCL_VAR int V01 loc0
[000122] -------N---- | \--* CNS_INT int 2
[000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
fgMorphTree BB03, STMT00006 (before)
[000038] -A-X-------- * ASG int
[000037] D------N---- +--* LCL_VAR int V05 tmp0
[000036] #--X-------- \--* IND int
[000035] ------------ \--* LCL_VAR ref V00 this
Non-null prop for index #01 in BB03:
[000036] #--X-------- * IND int
fgMorphTree BB03, STMT00007 (before)
[000063] -AC-G------- * ASG int
[000062] D------N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G------- \--* QMARK int
[000051] Q----------- if +--* NE int
[000047] n----------- | +--* IND int
[000046] ------------ | | \--* ADD int
[000044] #----------- | | +--* IND int
[000043] #----------- | | | \--* IND int
[000042] ------------ | | | \--* ADD int
[000040] ------------ | | | +--* LCL_VAR int V05 tmp0
[000041] ------------ | | | \--* CNS_INT int 32
[000045] ------------ | | \--* CNS_INT int 12
[000050] ------------ | \--* CNS_INT int 0
[000060] --C-G------- if \--* COLON int
[000049] --C-G------- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] ------------ arg0 | +--* LCL_VAR int V05 tmp0
[000048] ------------ arg1 | \--* CNS_INT(h) int 0x8283EB8 token
[000052] n----------- then \--* IND int
[000053] ------------ \--* ADD int
[000054] #----------- +--* IND int
[000055] #----------- | \--* IND int
[000056] ------------ | \--* ADD int
[000057] ------------ | +--* LCL_VAR int V05 tmp0
[000058] ------------ | \--* CNS_INT int 32
[000059] ------------ \--* CNS_INT int 12
Initializing arg info for 49.CALL:
ArgTable for 49.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 39.LCL_VAR int, 1 reg: ecx, align=1]
fgArgTabEntry[arg 1 48.CNS_INT int, 1 reg: edx, align=1]
Morphing args for 49.CALL:
Sorting the arguments:
Deferred argument ('ecx'):
[000039] -----+------ * LCL_VAR int V05 tmp0
Replaced with placeholder node:
[000126] ----------L- * ARGPLACE int
Deferred argument ('edx'):
[000048] -----+------ * CNS_INT(h) int 0x8283EB8 token
Replaced with placeholder node:
[000127] ----------L- * ARGPLACE int
Shuffled argument table: ecx edx
ArgTable for 49.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 39.LCL_VAR int, 1 reg: ecx, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 48.CNS_INT int, 1 reg: edx, align=1, lateArgInx=1, processed]
fgMorphTree BB03, STMT00007 (after)
[000063] -AC-G+------ * ASG int
[000062] D----+-N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G+------ \--* QMARK int
[000051] J----+-N---- if +--* NE int
[000047] n----+------ | +--* IND int
[000046] -----+------ | | \--* ADD int
[000044] #----+------ | | +--* IND int
[000043] #----+------ | | | \--* IND int
[000042] -----+------ | | | \--* ADD int
[000040] -----+------ | | | +--* LCL_VAR int V05 tmp0
[000041] -----+------ | | | \--* CNS_INT int 32
[000045] -----+------ | | \--* CNS_INT int 12
[000050] -----+------ | \--* CNS_INT int 0
[000060] --C-G+?----- if \--* COLON int
[000049] --C-G+?----- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] -----+?----- arg0 in ecx | +--* LCL_VAR int V05 tmp0
[000048] -----+?----- arg1 in edx | \--* CNS_INT(h) int 0x8283EB8 token
[000052] n----+?----- then \--* IND int
[000053] -----+?----- \--* ADD int
[000054] #----+?----- +--* IND int
[000055] #----+?----- | \--* IND int
[000056] -----+?----- | \--* ADD int
[000057] -----+?----- | +--* LCL_VAR int V05 tmp0
[000058] -----+?----- | \--* CNS_INT int 32
[000059] -----+?----- \--* CNS_INT int 12
fgMorphTree BB03, STMT00009 (before)
[000069] ------------ * NOP void
fgMorphTree BB03, STMT00011 (before)
[000077] IA---------- * ASG struct (init)
[000074] D------N---- +--* LCL_VAR struct<RefAsValueType`1, 4>(P) V04 loc3
+--* ref V04.Value (offs=0x00) -> V08 tmp3
[000076] ------------ \--* CNS_INT int 0
fgMorphInitBlock: using field by field initialization.
GenTreeNode creates assertion:
[000130] -A---------- * ASG ref
In BB03 New Local Constant Assertion: V08 == null index=#03, mask=0000000000000004
fgMorphInitBlock (after):
[000130] -A---+------ * ASG ref
[000128] D------N---- +--* LCL_VAR ref V08 tmp3
[000129] ------------ \--* CNS_INT ref null
The assignment [000130] using V08 removes: Constant Assertion: V08 == null
GenTreeNode creates assertion:
[000130] -A---+------ * ASG ref
In BB03 New Local Constant Assertion: V08 == null index=#03, mask=0000000000000004
fgMorphTree BB03, STMT00011 (after)
[000130] -A---+------ * ASG ref
[000128] D------N---- +--* LCL_VAR ref V08 tmp3
[000129] ------------ \--* CNS_INT ref null
fgMorphTree BB03, STMT00012 (before)
[000081] -A-XG------- * ASG struct (copy)
[000079] ---XG------- +--* INDEX struct
[000072] ------------ | +--* LCL_VAR ref V02 loc1
[000073] ------------ | \--* LCL_VAR int V01 loc0
[000078] ------------ \--* LCL_VAR struct<RefAsValueType`1, 4>(P) V04 loc3
\--* ref V04.Value (offs=0x00) -> V08 tmp3
fgMorphCopyBlock:block assignment to morph:
[000081] -A-XG------- * ASG struct (copy)
[000142] ---XG+------ +--* OBJ struct<RefAsValueType`1, 4>
[000140] ---XG+------ | \--* COMMA byref
[000134] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void
[000073] -----+------ | | +--* LCL_VAR int V01 loc0
[000133] ---X-+------ | | \--* ARR_LENGTH int
[000072] -----+------ | | \--* LCL_VAR ref V02 loc1
[000141] ---XG+------ | \--* ADDR byref
[000079] a--XG+------ | \--* IND struct
[000139] -----+------ | \--* ADD byref
[000131] -----+------ | +--* LCL_VAR ref V02 loc1
[000138] -----+------ | \--* ADD int
[000136] -----+------ | +--* LSH int
[000132] i----+------ | | +--* LCL_VAR int V01 loc0
[000135] -----+-N---- | | \--* CNS_INT int 2
[000137] -----+------ | \--* CNS_INT int 8 Fseq[#FirstElem]
[000078] -----+------ \--* LCL_VAR struct<RefAsValueType`1, 4>(P) V04 loc3
\--* ref V04.Value (offs=0x00) -> V08 tmp3
(srcDoFldAsg=true) using field by field assignments.
fgAddFieldSeqForZeroOffset for Fseq[Value]
addr (Before)
[000143] ---XG------- COMMA byref
(After)
[000143] ---XG------- COMMA byref Zero Fseq[Value]
fgMorphCopyBlock (after):
[000159] -A-XG+------ * ASG ref
[000157] *--XG--N---- +--* IND ref
[000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
[000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000146] ------------ | | +--* LCL_VAR int V01 loc0
[000144] ---X-------- | | \--* ARR_LENGTH int
[000145] ------------ | | \--* LCL_VAR ref V02 loc1
[000148] ---XG------- | \--* ADDR byref
[000149] a--XG------- | \--* IND struct
[000150] ------------ | \--* ADD byref
[000151] ------------ | +--* LCL_VAR ref V02 loc1
[000152] ------------ | \--* ADD int
[000153] ------------ | +--* LSH int
[000154] i----------- | | +--* LCL_VAR int V01 loc0
[000155] -------N---- | | \--* CNS_INT int 2
[000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
[000158] ------------ \--* LCL_VAR ref V08 tmp3
fgMorphTree BB03, STMT00012 (after)
[000159] -A-XG+------ * ASG ref
[000157] *--XG--N---- +--* IND ref
[000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
[000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000146] ------------ | | +--* LCL_VAR int V01 loc0
[000144] ---X-------- | | \--* ARR_LENGTH int
[000145] ------------ | | \--* LCL_VAR ref V02 loc1
[000148] ---XG------- | \--* ADDR byref
[000149] a--XG------- | \--* IND struct
[000150] ------------ | \--* ADD byref
[000151] ------------ | +--* LCL_VAR ref V02 loc1
[000152] ------------ | \--* ADD int
[000153] ------------ | +--* LSH int
[000154] i----------- | | +--* LCL_VAR int V01 loc0
[000155] -------N---- | | \--* CNS_INT int 2
[000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
[000158] ------------ \--* LCL_VAR ref V08 tmp3
fgMorphTree BB03, STMT00010 (before)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_VAR ref V07 tmp2
Expanding top-level qmark in BB03 (before)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB03 [0002] 1 BB01 1 [01C..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB03 [01C..052) (return), preds={BB01} succs={}
***** BB03
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG+------ * ASG int
[000020] ---XG+-N---- +--* IND int
[000093] -----+------ | \--* ADD byref
[000015] -----+------ | +--* LCL_VAR ref V00 this
[000092] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000019] ---XG+------ \--* ADD int
[000017] ---XG+------ +--* IND int
[000095] -----+------ | \--* ADD byref
[000016] -----+------ | +--* LCL_VAR ref V00 this
[000094] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000018] -----+------ \--* CNS_INT int 1
***** BB03
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG+------ * ASG int
[000024] ---XG+-N---- +--* IND int
[000097] -----+------ | \--* ADD byref
[000022] -----+------ | +--* LCL_VAR ref V00 this
[000096] -----+------ | \--* CNS_INT int 8 field offset Fseq[_size]
[000023] -----+------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00005 (IL 0x031...0x038)
[000125] -A-XG+------ * ASG ref
[000109] D------N---- +--* LCL_VAR ref V07 tmp2
[000124] ---XG------- \--* IND ref
[000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
[000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
[000113] ------------ | +--* LCL_VAR int V01 loc0
[000111] ---X-------- | \--* ARR_LENGTH int
[000112] ------------ | \--* LCL_VAR ref V02 loc1
[000115] ----G------- \--* ADDR byref
[000116] a---G--N---- \--* IND struct
[000117] ------------ \--* ADD byref
[000118] ------------ +--* LCL_VAR ref V02 loc1
[000119] ------------ \--* ADD int
[000120] ------------ +--* LSH int
[000121] i----------- | +--* LCL_VAR int V01 loc0
[000122] -------N---- | \--* CNS_INT int 2
[000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
***** BB03
STMT00006 (IL 0x039...0x03E)
[000038] -A---+------ * ASG int
[000037] D----+-N---- +--* LCL_VAR int V05 tmp0
[000036] #----+------ \--* IND int
[000035] -----+------ \--* LCL_VAR ref V00 this
***** BB03
STMT00007 (IL ???... ???)
[000063] -AC-G+------ * ASG int
[000062] D----+-N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G+------ \--* QMARK int
[000051] J----+-N---- if +--* NE int
[000047] n----+------ | +--* IND int
[000046] -----+------ | | \--* ADD int
[000044] #----+------ | | +--* IND int
[000043] #----+------ | | | \--* IND int
[000042] -----+------ | | | \--* ADD int
[000040] -----+------ | | | +--* LCL_VAR int V05 tmp0
[000041] -----+------ | | | \--* CNS_INT int 32
[000045] -----+------ | | \--* CNS_INT int 12
[000050] -----+------ | \--* CNS_INT int 0
[000060] --C-G+?----- if \--* COLON int
[000049] --C-G+?----- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] -----+?----- arg0 in ecx | +--* LCL_VAR int V05 tmp0
[000048] -----+?----- arg1 in edx | \--* CNS_INT(h) int 0x8283EB8 token
[000052] n----+?----- then \--* IND int
[000053] -----+?----- \--* ADD int
[000054] #----+?----- +--* IND int
[000055] #----+?----- | \--* IND int
[000056] -----+?----- | \--* ADD int
[000057] -----+?----- | +--* LCL_VAR int V05 tmp0
[000058] -----+?----- | \--* CNS_INT int 32
[000059] -----+?----- \--* CNS_INT int 12
***** BB03
STMT00011 (IL 0x040...0x045)
[000130] -A---+------ * ASG ref
[000128] D------N---- +--* LCL_VAR ref V08 tmp3
[000129] ------------ \--* CNS_INT ref null
***** BB03
STMT00012 (IL ???...0x04B)
[000159] -A-XG+------ * ASG ref
[000157] *--XG--N---- +--* IND ref
[000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
[000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000146] ------------ | | +--* LCL_VAR int V01 loc0
[000144] ---X-------- | | \--* ARR_LENGTH int
[000145] ------------ | | \--* LCL_VAR ref V02 loc1
[000148] ---XG------- | \--* ADDR byref
[000149] a--XG------- | \--* IND struct
[000150] ------------ | \--* ADD byref
[000151] ------------ | +--* LCL_VAR ref V02 loc1
[000152] ------------ | \--* ADD int
[000153] ------------ | +--* LSH int
[000154] i----------- | | +--* LCL_VAR int V01 loc0
[000155] -------N---- | | \--* CNS_INT int 2
[000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
[000158] ------------ \--* LCL_VAR ref V08 tmp3
***** BB03
STMT00010 (IL 0x050...0x051)
[000071] -----+------ * RETURN ref
[000070] -----+------ \--* LCL_VAR ref V07 tmp2
-------------------------------------------------------------------------------------------------------------------
New Basic Block BB06 [0006] created.
New Basic Block BB07 [0007] created.
New Basic Block BB08 [0008] created.
New Basic Block BB09 [0009] created.
Removing statement STMT00007 (IL ???... ???)
[000063] -AC-G+------ * ASG int
[000062] D----+-N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G+------ \--* QMARK int
[000051] J----+-N---- if +--* EQ int
[000047] n----+------ | +--* IND int
[000046] -----+------ | | \--* ADD int
[000044] #----+------ | | +--* IND int
[000043] #----+------ | | | \--* IND int
[000042] -----+------ | | | \--* ADD int
[000040] -----+------ | | | +--* LCL_VAR int V05 tmp0
[000041] -----+------ | | | \--* CNS_INT int 32
[000045] -----+------ | | \--* CNS_INT int 12
[000050] -----+------ | \--* CNS_INT int 0
[000060] --C-G+?----- if \--* COLON int
[000049] --C-G+?----- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] -----+?----- arg0 in ecx | +--* LCL_VAR int V05 tmp0
[000048] -----+?----- arg1 in edx | \--* CNS_INT(h) int 0x8283EB8 token
[000052] n----+?----- then \--* IND int
[000053] -----+?----- \--* ADD int
[000054] #----+?----- +--* IND int
[000055] #----+?----- | \--* IND int
[000056] -----+?----- | \--* ADD int
[000057] -----+?----- | +--* LCL_VAR int V05 tmp0
[000058] -----+?----- | \--* CNS_INT int 32
[000059] -----+?----- \--* CNS_INT int 12
in BB03 as useless:
Expanding top-level qmark in BB03 (after)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB03 [0002] 1 BB01 1 [01C..040) i label target idxlen
BB07 [0007] 1 BB03 1 [???..???)-> BB08 ( cond ) i
BB09 [0009] 1 BB07 0.50 [???..???)-> BB06 (always) i
BB08 [0008] 1 BB07 0.50 [???..???) i label target
BB06 [0006] 2 BB08,BB09 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB03 [01C..040), preds={BB01} succs={BB07}
***** BB03
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG+------ * ASG int
[000020] ---XG+-N---- +--* IND int
[000093] -----+------ | \--* ADD byref
[000015] -----+------ | +--* LCL_VAR ref V00 this
[000092] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000019] ---XG+------ \--* ADD int
[000017] ---XG+------ +--* IND int
[000095] -----+------ | \--* ADD byref
[000016] -----+------ | +--* LCL_VAR ref V00 this
[000094] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000018] -----+------ \--* CNS_INT int 1
***** BB03
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG+------ * ASG int
[000024] ---XG+-N---- +--* IND int
[000097] -----+------ | \--* ADD byref
[000022] -----+------ | +--* LCL_VAR ref V00 this
[000096] -----+------ | \--* CNS_INT int 8 field offset Fseq[_size]
[000023] -----+------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00005 (IL 0x031...0x038)
[000125] -A-XG+------ * ASG ref
[000109] D------N---- +--* LCL_VAR ref V07 tmp2
[000124] ---XG------- \--* IND ref
[000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
[000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
[000113] ------------ | +--* LCL_VAR int V01 loc0
[000111] ---X-------- | \--* ARR_LENGTH int
[000112] ------------ | \--* LCL_VAR ref V02 loc1
[000115] ----G------- \--* ADDR byref
[000116] a---G--N---- \--* IND struct
[000117] ------------ \--* ADD byref
[000118] ------------ +--* LCL_VAR ref V02 loc1
[000119] ------------ \--* ADD int
[000120] ------------ +--* LSH int
[000121] i----------- | +--* LCL_VAR int V01 loc0
[000122] -------N---- | \--* CNS_INT int 2
[000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
***** BB03
STMT00006 (IL 0x039...0x03E)
[000038] -A---+------ * ASG int
[000037] D----+-N---- +--* LCL_VAR int V05 tmp0
[000036] #----+------ \--* IND int
[000035] -----+------ \--* LCL_VAR ref V00 this
------------ BB07 [???..???) -> BB08 (cond), preds={BB03} succs={BB09,BB08}
***** BB07
STMT00014 (IL ???... ???)
[000160] ------------ * JTRUE void
[000051] J----+-N---- \--* EQ int
[000047] n----+------ +--* IND int
[000046] -----+------ | \--* ADD int
[000044] #----+------ | +--* IND int
[000043] #----+------ | | \--* IND int
[000042] -----+------ | | \--* ADD int
[000040] -----+------ | | +--* LCL_VAR int V05 tmp0
[000041] -----+------ | | \--* CNS_INT int 32
[000045] -----+------ | \--* CNS_INT int 12
[000050] -----+------ \--* CNS_INT int 0
------------ BB09 [???..???) -> BB06 (always), preds={BB07} succs={BB06}
***** BB09
STMT00015 (IL ???... ???)
[000162] -A---------- * ASG int
[000161] D------N---- +--* LCL_VAR int V06 tmp1
[000052] n----+?----- \--* IND int
[000053] -----+?----- \--* ADD int
[000054] #----+?----- +--* IND int
[000055] #----+?----- | \--* IND int
[000056] -----+?----- | \--* ADD int
[000057] -----+?----- | +--* LCL_VAR int V05 tmp0
[000058] -----+?----- | \--* CNS_INT int 32
[000059] -----+?----- \--* CNS_INT int 12
------------ BB08 [???..???), preds={BB07} succs={BB06}
***** BB08
STMT00016 (IL ???... ???)
[000164] -AC-G------- * ASG int
[000163] D------N---- +--* LCL_VAR int V06 tmp1
[000049] --C-G+?----- \--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] -----+?----- arg0 in ecx +--* LCL_VAR int V05 tmp0
[000048] -----+?----- arg1 in edx \--* CNS_INT(h) int 0x8283EB8 token
------------ BB06 [040..052) (return), preds={BB08,BB09} succs={}
***** BB06
STMT00011 (IL 0x040...0x045)
[000130] -A---+------ * ASG ref
[000128] D------N---- +--* LCL_VAR ref V08 tmp3
[000129] ------------ \--* CNS_INT ref null
***** BB06
STMT00012 (IL ???...0x04B)
[000159] -A-XG+------ * ASG ref
[000157] *--XG--N---- +--* IND ref
[000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
[000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000146] ------------ | | +--* LCL_VAR int V01 loc0
[000144] ---X-------- | | \--* ARR_LENGTH int
[000145] ------------ | | \--* LCL_VAR ref V02 loc1
[000148] ---XG------- | \--* ADDR byref
[000149] a--XG------- | \--* IND struct
[000150] ------------ | \--* ADD byref
[000151] ------------ | +--* LCL_VAR ref V02 loc1
[000152] ------------ | \--* ADD int
[000153] ------------ | +--* LSH int
[000154] i----------- | | +--* LCL_VAR int V01 loc0
[000155] -------N---- | | \--* CNS_INT int 2
[000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
[000158] ------------ \--* LCL_VAR ref V08 tmp3
***** BB06
STMT00010 (IL 0x050...0x051)
[000071] -----+------ * RETURN ref
[000070] -----+------ \--* LCL_VAR ref V07 tmp2
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Morph - Global
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie
*************** Starting PHASE Mark GC poll blocks
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare gcsafe
BB03 [0002] 1 BB01 1 [01C..040) i label target idxlen
BB07 [0007] 1 BB03 1 [???..???)-> BB08 ( cond ) i
BB09 [0009] 1 BB07 0.50 [???..???)-> BB06 (always) i
BB08 [0008] 1 BB07 0.50 [???..???) i label target
BB06 [0006] 2 BB08,BB09 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB07 to BB04
Renumber BB09 to BB05
Renumber BB08 to BB06
Renumber BB06 to BB07
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare gcsafe
BB03 [0002] 1 BB01 1 [01C..040) i label target idxlen
BB04 [0007] 1 BB03 1 [???..???)-> BB06 ( cond ) i
BB05 [0009] 1 BB04 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB04 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 3, # of blocks (including unused BB00): 8, bitset array size: 1 (short)
*************** Finishing PHASE Mark GC poll blocks
*************** Starting PHASE Compute edge weights (1, false)
*************** In fgComputeBlockAndEdgeWeights()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare gcsafe
BB03 [0002] 1 BB01 1 [01C..040) i label target idxlen
BB04 [0007] 1 BB03 1 [???..???)-> BB06 ( cond ) i
BB05 [0009] 1 BB04 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB04 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
fgComputeEdgeWeights() was able to compute exact edge weights for all of the 7 edges, using 1 passes.
Edge weights into BB02 :BB01 (0)
Edge weights into BB03 :BB01 (100)
Edge weights into BB04 :BB03 (100)
Edge weights into BB05 :BB04 (50)
Edge weights into BB06 :BB04 (50)
Edge weights into BB07 :BB06 (50), BB05 (50)
*************** Finishing PHASE Compute edge weights (1, false)
*************** Starting PHASE Merge throw blocks
*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.
*************** Finishing PHASE Merge throw blocks
*************** Starting PHASE Optimize layout
*************** In optOptimizeLayout()
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare gcsafe
BB03 [0002] 1 BB01 1 [01C..040) i label target idxlen
BB04 [0007] 1 BB03 1 [???..???)-> BB06 ( cond ) i
BB05 [0009] 1 BB04 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB04 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
Compacting blocks BB03 and BB04:
*************** In fgDebugCheckBBlist
After updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare gcsafe
BB03 [0002] 1 BB01 1 [01C..040)-> BB06 ( cond ) i label target idxlen
BB05 [0009] 1 BB03 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB03 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** In fgRelocateEHRegions()
*************** In fgReorderBlocks()
Initial BasicBlocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare gcsafe
BB03 [0002] 1 BB01 1 [01C..040)-> BB06 ( cond ) i label target idxlen
BB05 [0009] 1 BB03 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB03 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
Decided to reverse conditional branch at block BB01 branch to BB03 since it falls into a rarely run block
Relocated rarely run block BB02 by reversing conditional jump at BB01
Relocated block [BB02..BB02] inserted after BB07 at the end of method
After this change in fgReorderBlocks the BB graph is:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB02 ( cond ) i label target idxlen
BB03 [0002] 1 BB01 1 [01C..040)-> BB06 ( cond ) i label target idxlen
BB05 [0009] 1 BB03 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB03 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB02 ( cond ) i label target idxlen
BB03 [0002] 1 BB01 1 [01C..040)-> BB06 ( cond ) i label target idxlen
BB05 [0009] 1 BB03 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB03 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize layout
*************** Starting PHASE Compute blocks reachability
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB02 ( cond ) i label target idxlen
BB03 [0002] 1 BB01 1 [01C..040)-> BB06 ( cond ) i label target idxlen
BB05 [0009] 1 BB03 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB03 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB05 to BB03
Renumber BB06 to BB04
Renumber BB07 to BB05
Renumber BB02 to BB06
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.50 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.50 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 4, # of blocks (including unused BB00): 7, bitset array size: 1 (short)
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
BB02 : BB01 BB02
BB03 : BB01 BB02 BB03
BB04 : BB01 BB02 BB04
BB05 : BB01 BB02 BB03 BB04 BB05
BB06 : BB01 BB06
After computing reachability:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.50 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.50 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
BB02: BB02 BB01
BB03: BB03 BB02 BB01
BB04: BB04 BB02 BB01
BB05: BB05 BB02 BB01
BB06: BB06 BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB06 BB02
BB02 : BB05 BB04 BB03
After numbering the dominator tree:
BB01: pre=01, post=06
BB02: pre=03, post=05
BB03: pre=06, post=04
BB04: pre=05, post=03
BB05: pre=04, post=02
BB06: pre=02, post=01
*************** Finishing PHASE Compute blocks reachability
*************** Starting PHASE Optimize loops
*************** In optOptimizeLoops()
After optSetBlockWeights:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize loops
*************** Starting PHASE Clone loops
*************** In optCloneLoops()
*************** Finishing PHASE Clone loops
*************** Starting PHASE Unroll loops
*************** Finishing PHASE Unroll loops
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
*** marking local variables in block BB01 (weight=1 )
STMT00000 (IL 0x000...0x008)
[000005] -A-XG+------ * ASG int
[000004] D----+-N---- +--* LCL_VAR int V01 loc0
[000003] ---XG+------ \--* ADD int
[000001] ---XG+------ +--* IND int
[000088] -----+------ | \--* ADD byref
[000000] -----+------ | +--* LCL_VAR ref V00 this
[000087] -----+------ | \--* CNS_INT int 8 field offset Fseq[_size]
[000002] -----+------ \--* CNS_INT int -1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 1, refCntWtd = 1
STMT00001 (IL 0x009...0x00F)
[000009] -A-XG+------ * ASG ref
[000008] D----+-N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG+------ \--* IND ref
[000090] -----+------ \--* ADD byref
[000006] -----+------ +--* LCL_VAR ref V00 this
[000089] -----+------ \--* CNS_INT int 4 field offset Fseq[_array]
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 2, refCntWtd = 2
STMT00002 (IL 0x010...0x014)
[000014] ---X-+------ * JTRUE void
[000013] N--X-+-N-U-- \--* GE int
[000010] -----+------ +--* LCL_VAR int V01 loc0
[000012] ---X-+------ \--* ARR_LENGTH int
[000011] -----+------ \--* LCL_VAR ref V02 loc1
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 2, refCntWtd = 2
*** marking local variables in block BB02 (weight=1 )
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG+------ * ASG int
[000020] ---XG+-N---- +--* IND int
[000093] -----+------ | \--* ADD byref
[000015] -----+------ | +--* LCL_VAR ref V00 this
[000092] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000019] ---XG+------ \--* ADD int
[000017] ---XG+------ +--* IND int
[000095] -----+------ | \--* ADD byref
[000016] -----+------ | +--* LCL_VAR ref V00 this
[000094] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000018] -----+------ \--* CNS_INT int 1
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 4, refCntWtd = 4
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG+------ * ASG int
[000024] ---XG+-N---- +--* IND int
[000097] -----+------ | \--* ADD byref
[000022] -----+------ | +--* LCL_VAR ref V00 this
[000096] -----+------ | \--* CNS_INT int 8 field offset Fseq[_size]
[000023] -----+------ \--* LCL_VAR int V01 loc0
New refCnts for V00: refCnt = 5, refCntWtd = 5
New refCnts for V01: refCnt = 3, refCntWtd = 3
STMT00005 (IL 0x031...0x038)
[000125] -A-XG+------ * ASG ref
[000109] D------N---- +--* LCL_VAR ref V07 tmp2
[000124] ---XG------- \--* IND ref
[000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
[000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
[000113] ------------ | +--* LCL_VAR int V01 loc0
[000111] ---X-------- | \--* ARR_LENGTH int
[000112] ------------ | \--* LCL_VAR ref V02 loc1
[000115] ----G------- \--* ADDR byref
[000116] a---G--N---- \--* IND struct
[000117] ------------ \--* ADD byref
[000118] ------------ +--* LCL_VAR ref V02 loc1
[000119] ------------ \--* ADD int
[000120] ------------ +--* LSH int
[000121] i----------- | +--* LCL_VAR int V01 loc0
[000122] -------N---- | \--* CNS_INT int 2
[000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
New refCnts for V07: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 4, refCntWtd = 4
New refCnts for V02: refCnt = 3, refCntWtd = 3
New refCnts for V02: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 5, refCntWtd = 5
STMT00006 (IL 0x039...0x03E)
[000038] -A---+------ * ASG int
[000037] D----+-N---- +--* LCL_VAR int V05 tmp0
[000036] #----+------ \--* IND int
[000035] -----+------ \--* LCL_VAR ref V00 this
New refCnts for V05: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 6, refCntWtd = 6
STMT00014 (IL ???... ???)
[000160] ------------ * JTRUE void
[000051] J----+-N---- \--* EQ int
[000047] n----+------ +--* IND int
[000046] -----+------ | \--* ADD int
[000044] #----+------ | +--* IND int
[000043] #----+------ | | \--* IND int
[000042] -----+------ | | \--* ADD int
[000040] -----+------ | | +--* LCL_VAR int V05 tmp0
[000041] -----+------ | | \--* CNS_INT int 32
[000045] -----+------ | \--* CNS_INT int 12
[000050] -----+------ \--* CNS_INT int 0
New refCnts for V05: refCnt = 2, refCntWtd = 4
*** marking local variables in block BB03 (weight=0.25)
STMT00015 (IL ???... ???)
[000162] -A---------- * ASG int
[000161] D------N---- +--* LCL_VAR int V06 tmp1
[000052] n----+?----- \--* IND int
[000053] -----+?----- \--* ADD int
[000054] #----+?----- +--* IND int
[000055] #----+?----- | \--* IND int
[000056] -----+?----- | \--* ADD int
[000057] -----+?----- | +--* LCL_VAR int V05 tmp0
[000058] -----+?----- | \--* CNS_INT int 32
[000059] -----+?----- \--* CNS_INT int 12
New refCnts for V06: refCnt = 1, refCntWtd = 0.50
New refCnts for V05: refCnt = 3, refCntWtd = 4.50
*** marking local variables in block BB04 (weight=0.25)
STMT00016 (IL ???... ???)
[000164] -AC-G------- * ASG int
[000163] D------N---- +--* LCL_VAR int V06 tmp1
[000049] --C-G+?----- \--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] -----+?----- arg0 in ecx +--* LCL_VAR int V05 tmp0
[000048] -----+?----- arg1 in edx \--* CNS_INT(h) int 0x8283EB8 token
New refCnts for V06: refCnt = 2, refCntWtd = 1
New refCnts for V05: refCnt = 4, refCntWtd = 5
*** marking local variables in block BB05 (weight=1 )
STMT00011 (IL 0x040...0x045)
[000130] -A---+------ * ASG ref
[000128] D------N---- +--* LCL_VAR ref V08 tmp3
[000129] ------------ \--* CNS_INT ref null
New refCnts for V08: refCnt = 1, refCntWtd = 1
STMT00012 (IL ???...0x04B)
[000159] -A-XG+------ * ASG ref
[000157] *--XG--N---- +--* IND ref
[000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
[000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000146] ------------ | | +--* LCL_VAR int V01 loc0
[000144] ---X-------- | | \--* ARR_LENGTH int
[000145] ------------ | | \--* LCL_VAR ref V02 loc1
[000148] ---XG------- | \--* ADDR byref
[000149] a--XG------- | \--* IND struct
[000150] ------------ | \--* ADD byref
[000151] ------------ | +--* LCL_VAR ref V02 loc1
[000152] ------------ | \--* ADD int
[000153] ------------ | +--* LSH int
[000154] i----------- | | +--* LCL_VAR int V01 loc0
[000155] -------N---- | | \--* CNS_INT int 2
[000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
[000158] ------------ \--* LCL_VAR ref V08 tmp3
New refCnts for V01: refCnt = 6, refCntWtd = 6
New refCnts for V02: refCnt = 5, refCntWtd = 5
New refCnts for V02: refCnt = 6, refCntWtd = 6
New refCnts for V01: refCnt = 7, refCntWtd = 7
New refCnts for V08: refCnt = 2, refCntWtd = 2
STMT00010 (IL 0x050...0x051)
[000071] -----+------ * RETURN ref
[000070] -----+------ \--* LCL_VAR ref V07 tmp2
New refCnts for V07: refCnt = 2, refCntWtd = 2
*** marking local variables in block BB06 (weight=0 )
STMT00013 (IL 0x016...0x017)
[000083] --CXG+------ * CALL void Stack`1.ThrowForEmptyStack
[000082] -----+------ this in ecx \--* LCL_VAR ref V00 this
New refCnts for V00: refCnt = 7, refCntWtd = 6
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 8, refCntWtd = 7
New refCnts for V00: refCnt = 9, refCntWtd = 8
*************** In optAddCopies()
*************** Finishing PHASE Mark local vars
*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize bools
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 17 tree nodes
*************** Finishing PHASE Set block order
Trees before Build SSA representation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0
N006 ( 6, 6) [000003] ---XG------- \--* ADD int
N004 ( 4, 4) [000001] ---XG------- +--* IND int
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1
N004 ( 4, 4) [000007] ---XG------- \--* IND ref
N003 ( 2, 2) [000090] -------N---- \--* ADD byref
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array]
***** BB01
STMT00002 (IL 0x010...0x014)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int
N010 ( 4, 4) [000020] ---XG--N---- +--* IND int
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N006 ( 6, 6) [000019] ---XG------- \--* ADD int
N004 ( 4, 4) [000017] ---XG------- +--* IND int
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int
N004 ( 4, 4) [000024] ---XG--N---- +--* IND int
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0
***** BB02
STMT00005 (IL 0x031...0x038)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2
N015 ( 20, 22) [000124] ---XG------- \--* IND ref
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct
N011 ( 4, 4) [000117] -------N---- \--* ADD byref
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1
N010 ( 3, 3) [000119] -------N---- \--* ADD int
N008 ( 2, 2) [000120] -------N---- +--* LSH int
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0
N002 ( 3, 2) [000036] #----O------ \--* IND int
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int
N008 ( 10, 9) [000047] n----------- +--* IND int
N007 ( 8, 7) [000046] -------N---- | \--* ADD int
N005 ( 7, 6) [000044] #----------- | +--* IND int
N004 ( 4, 4) [000043] #----------- | | \--* IND int
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00015 (IL ???... ???)
N010 ( 14, 12) [000162] -A------R--- * ASG int
N009 ( 3, 2) [000161] D------N---- +--* LCL_VAR int V06 tmp1
N008 ( 10, 9) [000052] n-----?----- \--* IND int
N007 ( 8, 7) [000053] ------?N---- \--* ADD int
N005 ( 7, 6) [000054] #-----?----- +--* IND int
N004 ( 4, 4) [000055] #-----?----- | \--* IND int
N003 ( 2, 2) [000056] ------?N---- | \--* ADD int
N001 ( 1, 1) [000057] ------?----- | +--* LCL_VAR int V05 tmp0
N002 ( 1, 1) [000058] ------?----- | \--* CNS_INT int 32
N006 ( 1, 1) [000059] ------?----- \--* CNS_INT int 12
------------ BB04 [???..???), preds={BB02} succs={BB05}
***** BB04
STMT00016 (IL ???... ???)
N007 ( 20, 15) [000164] -AC-G---R--- * ASG int
N006 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V06 tmp1
N005 ( 16, 12) [000049] --C-G-?----- \--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000039] ------?----- arg0 in ecx +--* LCL_VAR int V05 tmp0
N004 ( 1, 4) [000048] ------?----- arg1 in edx \--* CNS_INT(h) int 0x8283EB8 token
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null
***** BB05
STMT00012 (IL ???...0x04B)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1
N013 ( 9, 9) [000148] ---XG------- | \--* ADDR byref
N012 ( 5, 5) [000149] a--XG------- | \--* IND struct
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1
N010 ( 3, 3) [000152] -------N---- | \--* ADD int
N008 ( 2, 2) [000153] -------N---- | +--* LSH int
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 7.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB06 BB02
BB02 : BB05 BB04 BB03
*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Tracked variable (7 out of 9) table:
V00 this [ ref]: refCnt = 9, refCntWtd = 8
V01 loc0 [ int]: refCnt = 7, refCntWtd = 7
V02 loc1 [ ref]: refCnt = 6, refCntWtd = 6
V05 tmp0 [ int]: refCnt = 4, refCntWtd = 5
V07 tmp2 [ ref]: refCnt = 2, refCntWtd = 2
V08 tmp3 [ ref]: refCnt = 2, refCntWtd = 2
V06 tmp1 [ int]: refCnt = 2, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 } + ByrefExposed + GcHeap
DEF(2)={ V01 V02}
BB02 USE(3)={V00 V01 V02 } + ByrefExposed + GcHeap
DEF(2)={ V05 V07} + ByrefExposed + GcHeap
BB03 USE(1)={V05 } + ByrefExposed + GcHeap
DEF(1)={ V06}
BB04 USE(1)={V05 }
DEF(1)={ V06}
BB05 USE(3)={V01 V02 V07 } + ByrefExposed + GcHeap
DEF(1)={ V08} + ByrefExposed + GcHeap
BB06 USE(1)={V00} + ByrefExposed + GcHeap
DEF(0)={ } + ByrefExposed* + GcHeap*
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00 } + ByrefExposed + GcHeap
OUT(3)={V00 V01 V02} + ByrefExposed + GcHeap
BB02 IN (3)={V00 V01 V02 } + ByrefExposed + GcHeap
OUT(4)={ V01 V02 V05 V07} + ByrefExposed + GcHeap
BB03 IN (4)={V01 V02 V05 V07} + ByrefExposed + GcHeap
OUT(3)={V01 V02 V07} + ByrefExposed + GcHeap
BB04 IN (4)={V01 V02 V05 V07} + ByrefExposed + GcHeap
OUT(3)={V01 V02 V07} + ByrefExposed + GcHeap
BB05 IN (3)={V01 V02 V07} + ByrefExposed + GcHeap
OUT(0)={ }
BB06 IN (1)={V00} + ByrefExposed + GcHeap
OUT(0)={ }
top level assign
removing stmt with no side effects
Removing statement STMT00015 (IL ???... ???)
N010 ( 14, 12) [000162] -A------R--- * ASG int
N009 ( 3, 2) [000161] D------N---- +--* LCL_VAR int V06 tmp1
N008 ( 10, 9) [000052] n-----?----- \--* IND int
N007 ( 8, 7) [000053] ------?N---- \--* ADD int
N005 ( 7, 6) [000054] #-----?----- +--* IND int
N004 ( 4, 4) [000055] #-----?----- | \--* IND int
N003 ( 2, 2) [000056] ------?N---- | \--* ADD int
N001 ( 1, 1) [000057] ------?----- | +--* LCL_VAR int V05 tmp0
N002 ( 1, 1) [000058] ------?----- | \--* CNS_INT int 32
N006 ( 1, 1) [000059] ------?----- \--* CNS_INT int 12
in BB03 as useless:
BB03 becomes empty
BB04 - Dead assignment has side effects...
N007 ( 20, 15) [000164] -AC-G---R--- * ASG int
N006 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V06 tmp1
N005 ( 16, 12) [000049] --C-G-?----- \--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000039] ------?----- arg0 in ecx +--* LCL_VAR int V05 tmp0
N004 ( 1, 4) [000048] ------?----- arg1 in edx \--* CNS_INT(h) int 0x8283EB8 token
top level assign
removing stmt with no side effects
Removing statement STMT00016 (IL ???... ???)
N007 ( 20, 15) [000164] -AC-G---R--- * ASG int
N006 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V06 tmp1
N005 ( 16, 12) [000049] --C-G-?----- \--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000039] ------?----- arg0 in ecx +--* LCL_VAR int V05 tmp0
N004 ( 1, 4) [000048] ------?----- arg1 in edx \--* CNS_INT(h) int 0x8283EB8 token
in BB04 as useless:
BB04 becomes empty
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 } + ByrefExposed + GcHeap
DEF(2)={ V01 V02}
BB02 USE(3)={V00 V01 V02 } + ByrefExposed + GcHeap
DEF(2)={ V05 V07} + ByrefExposed + GcHeap
BB03 USE(0)={}
DEF(0)={}
BB04 USE(0)={}
DEF(0)={}
BB05 USE(3)={V01 V02 V07 } + ByrefExposed + GcHeap
DEF(1)={ V08} + ByrefExposed + GcHeap
BB06 USE(1)={V00} + ByrefExposed + GcHeap
DEF(0)={ } + ByrefExposed* + GcHeap*
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00 } + ByrefExposed + GcHeap
OUT(3)={V00 V01 V02} + ByrefExposed + GcHeap
BB02 IN (3)={V00 V01 V02 } + ByrefExposed + GcHeap
OUT(3)={ V01 V02 V07} + ByrefExposed + GcHeap
BB03 IN (3)={V01 V02 V07} + ByrefExposed + GcHeap
OUT(3)={V01 V02 V07} + ByrefExposed + GcHeap
BB04 IN (3)={V01 V02 V07} + ByrefExposed + GcHeap
OUT(3)={V01 V02 V07} + ByrefExposed + GcHeap
BB05 IN (3)={V01 V02 V07} + ByrefExposed + GcHeap
OUT(0)={ }
BB06 IN (1)={V00} + ByrefExposed + GcHeap
OUT(0)={ }
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1
N006 ( 6, 6) [000003] ---XG------- \--* ADD int
N004 ( 4, 4) [000001] ---XG------- +--* IND int
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1
N004 ( 4, 4) [000007] ---XG------- \--* IND ref
N003 ( 2, 2) [000090] -------N---- \--* ADD byref
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array]
***** BB01
STMT00002 (IL 0x010...0x014)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N006 ( 6, 6) [000019] ---XG------- \--* ADD int
N004 ( 4, 4) [000017] ---XG------- +--* IND int
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1
***** BB02
STMT00005 (IL 0x031...0x038)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1
N015 ( 20, 22) [000124] ---XG------- \--* IND ref
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct
N011 ( 4, 4) [000117] -------N---- \--* ADD byref
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1
N010 ( 3, 3) [000119] -------N---- \--* ADD int
N008 ( 2, 2) [000120] -------N---- +--* LSH int
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1
N002 ( 3, 2) [000036] #----O------ \--* IND int
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use)
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int
N008 ( 10, 9) [000047] n----------- +--* IND int
N007 ( 8, 7) [000046] -------N---- | \--* ADD int
N005 ( 7, 6) [000044] #----------- | +--* IND int
N004 ( 4, 4) [000043] #----------- | | \--* IND int
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use)
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null
***** BB05
STMT00012 (IL ???...0x04B)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000148] ---XG------- | \--* ADDR byref
N012 ( 5, 5) [000149] a--XG------- | \--* IND struct
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use)
N010 ( 3, 3) [000152] -------N---- | \--* ADD int
N008 ( 2, 2) [000153] -------N---- | +--* LSH int
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use)
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use)
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use)
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1
N006 ( 6, 6) [000003] ---XG------- \--* ADD int
N004 ( 4, 4) [000001] ---XG------- +--* IND int
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1
N004 ( 4, 4) [000007] ---XG------- \--* IND ref
N003 ( 2, 2) [000090] -------N---- \--* ADD byref
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array]
***** BB01
STMT00002 (IL 0x010...0x014)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N006 ( 6, 6) [000019] ---XG------- \--* ADD int
N004 ( 4, 4) [000017] ---XG------- +--* IND int
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1
***** BB02
STMT00005 (IL 0x031...0x038)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1
N015 ( 20, 22) [000124] ---XG------- \--* IND ref
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct
N011 ( 4, 4) [000117] -------N---- \--* ADD byref
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1
N010 ( 3, 3) [000119] -------N---- \--* ADD int
N008 ( 2, 2) [000120] -------N---- +--* LSH int
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1
N002 ( 3, 2) [000036] #----O------ \--* IND int
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use)
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int
N008 ( 10, 9) [000047] n----------- +--* IND int
N007 ( 8, 7) [000046] -------N---- | \--* ADD int
N005 ( 7, 6) [000044] #----------- | +--* IND int
N004 ( 4, 4) [000043] #----------- | | \--* IND int
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use)
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null
***** BB05
STMT00012 (IL ???...0x04B)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000148] ---XG------- | \--* ADDR byref
N012 ( 5, 5) [000149] a--XG------- | \--* IND struct
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use)
N010 ( 3, 3) [000152] -------N---- | \--* ADD int
N008 ( 2, 2) [000153] -------N---- | +--* LSH int
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use)
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use)
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use)
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Early Value Propagation
*************** In optEarlyProp()
After optEarlyProp:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1
N006 ( 6, 6) [000003] ---XG------- \--* ADD int
N004 ( 4, 4) [000001] ---XG------- +--* IND int
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1
N004 ( 4, 4) [000007] ---XG------- \--* IND ref
N003 ( 2, 2) [000090] -------N---- \--* ADD byref
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array]
***** BB01
STMT00002 (IL 0x010...0x014)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N006 ( 6, 6) [000019] ---XG------- \--* ADD int
N004 ( 4, 4) [000017] ---XG------- +--* IND int
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1
***** BB02
STMT00005 (IL 0x031...0x038)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1
N015 ( 20, 22) [000124] ---XG------- \--* IND ref
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct
N011 ( 4, 4) [000117] -------N---- \--* ADD byref
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1
N010 ( 3, 3) [000119] -------N---- \--* ADD int
N008 ( 2, 2) [000120] -------N---- +--* LSH int
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1
N002 ( 3, 2) [000036] #----O------ \--* IND int
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use)
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int
N008 ( 10, 9) [000047] n----------- +--* IND int
N007 ( 8, 7) [000046] -------N---- | \--* ADD int
N005 ( 7, 6) [000044] #----------- | +--* IND int
N004 ( 4, 4) [000043] #----------- | | \--* IND int
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use)
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null
***** BB05
STMT00012 (IL ???...0x04B)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000148] ---XG------- | \--* ADDR byref
N012 ( 5, 5) [000149] a--XG------- | \--* IND struct
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use)
N010 ( 3, 3) [000152] -------N---- | \--* ADD int
N008 ( 2, 2) [000153] -------N---- | +--* LSH int
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use)
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use)
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use)
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Early Value Propagation
*************** Starting PHASE Do value numbering
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $81
The SSA definition for ByrefExposed (#1) at start of BB01 is $81 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB01 is $81 {InitVal($41)}
***** BB01, STMT00000(before)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1
N006 ( 6, 6) [000003] ---XG------- \--* ADD int
N004 ( 4, 4) [000001] ---XG------- +--* IND int
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1
N001 [000000] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
N002 [000087] CNS_INT 8 field offset Fseq[_size] => $42 {IntCns 8}
N003 [000088] ADD => $c0 {ADD($42, $80)}
VNApplySelectors:
VNForHandle(_size) is $100, fieldType is int
VNForMapSelect($81, $100):int returns $140 {$81[$100]}
VNForMapSelect($140, $80):int returns $141 {$140[$80]}
N004 [000001] IND => <l:$143 {norm=$141 {$140[$80]}, exc=$1c0 {NullPtrExc($80)}}, c:$142 {norm=$180 {180}, exc=$1c0 {NullPtrExc($80)}}>
N005 [000002] CNS_INT -1 => $41 {IntCns -1}
N006 [000003] ADD => <l:$147 {norm=$145 {ADD($41, $141)}, exc=$1c0 {NullPtrExc($80)}}, c:$146 {norm=$144 {ADD($41, $180)}, exc=$1c0 {NullPtrExc($80)}}>
N007 [000004] LCL_VAR V01 loc0 d:1 => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
N008 [000005] ASG => <l:$147 {norm=$145 {ADD($41, $141)}, exc=$1c0 {NullPtrExc($80)}}, c:$146 {norm=$144 {ADD($41, $180)}, exc=$1c0 {NullPtrExc($80)}}>
***** BB01, STMT00000(after)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int <l:$147, c:$146>
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1 <l:$145, c:$144>
N006 ( 6, 6) [000003] ---XG------- \--* ADD int <l:$147, c:$146>
N004 ( 4, 4) [000001] ---XG------- +--* IND int <l:$143, c:$142>
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1 $41
---------
***** BB01, STMT00001(before)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1
N004 ( 4, 4) [000007] ---XG------- \--* IND ref
N003 ( 2, 2) [000090] -------N---- \--* ADD byref
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array]
N001 [000006] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
N002 [000089] CNS_INT 4 field offset Fseq[_array] => $43 {IntCns 4}
N003 [000090] ADD => $c1 {ADD($43, $80)}
VNApplySelectors:
VNForHandle(_array) is $101, fieldType is ref
VNForMapSelect($81, $101):ref returns $1c1 {$81[$101]}
VNForMapSelect($1c1, $80):ref returns $1c2 {$1c1[$80]}
N004 [000007] IND => <l:$1c4 {norm=$1c2 {$1c1[$80]}, exc=$1c0 {NullPtrExc($80)}}, c:$1c3 {norm=$200 {200}, exc=$1c0 {NullPtrExc($80)}}>
N005 [000008] LCL_VAR V02 loc1 d:1 => <l:$1c2 {$1c1[$80]}, c:$200 {200}>
N006 [000009] ASG => <l:$1c4 {norm=$1c2 {$1c1[$80]}, exc=$1c0 {NullPtrExc($80)}}, c:$1c3 {norm=$200 {200}, exc=$1c0 {NullPtrExc($80)}}>
***** BB01, STMT00001(after)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1 <l:$1c2, c:$200>
N004 ( 4, 4) [000007] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000090] -------N---- \--* ADD byref $c1
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array] $43
---------
***** BB01, STMT00002(before)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1
N001 [000011] LCL_VAR V02 loc1 u:1 => <l:$1c2 {$1c1[$80]}, c:$200 {200}>
N002 [000012] ARR_LENGTH => <l:$149 {norm=$241 {ARR_LENGTH($1c2)}, exc=$1c6 {NullPtrExc($1c2)}}, c:$148 {norm=$240 {ARR_LENGTH($200)}, exc=$1c5 {NullPtrExc($200)}}>
N003 [000010] LCL_VAR V01 loc0 u:1 => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
N004 [000013] LE => <l:$14d {norm=$14b {LE_UN($241, $145)}, exc=$1c6 {NullPtrExc($1c2)}}, c:$14c {norm=$14a {LE_UN($240, $144)}, exc=$1c5 {NullPtrExc($200)}}>
***** BB01, STMT00002(after)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int <l:$14d, c:$14c>
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int <l:$149, c:$148>
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
finish(BB01).
Succ(BB02).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB06).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#1) at start of BB06 is $81 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB06 is $81 {InitVal($41)}
***** BB06, STMT00013(before)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use)
N001 [000091] ARGPLACE => $202 {202}
N002 [000082] LCL_VAR V00 this u:1 (last use) => $80 {InitVal($40)}
fgCurMemoryVN[GcHeap] assigned for CALL at [000083] to VN: $203.
N003 [000083] CALL => $VN.Void
***** BB06, STMT00013(after)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use) $80
finish(BB06).
The SSA definition for ByrefExposed (#1) at start of BB02 is $81 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB02 is $81 {InitVal($41)}
***** BB02, STMT00003(before)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N006 ( 6, 6) [000019] ---XG------- \--* ADD int
N004 ( 4, 4) [000017] ---XG------- +--* IND int
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1
N001 [000016] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
N002 [000094] CNS_INT 12 field offset Fseq[_version] => $44 {IntCns 12}
N003 [000095] ADD => $c2 {ADD($44, $80)}
VNApplySelectors:
VNForHandle(_version) is $102, fieldType is int
VNForMapSelect($81, $102):int returns $14e {$81[$102]}
VNForMapSelect($14e, $80):int returns $14f {$14e[$80]}
N004 [000017] IND => <l:$151 {norm=$14f {$14e[$80]}, exc=$1c0 {NullPtrExc($80)}}, c:$150 {norm=$182 {182}, exc=$1c0 {NullPtrExc($80)}}>
N005 [000018] CNS_INT 1 => $45 {IntCns 1}
N006 [000019] ADD => <l:$155 {norm=$153 {ADD($45, $14f)}, exc=$1c0 {NullPtrExc($80)}}, c:$154 {norm=$152 {ADD($45, $182)}, exc=$1c0 {NullPtrExc($80)}}>
N007 [000015] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
N008 [000092] CNS_INT 12 field offset Fseq[_version] => $44 {IntCns 12}
N009 [000093] ADD => $c2 {ADD($44, $80)}
VNApplySelectors:
VNForHandle(_version) is $102, fieldType is int
VNForMapSelect($81, $102):int returns $14e {$81[$102]}
VNForMapSelect($14e, $80):int returns $14f {$14e[$80]}
VNForMapStore($14e, $80, $153):int returns $280 {$14e[$80 := $153]}
VNApplySelectorsAssign:
VNForHandle(_version) is $102, fieldType is int
VNForMapStore($81, $102, $280):int returns $281 {$81[$102 := $280]}
fgCurMemoryVN[GcHeap] assigned for StoreField at [000021] to VN: $281.
N011 [000021] ASG => $VN.Void
***** BB02, STMT00003(after)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int $VN.Void
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int $153
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref $c2
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N006 ( 6, 6) [000019] ---XG------- \--* ADD int <l:$155, c:$154>
N004 ( 4, 4) [000017] ---XG------- +--* IND int <l:$151, c:$150>
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref $c2
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1 $45
---------
***** BB02, STMT00004(before)
N006 ( 6, 6) [000025] -A-XG------- * ASG int
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1
N001 [000022] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
N002 [000096] CNS_INT 8 field offset Fseq[_size] => $42 {IntCns 8}
N003 [000097] ADD => $c0 {ADD($42, $80)}
N005 [000023] LCL_VAR V01 loc0 u:1 => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
VNApplySelectors:
VNForHandle(_size) is $100, fieldType is int
AX2: $100 != $102 ==> select([$281]store($81, $102, $280), $100) ==> select($81, $100).
VNForMapSelect($281, $100):int returns $140 {$81[$100]}
VNForMapSelect($140, $80):int returns $141 {$140[$80]}
VNForMapStore($140, $80, $145):int returns $282 {$140[$80 := $145]}
VNApplySelectorsAssign:
VNForHandle(_size) is $100, fieldType is int
VNForMapStore($281, $100, $282):int returns $283 {$281[$100 := $282]}
fgCurMemoryVN[GcHeap] assigned for StoreField at [000025] to VN: $283.
N006 [000025] ASG => $VN.Void
***** BB02, STMT00004(after)
N006 ( 6, 6) [000025] -A-XG------- * ASG int $VN.Void
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int $145
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
---------
***** BB02, STMT00005(before)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1
N015 ( 20, 22) [000124] ---XG------- \--* IND ref
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct
N011 ( 4, 4) [000117] -------N---- \--* ADD byref
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1
N010 ( 3, 3) [000119] -------N---- \--* ADD int
N008 ( 2, 2) [000120] -------N---- +--* LSH int
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
N001 [000113] LCL_VAR V01 loc0 u:1 => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
N002 [000112] LCL_VAR V02 loc1 u:1 => <l:$1c2 {$1c1[$80]}, c:$200 {200}>
N003 [000111] ARR_LENGTH => <l:$149 {norm=$241 {ARR_LENGTH($1c2)}, exc=$1c6 {NullPtrExc($1c2)}}, c:$148 {norm=$240 {ARR_LENGTH($200)}, exc=$1c5 {NullPtrExc($200)}}>
N004 [000114] ARR_BOUNDS_CHECK_Rng => <l:$1d0 {norm=$3 {3}, exc=$1ce( {NullPtrExc($1c2)}, {IndexOutOfRangeExc($145, $241)})}, c:$1cf {norm=$3 {3}, exc=$1cd( {NullPtrExc($200)}, {IndexOutOfRangeExc($144, $240)})}>
N005 [000118] LCL_VAR V02 loc1 u:1 => <l:$1c2 {$1c1[$80]}, c:$200 {200}>
N006 [000121] LCL_VAR V01 loc0 u:1 => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
N007 [000122] CNS_INT 2 => $46 {IntCns 2}
N008 [000120] LSH => <l:$157 {LSH($145, $46)}, c:$156 {LSH($144, $46)}>
N009 [000123] CNS_INT 8 Fseq[#FirstElem] => $42 {IntCns 8}
N010 [000119] ADD => <l:$159 {ADD($42, $157)}, c:$158 {ADD($42, $156)}>
N011 [000117] ADD => <l:$c4 {ADD($159, $1c2)}, c:$c3 {ADD($158, $200)}>
VNForHandle(arrElemType: RefAsValueType`1) is $103
Relabeled IND_ARR_INDEX address node [000117] with l:$300: {PtrToArrElem($103, $1c2, $145, $0)}
AX2: $103 != $100 ==> select([$283]store($281, $100, $282), $103) ==> select($281, $103).
AX2: $103 != $102 ==> select([$281]store($81, $102, $280), $103) ==> select($81, $103).
VNForMapSelect($283, $103):ref returns $1d1 {$81[$103]}
VNForMapSelect($1d1, $1c2):ref returns $1d2 {$1d1[$1c2]}
VNForMapSelect($1d2, $145):struct returns $340 {$1d2[$145]}
hAtArrType $1d1 is MapSelect(curGcHeap($283), RefAsValueType`1[]).
hAtArrTypeAtArr $1d2 is MapSelect(hAtArrType($1d1), arr=$1c2).
wholeElem $340 is MapSelect(hAtArrTypeAtArr($1d2), ind=$145).
N012 [000116] IND => <l:$340 {$1d2[$145]}, c:$380 {380}>
N013 [000115] ADDR => $300 {PtrToArrElem($103, $1c2, $145, $0)}
N014 [000110] COMMA => <l:$c6 {norm=$300 {PtrToArrElem($103, $1c2, $145, $0)}, exc=$1ce( {NullPtrExc($1c2)}, {IndexOutOfRangeExc($145, $241)})}, c:$c5 {norm=$300 {PtrToArrElem($103, $1c2, $145, $0)}, exc=$1cd( {NullPtrExc($200)}, {IndexOutOfRangeExc($144, $240)})}>
AX2: $103 != $100 ==> select([$283]store($281, $100, $282), $103) ==> select($281, $103).
AX2: $103 != $102 ==> select([$281]store($81, $102, $280), $103) ==> select($81, $103).
VNForMapSelect($283, $103):ref returns $1d1 {$81[$103]}
VNForMapSelect($1d1, $1c2):ref returns $1d2 {$1d1[$1c2]}
VNForMapSelect($1d2, $145):struct returns $340 {$1d2[$145]}
hAtArrType $1d1 is MapSelect(curGcHeap($283), RefAsValueType`1[]).
hAtArrTypeAtArr $1d2 is MapSelect(hAtArrType($1d1), arr=$1c2).
wholeElem $340 is MapSelect(hAtArrTypeAtArr($1d2), ind=$145).
selectedElem is $341 after applying selectors.
N015 [000124] IND => <l:$341 {norm=$340 {$1d2[$145]}, exc=$1ce( {NullPtrExc($1c2)}, {IndexOutOfRangeExc($145, $241)})}, c:$204 {204}>
N016 [000109] LCL_VAR V07 tmp2 d:1 => <l:$340 {$1d2[$145]}, c:$204 {204}>
N017 [000125] ASG => <l:$341 {norm=$340 {$1d2[$145]}, exc=$1ce( {NullPtrExc($1c2)}, {IndexOutOfRangeExc($145, $241)})}, c:$204 {204}>
***** BB02, STMT00005(after)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N015 ( 20, 22) [000124] ---XG------- \--* IND ref <l:$341, c:$204>
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref $300
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct <l:$340, c:$380>
N011 ( 4, 4) [000117] -------N---- \--* ADD byref $300
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N010 ( 3, 3) [000119] -------N---- \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000120] -------N---- +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
---------
***** BB02, STMT00006(before)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1
N002 ( 3, 2) [000036] #----O------ \--* IND int
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use)
N001 [000035] LCL_VAR V00 this u:1 (last use) => $80 {InitVal($40)}
VNForMapSelect($2, $80):ref returns $1d3 {$VN.ReadOnlyHeap[$80]}
VNForMapSelect($2, $80):ref returns $1d3 {$VN.ReadOnlyHeap[$80]}
N002 [000036] IND => $1d3 {$VN.ReadOnlyHeap[$80]}
N003 [000037] LCL_VAR V05 tmp0 d:1 => $1d3 {$VN.ReadOnlyHeap[$80]}
N004 [000038] ASG => $1d3 {$VN.ReadOnlyHeap[$80]}
***** BB02, STMT00006(after)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int $1d3
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1 $1d3
N002 ( 3, 2) [000036] #----O------ \--* IND int $1d3
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use) $80
---------
***** BB02, STMT00014(before)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int
N008 ( 10, 9) [000047] n----------- +--* IND int
N007 ( 8, 7) [000046] -------N---- | \--* ADD int
N005 ( 7, 6) [000044] #----------- | +--* IND int
N004 ( 4, 4) [000043] #----------- | | \--* IND int
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use)
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0
N001 [000040] LCL_VAR V05 tmp0 u:1 (last use) => $1d3 {$VN.ReadOnlyHeap[$80]}
N002 [000041] CNS_INT 32 => $47 {IntCns 32}
N003 [000042] ADD => $15b {ADD($47, $1d3)}
VNForMapSelect($2, $15b):ref returns $1d4 {$VN.ReadOnlyHeap[$15b]}
VNForMapSelect($2, $15b):ref returns $1d4 {$VN.ReadOnlyHeap[$15b]}
N004 [000043] IND => $1d4 {$VN.ReadOnlyHeap[$15b]}
VNForMapSelect($2, $1d4):ref returns $1d5 {$VN.ReadOnlyHeap[$1d4]}
VNForMapSelect($2, $1d4):ref returns $1d5 {$VN.ReadOnlyHeap[$1d4]}
N005 [000044] IND => $1d5 {$VN.ReadOnlyHeap[$1d4]}
N006 [000045] CNS_INT 12 => $44 {IntCns 12}
N007 [000046] ADD => $15c {ADD($44, $1d5)}
N008 [000047] IND => <l:$284 {ByrefExposedLoad($48, $15c, $283)}, c:$184 {184}>
N009 [000050] CNS_INT 0 => $40 {IntCns 0}
N010 [000051] EQ => <l:$15e {EQ($284, $40)}, c:$15d {EQ($184, $40)}>
***** BB02, STMT00014(after)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int <l:$15e, c:$15d>
N008 ( 10, 9) [000047] n----------- +--* IND int <l:$284, c:$184>
N007 ( 8, 7) [000046] -------N---- | \--* ADD int $15c
N005 ( 7, 6) [000044] #----------- | +--* IND int $1d5
N004 ( 4, 4) [000043] #----------- | | \--* IND int $1d4
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int $15b
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use) $1d3
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32 $47
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12 $44
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40
finish(BB02).
Succ(BB03).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB04).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#3) at start of BB04 is $283 {$281[$100 := $282]}
The SSA definition for GcHeap (#3) at start of BB04 is $283 {$281[$100 := $282]}
finish(BB04).
Succ(BB05).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
The SSA definition for ByrefExposed (#3) at start of BB03 is $283 {$281[$100 := $282]}
The SSA definition for GcHeap (#3) at start of BB03 is $283 {$281[$100 := $282]}
finish(BB03).
Succ(BB05).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#3) at start of BB05 is $283 {$281[$100 := $282]}
The SSA definition for GcHeap (#3) at start of BB05 is $283 {$281[$100 := $282]}
***** BB05, STMT00011(before)
N003 ( 5, 4) [000130] -A------R--- * ASG ref
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null
N001 [000129] CNS_INT null => $VN.Null
N002 [000128] LCL_VAR V08 tmp3 d:1 => $VN.Null
N003 [000130] ASG => $VN.Null
***** BB05, STMT00011(after)
N003 ( 5, 4) [000130] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1 $VN.Null
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null $VN.Null
---------
***** BB05, STMT00012(before)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000148] ---XG------- | \--* ADDR byref
N012 ( 5, 5) [000149] a--XG------- | \--* IND struct
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use)
N010 ( 3, 3) [000152] -------N---- | \--* ADD int
N008 ( 2, 2) [000153] -------N---- | +--* LSH int
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use)
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use)
N001 [000146] LCL_VAR V01 loc0 u:1 => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
N002 [000145] LCL_VAR V02 loc1 u:1 => <l:$1c2 {$1c1[$80]}, c:$200 {200}>
N003 [000144] ARR_LENGTH => <l:$149 {norm=$241 {ARR_LENGTH($1c2)}, exc=$1c6 {NullPtrExc($1c2)}}, c:$148 {norm=$240 {ARR_LENGTH($200)}, exc=$1c5 {NullPtrExc($200)}}>
N004 [000147] ARR_BOUNDS_CHECK_Rng => <l:$1d0 {norm=$3 {3}, exc=$1ce( {NullPtrExc($1c2)}, {IndexOutOfRangeExc($145, $241)})}, c:$1cf {norm=$3 {3}, exc=$1cd( {NullPtrExc($200)}, {IndexOutOfRangeExc($144, $240)})}>
N005 [000151] LCL_VAR V02 loc1 u:1 (last use) => <l:$1c2 {$1c1[$80]}, c:$200 {200}>
N006 [000154] LCL_VAR V01 loc0 u:1 (last use) => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
N007 [000155] CNS_INT 2 => $46 {IntCns 2}
N008 [000153] LSH => <l:$157 {LSH($145, $46)}, c:$156 {LSH($144, $46)}>
N009 [000156] CNS_INT 8 Fseq[#FirstElem] => $42 {IntCns 8}
N010 [000152] ADD => <l:$159 {ADD($42, $157)}, c:$158 {ADD($42, $156)}>
N011 [000150] ADD => <l:$c4 {ADD($159, $1c2)}, c:$c3 {ADD($158, $200)}>
VNForHandle(arrElemType: RefAsValueType`1) is $103
Relabeled IND_ARR_INDEX address node [000150] with l:$300: {PtrToArrElem($103, $1c2, $145, $0)}
AX2: $103 != $100 ==> select([$283]store($281, $100, $282), $103) ==> select($281, $103).
AX2: $103 != $102 ==> select([$281]store($81, $102, $280), $103) ==> select($81, $103).
VNForMapSelect($283, $103):ref returns $1d1 {$81[$103]}
VNForMapSelect($1d1, $1c2):ref returns $1d2 {$1d1[$1c2]}
VNForMapSelect($1d2, $145):struct returns $340 {$1d2[$145]}
hAtArrType $1d1 is MapSelect(curGcHeap($283), RefAsValueType`1[]).
hAtArrTypeAtArr $1d2 is MapSelect(hAtArrType($1d1), arr=$1c2).
wholeElem $340 is MapSelect(hAtArrTypeAtArr($1d2), ind=$145).
N012 [000149] IND => <l:$343 {norm=$340 {$1d2[$145]}, exc=$1d6 {NullPtrExc($300)}}, c:$342 {norm=$381 {381}, exc=$1d6 {NullPtrExc($300)}}>
N013 [000148] ADDR => $300 {PtrToArrElem($103, $1c2, $145, $0)}
N014 [000143] COMMA => <l:$c6 {norm=$300 {PtrToArrElem($103, $1c2, $145, $0)}, exc=$1ce( {NullPtrExc($1c2)}, {IndexOutOfRangeExc($145, $241)})}, c:$c5 {norm=$300 {PtrToArrElem($103, $1c2, $145, $0)}, exc=$1cd( {NullPtrExc($200)}, {IndexOutOfRangeExc($144, $240)})}>
N016 [000158] LCL_VAR V08 tmp3 u:1 (last use) => $VN.Null
Tree [000159] assigns to an array element:
AX2: $103 != $100 ==> select([$283]store($281, $100, $282), $103) ==> select($281, $103).
AX2: $103 != $102 ==> select([$281]store($81, $102, $280), $103) ==> select($81, $103).
VNForMapSelect($283, $103):ref returns $1d1 {$81[$103]}
VNForMapSelect($1d1, $1c2):ref returns $1d2 {$1d1[$1c2]}
VNForMapSelect($1d2, $145):struct returns $340 {$1d2[$145]}
*** Mismatched types in fgValueNumberArrIndexAssign
hAtArrType $1d1 is MapSelect(curGcHeap($283), RefAsValueType`1[]).
hAtArrTypeAtArr $1d2 is MapSelect(hAtArrType($1d1), arr=$1c2)
hAtArrTypeAtArrAtInx $340 is MapSelect(hAtArrTypeAtArr($1d2), inx=$145):struct
newValAtArrType $207 is {207}
VNForMapStore($283, $103, $207):ref returns $3c0 {$283[$103 := $207]}
fgCurMemoryVN[GcHeap] assigned for ArrIndexAssign (case 1) at [000159] to VN: $3c0.
N017 [000159] ASG => $VN.Void
***** BB05, STMT00012(after)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref $VN.Void
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref $VN.Null
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000148] ---XG------- | \--* ADDR byref $300
N012 ( 5, 5) [000149] a--XG------- | \--* IND struct <l:$343, c:$342>
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref $300
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N010 ( 3, 3) [000152] -------N---- | \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000153] -------N---- | +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use) $VN.Null
---------
***** BB05, STMT00010(before)
N002 ( 4, 3) [000071] ------------ * RETURN ref
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use)
N001 [000070] LCL_VAR V07 tmp2 u:1 (last use) => <l:$340 {$1d2[$145]}, c:$204 {204}>
N002 [000071] RETURN => $208 {208}
***** BB05, STMT00010(after)
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
finish(BB05).
*************** Finishing PHASE Do value numbering
*************** Starting PHASE Hoist loop code
*************** Finishing PHASE Hoist loop code
*************** Starting PHASE VN based copy prop
*************** In optVnCopyProp()
Copy Assertion for BB01
curSsaName stack: { }
Live vars: {V00} => {V00 V01}
Live vars: {V00 V01} => {V00 V01 V02}
Copy Assertion for BB06
curSsaName stack: { 0-[000000]:V00 1-[000004]:V01 2-[000008]:V02 }
Live vars: {V00} => {}
Copy Assertion for BB02
curSsaName stack: { 0-[000000]:V00 1-[000004]:V01 2-[000008]:V02 }
Live vars: {V00 V01 V02} => {V00 V01 V02 V07}
Live vars: {V00 V01 V02 V07} => {V01 V02 V07}
Live vars: {V01 V02 V07} => {V01 V02 V05 V07}
Live vars: {V01 V02 V05 V07} => {V01 V02 V07}
Copy Assertion for BB05
curSsaName stack: { 0-[000000]:V00 1-[000004]:V01 2-[000008]:V02 5-[000037]:V05 7-[000109]:V07 }
Live vars: {V01 V02 V07} => {V01 V02 V07 V08}
Live vars: {V01 V02 V07 V08} => {V01 V07 V08}
Live vars: {V01 V07 V08} => {V07 V08}
Live vars: {V07 V08} => {V07}
Live vars: {V07} => {}
Copy Assertion for BB04
curSsaName stack: { 0-[000000]:V00 1-[000004]:V01 2-[000008]:V02 5-[000037]:V05 7-[000109]:V07 }
Copy Assertion for BB03
curSsaName stack: { 0-[000000]:V00 1-[000004]:V01 2-[000008]:V02 5-[000037]:V05 7-[000109]:V07 }
*************** Finishing PHASE VN based copy prop
*************** Starting PHASE Optimize Valnum CSEs
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int <l:$147, c:$146>
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1 <l:$145, c:$144>
N006 ( 6, 6) [000003] ---XG------- \--* ADD int <l:$147, c:$146>
N004 ( 4, 4) [000001] ---XG------- +--* IND int <l:$143, c:$142>
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1 $41
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1 <l:$1c2, c:$200>
N004 ( 4, 4) [000007] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000090] -------N---- \--* ADD byref $c1
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array] $43
***** BB01
STMT00002 (IL 0x010...0x014)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int <l:$14d, c:$14c>
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int <l:$149, c:$148>
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int $VN.Void
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int $153
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref $c2
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N006 ( 6, 6) [000019] ---XG------- \--* ADD int <l:$155, c:$154>
N004 ( 4, 4) [000017] ---XG------- +--* IND int <l:$151, c:$150>
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref $c2
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1 $45
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int $VN.Void
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int $145
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
***** BB02
STMT00005 (IL 0x031...0x038)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N015 ( 20, 22) [000124] ---XG------- \--* IND ref <l:$341, c:$204>
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref $300
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct <l:$340, c:$380>
N011 ( 4, 4) [000117] -------N---- \--* ADD byref $300
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N010 ( 3, 3) [000119] -------N---- \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000120] -------N---- +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int $1d3
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1 $1d3
N002 ( 3, 2) [000036] #----O------ \--* IND int $1d3
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use) $80
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int <l:$15e, c:$15d>
N008 ( 10, 9) [000047] n----------- +--* IND int <l:$284, c:$184>
N007 ( 8, 7) [000046] -------N---- | \--* ADD int $15c
N005 ( 7, 6) [000044] #----------- | +--* IND int $1d5
N004 ( 4, 4) [000043] #----------- | | \--* IND int $1d4
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int $15b
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use) $1d3
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32 $47
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12 $44
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1 $VN.Null
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null $VN.Null
***** BB05
STMT00012 (IL ???...0x04B)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref $VN.Void
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref $VN.Null
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000148] ---XG------- | \--* ADDR byref $300
N012 ( 5, 5) [000149] a--XG------- | \--* IND struct <l:$343, c:$342>
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref $300
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N010 ( 3, 3) [000152] -------N---- | \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000153] -------N---- | +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use) $VN.Null
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use) $80
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
CSE candidate #01, vn=$241 in BB02, [cost= 3, size= 3]:
N003 ( 3, 3) CSE #01 (use)[000111] ---X-------- * ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
CSE candidate #02, vn=$340 in BB05, [cost= 5, size= 5]:
N012 ( 5, 5) CSE #02 (use)[000149] a--XG------- * IND struct <l:$343, c:$342>
N011 ( 4, 4) [000150] -------N---- \--* ADD byref $300
N005 ( 1, 1) [000151] ------------ +--* LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N010 ( 3, 3) [000152] -------N---- \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000153] -------N---- +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000154] i----------- | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
N007 ( 1, 1) [000155] -------N---- | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000156] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
CSE candidate #03, vn=$c6 in BB05, [cost=17, size=20]:
N014 ( 17, 20) CSE #03 (use)[000143] ---XG------- * COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000147] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000146] ------------ | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) CSE #01 (use)[000144] ---X-------- | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000145] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000148] ---XG------- \--* ADDR byref $300
N012 ( 5, 5) CSE #02 (use)[000149] a--XG------- \--* IND struct <l:$343, c:$342>
N011 ( 4, 4) [000150] -------N---- \--* ADD byref $300
N005 ( 1, 1) [000151] ------------ +--* LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N010 ( 3, 3) [000152] -------N---- \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000153] -------N---- +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000154] i----------- | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
N007 ( 1, 1) [000155] -------N---- | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000156] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
Blocks that generate CSE def/uses
BB01 cseGen = 00000003
BB02 cseGen = 0000003F
BB05 cseGen = 0000003F
Performing DataFlow for ValnumCSE's
StartMerge BB01
:: cseOut = 0000007F
EndMerge BB01
:: cseIn = 00000000
:: cseGen = 00000003
=> cseOut = 00000003
!= preMerge = 0000007F, => true
StartMerge BB02
:: cseOut = 0000007F
Merge BB02 and BB01
:: cseIn = 0000007F
:: cseOut = 0000007F
=> cseIn = 00000003
EndMerge BB02
:: cseIn = 00000003
-- cseKill = 00000015
:: cseGen = 0000003F
=> cseOut = 0000003F
!= preMerge = 0000007F, => true
StartMerge BB06
:: cseOut = 0000007F
Merge BB06 and BB01
:: cseIn = 0000007F
:: cseOut = 0000007F
=> cseIn = 00000003
EndMerge BB06
:: cseIn = 00000003
-- cseKill = 00000015
:: cseGen = 00000000
=> cseOut = 00000001
!= preMerge = 0000007F, => true
StartMerge BB03
:: cseOut = 0000007F
Merge BB03 and BB02
:: cseIn = 0000007F
:: cseOut = 0000007F
=> cseIn = 0000003F
EndMerge BB03
:: cseIn = 0000003F
:: cseGen = 00000000
=> cseOut = 0000003F
!= preMerge = 0000007F, => true
StartMerge BB04
:: cseOut = 0000007F
Merge BB04 and BB02
:: cseIn = 0000007F
:: cseOut = 0000007F
=> cseIn = 0000003F
EndMerge BB04
:: cseIn = 0000003F
:: cseGen = 00000000
=> cseOut = 0000003F
!= preMerge = 0000007F, => true
StartMerge BB05
:: cseOut = 0000007F
Merge BB05 and BB04
:: cseIn = 0000007F
:: cseOut = 0000007F
=> cseIn = 0000003F
Merge BB05 and BB03
:: cseIn = 0000003F
:: cseOut = 0000007F
=> cseIn = 0000003F
EndMerge BB05
:: cseIn = 0000003F
:: cseGen = 0000003F
=> cseOut = 0000003F
!= preMerge = 0000007F, => true
StartMerge BB05
:: cseOut = 0000003F
Merge BB05 and BB04
:: cseIn = 0000003F
:: cseOut = 0000003F
=> cseIn = 0000003F
Merge BB05 and BB03
:: cseIn = 0000003F
:: cseOut = 0000003F
=> cseIn = 0000003F
EndMerge BB05
:: cseIn = 0000003F
:: cseGen = 0000003F
=> cseOut = 0000003F
!= preMerge = 0000003F, => false
After performing DataFlow for ValnumCSE's
BB01 cseIn = 00000000, cseGen = 00000003, cseOut = 00000003
BB02 cseIn = 00000003, cseGen = 0000003F, cseOut = 0000003F
BB03 cseIn = 0000003F, cseGen = 00000000, cseOut = 0000003F
BB04 cseIn = 0000003F, cseGen = 00000000, cseOut = 0000003F
BB05 cseIn = 0000003F, cseGen = 0000003F, cseOut = 0000003F
BB06 cseIn = 00000003, cseGen = 00000000, cseOut = 00000001
Labeling the CSEs with Use/Def information
BB01 [000012] Def of CSE #01 [weight=1 ]
BB02 [000111] Use of CSE #01 [weight=1 ]
BB02 [000110] Def of CSE #03 [weight=1 ]
BB02 [000124] Def of CSE #02 [weight=1 ]
BB05 [000144] Use of CSE #01 [weight=1 ]
BB05 [000149] Use of CSE #02 [weight=1 ]
NO_CSE - This use has an exception set item that isn't contained in the defs!
BB05 [000143] Use of CSE #03 [weight=1 ]
************ Trees at start of optValnumCSE_Heuristic()
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int <l:$147, c:$146>
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1 <l:$145, c:$144>
N006 ( 6, 6) [000003] ---XG------- \--* ADD int <l:$147, c:$146>
N004 ( 4, 4) [000001] ---XG------- +--* IND int <l:$143, c:$142>
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1 $41
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1 <l:$1c2, c:$200>
N004 ( 4, 4) [000007] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000090] -------N---- \--* ADD byref $c1
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array] $43
***** BB01
STMT00002 (IL 0x010...0x014)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int <l:$14d, c:$14c>
N002 ( 3, 3) CSE #01 (def)[000012] ---X-------- +--* ARR_LENGTH int <l:$149, c:$148>
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int $VN.Void
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int $153
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref $c2
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N006 ( 6, 6) [000019] ---XG------- \--* ADD int <l:$155, c:$154>
N004 ( 4, 4) [000017] ---XG------- +--* IND int <l:$151, c:$150>
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref $c2
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1 $45
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int $VN.Void
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int $145
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
***** BB02
STMT00005 (IL 0x031...0x038)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N015 ( 20, 22) CSE #02 (def)[000124] ---XG------- \--* IND ref <l:$341, c:$204>
N014 ( 17, 20) CSE #03 (def)[000110] ---XG------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) CSE #01 (use)[000111] ---X-------- | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref $300
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct <l:$340, c:$380>
N011 ( 4, 4) [000117] -------N---- \--* ADD byref $300
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N010 ( 3, 3) [000119] -------N---- \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000120] -------N---- +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int $1d3
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1 $1d3
N002 ( 3, 2) [000036] #----O------ \--* IND int $1d3
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use) $80
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int <l:$15e, c:$15d>
N008 ( 10, 9) [000047] n----------- +--* IND int <l:$284, c:$184>
N007 ( 8, 7) [000046] -------N---- | \--* ADD int $15c
N005 ( 7, 6) [000044] #----------- | +--* IND int $1d5
N004 ( 4, 4) [000043] #----------- | | \--* IND int $1d4
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int $15b
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use) $1d3
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32 $47
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12 $44
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1 $VN.Null
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null $VN.Null
***** BB05
STMT00012 (IL ???...0x04B)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref $VN.Void
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref $VN.Null
N014 ( 17, 20) CSE #03 (use)[000143] ---XG------- | \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) CSE #01 (use)[000144] ---X-------- | | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000148] ---XG------- | \--* ADDR byref $300
N012 ( 5, 5) [000149] a--XG------- | \--* IND struct <l:$343, c:$342>
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref $300
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N010 ( 3, 3) [000152] -------N---- | \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000153] -------N---- | +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use) $VN.Null
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use) $80
-------------------------------------------------------------------------------------------------------------------
Aggressive CSE Promotion cutoff is 300
Moderate CSE Promotion cutoff is 100
enregCount is 7
Framesize estimate is 0x0000
We have a small frame
Sorted CSE candidates:
CSE #02, {$340, $4 } useCnt=0: [def=100, use= 0, cost= 20 ]
:: N015 ( 20, 22) CSE #02 (def)[000124] ---XG------- * IND ref <l:$341, c:$204>
CSE #03, {$c6 , $1ce} useCnt=1: [def=100, use=100, cost= 17 ]
:: N014 ( 17, 20) CSE #03 (def)[000110] ---XG------- * COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
CSE #01, {$241, $1c6} useCnt=2: [def=100, use=200, cost= 3 ]
:: N002 ( 3, 3) CSE #01 (def)[000012] ---X-------- * ARR_LENGTH int <l:$149, c:$148>
Skipped CSE #02 because use count is 0
Considering CSE #03 {$c6 , $1ce} [def=100, use=100, cost= 17 ]
CSE Expression :
N014 ( 17, 20) CSE #03 (def)[000110] ---XG------- * COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) CSE #01 (use)[000111] ---X-------- | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref $300
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct <l:$340, c:$380>
N011 ( 4, 4) [000117] -------N---- \--* ADD byref $300
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N010 ( 3, 3) [000119] -------N---- \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000120] -------N---- +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
Aggressive CSE Promotion (300 >= 300)
cseRefCnt=300, aggressiveRefCnt=300, moderateRefCnt=100
defCnt=100, useCnt=100, cost=17, size=20
def_cost=1, use_cost=1, extra_no_cost=38, extra_yes_cost=0
CSE cost savings check (1738 >= 200) passes
Promoting CSE:
lvaGrabTemp returning 9 (V09 rat0) (a long lifetime temp) called for CSE - aggressive.
CSE #03 is single-def, so associated CSE temp V09 will be in SSA
CSE #03 def at [000110] replaced in BB02 with def of V09
fgAddFieldSeqForZeroOffset for Fseq[Value]
addr (Before)
[000167] ------------ LCL_VAR byref <l:$c6, c:$c5>
(After)
[000167] ------------ LCL_VAR byref Zero Fseq[Value] <l:$c6, c:$c5>
fgAddFieldSeqForZeroOffset for Fseq[Value]
addr (Before)
[000168] -A-XG------- COMMA byref <l:$c6, c:$c5>
(After)
[000168] -A-XG------- COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
optValnumCSE morphed tree:
N021 ( 31, 30) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N020 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N019 ( 27, 27) CSE #02 (def)[000124] -A-XG------- \--* IND ref <l:$341, c:$204>
N018 ( 24, 25) [000168] -A-XG------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N016 ( 21, 23) [000166] -A-XG---R--- +--* ASG byref $VN.Void
N015 ( 3, 2) [000165] D------N---- | +--* LCL_VAR byref V09 cse0 d:1 <l:$c6, c:$c5>
N014 ( 17, 20) [000110] ---XG------- | \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000114] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) CSE #01 (use)[000111] ---X-------- | | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000112] ------------ | | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000115] ----G------- | \--* ADDR byref $300
N012 ( 5, 5) [000116] a---G--N---- | \--* IND struct <l:$340, c:$380>
N011 ( 4, 4) [000117] -------N---- | \--* ADD byref $300
N005 ( 1, 1) [000118] ------------ | +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N010 ( 3, 3) [000119] -------N---- | \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000120] -------N---- | +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000121] i----------- | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N007 ( 1, 1) [000122] -------N---- | | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000123] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N017 ( 3, 2) [000167] ------------ \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
Working on the replacement of the CSE #03 use at [000143] in BB05
Unmark CSE use #01 at [000144]: 2 -> 1
fgAddFieldSeqForZeroOffset for Fseq[Value]
addr (Before)
[000169] ------------ LCL_VAR byref $300
(After)
[000169] ------------ LCL_VAR byref Zero Fseq[Value] $300
optValnumCSE morphed tree:
N004 ( 10, 7) [000159] -A-XG------- * ASG ref $VN.Void
N002 ( 6, 4) [000157] *--XG--N---- +--* IND ref $VN.Null
N001 ( 3, 2) [000169] ------------ | \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] $300
N003 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use) $VN.Null
Considering CSE #01 {$241, $1c6} [def=100, use=100, cost= 3 ]
CSE Expression :
N002 ( 3, 3) CSE #01 (def)[000012] ---X-------- * ARR_LENGTH int <l:$149, c:$148>
N001 ( 1, 1) [000011] ------------ \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
Aggressive CSE Promotion (300 >= 300)
cseRefCnt=300, aggressiveRefCnt=300, moderateRefCnt=100
defCnt=100, useCnt=100, cost=3, size=3
def_cost=1, use_cost=1, extra_no_cost=4, extra_yes_cost=0
CSE cost savings check (304 >= 200) passes
Promoting CSE:
lvaGrabTemp returning 10 (V10 rat0) (a long lifetime temp) called for CSE - aggressive.
CSE #01 is single-def, so associated CSE temp V10 will be in SSA
CSE #01 def at [000012] replaced in BB01 with def of V10
optValnumCSE morphed tree:
N009 ( 14, 12) [000014] -A-X-------- * JTRUE void
N008 ( 12, 10) [000013] NA-X---N-U-- \--* LE int <l:$14d, c:$14c>
N006 ( 10, 8) [000173] -A-X-------- +--* COMMA int <l:$149, c:$148>
N004 ( 7, 6) [000171] -A-X----R--- | +--* ASG int $VN.Void
N003 ( 3, 2) [000170] D------N---- | | +--* LCL_VAR int V10 cse1 d:1 <l:$149, c:$148>
N002 ( 3, 3) [000012] ---X-------- | | \--* ARR_LENGTH int <l:$149, c:$148>
N001 ( 1, 1) [000011] ------------ | | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N005 ( 3, 2) [000172] ------------ | \--* LCL_VAR int V10 cse1 u:1 <l:$149, c:$148>
N007 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
Working on the replacement of the CSE #01 use at [000111] in BB02
optValnumCSE morphed tree:
N020 ( 31, 29) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N019 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N018 ( 27, 26) CSE #02 (def)[000124] -A-XG------- \--* IND ref <l:$341, c:$204>
N017 ( 24, 24) [000168] -A-XG------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N015 ( 21, 22) [000166] -A-XG---R--- +--* ASG byref $VN.Void
N014 ( 3, 2) [000165] D------N---- | +--* LCL_VAR byref V09 cse0 d:1 <l:$c6, c:$c5>
N013 ( 17, 19) [000110] ---XG------- | \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N003 ( 8, 10) [000114] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N002 ( 3, 2) [000174] ------------ | | \--* LCL_VAR int V10 cse1 u:1 <l:$241, c:$240>
N012 ( 9, 9) [000115] ----G------- | \--* ADDR byref $300
N011 ( 5, 5) [000116] a---G--N---- | \--* IND struct <l:$340, c:$380>
N010 ( 4, 4) [000117] -------N---- | \--* ADD byref $300
N004 ( 1, 1) [000118] ------------ | +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N009 ( 3, 3) [000119] -------N---- | \--* ADD int <l:$159, c:$158>
N007 ( 2, 2) [000120] -------N---- | +--* LSH int <l:$157, c:$156>
N005 ( 1, 1) [000121] i----------- | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N006 ( 1, 1) [000122] -------N---- | | \--* CNS_INT int 2 $46
N008 ( 1, 1) [000123] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N016 ( 3, 2) [000167] ------------ \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
*************** Finishing PHASE Optimize Valnum CSEs
*************** Starting PHASE Assertion prop
*************** In optAssertionPropMain()
Blocks/Trees at start of phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int <l:$147, c:$146>
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1 <l:$145, c:$144>
N006 ( 6, 6) [000003] ---XG------- \--* ADD int <l:$147, c:$146>
N004 ( 4, 4) [000001] ---XG------- +--* IND int <l:$143, c:$142>
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1 $41
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1 <l:$1c2, c:$200>
N004 ( 4, 4) [000007] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000090] -------N---- \--* ADD byref $c1
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array] $43
***** BB01
STMT00002 (IL 0x010...0x014)
N009 ( 14, 12) [000014] -A-X-------- * JTRUE void
N008 ( 12, 10) [000013] NA-X---N-U-- \--* LE int <l:$14d, c:$14c>
N006 ( 10, 8) [000173] -A-X-------- +--* COMMA int <l:$149, c:$148>
N004 ( 7, 6) [000171] -A-X----R--- | +--* ASG int $VN.Void
N003 ( 3, 2) [000170] D------N---- | | +--* LCL_VAR int V10 cse1 d:1 <l:$149, c:$148>
N002 ( 3, 3) [000012] ---X-------- | | \--* ARR_LENGTH int <l:$149, c:$148>
N001 ( 1, 1) [000011] ------------ | | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N005 ( 3, 2) [000172] ------------ | \--* LCL_VAR int V10 cse1 u:1 <l:$149, c:$148>
N007 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int $VN.Void
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int $153
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref $c2
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N006 ( 6, 6) [000019] ---XG------- \--* ADD int <l:$155, c:$154>
N004 ( 4, 4) [000017] ---XG------- +--* IND int <l:$151, c:$150>
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref $c2
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1 $45
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int $VN.Void
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int $145
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
***** BB02
STMT00005 (IL 0x031...0x038)
N020 ( 31, 29) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N019 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N018 ( 27, 26) [000124] -A-XG------- \--* IND ref <l:$341, c:$204>
N017 ( 24, 24) [000168] -A-XG------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N015 ( 21, 22) [000166] -A-XG---R--- +--* ASG byref $VN.Void
N014 ( 3, 2) [000165] D------N---- | +--* LCL_VAR byref V09 cse0 d:1 <l:$c6, c:$c5>
N013 ( 17, 19) [000110] ---XG------- | \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N003 ( 8, 10) [000114] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N002 ( 3, 2) [000174] ------------ | | \--* LCL_VAR int V10 cse1 u:1 <l:$241, c:$240>
N012 ( 9, 9) [000115] ----G------- | \--* ADDR byref $300
N011 ( 5, 5) [000116] a---G--N---- | \--* IND struct <l:$340, c:$380>
N010 ( 4, 4) [000117] -------N---- | \--* ADD byref $300
N004 ( 1, 1) [000118] ------------ | +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N009 ( 3, 3) [000119] -------N---- | \--* ADD int <l:$159, c:$158>
N007 ( 2, 2) [000120] -------N---- | +--* LSH int <l:$157, c:$156>
N005 ( 1, 1) [000121] i----------- | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N006 ( 1, 1) [000122] -------N---- | | \--* CNS_INT int 2 $46
N008 ( 1, 1) [000123] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N016 ( 3, 2) [000167] ------------ \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int $1d3
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1 $1d3
N002 ( 3, 2) [000036] #----O------ \--* IND int $1d3
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use) $80
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int <l:$15e, c:$15d>
N008 ( 10, 9) [000047] n----------- +--* IND int <l:$284, c:$184>
N007 ( 8, 7) [000046] -------N---- | \--* ADD int $15c
N005 ( 7, 6) [000044] #----------- | +--* IND int $1d5
N004 ( 4, 4) [000043] #----------- | | \--* IND int $1d4
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int $15b
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use) $1d3
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32 $47
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12 $44
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1 $VN.Null
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null $VN.Null
***** BB05
STMT00012 (IL ???...0x04B)
N004 ( 10, 7) [000159] -A-XG------- * ASG ref $VN.Void
N002 ( 6, 4) [000157] *--XG--N---- +--* IND ref $VN.Null
N001 ( 3, 2) [000169] ------------ | \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] $300
N003 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use) $VN.Null
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use) $80
-------------------------------------------------------------------------------------------------------------------
GenTreeNode creates assertion:
N004 ( 4, 4) [000001] ---XG------- * IND int <l:$143, c:$142>
In BB01 New Global Constant Assertion: (128, 0) ($80,$0) V00.01 != null index=#01, mask=0000000000000001
GenTreeNode creates assertion:
N002 ( 3, 3) [000012] ---X-------- * ARR_LENGTH int <l:$149, c:$148>
In BB01 New Global Constant Assertion: (512, 0) ($200,$0) V02.01 != null index=#02, mask=0000000000000002
GenTreeNode creates assertion:
N009 ( 14, 12) [000014] -A-X-------- * JTRUE void
In BB01 New Global ArrBnds Assertion: (330, -1) ($14a,$ffffffff) [idx: {ADD($41, $180)};len: {ARR_LENGTH($200)}] in range index=#03, mask=0000000000000004
After constant propagation on [000158]:
STMT00012 (IL ???...0x04B)
N004 ( 10, 7) [000159] -A-XG------- * ASG ref $VN.Void
N002 ( 6, 4) [000157] *--XG--N---- +--* IND ref $VN.Null
N001 ( 3, 2) [000169] ------------ | \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] $300
[000175] ------------ \--* CNS_INT ref null $VN.Null
optVNAssertionPropCurStmt morphed tree:
N004 ( 8, 6) [000159] -A-XG------- * ASG ref $VN.Void
N002 ( 6, 4) [000157] *--XG--N---- +--* IND ref $VN.Null
N001 ( 3, 2) [000169] ------------ | \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] $300
N003 ( 1, 1) [000175] ------------ \--* CNS_INT ref null $VN.Null
GenTreeNode creates assertion:
N002 ( 6, 4) [000157] *--XG--N---- * IND ref $VN.Null
In BB05 New Global Constant Assertion: (768, 0) ($300,$0) Value_Number {PtrToArrElem($103, $1c2, $145, $0)} is not 0 index=#04, mask=0000000000000008
BB01 valueGen = 0000000000000007 => BB06 valueGen = 0000000000000003,
BB02 valueGen = 0000000000000005 => BB04 valueGen = 0000000000000005,
BB03 valueGen = 0000000000000000
BB04 valueGen = 0000000000000000
BB05 valueGen = 0000000000000008
BB06 valueGen = 0000000000000000
AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000
AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000
AssertionPropCallback::Changed : BB01 before out -> 000000000000000F; after out -> 0000000000000007;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000003;
AssertionPropCallback::StartMerge: BB02 in -> 000000000000000F
AssertionPropCallback::Merge : BB02 in -> 000000000000000F, predBlock BB01 out -> 0000000000000007
AssertionPropCallback::EndMerge : BB02 in -> 0000000000000007
AssertionPropCallback::Changed : BB02 before out -> 000000000000000F; after out -> 0000000000000007;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000007;
AssertionPropCallback::StartMerge: BB06 in -> 000000000000000F
AssertionPropCallback::Merge : BB06 in -> 000000000000000F, predBlock BB01 out -> 0000000000000007
AssertionPropCallback::EndMerge : BB06 in -> 0000000000000003
AssertionPropCallback::Changed : BB06 before out -> 000000000000000F; after out -> 0000000000000003;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000003;
AssertionPropCallback::StartMerge: BB03 in -> 000000000000000F
AssertionPropCallback::Merge : BB03 in -> 000000000000000F, predBlock BB02 out -> 0000000000000007
AssertionPropCallback::EndMerge : BB03 in -> 0000000000000007
AssertionPropCallback::Changed : BB03 before out -> 000000000000000F; after out -> 0000000000000007;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000007;
AssertionPropCallback::StartMerge: BB04 in -> 000000000000000F
AssertionPropCallback::Merge : BB04 in -> 000000000000000F, predBlock BB02 out -> 0000000000000007
AssertionPropCallback::EndMerge : BB04 in -> 0000000000000007
AssertionPropCallback::Changed : BB04 before out -> 000000000000000F; after out -> 0000000000000007;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000007;
AssertionPropCallback::StartMerge: BB05 in -> 000000000000000F
AssertionPropCallback::Merge : BB05 in -> 000000000000000F, predBlock BB04 out -> 0000000000000007
AssertionPropCallback::Merge : BB05 in -> 0000000000000007, predBlock BB03 out -> 0000000000000007
AssertionPropCallback::EndMerge : BB05 in -> 0000000000000007
AssertionPropCallback::Changed : BB05 before out -> 000000000000000F; after out -> 000000000000000F;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000007;
AssertionPropCallback::StartMerge: BB05 in -> 0000000000000007
AssertionPropCallback::Merge : BB05 in -> 0000000000000007, predBlock BB04 out -> 0000000000000007
AssertionPropCallback::Merge : BB05 in -> 0000000000000007, predBlock BB03 out -> 0000000000000007
AssertionPropCallback::EndMerge : BB05 in -> 0000000000000007
AssertionPropCallback::Unchanged : BB05 out -> 000000000000000F; jumpDest out -> 0000000000000007
BB01 valueIn = 0000000000000000 valueOut = 0000000000000007 => BB06 valueOut= 0000000000000003
BB02 valueIn = 0000000000000007 valueOut = 0000000000000007 => BB04 valueOut= 0000000000000007
BB03 valueIn = 0000000000000007 valueOut = 0000000000000007
BB04 valueIn = 0000000000000007 valueOut = 0000000000000007
BB05 valueIn = 0000000000000007 valueOut = 000000000000000F
BB06 valueIn = 0000000000000003 valueOut = 0000000000000003
Propagating 0000000000000000 assertions for BB01, stmt STMT00000, tree [000000], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00000, tree [000087], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00000, tree [000088], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00000, tree [000001], tree -> 1
Propagating 0000000000000001 assertions for BB01, stmt STMT00000, tree [000002], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00000, tree [000003], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00000, tree [000004], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00000, tree [000005], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000006], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000089], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000090], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000007], tree -> 1
Non-null prop for index #01 in BB01:
N004 ( 4, 4) [000007] ---XG------- * IND ref <l:$1c4, c:$1c3>
Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000008], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000009], tree -> 0
Re-morphing this stmt:
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1 <l:$1c2, c:$200>
N004 ( 4, 4) [000007] n---GO------ \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000090] -------N---- \--* ADD byref $c1
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array] $43
optAssertionPropMain morphed tree:
N006 ( 4, 4) [000009] -A--GO--R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1 <l:$1c2, c:$200>
N004 ( 4, 4) [000007] n---GO------ \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000090] -------N---- \--* ADD byref $c1
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array] $43
Propagating 0000000000000001 assertions for BB01, stmt STMT00002, tree [000011], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00002, tree [000012], tree -> 2
Propagating 0000000000000003 assertions for BB01, stmt STMT00002, tree [000170], tree -> 0
Propagating 0000000000000003 assertions for BB01, stmt STMT00002, tree [000171], tree -> 0
Propagating 0000000000000003 assertions for BB01, stmt STMT00002, tree [000172], tree -> 0
Propagating 0000000000000003 assertions for BB01, stmt STMT00002, tree [000173], tree -> 0
Propagating 0000000000000003 assertions for BB01, stmt STMT00002, tree [000010], tree -> 0
Propagating 0000000000000003 assertions for BB01, stmt STMT00002, tree [000013], tree -> 0
Propagating 0000000000000003 assertions for BB01, stmt STMT00002, tree [000014], tree -> 3
Propagating 0000000000000007 assertions for BB02, stmt STMT00003, tree [000016], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00003, tree [000094], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00003, tree [000095], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00003, tree [000017], tree -> 1
Non-null prop for index #01 in BB02:
N004 ( 4, 4) [000017] ---XG------- * IND int <l:$151, c:$150>
Propagating 0000000000000007 assertions for BB02, stmt STMT00003, tree [000018], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00003, tree [000019], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00003, tree [000015], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00003, tree [000092], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00003, tree [000093], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00003, tree [000020], tree -> 1
Non-null prop for index #01 in BB02:
N010 ( 4, 4) [000020] D--XG--N---- * IND int $153
Propagating 0000000000000007 assertions for BB02, stmt STMT00003, tree [000021], tree -> 0
Re-morphing this stmt:
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int $VN.Void
N010 ( 4, 4) [000020] n---GO-N---- +--* IND int $153
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref $c2
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N006 ( 6, 6) [000019] ---XG------- \--* ADD int <l:$155, c:$154>
N004 ( 4, 4) [000017] n---GO------ +--* IND int <l:$151, c:$150>
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref $c2
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1 $45
optAssertionPropMain morphed tree:
N011 ( 11, 11) [000021] -A--GO--R--- * ASG int $VN.Void
N010 ( 4, 4) [000020] n---GO-N---- +--* IND int $153
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref $c2
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N006 ( 6, 6) [000019] ----GO------ \--* ADD int <l:$155, c:$154>
N004 ( 4, 4) [000017] n---GO------ +--* IND int <l:$151, c:$150>
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref $c2
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1 $45
Propagating 0000000000000007 assertions for BB02, stmt STMT00004, tree [000022], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00004, tree [000096], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00004, tree [000097], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00004, tree [000024], tree -> 1
Non-null prop for index #01 in BB02:
N004 ( 4, 4) [000024] D--XG--N---- * IND int $145
Propagating 0000000000000007 assertions for BB02, stmt STMT00004, tree [000023], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00004, tree [000025], tree -> 0
Re-morphing this stmt:
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int $VN.Void
N004 ( 4, 4) [000024] n---GO-N---- +--* IND int $145
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
optAssertionPropMain morphed tree:
N006 ( 6, 6) [000025] -A--GO------ * ASG int $VN.Void
N004 ( 4, 4) [000024] n---GO-N---- +--* IND int $145
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000113], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000174], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000114], tree -> 3
VN based redundant (a[i] followed by a[i]) bounds check assertion prop for index #03 in BB02:
N003 ( 8, 10) [000114] ---X-------- * ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000118], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000121], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000122], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000120], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000123], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000119], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000117], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000116], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000115], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000110], tree -> 0
Before optRemoveRangeCheck:
N013 ( 17, 19) [000110] ---XG------- * COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N003 ( 8, 10) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N002 ( 3, 2) [000174] ------------ | \--* LCL_VAR int V10 cse1 u:1 <l:$241, c:$240>
N012 ( 9, 9) [000115] ----G------- \--* ADDR byref $300
N011 ( 5, 5) [000116] a---G--N---- \--* IND struct <l:$340, c:$380>
N010 ( 4, 4) [000117] -------N---- \--* ADD byref $300
N004 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N009 ( 3, 3) [000119] -------N---- \--* ADD int <l:$159, c:$158>
N007 ( 2, 2) [000120] -------N---- +--* LSH int <l:$157, c:$156>
N005 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N006 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2 $46
N008 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
After optRemoveRangeCheck:
N011 ( 9, 9) [000110] ----G--N---- * COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N001 ( 0, 0) [000176] ------------ +--* NOP void
N010 ( 9, 9) [000115] ----G------- \--* ADDR byref $300
N009 ( 5, 5) [000116] a---G--N---- \--* IND struct <l:$340, c:$380>
N008 ( 4, 4) [000117] -------N---- \--* ADD byref $300
N002 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N007 ( 3, 3) [000119] -------N---- \--* ADD int <l:$159, c:$158>
N005 ( 2, 2) [000120] -------N---- +--* LSH int <l:$157, c:$156>
N003 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N004 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2 $46
N006 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000165], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000166], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000167], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000168], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000124], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000109], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00005, tree [000125], tree -> 0
Re-morphing this stmt:
STMT00005 (IL 0x031...0x038)
N018 ( 23, 19) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N017 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N016 ( 19, 16) [000124] -A-XG------- \--* IND ref <l:$341, c:$204>
N015 ( 16, 14) [000168] -A--G------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N013 ( 13, 12) [000166] -A--G---R--- +--* ASG byref $VN.Void
N012 ( 3, 2) [000165] D------N---- | +--* LCL_VAR byref V09 cse0 d:1 <l:$c6, c:$c5>
N011 ( 9, 9) [000110] ----G--N---- | \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N001 ( 0, 0) [000176] ------------ | +--* NOP void
N010 ( 9, 9) [000115] ----G------- | \--* ADDR byref $300
N009 ( 5, 5) [000116] a---G--N---- | \--* IND struct <l:$340, c:$380>
N008 ( 4, 4) [000117] -------N---- | \--* ADD byref $300
N002 ( 1, 1) [000118] ------------ | +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N007 ( 3, 3) [000119] -------N---- | \--* ADD int <l:$159, c:$158>
N005 ( 2, 2) [000120] -------N---- | +--* LSH int <l:$157, c:$156>
N003 ( 1, 1) [000121] i----------- | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N004 ( 1, 1) [000122] -------N---- | | \--* CNS_INT int 2 $46
N006 ( 1, 1) [000123] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N014 ( 3, 2) [000167] ------------ \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
optAssertionPropMain morphed tree:
N016 ( 23, 19) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N015 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N014 ( 19, 16) [000124] -A-XG------- \--* IND ref <l:$341, c:$204>
N013 ( 16, 14) [000168] -A--G------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N011 ( 13, 12) [000166] -A--G---R--- +--* ASG byref $VN.Void
N010 ( 3, 2) [000165] D------N---- | +--* LCL_VAR byref V09 cse0 d:1 <l:$c6, c:$c5>
N009 ( 9, 9) [000115] ----G--N---- | \--* ADDR byref $300
N008 ( 5, 5) [000116] a---G--N---- | \--* IND struct <l:$340, c:$380>
N007 ( 4, 4) [000117] -------N---- | \--* ADD byref $300
N001 ( 1, 1) [000118] ------------ | +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N006 ( 3, 3) [000119] -------N---- | \--* ADD int <l:$159, c:$158>
N004 ( 2, 2) [000120] -------N---- | +--* LSH int <l:$157, c:$156>
N002 ( 1, 1) [000121] i----------- | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 1, 1) [000122] -------N---- | | \--* CNS_INT int 2 $46
N005 ( 1, 1) [000123] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N012 ( 3, 2) [000167] ------------ \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
Propagating 0000000000000007 assertions for BB02, stmt STMT00006, tree [000035], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00006, tree [000036], tree -> 1
Propagating 0000000000000007 assertions for BB02, stmt STMT00006, tree [000037], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00006, tree [000038], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00014, tree [000040], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00014, tree [000041], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00014, tree [000042], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00014, tree [000043], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00014, tree [000044], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00014, tree [000045], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00014, tree [000046], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00014, tree [000047], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00014, tree [000050], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00014, tree [000051], tree -> 0
Propagating 0000000000000007 assertions for BB02, stmt STMT00014, tree [000160], tree -> 0
Propagating 0000000000000007 assertions for BB05, stmt STMT00011, tree [000129], tree -> 0
Propagating 0000000000000007 assertions for BB05, stmt STMT00011, tree [000128], tree -> 0
Propagating 0000000000000007 assertions for BB05, stmt STMT00011, tree [000130], tree -> 0
Propagating 0000000000000007 assertions for BB05, stmt STMT00012, tree [000169], tree -> 0
Propagating 0000000000000007 assertions for BB05, stmt STMT00012, tree [000157], tree -> 4
Propagating 000000000000000F assertions for BB05, stmt STMT00012, tree [000175], tree -> 0
Propagating 000000000000000F assertions for BB05, stmt STMT00012, tree [000159], tree -> 0
Propagating 000000000000000F assertions for BB05, stmt STMT00010, tree [000070], tree -> 0
Propagating 000000000000000F assertions for BB05, stmt STMT00010, tree [000071], tree -> 0
Propagating 0000000000000003 assertions for BB06, stmt STMT00013, tree [000091], tree -> 0
Propagating 0000000000000003 assertions for BB06, stmt STMT00013, tree [000082], tree -> 0
Propagating 0000000000000003 assertions for BB06, stmt STMT00013, tree [000083], tree -> 0
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Assertion prop
*************** Starting PHASE Optimize index checks
*************** In OptimizeRangeChecks()
Blocks/trees before phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int <l:$147, c:$146>
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1 <l:$145, c:$144>
N006 ( 6, 6) [000003] ---XG------- \--* ADD int <l:$147, c:$146>
N004 ( 4, 4) [000001] ---XG------- +--* IND int <l:$143, c:$142>
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1 $41
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A--GO--R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1 <l:$1c2, c:$200>
N004 ( 4, 4) [000007] n---GO------ \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000090] -------N---- \--* ADD byref $c1
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array] $43
***** BB01
STMT00002 (IL 0x010...0x014)
N009 ( 14, 12) [000014] -A-X-------- * JTRUE void
N008 ( 12, 10) [000013] NA-X---N-U-- \--* LE int <l:$14d, c:$14c>
N006 ( 10, 8) [000173] -A-X-------- +--* COMMA int <l:$149, c:$148>
N004 ( 7, 6) [000171] -A-X----R--- | +--* ASG int $VN.Void
N003 ( 3, 2) [000170] D------N---- | | +--* LCL_VAR int V10 cse1 d:1 <l:$149, c:$148>
N002 ( 3, 3) [000012] ---X-------- | | \--* ARR_LENGTH int <l:$149, c:$148>
N001 ( 1, 1) [000011] ------------ | | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N005 ( 3, 2) [000172] ------------ | \--* LCL_VAR int V10 cse1 u:1 <l:$149, c:$148>
N007 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A--GO--R--- * ASG int $VN.Void
N010 ( 4, 4) [000020] n---GO-N---- +--* IND int $153
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref $c2
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N006 ( 6, 6) [000019] ----GO------ \--* ADD int <l:$155, c:$154>
N004 ( 4, 4) [000017] n---GO------ +--* IND int <l:$151, c:$150>
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref $c2
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1 $45
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A--GO------ * ASG int $VN.Void
N004 ( 4, 4) [000024] n---GO-N---- +--* IND int $145
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
***** BB02
STMT00005 (IL 0x031...0x038)
N016 ( 23, 19) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N015 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N014 ( 19, 16) [000124] -A-XG------- \--* IND ref <l:$341, c:$204>
N013 ( 16, 14) [000168] -A--G------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N011 ( 13, 12) [000166] -A--G---R--- +--* ASG byref $VN.Void
N010 ( 3, 2) [000165] D------N---- | +--* LCL_VAR byref V09 cse0 d:1 <l:$c6, c:$c5>
N009 ( 9, 9) [000115] ----G--N---- | \--* ADDR byref $300
N008 ( 5, 5) [000116] a---G--N---- | \--* IND struct <l:$340, c:$380>
N007 ( 4, 4) [000117] -------N---- | \--* ADD byref $300
N001 ( 1, 1) [000118] ------------ | +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N006 ( 3, 3) [000119] -------N---- | \--* ADD int <l:$159, c:$158>
N004 ( 2, 2) [000120] -------N---- | +--* LSH int <l:$157, c:$156>
N002 ( 1, 1) [000121] i----------- | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 1, 1) [000122] -------N---- | | \--* CNS_INT int 2 $46
N005 ( 1, 1) [000123] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N012 ( 3, 2) [000167] ------------ \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int $1d3
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1 $1d3
N002 ( 3, 2) [000036] #----O------ \--* IND int $1d3
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use) $80
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int <l:$15e, c:$15d>
N008 ( 10, 9) [000047] n----------- +--* IND int <l:$284, c:$184>
N007 ( 8, 7) [000046] -------N---- | \--* ADD int $15c
N005 ( 7, 6) [000044] #----------- | +--* IND int $1d5
N004 ( 4, 4) [000043] #----------- | | \--* IND int $1d4
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int $15b
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use) $1d3
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32 $47
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12 $44
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1 $VN.Null
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null $VN.Null
***** BB05
STMT00012 (IL ???...0x04B)
N004 ( 8, 6) [000159] -A-XG------- * ASG ref $VN.Void
N002 ( 6, 4) [000157] *--XG--N---- +--* IND ref $VN.Null
N001 ( 3, 2) [000169] ------------ | \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] $300
N003 ( 1, 1) [000175] ------------ \--* CNS_INT ref null $VN.Null
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use) $80
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Optimize index checks
*************** Starting PHASE Determine first cold block
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** Finishing PHASE Determine first cold block
Trees before Rationalize IR
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int <l:$147, c:$146>
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1 <l:$145, c:$144>
N006 ( 6, 6) [000003] ---XG------- \--* ADD int <l:$147, c:$146>
N004 ( 4, 4) [000001] ---XG------- +--* IND int <l:$143, c:$142>
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1 $41
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A--GO--R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1 <l:$1c2, c:$200>
N004 ( 4, 4) [000007] n---GO------ \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000090] -------N---- \--* ADD byref $c1
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array] $43
***** BB01
STMT00002 (IL 0x010...0x014)
N009 ( 14, 12) [000014] -A-X-------- * JTRUE void
N008 ( 12, 10) [000013] NA-X---N-U-- \--* LE int <l:$14d, c:$14c>
N006 ( 10, 8) [000173] -A-X-------- +--* COMMA int <l:$149, c:$148>
N004 ( 7, 6) [000171] -A-X----R--- | +--* ASG int $VN.Void
N003 ( 3, 2) [000170] D------N---- | | +--* LCL_VAR int V10 cse1 d:1 <l:$149, c:$148>
N002 ( 3, 3) [000012] ---X-------- | | \--* ARR_LENGTH int <l:$149, c:$148>
N001 ( 1, 1) [000011] ------------ | | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N005 ( 3, 2) [000172] ------------ | \--* LCL_VAR int V10 cse1 u:1 <l:$149, c:$148>
N007 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A--GO--R--- * ASG int $VN.Void
N010 ( 4, 4) [000020] n---GO-N---- +--* IND int $153
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref $c2
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N006 ( 6, 6) [000019] ----GO------ \--* ADD int <l:$155, c:$154>
N004 ( 4, 4) [000017] n---GO------ +--* IND int <l:$151, c:$150>
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref $c2
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1 $45
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A--GO------ * ASG int $VN.Void
N004 ( 4, 4) [000024] n---GO-N---- +--* IND int $145
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
***** BB02
STMT00005 (IL 0x031...0x038)
N016 ( 23, 19) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N015 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N014 ( 19, 16) [000124] -A-XG------- \--* IND ref <l:$341, c:$204>
N013 ( 16, 14) [000168] -A--G------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N011 ( 13, 12) [000166] -A--G---R--- +--* ASG byref $VN.Void
N010 ( 3, 2) [000165] D------N---- | +--* LCL_VAR byref V09 cse0 d:1 <l:$c6, c:$c5>
N009 ( 9, 9) [000115] ----G--N---- | \--* ADDR byref $300
N008 ( 5, 5) [000116] a---G--N---- | \--* IND struct <l:$340, c:$380>
N007 ( 4, 4) [000117] -------N---- | \--* ADD byref $300
N001 ( 1, 1) [000118] ------------ | +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N006 ( 3, 3) [000119] -------N---- | \--* ADD int <l:$159, c:$158>
N004 ( 2, 2) [000120] -------N---- | +--* LSH int <l:$157, c:$156>
N002 ( 1, 1) [000121] i----------- | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 1, 1) [000122] -------N---- | | \--* CNS_INT int 2 $46
N005 ( 1, 1) [000123] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N012 ( 3, 2) [000167] ------------ \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int $1d3
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1 $1d3
N002 ( 3, 2) [000036] #----O------ \--* IND int $1d3
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use) $80
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int <l:$15e, c:$15d>
N008 ( 10, 9) [000047] n----------- +--* IND int <l:$284, c:$184>
N007 ( 8, 7) [000046] -------N---- | \--* ADD int $15c
N005 ( 7, 6) [000044] #----------- | +--* IND int $1d5
N004 ( 4, 4) [000043] #----------- | | \--* IND int $1d4
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int $15b
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use) $1d3
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32 $47
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12 $44
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1 $VN.Null
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null $VN.Null
***** BB05
STMT00012 (IL ???...0x04B)
N004 ( 8, 6) [000159] -A-XG------- * ASG ref $VN.Void
N002 ( 6, 4) [000157] *--XG--N---- +--* IND ref $VN.Null
N001 ( 3, 2) [000169] ------------ | \--* LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] $300
N003 ( 1, 1) [000175] ------------ \--* CNS_INT ref null $VN.Null
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use) $80
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Rationalize IR
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N008 ( 6, 6) [000005] DA-XG------- * STORE_LCL_VAR int V01 loc0 d:1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N006 ( 4, 4) [000009] DA--GO------ * STORE_LCL_VAR ref V02 loc1 d:1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 7, 6) [000171] DA-X-------- * STORE_LCL_VAR int V10 cse1 d:1
Rewriting GT_ADDR(GT_IND(X)) to X:
N001 ( 1, 1) [000118] ------------ t118 = LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 1, 1) [000122] -------N---- t122 = CNS_INT int 2 $46
/--* t121 int
+--* t122 int
N004 ( 2, 2) [000120] -------N---- t120 = * LSH int <l:$157, c:$156>
N005 ( 1, 1) [000123] ------------ t123 = CNS_INT int 8 Fseq[#FirstElem] $42
/--* t120 int
+--* t123 int
N006 ( 3, 3) [000119] -------N---- t119 = * ADD int <l:$159, c:$158>
/--* t118 ref
+--* t119 int
N007 ( 4, 4) [000117] -------N---- t117 = * ADD byref $300
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N011 ( 13, 12) [000166] DA--G------- * STORE_LCL_VAR byref V09 cse0 d:1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N016 ( 23, 19) [000125] DA-XG------- * STORE_LCL_VAR ref V07 tmp2 d:1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 3, 3) [000038] DA---O------ * STORE_LCL_VAR int V05 tmp0 d:1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 5, 4) [000130] DA---------- * STORE_LCL_VAR ref V08 tmp3 d:1
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen LIR
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen LIR
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i LIR
BB04 [0008] 1 BB02 0.25 [???..???) i label target LIR
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen LIR
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
[000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000087] ------------ t87 = CNS_INT int 8 field offset Fseq[_size] $42
/--* t0 ref
+--* t87 int
N003 ( 2, 2) [000088] -------N---- t88 = * ADD byref $c0
/--* t88 byref
N004 ( 4, 4) [000001] ---XG------- t1 = * IND int <l:$143, c:$142>
N005 ( 1, 1) [000002] ------------ t2 = CNS_INT int -1 $41
/--* t1 int
+--* t2 int
N006 ( 6, 6) [000003] ---XG------- t3 = * ADD int <l:$147, c:$146>
/--* t3 int
N008 ( 6, 6) [000005] DA-XG------- * STORE_LCL_VAR int V01 loc0 d:1
[000178] ------------ IL_OFFSET void IL offset: 0x9
N001 ( 1, 1) [000006] ------------ t6 = LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ t89 = CNS_INT int 4 field offset Fseq[_array] $43
/--* t6 ref
+--* t89 int
N003 ( 2, 2) [000090] -------N---- t90 = * ADD byref $c1
/--* t90 byref
N004 ( 4, 4) [000007] n---GO------ t7 = * IND ref <l:$1c4, c:$1c3>
/--* t7 ref
N006 ( 4, 4) [000009] DA--GO------ * STORE_LCL_VAR ref V02 loc1 d:1
[000179] ------------ IL_OFFSET void IL offset: 0x10
N001 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
/--* t11 ref
N002 ( 3, 3) [000012] ---X-------- t12 = * ARR_LENGTH int <l:$149, c:$148>
/--* t12 int
N004 ( 7, 6) [000171] DA-X-------- * STORE_LCL_VAR int V10 cse1 d:1
N005 ( 3, 2) [000172] ------------ t172 = LCL_VAR int V10 cse1 u:1 <l:$149, c:$148>
N007 ( 1, 1) [000010] ------------ t10 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t172 int
+--* t10 int
N008 ( 12, 10) [000013] N--X---N-U-- t13 = * LE int <l:$14d, c:$14c>
/--* t13 int
N009 ( 14, 12) [000014] ---X-------- * JTRUE void
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
[000180] ------------ IL_OFFSET void IL offset: 0x1c
N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ t94 = CNS_INT int 12 field offset Fseq[_version] $44
/--* t16 ref
+--* t94 int
N003 ( 2, 2) [000095] -------N---- t95 = * ADD byref $c2
/--* t95 byref
N004 ( 4, 4) [000017] n---GO------ t17 = * IND int <l:$151, c:$150>
N005 ( 1, 1) [000018] ------------ t18 = CNS_INT int 1 $45
/--* t17 int
+--* t18 int
N006 ( 6, 6) [000019] ----GO------ t19 = * ADD int <l:$155, c:$154>
N007 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ t92 = CNS_INT int 12 field offset Fseq[_version] $44
/--* t15 ref
+--* t92 int
N009 ( 2, 2) [000093] -------N---- t93 = * ADD byref $c2
/--* t93 byref
+--* t19 int
[000181] -A--GO------ * STOREIND int
[000182] ------------ IL_OFFSET void IL offset: 0x2a
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ t96 = CNS_INT int 8 field offset Fseq[_size] $42
/--* t22 ref
+--* t96 int
N003 ( 2, 2) [000097] -------N---- t97 = * ADD byref $c0
N005 ( 1, 1) [000023] ------------ t23 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t97 byref
+--* t23 int
[000183] -A--GO------ * STOREIND int
[000184] ------------ IL_OFFSET void IL offset: 0x31
N001 ( 1, 1) [000118] ------------ t118 = LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 1, 1) [000122] -------N---- t122 = CNS_INT int 2 $46
/--* t121 int
+--* t122 int
N004 ( 2, 2) [000120] -------N---- t120 = * LSH int <l:$157, c:$156>
N005 ( 1, 1) [000123] ------------ t123 = CNS_INT int 8 Fseq[#FirstElem] $42
/--* t120 int
+--* t123 int
N006 ( 3, 3) [000119] -------N---- t119 = * ADD int <l:$159, c:$158>
/--* t118 ref
+--* t119 int
N007 ( 4, 4) [000117] -------N---- t117 = * ADD byref $300
/--* t117 byref
N011 ( 13, 12) [000166] DA--G------- * STORE_LCL_VAR byref V09 cse0 d:1
N012 ( 3, 2) [000167] ------------ t167 = LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
/--* t167 byref
N014 ( 19, 16) [000124] ---XG------- t124 = * IND ref <l:$341, c:$204>
/--* t124 ref
N016 ( 23, 19) [000125] DA-XG------- * STORE_LCL_VAR ref V07 tmp2 d:1
[000185] ------------ IL_OFFSET void IL offset: 0x39
N001 ( 1, 1) [000035] ------------ t35 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t35 ref
N002 ( 3, 2) [000036] #----O------ t36 = * IND int $1d3
/--* t36 int
N004 ( 3, 3) [000038] DA---O------ * STORE_LCL_VAR int V05 tmp0 d:1
N001 ( 1, 1) [000040] ------------ t40 = LCL_VAR int V05 tmp0 u:1 (last use) $1d3
N002 ( 1, 1) [000041] ------------ t41 = CNS_INT int 32 $47
/--* t40 int
+--* t41 int
N003 ( 2, 2) [000042] -------N---- t42 = * ADD int $15b
/--* t42 int
N004 ( 4, 4) [000043] #----------- t43 = * IND int $1d4
/--* t43 int
N005 ( 7, 6) [000044] #----------- t44 = * IND int $1d5
N006 ( 1, 1) [000045] ------------ t45 = CNS_INT int 12 $44
/--* t44 int
+--* t45 int
N007 ( 8, 7) [000046] -------N---- t46 = * ADD int $15c
/--* t46 int
N008 ( 10, 9) [000047] n----------- t47 = * IND int <l:$284, c:$184>
N009 ( 1, 1) [000050] ------------ t50 = CNS_INT int 0 $40
/--* t47 int
+--* t50 int
N010 ( 12, 11) [000051] J------N---- t51 = * EQ int <l:$15e, c:$15d>
/--* t51 int
N011 ( 14, 13) [000160] ------------ * JTRUE void
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
[000186] ------------ IL_OFFSET void IL offset: 0x40
N001 ( 1, 1) [000129] ------------ t129 = CNS_INT ref null $VN.Null
/--* t129 ref
N003 ( 5, 4) [000130] DA---------- * STORE_LCL_VAR ref V08 tmp3 d:1
N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] $300
N003 ( 1, 1) [000175] ------------ t175 = CNS_INT ref null $VN.Null
/--* t169 byref
+--* t175 ref
[000187] -A-XG------- * STOREIND ref
[000188] ------------ IL_OFFSET void IL offset: 0x50
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
/--* t70 ref
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
[000189] ------------ IL_OFFSET void IL offset: 0x16
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t82 ref this in ecx
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Do 'simple' lowering
*************** Finishing PHASE Do 'simple' lowering
*************** In fgDebugCheckBBlist
Trees before Lowering nodeinfo
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen LIR
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen LIR
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i LIR
BB04 [0008] 1 BB02 0.25 [???..???) i label target LIR
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen LIR
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
[000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000087] ------------ t87 = CNS_INT int 8 field offset Fseq[_size] $42
/--* t0 ref
+--* t87 int
N003 ( 2, 2) [000088] -------N---- t88 = * ADD byref $c0
/--* t88 byref
N004 ( 4, 4) [000001] ---XG------- t1 = * IND int <l:$143, c:$142>
N005 ( 1, 1) [000002] ------------ t2 = CNS_INT int -1 $41
/--* t1 int
+--* t2 int
N006 ( 6, 6) [000003] ---XG------- t3 = * ADD int <l:$147, c:$146>
/--* t3 int
N008 ( 6, 6) [000005] DA-XG------- * STORE_LCL_VAR int V01 loc0 d:1
[000178] ------------ IL_OFFSET void IL offset: 0x9
N001 ( 1, 1) [000006] ------------ t6 = LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ t89 = CNS_INT int 4 field offset Fseq[_array] $43
/--* t6 ref
+--* t89 int
N003 ( 2, 2) [000090] -------N---- t90 = * ADD byref $c1
/--* t90 byref
N004 ( 4, 4) [000007] n---GO------ t7 = * IND ref <l:$1c4, c:$1c3>
/--* t7 ref
N006 ( 4, 4) [000009] DA--GO------ * STORE_LCL_VAR ref V02 loc1 d:1
[000179] ------------ IL_OFFSET void IL offset: 0x10
N001 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
[000190] ------------ t190 = CNS_INT int 4
/--* t11 ref
+--* t190 int
[000191] ------------ t191 = * ADD ref
/--* t191 ref
N002 ( 3, 3) [000012] ---X-------- t12 = * IND int <l:$149, c:$148>
/--* t12 int
N004 ( 7, 6) [000171] DA-X-------- * STORE_LCL_VAR int V10 cse1 d:1
N005 ( 3, 2) [000172] ------------ t172 = LCL_VAR int V10 cse1 u:1 <l:$149, c:$148>
N007 ( 1, 1) [000010] ------------ t10 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t172 int
+--* t10 int
N008 ( 12, 10) [000013] N--X---N-U-- t13 = * LE int <l:$14d, c:$14c>
/--* t13 int
N009 ( 14, 12) [000014] ---X-------- * JTRUE void
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
[000180] ------------ IL_OFFSET void IL offset: 0x1c
N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ t94 = CNS_INT int 12 field offset Fseq[_version] $44
/--* t16 ref
+--* t94 int
N003 ( 2, 2) [000095] -------N---- t95 = * ADD byref $c2
/--* t95 byref
N004 ( 4, 4) [000017] n---GO------ t17 = * IND int <l:$151, c:$150>
N005 ( 1, 1) [000018] ------------ t18 = CNS_INT int 1 $45
/--* t17 int
+--* t18 int
N006 ( 6, 6) [000019] ----GO------ t19 = * ADD int <l:$155, c:$154>
N007 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ t92 = CNS_INT int 12 field offset Fseq[_version] $44
/--* t15 ref
+--* t92 int
N009 ( 2, 2) [000093] -------N---- t93 = * ADD byref $c2
/--* t93 byref
+--* t19 int
[000181] -A--GO------ * STOREIND int
[000182] ------------ IL_OFFSET void IL offset: 0x2a
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ t96 = CNS_INT int 8 field offset Fseq[_size] $42
/--* t22 ref
+--* t96 int
N003 ( 2, 2) [000097] -------N---- t97 = * ADD byref $c0
N005 ( 1, 1) [000023] ------------ t23 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t97 byref
+--* t23 int
[000183] -A--GO------ * STOREIND int
[000184] ------------ IL_OFFSET void IL offset: 0x31
N001 ( 1, 1) [000118] ------------ t118 = LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 1, 1) [000122] -------N---- t122 = CNS_INT int 2 $46
/--* t121 int
+--* t122 int
N004 ( 2, 2) [000120] -------N---- t120 = * LSH int <l:$157, c:$156>
N005 ( 1, 1) [000123] ------------ t123 = CNS_INT int 8 Fseq[#FirstElem] $42
/--* t120 int
+--* t123 int
N006 ( 3, 3) [000119] -------N---- t119 = * ADD int <l:$159, c:$158>
/--* t118 ref
+--* t119 int
N007 ( 4, 4) [000117] -------N---- t117 = * ADD byref $300
/--* t117 byref
N011 ( 13, 12) [000166] DA--G------- * STORE_LCL_VAR byref V09 cse0 d:1
N012 ( 3, 2) [000167] ------------ t167 = LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
/--* t167 byref
N014 ( 19, 16) [000124] ---XG------- t124 = * IND ref <l:$341, c:$204>
/--* t124 ref
N016 ( 23, 19) [000125] DA-XG------- * STORE_LCL_VAR ref V07 tmp2 d:1
[000185] ------------ IL_OFFSET void IL offset: 0x39
N001 ( 1, 1) [000035] ------------ t35 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t35 ref
N002 ( 3, 2) [000036] #----O------ t36 = * IND int $1d3
/--* t36 int
N004 ( 3, 3) [000038] DA---O------ * STORE_LCL_VAR int V05 tmp0 d:1
N001 ( 1, 1) [000040] ------------ t40 = LCL_VAR int V05 tmp0 u:1 (last use) $1d3
N002 ( 1, 1) [000041] ------------ t41 = CNS_INT int 32 $47
/--* t40 int
+--* t41 int
N003 ( 2, 2) [000042] -------N---- t42 = * ADD int $15b
/--* t42 int
N004 ( 4, 4) [000043] #----------- t43 = * IND int $1d4
/--* t43 int
N005 ( 7, 6) [000044] #----------- t44 = * IND int $1d5
N006 ( 1, 1) [000045] ------------ t45 = CNS_INT int 12 $44
/--* t44 int
+--* t45 int
N007 ( 8, 7) [000046] -------N---- t46 = * ADD int $15c
/--* t46 int
N008 ( 10, 9) [000047] n----------- t47 = * IND int <l:$284, c:$184>
N009 ( 1, 1) [000050] ------------ t50 = CNS_INT int 0 $40
/--* t47 int
+--* t50 int
N010 ( 12, 11) [000051] J------N---- t51 = * EQ int <l:$15e, c:$15d>
/--* t51 int
N011 ( 14, 13) [000160] ------------ * JTRUE void
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
[000186] ------------ IL_OFFSET void IL offset: 0x40
N001 ( 1, 1) [000129] ------------ t129 = CNS_INT ref null $VN.Null
/--* t129 ref
N003 ( 5, 4) [000130] DA---------- * STORE_LCL_VAR ref V08 tmp3 d:1
N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] $300
N003 ( 1, 1) [000175] ------------ t175 = CNS_INT ref null $VN.Null
/--* t169 byref
+--* t175 ref
[000187] -A-XG------- * STOREIND ref
[000188] ------------ IL_OFFSET void IL offset: 0x50
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
/--* t70 ref
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
[000189] ------------ IL_OFFSET void IL offset: 0x16
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t82 ref this in ecx
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Lowering nodeinfo
Addressing mode:
Base
N001 ( 1, 1) [000000] ------------ * LCL_VAR ref V00 this u:1 $80
+ 8
Removing unused node:
N002 ( 1, 1) [000087] -c---------- * CNS_INT int 8 field offset Fseq[_size] $42
New addressing mode node:
N003 ( 2, 2) [000088] ------------ * LEA(b+8) byref
Addressing mode:
Base
N001 ( 1, 1) [000006] ------------ * LCL_VAR ref V00 this u:1 $80
+ 4
Removing unused node:
N002 ( 1, 1) [000089] -c---------- * CNS_INT int 4 field offset Fseq[_array] $43
New addressing mode node:
N003 ( 2, 2) [000090] ------------ * LEA(b+4) byref
Addressing mode:
Base
N001 ( 1, 1) [000011] ------------ * LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
+ 4
Removing unused node:
[000190] -c---------- * CNS_INT int 4
New addressing mode node:
[000191] ------------ * LEA(b+4) ref
Addressing mode:
Base
N001 ( 1, 1) [000016] ------------ * LCL_VAR ref V00 this u:1 $80
+ 12
Removing unused node:
N002 ( 1, 1) [000094] -c---------- * CNS_INT int 12 field offset Fseq[_version] $44
New addressing mode node:
N003 ( 2, 2) [000095] ------------ * LEA(b+12) byref
Addressing mode:
Base
N007 ( 1, 1) [000015] ------------ * LCL_VAR ref V00 this u:1 $80
+ 12
Removing unused node:
N008 ( 1, 1) [000092] -c---------- * CNS_INT int 12 field offset Fseq[_version] $44
New addressing mode node:
N009 ( 2, 2) [000093] ------------ * LEA(b+12) byref
Lower succesfully detected an assignment of the form: *addrMode BinOp= source
N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR ref V00 this u:1 $80
/--* t16 ref
N003 ( 2, 2) [000095] -c---------- t95 = * LEA(b+12) byref
/--* t95 byref
N004 ( 4, 4) [000017] n---GO------ t17 = * IND int <l:$151, c:$150>
N005 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 1 $45
/--* t17 int
+--* t18 int
N006 ( 6, 6) [000019] ----GO------ t19 = * ADD int <l:$155, c:$154>
N007 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $80
/--* t15 ref
N009 ( 2, 2) [000093] ------------ t93 = * LEA(b+12) byref
/--* t93 byref
+--* t19 int
[000181] -A--GO------ * STOREIND int
Addressing mode:
Base
N001 ( 1, 1) [000022] ------------ * LCL_VAR ref V00 this u:1 $80
+ 8
Removing unused node:
N002 ( 1, 1) [000096] -c---------- * CNS_INT int 8 field offset Fseq[_size] $42
New addressing mode node:
N003 ( 2, 2) [000097] ------------ * LEA(b+8) byref
Lower of StoreInd didn't mark the node as self contained for reason: 4
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V00 this u:1 $80
/--* t22 ref
N003 ( 2, 2) [000097] ------------ t97 = * LEA(b+8) byref
N005 ( 1, 1) [000023] ------------ t23 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t97 byref
+--* t23 int
[000183] -A--GO------ * STOREIND int
Addressing mode:
Base
N001 ( 1, 1) [000118] ------------ * LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
+ Index * 4 + 8
N002 ( 1, 1) [000121] ------------ * LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
Removing unused node:
N006 ( 3, 3) [000119] -------N---- * ADD int <l:$159, c:$158>
Removing unused node:
N005 ( 1, 1) [000123] -c---------- * CNS_INT int 8 Fseq[#FirstElem] $42
Removing unused node:
N004 ( 2, 2) [000120] -------N---- * LSH int <l:$157, c:$156>
Removing unused node:
N003 ( 1, 1) [000122] -c-----N---- * CNS_INT int 2 $46
New addressing mode node:
N007 ( 4, 4) [000117] -------N---- * LEA(b+(i*4)+8) byref
Addressing mode:
Base
N001 ( 1, 1) [000040] ------------ * LCL_VAR int V05 tmp0 u:1 (last use) $1d3
+ 32
Removing unused node:
N002 ( 1, 1) [000041] -c---------- * CNS_INT int 32 $47
New addressing mode node:
N003 ( 2, 2) [000042] ------------ * LEA(b+32) int
Addressing mode:
Base
N005 ( 7, 6) [000044] #----------- * IND int $1d5
+ 12
Removing unused node:
N006 ( 1, 1) [000045] -c---------- * CNS_INT int 12 $44
New addressing mode node:
N007 ( 8, 7) [000046] ------------ * LEA(b+12) int
Lower of StoreInd didn't mark the node as self contained for reason: 4
N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] $300
N003 ( 1, 1) [000175] ------------ t175 = CNS_INT ref null $VN.Null
/--* t169 byref
+--* t175 ref
[000187] -A-XG------- * STOREIND ref
lowering GT_RETURN
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
============lowering call (before):
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t82 ref this in ecx
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
objp:
======
lowering arg : N001 ( 0, 0) [000091] ----------L- * ARGPLACE ref $202
args:
======
late:
======
lowering arg : N002 ( 1, 1) [000082] ------------ * LCL_VAR ref V00 this u:1 (last use) $80
new node is : [000192] ------------ * PUTARG_REG ref REG ecx
lowering call (after):
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t82 ref
[000192] ------------ t192 = * PUTARG_REG ref REG ecx
/--* t192 ref this in ecx
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
Lower has completed modifying nodes.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen LIR
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen LIR
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i LIR
BB04 [0008] 1 BB02 0.25 [???..???) i label target LIR
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen LIR
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
[000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V00 this u:1 $80
/--* t0 ref
N003 ( 2, 2) [000088] -c---------- t88 = * LEA(b+8) byref
/--* t88 byref
N004 ( 4, 4) [000001] ---XG------- t1 = * IND int <l:$143, c:$142>
N005 ( 1, 1) [000002] -c---------- t2 = CNS_INT int -1 $41
/--* t1 int
+--* t2 int
N006 ( 6, 6) [000003] ---XG------- t3 = * ADD int <l:$147, c:$146>
/--* t3 int
N008 ( 6, 6) [000005] DA-XG------- * STORE_LCL_VAR int V01 loc0 d:1
[000178] ------------ IL_OFFSET void IL offset: 0x9
N001 ( 1, 1) [000006] ------------ t6 = LCL_VAR ref V00 this u:1 $80
/--* t6 ref
N003 ( 2, 2) [000090] -c---------- t90 = * LEA(b+4) byref
/--* t90 byref
N004 ( 4, 4) [000007] n---GO------ t7 = * IND ref <l:$1c4, c:$1c3>
/--* t7 ref
N006 ( 4, 4) [000009] DA--GO------ * STORE_LCL_VAR ref V02 loc1 d:1
[000179] ------------ IL_OFFSET void IL offset: 0x10
N001 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
/--* t11 ref
[000191] -c---------- t191 = * LEA(b+4) ref
/--* t191 ref
N002 ( 3, 3) [000012] ---X-------- t12 = * IND int <l:$149, c:$148>
/--* t12 int
N004 ( 7, 6) [000171] DA-X-------- * STORE_LCL_VAR int V10 cse1 d:1
N005 ( 3, 2) [000172] ------------ t172 = LCL_VAR int V10 cse1 u:1 <l:$149, c:$148>
N007 ( 1, 1) [000010] ------------ t10 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t172 int
+--* t10 int
N008 ( 12, 10) [000013] N--X---N-U-- * LE void <l:$14d, c:$14c>
N009 ( 14, 12) [000014] ---X-------- * JTRUE void
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
[000180] ------------ IL_OFFSET void IL offset: 0x1c
N001 ( 1, 1) [000016] -c---------- t16 = LCL_VAR ref V00 this u:1 $80
/--* t16 ref
N003 ( 2, 2) [000095] -c---------- t95 = * LEA(b+12) byref
/--* t95 byref
N004 ( 4, 4) [000017] nc--GO------ t17 = * IND int <l:$151, c:$150>
N005 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 1 $45
/--* t17 int
+--* t18 int
N006 ( 6, 6) [000019] -c--GO------ t19 = * ADD int <l:$155, c:$154>
N007 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $80
/--* t15 ref
N009 ( 2, 2) [000093] -c---------- t93 = * LEA(b+12) byref
/--* t93 byref
+--* t19 int
[000181] -A--GO------ * STOREIND int
[000182] ------------ IL_OFFSET void IL offset: 0x2a
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V00 this u:1 $80
/--* t22 ref
N003 ( 2, 2) [000097] -c---------- t97 = * LEA(b+8) byref
N005 ( 1, 1) [000023] ------------ t23 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t97 byref
+--* t23 int
[000183] -A--GO------ * STOREIND int
[000184] ------------ IL_OFFSET void IL offset: 0x31
N001 ( 1, 1) [000118] ------------ t118 = LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t118 ref
+--* t121 int
N007 ( 4, 4) [000117] -------N---- t117 = * LEA(b+(i*4)+8) byref
/--* t117 byref
N011 ( 13, 12) [000166] DA--G------- * STORE_LCL_VAR byref V09 cse0 d:1
N012 ( 3, 2) [000167] ------------ t167 = LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
/--* t167 byref
N014 ( 19, 16) [000124] ---XG------- t124 = * IND ref <l:$341, c:$204>
/--* t124 ref
N016 ( 23, 19) [000125] DA-XG------- * STORE_LCL_VAR ref V07 tmp2 d:1
[000185] ------------ IL_OFFSET void IL offset: 0x39
N001 ( 1, 1) [000035] ------------ t35 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t35 ref
N002 ( 3, 2) [000036] #----O------ t36 = * IND int $1d3
/--* t36 int
N004 ( 3, 3) [000038] DA---O------ * STORE_LCL_VAR int V05 tmp0 d:1
N001 ( 1, 1) [000040] ------------ t40 = LCL_VAR int V05 tmp0 u:1 (last use) $1d3
/--* t40 int
N003 ( 2, 2) [000042] -c---------- t42 = * LEA(b+32) int
/--* t42 int
N004 ( 4, 4) [000043] #----------- t43 = * IND int $1d4
/--* t43 int
N005 ( 7, 6) [000044] #----------- t44 = * IND int $1d5
/--* t44 int
N007 ( 8, 7) [000046] -c---------- t46 = * LEA(b+12) int
/--* t46 int
N008 ( 10, 9) [000047] nc---------- t47 = * IND int <l:$284, c:$184>
N009 ( 1, 1) [000050] -c---------- t50 = CNS_INT int 0 $40
/--* t47 int
+--* t50 int
N010 ( 12, 11) [000051] J------N---- * EQ void <l:$15e, c:$15d>
N011 ( 14, 13) [000160] ------------ * JTRUE void
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
[000186] ------------ IL_OFFSET void IL offset: 0x40
N001 ( 1, 1) [000129] ------------ t129 = CNS_INT ref null $VN.Null
/--* t129 ref
N003 ( 5, 4) [000130] DA---------- * STORE_LCL_VAR ref V08 tmp3 d:1
N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] $300
N003 ( 1, 1) [000175] ------------ t175 = CNS_INT ref null $VN.Null
/--* t169 byref
+--* t175 ref
[000187] -A-XG------- * STOREIND ref
[000188] ------------ IL_OFFSET void IL offset: 0x50
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
/--* t70 ref
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
[000189] ------------ IL_OFFSET void IL offset: 0x16
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t82 ref
[000192] ------------ t192 = * PUTARG_REG ref REG ecx
/--* t192 ref this in ecx
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V10: refCnt = 1, refCntWtd = 1
New refCnts for V10: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 4, refCntWtd = 4
New refCnts for V00: refCnt = 5, refCntWtd = 5
New refCnts for V01: refCnt = 3, refCntWtd = 3
New refCnts for V02: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 4, refCntWtd = 4
New refCnts for V09: refCnt = 1, refCntWtd = 1
New refCnts for V09: refCnt = 2, refCntWtd = 2
New refCnts for V07: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 6, refCntWtd = 6
New refCnts for V05: refCnt = 1, refCntWtd = 2
New refCnts for V05: refCnt = 2, refCntWtd = 4
New refCnts for V08: refCnt = 1, refCntWtd = 1
New refCnts for V09: refCnt = 3, refCntWtd = 3
New refCnts for V07: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 7, refCntWtd = 6
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 8, refCntWtd = 7
New refCnts for V00: refCnt = 9, refCntWtd = 8
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 int
; V02 loc1 ref class-hnd
; V03 loc2 struct ( 4)
; V04 loc3 struct ( 4) ld-addr-op
; V05 tmp0 int "impRuntimeLookup slot"
; V06 tmp1 int "spilling Runtime Lookup tree"
; V07 tmp2 ref V03.Value(offs=0x00) P-INDEP "field V03.Value (fldOffset=0x0)"
; V08 tmp3 ref V04.Value(offs=0x00) P-INDEP "field V04.Value (fldOffset=0x0)"
; V09 cse0 byref "CSE - aggressive"
; V10 cse1 int "CSE - aggressive"
In fgLocalVarLivenessInit
Tracked variable (8 out of 11) table:
V00 this [ ref]: refCnt = 9, refCntWtd = 8
V01 loc0 [ int]: refCnt = 4, refCntWtd = 4
V05 tmp0 [ int]: refCnt = 2, refCntWtd = 4
V02 loc1 [ ref]: refCnt = 3, refCntWtd = 3
V09 cse0 [ byref]: refCnt = 3, refCntWtd = 3
V07 tmp2 [ ref]: refCnt = 2, refCntWtd = 2
V10 cse1 [ int]: refCnt = 2, refCntWtd = 2
V08 tmp3 [ ref]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 } + ByrefExposed + GcHeap
DEF(3)={ V01 V02 V10}
BB02 USE(3)={V00 V01 V02 } + ByrefExposed + GcHeap
DEF(3)={ V05 V09 V07}
BB03 USE(0)={}
DEF(0)={}
BB04 USE(0)={}
DEF(0)={}
BB05 USE(2)={V09 V07 }
DEF(1)={ V08}
BB06 USE(1)={V00} + ByrefExposed + GcHeap
DEF(0)={ } + ByrefExposed* + GcHeap*
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00 } + ByrefExposed + GcHeap
OUT(3)={V00 V01 V02} + ByrefExposed + GcHeap
BB02 IN (3)={V00 V01 V02 } + ByrefExposed + GcHeap
OUT(2)={ V09 V07}
BB03 IN (2)={V09 V07}
OUT(2)={V09 V07}
BB04 IN (2)={V09 V07}
OUT(2)={V09 V07}
BB05 IN (2)={V09 V07}
OUT(0)={ }
BB06 IN (1)={V00} + ByrefExposed + GcHeap
OUT(0)={ }
Removing dead store:
N003 ( 5, 4) [000130] DA---------- * STORE_LCL_VAR ref V08 tmp3 d:1 (last use)
Removing dead node:
N001 ( 1, 1) [000129] ------------ * CNS_INT ref null $VN.Null
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen LIR
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen LIR
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i LIR
BB04 [0008] 1 BB02 0.25 [???..???) i label target LIR
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen LIR
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
Reversing a conditional jump around an unconditional jump (BB02 -> BB04 -> BB05)
After reversing the jump:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen LIR
BB02 [0002] 1 BB01 1 [01C..040)-> BB05 ( cond ) i label target idxlen LIR
BB04 [0008] 1 BB02 0.25 [???..???) i label target LIR
BB05 [0006] 2 BB02,BB04 1 [040..052) (return) i label target idxlen LIR
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
Compacting blocks BB04 and BB05:
Second block has multiple incoming edges
*************** In fgDebugCheckBBlist
Removing conditional jump to next block (BB02 -> BB04)
Compacting blocks BB02 and BB04:
*************** In fgDebugCheckBBlist
After updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen LIR
BB02 [0002] 1 BB01 1 [01C..052) (return) i label target idxlen LIR
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
had to run another liveness pass:
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 int
; V02 loc1 ref class-hnd
; V03 loc2 struct ( 4)
; V04 loc3 struct ( 4) ld-addr-op
; V05 tmp0 int "impRuntimeLookup slot"
; V06 tmp1 int "spilling Runtime Lookup tree"
; V07 tmp2 ref V03.Value(offs=0x00) P-INDEP "field V03.Value (fldOffset=0x0)"
; V08 tmp3 ref V04.Value(offs=0x00) P-INDEP "field V04.Value (fldOffset=0x0)"
; V09 cse0 byref "CSE - aggressive"
; V10 cse1 int "CSE - aggressive"
In fgLocalVarLivenessInit
Tracked variable (8 out of 11) table:
V00 this [ ref]: refCnt = 9, refCntWtd = 8
V01 loc0 [ int]: refCnt = 4, refCntWtd = 4
V05 tmp0 [ int]: refCnt = 2, refCntWtd = 4
V02 loc1 [ ref]: refCnt = 3, refCntWtd = 3
V09 cse0 [ byref]: refCnt = 3, refCntWtd = 3
V07 tmp2 [ ref]: refCnt = 2, refCntWtd = 2
V10 cse1 [ int]: refCnt = 2, refCntWtd = 2
V08 tmp3 [ ref]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 } + ByrefExposed + GcHeap
DEF(3)={ V01 V02 V10}
BB02 USE(3)={V00 V01 V02 } + ByrefExposed + GcHeap
DEF(3)={ V05 V09 V07}
BB06 USE(1)={V00} + ByrefExposed + GcHeap
DEF(0)={ } + ByrefExposed* + GcHeap*
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00 } + ByrefExposed + GcHeap
OUT(3)={V00 V01 V02} + ByrefExposed + GcHeap
BB02 IN (3)={V00 V01 V02} + ByrefExposed + GcHeap
OUT(0)={ }
BB06 IN (1)={V00} + ByrefExposed + GcHeap
OUT(0)={ }
Removing dead store:
N004 ( 3, 3) [000038] DA---O------ * STORE_LCL_VAR int V05 tmp0 d:1 (last use)
Removing dead node:
N002 ( 3, 2) [000036] #----O------ * IND int $1d3
Removing dead LclVar use:
N001 ( 1, 1) [000035] ------------ * LCL_VAR ref V00 this u:1 (last use) $80
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 2, refCntWtd = 2
New refCnts for V10: refCnt = 1, refCntWtd = 1
New refCnts for V10: refCnt = 2, refCntWtd = 2
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 4, refCntWtd = 4
New refCnts for V00: refCnt = 5, refCntWtd = 5
New refCnts for V01: refCnt = 3, refCntWtd = 3
New refCnts for V02: refCnt = 3, refCntWtd = 3
New refCnts for V01: refCnt = 4, refCntWtd = 4
New refCnts for V09: refCnt = 1, refCntWtd = 1
New refCnts for V09: refCnt = 2, refCntWtd = 2
New refCnts for V07: refCnt = 1, refCntWtd = 1
New refCnts for V09: refCnt = 3, refCntWtd = 3
New refCnts for V07: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 6, refCntWtd = 5
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 7, refCntWtd = 6
New refCnts for V00: refCnt = 8, refCntWtd = 7
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen LIR
BB02 [0002] 1 BB01 1 [01C..052) (return) i label target idxlen LIR
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
[000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V00 this u:1 $80
/--* t0 ref
N003 ( 2, 2) [000088] -c---------- t88 = * LEA(b+8) byref
/--* t88 byref
N004 ( 4, 4) [000001] ---XG------- t1 = * IND int <l:$143, c:$142>
N005 ( 1, 1) [000002] -c---------- t2 = CNS_INT int -1 $41
/--* t1 int
+--* t2 int
N006 ( 6, 6) [000003] ---XG------- t3 = * ADD int <l:$147, c:$146>
/--* t3 int
N008 ( 6, 6) [000005] DA-XG------- * STORE_LCL_VAR int V01 loc0 d:1
[000178] ------------ IL_OFFSET void IL offset: 0x9
N001 ( 1, 1) [000006] ------------ t6 = LCL_VAR ref V00 this u:1 $80
/--* t6 ref
N003 ( 2, 2) [000090] -c---------- t90 = * LEA(b+4) byref
/--* t90 byref
N004 ( 4, 4) [000007] n---GO------ t7 = * IND ref <l:$1c4, c:$1c3>
/--* t7 ref
N006 ( 4, 4) [000009] DA--GO------ * STORE_LCL_VAR ref V02 loc1 d:1
[000179] ------------ IL_OFFSET void IL offset: 0x10
N001 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
/--* t11 ref
[000191] -c---------- t191 = * LEA(b+4) ref
/--* t191 ref
N002 ( 3, 3) [000012] ---X-------- t12 = * IND int <l:$149, c:$148>
/--* t12 int
N004 ( 7, 6) [000171] DA-X-------- * STORE_LCL_VAR int V10 cse1 d:1
N005 ( 3, 2) [000172] ------------ t172 = LCL_VAR int V10 cse1 u:1 (last use) <l:$149, c:$148>
N007 ( 1, 1) [000010] ------------ t10 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t172 int
+--* t10 int
N008 ( 12, 10) [000013] N--X---N-U-- * LE void <l:$14d, c:$14c>
N009 ( 14, 12) [000014] ---X-------- * JTRUE void
------------ BB02 [01C..052) (return), preds={BB01} succs={}
[000180] ------------ IL_OFFSET void IL offset: 0x1c
N001 ( 1, 1) [000016] -c---------- t16 = LCL_VAR ref V00 this u:1 $80
/--* t16 ref
N003 ( 2, 2) [000095] -c---------- t95 = * LEA(b+12) byref
/--* t95 byref
N004 ( 4, 4) [000017] nc--GO------ t17 = * IND int <l:$151, c:$150>
N005 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 1 $45
/--* t17 int
+--* t18 int
N006 ( 6, 6) [000019] -c--GO------ t19 = * ADD int <l:$155, c:$154>
N007 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $80
/--* t15 ref
N009 ( 2, 2) [000093] -c---------- t93 = * LEA(b+12) byref
/--* t93 byref
+--* t19 int
[000181] -A--GO------ * STOREIND int
[000182] ------------ IL_OFFSET void IL offset: 0x2a
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t22 ref
N003 ( 2, 2) [000097] -c---------- t97 = * LEA(b+8) byref
N005 ( 1, 1) [000023] ------------ t23 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t97 byref
+--* t23 int
[000183] -A--GO------ * STOREIND int
[000184] ------------ IL_OFFSET void IL offset: 0x31
N001 ( 1, 1) [000118] ------------ t118 = LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
/--* t118 ref
+--* t121 int
N007 ( 4, 4) [000117] -------N---- t117 = * LEA(b+(i*4)+8) byref
/--* t117 byref
N011 ( 13, 12) [000166] DA--G------- * STORE_LCL_VAR byref V09 cse0 d:1
N012 ( 3, 2) [000167] ------------ t167 = LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
/--* t167 byref
N014 ( 19, 16) [000124] ---XG------- t124 = * IND ref <l:$341, c:$204>
/--* t124 ref
N016 ( 23, 19) [000125] DA-XG------- * STORE_LCL_VAR ref V07 tmp2 d:1
[000185] ------------ IL_OFFSET void IL offset: 0x39
[000186] ------------ IL_OFFSET void IL offset: 0x40
N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR byref V09 cse0 u:1 (last use) Zero Fseq[Value] $300
N003 ( 1, 1) [000175] ------------ t175 = CNS_INT ref null $VN.Null
/--* t169 byref
+--* t175 ref
[000187] -A-XG------- * STOREIND ref
[000188] ------------ IL_OFFSET void IL offset: 0x50
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
/--* t70 ref
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
[000189] ------------ IL_OFFSET void IL offset: 0x16
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t82 ref
[000192] ------------ t192 = * PUTARG_REG ref REG ecx
/--* t192 ref this in ecx
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Trees before Calculate stack level slots
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen LIR
BB02 [0002] 1 BB01 1 [01C..052) (return) i label target idxlen LIR
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
[000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V00 this u:1 $80
/--* t0 ref
N003 ( 2, 2) [000088] -c---------- t88 = * LEA(b+8) byref
/--* t88 byref
N004 ( 4, 4) [000001] ---XG------- t1 = * IND int <l:$143, c:$142>
N005 ( 1, 1) [000002] -c---------- t2 = CNS_INT int -1 $41
/--* t1 int
+--* t2 int
N006 ( 6, 6) [000003] ---XG------- t3 = * ADD int <l:$147, c:$146>
/--* t3 int
N008 ( 6, 6) [000005] DA-XG------- * STORE_LCL_VAR int V01 loc0 d:1
[000178] ------------ IL_OFFSET void IL offset: 0x9
N001 ( 1, 1) [000006] ------------ t6 = LCL_VAR ref V00 this u:1 $80
/--* t6 ref
N003 ( 2, 2) [000090] -c---------- t90 = * LEA(b+4) byref
/--* t90 byref
N004 ( 4, 4) [000007] n---GO------ t7 = * IND ref <l:$1c4, c:$1c3>
/--* t7 ref
N006 ( 4, 4) [000009] DA--GO------ * STORE_LCL_VAR ref V02 loc1 d:1
[000179] ------------ IL_OFFSET void IL offset: 0x10
N001 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
/--* t11 ref
[000191] -c---------- t191 = * LEA(b+4) ref
/--* t191 ref
N002 ( 3, 3) [000012] ---X-------- t12 = * IND int <l:$149, c:$148>
/--* t12 int
N004 ( 7, 6) [000171] DA-X-------- * STORE_LCL_VAR int V10 cse1 d:1
N005 ( 3, 2) [000172] ------------ t172 = LCL_VAR int V10 cse1 u:1 (last use) <l:$149, c:$148>
N007 ( 1, 1) [000010] ------------ t10 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t172 int
+--* t10 int
N008 ( 12, 10) [000013] N--X---N-U-- * LE void <l:$14d, c:$14c>
N009 ( 14, 12) [000014] ---X-------- * JTRUE void
------------ BB02 [01C..052) (return), preds={BB01} succs={}
[000180] ------------ IL_OFFSET void IL offset: 0x1c
N001 ( 1, 1) [000016] -c---------- t16 = LCL_VAR ref V00 this u:1 $80
/--* t16 ref
N003 ( 2, 2) [000095] -c---------- t95 = * LEA(b+12) byref
/--* t95 byref
N004 ( 4, 4) [000017] nc--GO------ t17 = * IND int <l:$151, c:$150>
N005 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 1 $45
/--* t17 int
+--* t18 int
N006 ( 6, 6) [000019] -c--GO------ t19 = * ADD int <l:$155, c:$154>
N007 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $80
/--* t15 ref
N009 ( 2, 2) [000093] -c---------- t93 = * LEA(b+12) byref
/--* t93 byref
+--* t19 int
[000181] -A--GO------ * STOREIND int
[000182] ------------ IL_OFFSET void IL offset: 0x2a
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t22 ref
N003 ( 2, 2) [000097] -c---------- t97 = * LEA(b+8) byref
N005 ( 1, 1) [000023] ------------ t23 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t97 byref
+--* t23 int
[000183] -A--GO------ * STOREIND int
[000184] ------------ IL_OFFSET void IL offset: 0x31
N001 ( 1, 1) [000118] ------------ t118 = LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
/--* t118 ref
+--* t121 int
N007 ( 4, 4) [000117] -------N---- t117 = * LEA(b+(i*4)+8) byref
/--* t117 byref
N011 ( 13, 12) [000166] DA--G------- * STORE_LCL_VAR byref V09 cse0 d:1
N012 ( 3, 2) [000167] ------------ t167 = LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
/--* t167 byref
N014 ( 19, 16) [000124] ---XG------- t124 = * IND ref <l:$341, c:$204>
/--* t124 ref
N016 ( 23, 19) [000125] DA-XG------- * STORE_LCL_VAR ref V07 tmp2 d:1
[000185] ------------ IL_OFFSET void IL offset: 0x39
[000186] ------------ IL_OFFSET void IL offset: 0x40
N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR byref V09 cse0 u:1 (last use) Zero Fseq[Value] $300
N003 ( 1, 1) [000175] ------------ t175 = CNS_INT ref null $VN.Null
/--* t169 byref
+--* t175 ref
[000187] -A-XG------- * STOREIND ref
[000188] ------------ IL_OFFSET void IL offset: 0x50
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
/--* t70 ref
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
[000189] ------------ IL_OFFSET void IL offset: 0x16
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t82 ref
[000192] ------------ t192 = * PUTARG_REG ref REG ecx
/--* t192 ref this in ecx
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots
Trees after Calculate stack level slots
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen LIR
BB02 [0002] 1 BB01 1 [01C..052) (return) i label target idxlen LIR
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
[000177] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V00 this u:1 $80
/--* t0 ref
N003 ( 2, 2) [000088] -c---------- t88 = * LEA(b+8) byref
/--* t88 byref
N004 ( 4, 4) [000001] ---XG------- t1 = * IND int <l:$143, c:$142>
N005 ( 1, 1) [000002] -c---------- t2 = CNS_INT int -1 $41
/--* t1 int
+--* t2 int
N006 ( 6, 6) [000003] ---XG------- t3 = * ADD int <l:$147, c:$146>
/--* t3 int
N008 ( 6, 6) [000005] DA-XG------- * STORE_LCL_VAR int V01 loc0 d:1
[000178] ------------ IL_OFFSET void IL offset: 0x9
N001 ( 1, 1) [000006] ------------ t6 = LCL_VAR ref V00 this u:1 $80
/--* t6 ref
N003 ( 2, 2) [000090] -c---------- t90 = * LEA(b+4) byref
/--* t90 byref
N004 ( 4, 4) [000007] n---GO------ t7 = * IND ref <l:$1c4, c:$1c3>
/--* t7 ref
N006 ( 4, 4) [000009] DA--GO------ * STORE_LCL_VAR ref V02 loc1 d:1
[000179] ------------ IL_OFFSET void IL offset: 0x10
N001 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
/--* t11 ref
[000191] -c---------- t191 = * LEA(b+4) ref
/--* t191 ref
N002 ( 3, 3) [000012] ---X-------- t12 = * IND int <l:$149, c:$148>
/--* t12 int
N004 ( 7, 6) [000171] DA-X-------- * STORE_LCL_VAR int V10 cse1 d:1
N005 ( 3, 2) [000172] ------------ t172 = LCL_VAR int V10 cse1 u:1 (last use) <l:$149, c:$148>
N007 ( 1, 1) [000010] ------------ t10 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t172 int
+--* t10 int
N008 ( 12, 10) [000013] N--X---N-U-- * LE void <l:$14d, c:$14c>
N009 ( 14, 12) [000014] ---X-------- * JTRUE void
------------ BB02 [01C..052) (return), preds={BB01} succs={}
[000180] ------------ IL_OFFSET void IL offset: 0x1c
N001 ( 1, 1) [000016] -c---------- t16 = LCL_VAR ref V00 this u:1 $80
/--* t16 ref
N003 ( 2, 2) [000095] -c---------- t95 = * LEA(b+12) byref
/--* t95 byref
N004 ( 4, 4) [000017] nc--GO------ t17 = * IND int <l:$151, c:$150>
N005 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 1 $45
/--* t17 int
+--* t18 int
N006 ( 6, 6) [000019] -c--GO------ t19 = * ADD int <l:$155, c:$154>
N007 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $80
/--* t15 ref
N009 ( 2, 2) [000093] -c---------- t93 = * LEA(b+12) byref
/--* t93 byref
+--* t19 int
[000181] -A--GO------ * STOREIND int
[000182] ------------ IL_OFFSET void IL offset: 0x2a
N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t22 ref
N003 ( 2, 2) [000097] -c---------- t97 = * LEA(b+8) byref
N005 ( 1, 1) [000023] ------------ t23 = LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
/--* t97 byref
+--* t23 int
[000183] -A--GO------ * STOREIND int
[000184] ------------ IL_OFFSET void IL offset: 0x31
N001 ( 1, 1) [000118] ------------ t118 = LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N002 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
/--* t118 ref
+--* t121 int
N007 ( 4, 4) [000117] -------N---- t117 = * LEA(b+(i*4)+8) byref
/--* t117 byref
N011 ( 13, 12) [000166] DA--G------- * STORE_LCL_VAR byref V09 cse0 d:1
N012 ( 3, 2) [000167] ------------ t167 = LCL_VAR byref V09 cse0 u:1 Zero Fseq[Value] <l:$c6, c:$c5>
/--* t167 byref
N014 ( 19, 16) [000124] ---XG------- t124 = * IND ref <l:$341, c:$204>
/--* t124 ref
N016 ( 23, 19) [000125] DA-XG------- * STORE_LCL_VAR ref V07 tmp2 d:1
[000185] ------------ IL_OFFSET void IL offset: 0x39
[000186] ------------ IL_OFFSET void IL offset: 0x40
N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR byref V09 cse0 u:1 (last use) Zero Fseq[Value] $300
N003 ( 1, 1) [000175] ------------ t175 = CNS_INT ref null $VN.Null
/--* t169 byref
+--* t175 ref
[000187] -A-XG------- * STOREIND ref
[000188] ------------ IL_OFFSET void IL offset: 0x50
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
/--* t70 ref
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
[000189] ------------ IL_OFFSET void IL offset: 0x16
N002 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V00 this u:1 (last use) $80
/--* t82 ref
[000192] ------------ t192 = * PUTARG_REG ref REG ecx
/--* t192 ref this in ecx
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{V00}
{V01 V02 V10}
{V00}
{V00 V01 V02}
BB02 use def in out
{V00 V01 V02}
{V05 V07 V09}
{V00 V01 V02}
{}
BB06 use def in out
{V00}
{}
{V00}
{}
Interval 0: ref RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: ref RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: ref RefPositions {} physReg:NA Preferences=[allInt]
Interval 4: byref RefPositions {} physReg:NA Preferences=[allInt]
Interval 5: int RefPositions {} physReg:NA Preferences=[allInt]
Double alignment:
Bytes that could be saved by not using EBP frame: 9
Sum of weighted ref counts for EBP enregistered variables: 262
Sum of weighted ref counts for weighted stack based doubles: 0
Predicting not to double-align ESP to save 9 bytes of code.
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
; Decided to create an EBP based frame for ETW stackwalking (BasicBlock Count)
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 )
BB02( 1 )
BB06( 0 )
BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V00(t0)
N003. t88 = LEA(b+8) ; t0
N004. t1 = IND ; t88
N005. CNS_INT -1
N006. t3 = ADD ; t1
N008. V01(t5); t3
N000. IL_OFFSET IL offset: 0x9
N001. V00(t6)
N003. t90 = LEA(b+4) ; t6
N004. t7 = IND ; t90
N006. V02(t9); t7
N000. IL_OFFSET IL offset: 0x10
N001. V02(t11)
N000. t191 = LEA(b+4) ; t11
N002. t12 = IND ; t191
N004. V10(t171); t12
N005. V10(t172*)
N007. V01(t10)
N008. LE ; t172*,t10
N009. JTRUE
BB02 [01C..052) (return), preds={BB01} succs={}
=====
N000. IL_OFFSET IL offset: 0x1c
N001. V00(t16)
N003. LEA(b+12)
N004. IND
N005. CNS_INT 1
N006. ADD
N007. V00(t15)
N009. t93 = LEA(b+12); t15
N000. STOREIND ; t93
N000. IL_OFFSET IL offset: 0x2a
N001. V00(t22*)
N003. t97 = LEA(b+8) ; t22*
N005. V01(t23)
N000. STOREIND ; t97,t23
N000. IL_OFFSET IL offset: 0x31
N001. V02(t118*)
N002. V01(t121*)
N007. t117 = LEA(b+(i*4)+8); t118*,t121*
N011. V09(t166); t117
N012. V09(t167)
N014. t124 = IND ; t167
N016. V07(t125); t124
N000. IL_OFFSET IL offset: 0x39
N000. IL_OFFSET IL offset: 0x40
N001. V09(t169*)
N003. t175 = CNS_INT null
N000. STOREIND ; t169*,t175
N000. IL_OFFSET IL offset: 0x50
N001. V07(t70*)
N002. RETURN ; t70*
BB06 [016..01C) (throw), preds={BB01} succs={}
=====
N000. IL_OFFSET IL offset: 0x16
N002. V00(t82*)
N000. t192 = PUTARG_REG; t82*
N003. CALL ; t192
buildIntervals second part ========
Int arg V00 in reg ecx
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed>
NEW BLOCK BB01
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N003 (???,???) [000177] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
DefList: { }
N005 ( 1, 1) [000000] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $80
DefList: { }
N007 ( 2, 2) [000088] -c---------- * LEA(b+8) byref REG NA
Contained
DefList: { }
N009 ( 4, 4) [000001] ---XG------- * IND int REG NA <l:$143, c:$142>
<RefPosition #2 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 6: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #3 @10 RefTypeDef <Ivl:6> IND BB01 regmask=[allInt] minReg=1>
DefList: { N009.t1. IND }
N011 ( 1, 1) [000002] -c---------- * CNS_INT int -1 REG NA $41
Contained
DefList: { N009.t1. IND }
N013 ( 6, 6) [000003] ---XG------- * ADD int REG NA <l:$147, c:$146>
<RefPosition #4 @13 RefTypeUse <Ivl:6> BB01 regmask=[allInt] minReg=1 last>
Interval 7: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #5 @14 RefTypeDef <Ivl:7> ADD BB01 regmask=[allInt] minReg=1>
Assigning related <I7> to <I6>
DefList: { N013.t3. ADD }
N015 ( 6, 6) [000005] DA-XG------- * STORE_LCL_VAR int V01 loc0 d:1 NA REG NA
<RefPosition #6 @15 RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V01/L1> to <I7>
<RefPosition #7 @16 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N017 (???,???) [000178] ------------ * IL_OFFSET void IL offset: 0x9 REG NA
DefList: { }
N019 ( 1, 1) [000006] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $80
DefList: { }
N021 ( 2, 2) [000090] -c---------- * LEA(b+4) byref REG NA
Contained
DefList: { }
N023 ( 4, 4) [000007] n---GO------ * IND ref REG NA <l:$1c4, c:$1c3>
<RefPosition #8 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 8: ref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #9 @24 RefTypeDef <Ivl:8> IND BB01 regmask=[allInt] minReg=1>
DefList: { N023.t7. IND }
N025 ( 4, 4) [000009] DA--GO------ * STORE_LCL_VAR ref V02 loc1 d:1 NA REG NA
<RefPosition #10 @25 RefTypeUse <Ivl:8> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V02/L2> to <I8>
<RefPosition #11 @26 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N027 (???,???) [000179] ------------ * IL_OFFSET void IL offset: 0x10 REG NA
DefList: { }
N029 ( 1, 1) [000011] ------------ * LCL_VAR ref V02 loc1 u:1 NA REG NA <l:$1c2, c:$200>
DefList: { }
N031 (???,???) [000191] -c---------- * LEA(b+4) ref REG NA
Contained
DefList: { }
N033 ( 3, 3) [000012] ---X-------- * IND int REG NA <l:$149, c:$148>
<RefPosition #12 @33 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 9: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #13 @34 RefTypeDef <Ivl:9> IND BB01 regmask=[allInt] minReg=1>
DefList: { N033.t12. IND }
N035 ( 7, 6) [000171] DA-X-------- * STORE_LCL_VAR int V10 cse1 d:1 NA REG NA
<RefPosition #14 @35 RefTypeUse <Ivl:9> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V10/L5> to <I9>
<RefPosition #15 @36 RefTypeDef <Ivl:5 V10> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N037 ( 3, 2) [000172] ------------ * LCL_VAR int V10 cse1 u:1 NA (last use) REG NA <l:$149, c:$148>
DefList: { }
N039 ( 1, 1) [000010] ------------ * LCL_VAR int V01 loc0 u:1 NA REG NA <l:$145, c:$144>
DefList: { }
N041 ( 12, 10) [000013] N--X---N-U-- * LE void REG NA <l:$14d, c:$14c>
<RefPosition #16 @41 RefTypeUse <Ivl:5 V10> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
<RefPosition #17 @41 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N043 ( 14, 12) [000014] ---X-------- * JTRUE void REG NA
CHECKING LAST USES for BB01, liveout={V00 V01 V02}
==============================
use: {V00}
def: {V01 V02 V10}
NEW BLOCK BB02
Setting BB01 as the predecessor for determining incoming variable registers of BB02
<RefPosition #18 @45 RefTypeBB BB02 regmask=[] minReg=1>
DefList: { }
N047 (???,???) [000180] ------------ * IL_OFFSET void IL offset: 0x1c REG NA
DefList: { }
N049 ( 1, 1) [000016] -c---------- * LCL_VAR ref V00 this u:1 NA REG NA $80
Contained
DefList: { }
N051 ( 2, 2) [000095] -c---------- * LEA(b+12) byref REG NA
Contained
DefList: { }
N053 ( 4, 4) [000017] nc--GO------ * IND int REG NA <l:$151, c:$150>
Contained
DefList: { }
N055 ( 1, 1) [000018] -c---------- * CNS_INT int 1 REG NA $45
Contained
DefList: { }
N057 ( 6, 6) [000019] -c--GO------ * ADD int REG NA <l:$155, c:$154>
Contained
DefList: { }
N059 ( 1, 1) [000015] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $80
DefList: { }
N061 ( 2, 2) [000093] -c---------- * LEA(b+12) byref REG NA
Contained
DefList: { }
N063 (???,???) [000181] -A--GO------ * STOREIND int REG NA
<RefPosition #19 @63 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
DefList: { }
N065 (???,???) [000182] ------------ * IL_OFFSET void IL offset: 0x2a REG NA
DefList: { }
N067 ( 1, 1) [000022] ------------ * LCL_VAR ref V00 this u:1 NA (last use) REG NA $80
DefList: { }
N069 ( 2, 2) [000097] -c---------- * LEA(b+8) byref REG NA
Contained
DefList: { }
N071 ( 1, 1) [000023] ------------ * LCL_VAR int V01 loc0 u:1 NA REG NA <l:$145, c:$144>
DefList: { }
N073 (???,???) [000183] -A--GO------ * STOREIND int REG NA
<RefPosition #20 @73 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #21 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
DefList: { }
N075 (???,???) [000184] ------------ * IL_OFFSET void IL offset: 0x31 REG NA
DefList: { }
N077 ( 1, 1) [000118] ------------ * LCL_VAR ref V02 loc1 u:1 NA (last use) REG NA <l:$1c2, c:$200>
DefList: { }
N079 ( 1, 1) [000121] ------------ * LCL_VAR int V01 loc0 u:1 NA (last use) REG NA <l:$145, c:$144>
DefList: { }
N081 ( 4, 4) [000117] -------N---- * LEA(b+(i*4)+8) byref REG NA
<RefPosition #22 @81 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #23 @81 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 10: byref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #24 @82 RefTypeDef <Ivl:10> LEA BB02 regmask=[allInt] minReg=1>
DefList: { N081.t117. LEA }
N083 ( 13, 12) [000166] DA--G------- * STORE_LCL_VAR byref V09 cse0 d:1 NA REG NA
<RefPosition #25 @83 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last>
Assigning related <V09/L4> to <I10>
<RefPosition #26 @84 RefTypeDef <Ivl:4 V09> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
DefList: { }
N085 ( 3, 2) [000167] ------------ * LCL_VAR byref V09 cse0 u:1 NA Zero Fseq[Value] REG NA <l:$c6, c:$c5>
DefList: { }
N087 ( 19, 16) [000124] ---XG------- * IND ref REG NA <l:$341, c:$204>
<RefPosition #27 @87 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 11: ref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #28 @88 RefTypeDef <Ivl:11> IND BB02 regmask=[allInt] minReg=1>
DefList: { N087.t124. IND }
N089 ( 23, 19) [000125] DA-XG------- * STORE_LCL_VAR ref V07 tmp2 d:1 NA REG NA
<RefPosition #29 @89 RefTypeUse <Ivl:11> BB02 regmask=[allInt] minReg=1 last>
Assigning related <V07/L3> to <I11>
<RefPosition #30 @90 RefTypeDef <Ivl:3 V07> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
DefList: { }
N091 (???,???) [000185] ------------ * IL_OFFSET void IL offset: 0x39 REG NA
DefList: { }
N093 (???,???) [000186] ------------ * IL_OFFSET void IL offset: 0x40 REG NA
DefList: { }
N095 ( 3, 2) [000169] ------------ * LCL_VAR byref V09 cse0 u:1 NA (last use) Zero Fseq[Value] REG NA $300
DefList: { }
N097 ( 1, 1) [000175] ------------ * CNS_INT ref null REG NA $VN.Null
Interval 12: ref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #31 @98 RefTypeDef <Ivl:12> CNS_INT BB02 regmask=[allInt] minReg=1>
DefList: { N097.t175. CNS_INT }
N099 (???,???) [000187] -A-XG------- * STOREIND ref REG NA
<RefPosition #32 @99 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #33 @99 RefTypeUse <Ivl:12> BB02 regmask=[allInt] minReg=1 last>
DefList: { }
N101 (???,???) [000188] ------------ * IL_OFFSET void IL offset: 0x50 REG NA
DefList: { }
N103 ( 3, 2) [000070] ------------ * LCL_VAR ref V07 tmp2 u:1 NA (last use) REG NA <l:$340, c:$204>
DefList: { }
N105 ( 4, 3) [000071] ------------ * RETURN ref REG NA $208
<RefPosition #34 @105 RefTypeFixedReg <Reg:eax> BB02 regmask=[eax] minReg=1>
<RefPosition #35 @105 RefTypeUse <Ivl:3 V07> LCL_VAR BB02 regmask=[eax] minReg=1 last fixed>
CHECKING LAST USES for BB02, liveout={}
==============================
use: {V00 V01 V02}
def: {V05 V07 V09}
NEW BLOCK BB06
Setting BB01 as the predecessor for determining incoming variable registers of BB06
<RefPosition #36 @107 RefTypeBB BB06 regmask=[] minReg=1>
firstColdLoc = 109
DefList: { }
N109 (???,???) [000189] ------------ * IL_OFFSET void IL offset: 0x16 REG NA
DefList: { }
N111 ( 1, 1) [000082] ------------ * LCL_VAR ref V00 this u:1 NA (last use) REG NA $80
DefList: { }
N113 (???,???) [000192] ------------ * PUTARG_REG ref REG ecx
<RefPosition #37 @113 RefTypeFixedReg <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #38 @113 RefTypeUse <Ivl:0 V00> LCL_VAR BB06 regmask=[ecx] minReg=1 last fixed>
Interval 13: ref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #39 @114 RefTypeFixedReg <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #40 @114 RefTypeDef <Ivl:13> PUTARG_REG BB06 regmask=[ecx] minReg=1 fixed>
DefList: { N113.t192. PUTARG_REG }
N115 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack REG NA $VN.Void
<RefPosition #41 @115 RefTypeFixedReg <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #42 @115 RefTypeUse <Ivl:13> BB06 regmask=[ecx] minReg=1 last fixed>
<RefPosition #43 @116 RefTypeKill <Reg:eax> BB06 regmask=[eax] minReg=1>
<RefPosition #44 @116 RefTypeKill <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #45 @116 RefTypeKill <Reg:edx> BB06 regmask=[edx] minReg=1>
CHECKING LAST USES for BB06, liveout={}
==============================
use: {V00}
def: {}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) ref RefPositions {#0@0 #2@9 #8@23 #19@63 #20@73 #38@113} physReg:ecx Preferences=[ecx]
Interval 1: (V01) int RefPositions {#7@16 #17@41 #21@73 #23@81} physReg:NA Preferences=[allInt]
Interval 2: (V02) ref RefPositions {#11@26 #12@33 #22@81} physReg:NA Preferences=[allInt]
Interval 3: (V07) ref (struct) RefPositions {#30@90 #35@105} physReg:NA Preferences=[eax]
Interval 4: (V09) byref RefPositions {#26@84 #27@87 #32@99} physReg:NA Preferences=[allInt]
Interval 5: (V10) int RefPositions {#15@36 #16@41} physReg:NA Preferences=[allInt]
Interval 6: int RefPositions {#3@10 #4@13} physReg:NA Preferences=[allInt] RelatedInterval <I7>
Interval 7: int RefPositions {#5@14 #6@15} physReg:NA Preferences=[allInt] RelatedInterval <V01/L1>
Interval 8: ref RefPositions {#9@24 #10@25} physReg:NA Preferences=[allInt] RelatedInterval <V02/L2>
Interval 9: int RefPositions {#13@34 #14@35} physReg:NA Preferences=[allInt] RelatedInterval <V10/L5>
Interval 10: byref RefPositions {#24@82 #25@83} physReg:NA Preferences=[allInt] RelatedInterval <V09/L4>
Interval 11: ref RefPositions {#28@88 #29@89} physReg:NA Preferences=[allInt] RelatedInterval <V07/L3>
Interval 12: ref (constant) RefPositions {#31@98 #33@99} physReg:NA Preferences=[allInt]
Interval 13: ref RefPositions {#40@114 #42@115} physReg:NA Preferences=[ecx]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #3 @10 RefTypeDef <Ivl:6> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #4 @13 RefTypeUse <Ivl:6> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #5 @14 RefTypeDef <Ivl:7> ADD BB01 regmask=[allInt] minReg=1>
<RefPosition #6 @15 RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #7 @16 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #8 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @24 RefTypeDef <Ivl:8> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @25 RefTypeUse <Ivl:8> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #11 @26 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #12 @33 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #13 @34 RefTypeDef <Ivl:9> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #14 @35 RefTypeUse <Ivl:9> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #15 @36 RefTypeDef <Ivl:5 V10> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #16 @41 RefTypeUse <Ivl:5 V10> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #17 @41 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #18 @45 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #19 @63 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #20 @73 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #21 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #22 @81 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #23 @81 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #24 @82 RefTypeDef <Ivl:10> LEA BB02 regmask=[allInt] minReg=1>
<RefPosition #25 @83 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #26 @84 RefTypeDef <Ivl:4 V09> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #27 @87 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #28 @88 RefTypeDef <Ivl:11> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #29 @89 RefTypeUse <Ivl:11> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #30 @90 RefTypeDef <Ivl:3 V07> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #31 @98 RefTypeDef <Ivl:12> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @99 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #33 @99 RefTypeUse <Ivl:12> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #34 @105 RefTypeFixedReg <Reg:eax> BB02 regmask=[eax] minReg=1>
<RefPosition #35 @105 RefTypeUse <Ivl:3 V07> LCL_VAR BB02 regmask=[eax] minReg=1 last fixed>
<RefPosition #36 @107 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #37 @113 RefTypeFixedReg <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #38 @113 RefTypeUse <Ivl:0 V00> LCL_VAR BB06 regmask=[ecx] minReg=1 last fixed>
<RefPosition #39 @114 RefTypeFixedReg <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #40 @114 RefTypeDef <Ivl:13> PUTARG_REG BB06 regmask=[ecx] minReg=1 fixed>
<RefPosition #41 @115 RefTypeFixedReg <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #42 @115 RefTypeUse <Ivl:13> BB06 regmask=[ecx] minReg=1 last fixed>
<RefPosition #43 @116 RefTypeKill <Reg:eax> BB06 regmask=[eax] minReg=1 last>
<RefPosition #44 @116 RefTypeKill <Reg:ecx> BB06 regmask=[ecx] minReg=1 last>
<RefPosition #45 @116 RefTypeKill <Reg:edx> BB06 regmask=[edx] minReg=1 last>
-----------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional>
<RefPosition #2 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #8 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #19 @63 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #20 @73 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #38 @113 RefTypeUse <Ivl:0 V00> LCL_VAR BB06 regmask=[ecx] minReg=1 last fixed>
Pop: LocalVar V00: undefined use at 113
-----------------
<RefPosition #7 @16 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #17 @41 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #21 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #23 @81 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #11 @26 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #12 @33 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #22 @81 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #26 @84 RefTypeDef <Ivl:4 V09> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #27 @87 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @99 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #30 @90 RefTypeDef <Ivl:3 V07> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #35 @105 RefTypeUse <Ivl:3 V07> LCL_VAR BB02 regmask=[eax] minReg=1 last fixed>
-----------------
<RefPosition #15 @36 RefTypeDef <Ivl:5 V10> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #16 @41 RefTypeUse <Ivl:5 V10> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V00
BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
=====
N003. IL_OFFSET IL offset: 0x0
N005. V00(L0)
N007. LEA(b+8)
N009. IND
Use:<V00/L0>(#2)
Def:<I6>(#3) Pref:<I7>
N011. CNS_INT -1
N013. ADD
Use:<I6>(#4) *
Def:<I7>(#5) Pref:<V01/L1>
N015. V01(L1)
Use:<I7>(#6) *
Def:<V01/L1>(#7)
N017. IL_OFFSET IL offset: 0x9
N019. V00(L0)
N021. LEA(b+4)
N023. IND
Use:<V00/L0>(#8)
Def:<I8>(#9) Pref:<V02/L2>
N025. V02(L2)
Use:<I8>(#10) *
Def:<V02/L2>(#11)
N027. IL_OFFSET IL offset: 0x10
N029. V02(L2)
N031. LEA(b+4)
N033. IND
Use:<V02/L2>(#12)
Def:<I9>(#13) Pref:<V10/L5>
N035. V10(L5)
Use:<I9>(#14) *
Def:<V10/L5>(#15)
N037. V10(L5)
N039. V01(L1)
N041. LE
Use:<V10/L5>(#16) *
Use:<V01/L1>(#17)
N043. JTRUE
BB02 [01C..052) (return), preds={BB01} succs={}
=====
N047. IL_OFFSET IL offset: 0x1c
N049. V00(L0)
N051. LEA(b+12)
N053. IND
N055. CNS_INT 1
N057. ADD
N059. V00(L0)
N061. LEA(b+12)
N063. STOREIND
Use:<V00/L0>(#19)
N065. IL_OFFSET IL offset: 0x2a
N067. V00(L0)
N069. LEA(b+8)
N071. V01(L1)
N073. STOREIND
Use:<V00/L0>(#20) *
Use:<V01/L1>(#21)
N075. IL_OFFSET IL offset: 0x31
N077. V02(L2)
N079. V01(L1)
N081. LEA(b+(i*4)+8)
Use:<V02/L2>(#22) *
Use:<V01/L1>(#23) *
Def:<I10>(#24) Pref:<V09/L4>
N083. V09(L4)
Use:<I10>(#25) *
Def:<V09/L4>(#26)
N085. V09(L4)
N087. IND
Use:<V09/L4>(#27)
Def:<I11>(#28) Pref:<V07/L3>
N089. V07(L3)
Use:<I11>(#29) *
Def:<V07/L3>(#30)
N091. IL_OFFSET IL offset: 0x39
N093. IL_OFFSET IL offset: 0x40
N095. V09(L4)
N097. CNS_INT null
Def:<I12>(#31)
N099. STOREIND
Use:<V09/L4>(#32) *
Use:<I12>(#33) *
N101. IL_OFFSET IL offset: 0x50
N103. V07(L3)
N105. RETURN
Use:<V07/L3>(#35) Fixed:eax(#34) *
BB06 [016..01C) (throw), preds={BB01} succs={}
=====
N109. IL_OFFSET IL offset: 0x16
N111. V00(L0)
N113. PUTARG_REG
Use:<V00/L0>(#38) Fixed:ecx(#37) *
Def:<I13>(#40) ecx
N115. CALL
Use:<I13>(#42) Fixed:ecx(#41) *
Kill: eax ecx edx
Linear scan intervals after buildIntervals:
Interval 0: (V00) ref RefPositions {#0@0 #2@9 #8@23 #19@63 #20@73 #38@113} physReg:ecx Preferences=[ecx]
Interval 1: (V01) int RefPositions {#7@16 #17@41 #21@73 #23@81} physReg:NA Preferences=[allInt]
Interval 2: (V02) ref RefPositions {#11@26 #12@33 #22@81} physReg:NA Preferences=[allInt]
Interval 3: (V07) ref (struct) RefPositions {#30@90 #35@105} physReg:NA Preferences=[eax]
Interval 4: (V09) byref RefPositions {#26@84 #27@87 #32@99} physReg:NA Preferences=[allInt]
Interval 5: (V10) int RefPositions {#15@36 #16@41} physReg:NA Preferences=[allInt]
Interval 6: int RefPositions {#3@10 #4@13} physReg:NA Preferences=[allInt] RelatedInterval <I7>
Interval 7: int RefPositions {#5@14 #6@15} physReg:NA Preferences=[allInt] RelatedInterval <V01/L1>
Interval 8: ref RefPositions {#9@24 #10@25} physReg:NA Preferences=[allInt] RelatedInterval <V02/L2>
Interval 9: int RefPositions {#13@34 #14@35} physReg:NA Preferences=[allInt] RelatedInterval <V10/L5>
Interval 10: byref RefPositions {#24@82 #25@83} physReg:NA Preferences=[allInt] RelatedInterval <V09/L4>
Interval 11: ref RefPositions {#28@88 #29@89} physReg:NA Preferences=[allInt] RelatedInterval <V07/L3>
Interval 12: ref (constant) RefPositions {#31@98 #33@99} physReg:NA Preferences=[allInt]
Interval 13: ref RefPositions {#40@114 #42@115} physReg:NA Preferences=[ecx]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) ref RefPositions {#0@0 #2@9 #8@23 #19@63 #20@73 #38@113} physReg:ecx Preferences=[ecx]
Interval 1: (V01) int RefPositions {#7@16 #17@41 #21@73 #23@81} physReg:NA Preferences=[allInt]
Interval 2: (V02) ref RefPositions {#11@26 #12@33 #22@81} physReg:NA Preferences=[allInt]
Interval 3: (V07) ref (struct) RefPositions {#30@90 #35@105} physReg:NA Preferences=[eax]
Interval 4: (V09) byref RefPositions {#26@84 #27@87 #32@99} physReg:NA Preferences=[allInt]
Interval 5: (V10) int RefPositions {#15@36 #16@41} physReg:NA Preferences=[allInt]
Interval 6: int RefPositions {#3@10 #4@13} physReg:NA Preferences=[allInt] RelatedInterval <I7>
Interval 7: int RefPositions {#5@14 #6@15} physReg:NA Preferences=[allInt] RelatedInterval <V01/L1>
Interval 8: ref RefPositions {#9@24 #10@25} physReg:NA Preferences=[allInt] RelatedInterval <V02/L2>
Interval 9: int RefPositions {#13@34 #14@35} physReg:NA Preferences=[allInt] RelatedInterval <V10/L5>
Interval 10: byref RefPositions {#24@82 #25@83} physReg:NA Preferences=[allInt] RelatedInterval <V09/L4>
Interval 11: ref RefPositions {#28@88 #29@89} physReg:NA Preferences=[allInt] RelatedInterval <V07/L3>
Interval 12: ref (constant) RefPositions {#31@98 #33@99} physReg:NA Preferences=[allInt]
Interval 13: ref RefPositions {#40@114 #42@115} physReg:NA Preferences=[ecx]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #3 @10 RefTypeDef <Ivl:6> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #4 @13 RefTypeUse <Ivl:6> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #5 @14 RefTypeDef <Ivl:7> ADD BB01 regmask=[allInt] minReg=1>
<RefPosition #6 @15 RefTypeUse <Ivl:7> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #7 @16 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #8 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #9 @24 RefTypeDef <Ivl:8> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @25 RefTypeUse <Ivl:8> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #11 @26 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #12 @33 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #13 @34 RefTypeDef <Ivl:9> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #14 @35 RefTypeUse <Ivl:9> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #15 @36 RefTypeDef <Ivl:5 V10> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #16 @41 RefTypeUse <Ivl:5 V10> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #17 @41 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #18 @45 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #19 @63 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #20 @73 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #21 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #22 @81 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #23 @81 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #24 @82 RefTypeDef <Ivl:10> LEA BB02 regmask=[allInt] minReg=1>
<RefPosition #25 @83 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #26 @84 RefTypeDef <Ivl:4 V09> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #27 @87 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #28 @88 RefTypeDef <Ivl:11> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #29 @89 RefTypeUse <Ivl:11> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #30 @90 RefTypeDef <Ivl:3 V07> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #31 @98 RefTypeDef <Ivl:12> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @99 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #33 @99 RefTypeUse <Ivl:12> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #34 @105 RefTypeFixedReg <Reg:eax> BB02 regmask=[eax] minReg=1>
<RefPosition #35 @105 RefTypeUse <Ivl:3 V07> LCL_VAR BB02 regmask=[eax] minReg=1 last fixed>
<RefPosition #36 @107 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #37 @113 RefTypeFixedReg <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #38 @113 RefTypeUse <Ivl:0 V00> LCL_VAR BB06 regmask=[ecx] minReg=1 last fixed>
<RefPosition #39 @114 RefTypeFixedReg <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #40 @114 RefTypeDef <Ivl:13> PUTARG_REG BB06 regmask=[ecx] minReg=1 fixed>
<RefPosition #41 @115 RefTypeFixedReg <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #42 @115 RefTypeUse <Ivl:13> BB06 regmask=[ecx] minReg=1 last fixed>
<RefPosition #43 @116 RefTypeKill <Reg:eax> BB06 regmask=[eax] minReg=1 last>
<RefPosition #44 @116 RefTypeKill <Reg:ecx> BB06 regmask=[ecx] minReg=1 last>
<RefPosition #45 @116 RefTypeKill <Reg:edx> BB06 regmask=[edx] minReg=1 last>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional>
<RefPosition #2 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #8 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #19 @63 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #20 @73 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #38 @113 RefTypeUse <Ivl:0 V00> LCL_VAR BB06 regmask=[ecx] minReg=1 last fixed>
--- V01 (Interval 1)
<RefPosition #7 @16 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #17 @41 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #21 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #23 @81 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
--- V02 (Interval 2)
<RefPosition #11 @26 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #12 @33 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #22 @81 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
--- V03
--- V04
--- V05
--- V06
--- V07 (Interval 3)
<RefPosition #30 @90 RefTypeDef <Ivl:3 V07> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #35 @105 RefTypeUse <Ivl:3 V07> LCL_VAR BB02 regmask=[eax] minReg=1 last fixed>
--- V08
--- V09 (Interval 4)
<RefPosition #26 @84 RefTypeDef <Ivl:4 V09> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #27 @87 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @99 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
--- V10 (Interval 5)
<RefPosition #15 @36 RefTypeDef <Ivl:5 V10> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #16 @41 RefTypeUse <Ivl:5 V10> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
Columns are only printed up to the last modifed register, which may increase during allocation,
in which case additional columns will appear.
Registers which are not marked modified have ---- in their column.
-------------------------------+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |edi |
-------------------------------+----+----+----+----+
| |V0 a| | |
0.#0 V0 Parm Keep ecx | |V0 a| | |
1.#1 BB1 PredBB0 | |V0 a| | |
9.#2 V0 Use Keep ecx | |V0 a| | |
10.#3 I6 Def Alloc eax |I6 a|V0 a| | |
13.#4 I6 Use * Keep eax |I6 a|V0 a| | |
14.#5 I7 Def Alloc eax |I7 a|V0 a| | |
15.#6 I7 Use * Keep eax |I7 a|V0 a| | |
16.#7 V1 Def Alloc eax |V1 a|V0 a| | |
23.#8 V0 Use Keep ecx |V1 a|V0 a| | |
24.#9 I8 Def Alloc edx |V1 a|V0 a|I8 a| |
25.#10 I8 Use * Keep edx |V1 a|V0 a|I8 a| |
26.#11 V2 Def Alloc edx |V1 a|V0 a|V2 a| |
33.#12 V2 Use Keep edx |V1 a|V0 a|V2 a| |
-------------------------------+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |esi |edi |
-------------------------------+----+----+----+----+----+
34.#13 I9 Def Alloc esi |V1 a|V0 a|V2 a|I9 a| |
35.#14 I9 Use * Keep esi |V1 a|V0 a|V2 a|I9 a| |
36.#15 V10 Def Alloc esi |V1 a|V0 a|V2 a|V10a| |
41.#16 V10 Use * Keep esi |V1 a|V0 a|V2 a|V10a| |
41.#17 V1 Use Keep eax |V1 a|V0 a|V2 a|V10a| |
-------------------------------+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |esi |edi |
-------------------------------+----+----+----+----+----+
45.#18 BB2 PredBB1 |V1 a|V0 a|V2 a| | |
63.#19 V0 Use Keep ecx |V1 a|V0 a|V2 a| | |
73.#20 V0 Use * Keep ecx |V1 a|V0 i|V2 a| | |
73.#21 V1 Use Keep eax |V1 a|V0 i|V2 a| | |
81.#22 V2 Use * Keep edx |V1 a|V0 i|V2 a| | |
81.#23 V1 Use * Keep eax |V1 a|V0 i|V2 a| | |
82.#24 I10 Def Alloc eax |I10a|V0 i| | | |
83.#25 I10 Use * Keep eax |I10a|V0 i| | | |
84.#26 V9 Def Alloc eax |V9 a|V0 i| | | |
87.#27 V9 Use Keep eax |V9 a|V0 i| | | |
88.#28 I11 Def Alloc ecx |V9 a|I11a| | | |
89.#29 I11 Use * Keep ecx |V9 a|I11a| | | |
Restr ecx |V9 a|V0 i| | | |
90.#30 V7 Def Alloc ecx |V9 a|V7 a| | | |
98.#31 C12 Def Alloc edx |V9 a|V7 a|C12a| | |
99.#32 V9 Use * Keep eax |V9 a|V7 a|C12a| | |
99.#33 C12 Use * Keep edx |V9 a|V7 a|C12a| | |
105.#34 eax Fixd Keep eax | |V7 a|C12i| | |
105.#35 V7 Use * Copy eax |V7 a|V7 a|C12i| | |
Restr ecx | |V0 i|C12i| | |
-------------------------------+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |esi |edi |
-------------------------------+----+----+----+----+----+
107.#36 BB6 PredBB1 | |V0 a| | | |
113.#37 ecx Fixd Keep ecx | |V0 a| | | |
113.#38 V0 Use * Keep ecx | |V0 a| | | |
114.#39 ecx Fixd Keep ecx | | | | | |
114.#40 I13 Def Alloc ecx | |I13a| | | |
115.#41 ecx Fixd Keep ecx | |I13a| | | |
115.#42 I13 Use * Keep ecx | |I13a| | | |
116.#43 eax Kill Keep eax | | | | | |
116.#44 ecx Kill Keep ecx | | | | | |
116.#45 edx Kill Keep edx | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[ecx] minReg=1>
<RefPosition #3 @10 RefTypeDef <Ivl:6> IND BB01 regmask=[eax] minReg=1>
<RefPosition #4 @13 RefTypeUse <Ivl:6> BB01 regmask=[eax] minReg=1 last>
<RefPosition #5 @14 RefTypeDef <Ivl:7> ADD BB01 regmask=[eax] minReg=1>
<RefPosition #6 @15 RefTypeUse <Ivl:7> BB01 regmask=[eax] minReg=1 last>
<RefPosition #7 @16 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[eax] minReg=1>
<RefPosition #8 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[ecx] minReg=1>
<RefPosition #9 @24 RefTypeDef <Ivl:8> IND BB01 regmask=[edx] minReg=1>
<RefPosition #10 @25 RefTypeUse <Ivl:8> BB01 regmask=[edx] minReg=1 last>
<RefPosition #11 @26 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[edx] minReg=1>
<RefPosition #12 @33 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[edx] minReg=1>
<RefPosition #13 @34 RefTypeDef <Ivl:9> IND BB01 regmask=[esi] minReg=1>
<RefPosition #14 @35 RefTypeUse <Ivl:9> BB01 regmask=[esi] minReg=1 last>
<RefPosition #15 @36 RefTypeDef <Ivl:5 V10> STORE_LCL_VAR BB01 regmask=[esi] minReg=1>
<RefPosition #16 @41 RefTypeUse <Ivl:5 V10> LCL_VAR BB01 regmask=[esi] minReg=1 last regOptional>
<RefPosition #17 @41 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[eax] minReg=1>
<RefPosition #18 @45 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #19 @63 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[ecx] minReg=1>
<RefPosition #20 @73 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[ecx] minReg=1 last>
<RefPosition #21 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[eax] minReg=1>
<RefPosition #22 @81 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[edx] minReg=1 last>
<RefPosition #23 @81 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[eax] minReg=1 last>
<RefPosition #24 @82 RefTypeDef <Ivl:10> LEA BB02 regmask=[eax] minReg=1>
<RefPosition #25 @83 RefTypeUse <Ivl:10> BB02 regmask=[eax] minReg=1 last>
<RefPosition #26 @84 RefTypeDef <Ivl:4 V09> STORE_LCL_VAR BB02 regmask=[eax] minReg=1>
<RefPosition #27 @87 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[eax] minReg=1>
<RefPosition #28 @88 RefTypeDef <Ivl:11> IND BB02 regmask=[ecx] minReg=1>
<RefPosition #29 @89 RefTypeUse <Ivl:11> BB02 regmask=[ecx] minReg=1 last>
<RefPosition #30 @90 RefTypeDef <Ivl:3 V07> STORE_LCL_VAR BB02 regmask=[ecx] minReg=1>
<RefPosition #31 @98 RefTypeDef <Ivl:12> CNS_INT BB02 regmask=[edx] minReg=1>
<RefPosition #32 @99 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[eax] minReg=1 last>
<RefPosition #33 @99 RefTypeUse <Ivl:12> BB02 regmask=[edx] minReg=1 last>
<RefPosition #34 @105 RefTypeFixedReg <Reg:eax> BB02 regmask=[eax] minReg=1>
<RefPosition #35 @105 RefTypeUse <Ivl:3 V07> LCL_VAR BB02 regmask=[eax] minReg=1 last copy fixed>
<RefPosition #36 @107 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #37 @113 RefTypeFixedReg <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #38 @113 RefTypeUse <Ivl:0 V00> LCL_VAR BB06 regmask=[ecx] minReg=1 last fixed>
<RefPosition #39 @114 RefTypeFixedReg <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #40 @114 RefTypeDef <Ivl:13> PUTARG_REG BB06 regmask=[ecx] minReg=1 fixed>
<RefPosition #41 @115 RefTypeFixedReg <Reg:ecx> BB06 regmask=[ecx] minReg=1>
<RefPosition #42 @115 RefTypeUse <Ivl:13> BB06 regmask=[ecx] minReg=1 last fixed>
<RefPosition #43 @116 RefTypeKill <Reg:eax> BB06 regmask=[eax] minReg=1 last>
<RefPosition #44 @116 RefTypeKill <Reg:ecx> BB06 regmask=[ecx] minReg=1 last>
<RefPosition #45 @116 RefTypeKill <Reg:edx> BB06 regmask=[edx] minReg=1 last>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional>
<RefPosition #2 @9 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[ecx] minReg=1>
<RefPosition #8 @23 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[ecx] minReg=1>
<RefPosition #19 @63 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[ecx] minReg=1>
<RefPosition #20 @73 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[ecx] minReg=1 last>
<RefPosition #38 @113 RefTypeUse <Ivl:0 V00> LCL_VAR BB06 regmask=[ecx] minReg=1 last fixed>
--- V01 (Interval 1)
<RefPosition #7 @16 RefTypeDef <Ivl:1 V01> STORE_LCL_VAR BB01 regmask=[eax] minReg=1>
<RefPosition #17 @41 RefTypeUse <Ivl:1 V01> LCL_VAR BB01 regmask=[eax] minReg=1>
<RefPosition #21 @73 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[eax] minReg=1>
<RefPosition #23 @81 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[eax] minReg=1 last>
--- V02 (Interval 2)
<RefPosition #11 @26 RefTypeDef <Ivl:2 V02> STORE_LCL_VAR BB01 regmask=[edx] minReg=1>
<RefPosition #12 @33 RefTypeUse <Ivl:2 V02> LCL_VAR BB01 regmask=[edx] minReg=1>
<RefPosition #22 @81 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[edx] minReg=1 last>
--- V03
--- V04
--- V05
--- V06
--- V07 (Interval 3)
<RefPosition #30 @90 RefTypeDef <Ivl:3 V07> STORE_LCL_VAR BB02 regmask=[ecx] minReg=1>
<RefPosition #35 @105 RefTypeUse <Ivl:3 V07> LCL_VAR BB02 regmask=[eax] minReg=1 last copy fixed>
--- V08
--- V09 (Interval 4)
<RefPosition #26 @84 RefTypeDef <Ivl:4 V09> STORE_LCL_VAR BB02 regmask=[eax] minReg=1>
<RefPosition #27 @87 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[eax] minReg=1>
<RefPosition #32 @99 RefTypeUse <Ivl:4 V09> LCL_VAR BB02 regmask=[eax] minReg=1 last>
--- V10 (Interval 5)
<RefPosition #15 @36 RefTypeDef <Ivl:5 V10> STORE_LCL_VAR BB01 regmask=[esi] minReg=1>
<RefPosition #16 @41 RefTypeUse <Ivl:5 V10> LCL_VAR BB01 regmask=[esi] minReg=1 last regOptional>
Active intervals at end of allocation:
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V01 V02}
Has NoCritical Edges
Prior to Resolution
BB01
use def in out
{V00}
{V01 V02 V10}
{V00}
{V00 V01 V02}
Var=Reg beg of BB01: V00=ecx
Var=Reg end of BB01: V00=ecx V01=eax V02=edx
BB02
use def in out
{V00 V01 V02}
{V05 V07 V09}
{V00 V01 V02}
{}
Var=Reg beg of BB02: V00=ecx V01=eax V02=edx
Var=Reg end of BB02: none
BB06
use def in out
{V00}
{}
{V00}
{}
Var=Reg beg of BB06: V00=ecx
Var=Reg end of BB06: none
RESOLVING EDGES
Set V00 argument initial register to ecx
Trees after linear scan register allocator (LSRA)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen LIR
BB02 [0002] 1 BB01 1 [01C..052) (return) i label target idxlen LIR
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
N003 (???,???) [000177] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N005 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V00 this u:1 ecx REG ecx $80
/--* t0 ref
N007 ( 2, 2) [000088] -c---------- t88 = * LEA(b+8) byref REG NA
/--* t88 byref
N009 ( 4, 4) [000001] ---XG------- t1 = * IND int REG eax <l:$143, c:$142>
N011 ( 1, 1) [000002] -c---------- t2 = CNS_INT int -1 REG NA $41
/--* t1 int
+--* t2 int
N013 ( 6, 6) [000003] ---XG------- t3 = * ADD int REG eax <l:$147, c:$146>
/--* t3 int
N015 ( 6, 6) [000005] DA-XG------- * STORE_LCL_VAR int V01 loc0 d:1 eax REG eax
N017 (???,???) [000178] ------------ IL_OFFSET void IL offset: 0x9 REG NA
N019 ( 1, 1) [000006] ------------ t6 = LCL_VAR ref V00 this u:1 ecx REG ecx $80
/--* t6 ref
N021 ( 2, 2) [000090] -c---------- t90 = * LEA(b+4) byref REG NA
/--* t90 byref
N023 ( 4, 4) [000007] n---GO------ t7 = * IND ref REG edx <l:$1c4, c:$1c3>
/--* t7 ref
N025 ( 4, 4) [000009] DA--GO------ * STORE_LCL_VAR ref V02 loc1 d:1 edx REG edx
N027 (???,???) [000179] ------------ IL_OFFSET void IL offset: 0x10 REG NA
N029 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V02 loc1 u:1 edx REG edx <l:$1c2, c:$200>
/--* t11 ref
N031 (???,???) [000191] -c---------- t191 = * LEA(b+4) ref REG NA
/--* t191 ref
N033 ( 3, 3) [000012] ---X-------- t12 = * IND int REG esi <l:$149, c:$148>
/--* t12 int
N035 ( 7, 6) [000171] DA-X-------- * STORE_LCL_VAR int V10 cse1 d:1 esi REG esi
N037 ( 3, 2) [000172] ------------ t172 = LCL_VAR int V10 cse1 u:1 esi (last use) REG esi <l:$149, c:$148>
N039 ( 1, 1) [000010] ------------ t10 = LCL_VAR int V01 loc0 u:1 eax REG eax <l:$145, c:$144>
/--* t172 int
+--* t10 int
N041 ( 12, 10) [000013] N--X---N-U-- * LE void REG NA <l:$14d, c:$14c>
N043 ( 14, 12) [000014] ---X-------- * JTRUE void REG NA
------------ BB02 [01C..052) (return), preds={BB01} succs={}
N047 (???,???) [000180] ------------ IL_OFFSET void IL offset: 0x1c REG NA
N049 ( 1, 1) [000016] -c---------- t16 = LCL_VAR ref V00 this u:1 ecx REG NA $80
/--* t16 ref
N051 ( 2, 2) [000095] -c---------- t95 = * LEA(b+12) byref REG NA
/--* t95 byref
N053 ( 4, 4) [000017] nc--GO------ t17 = * IND int REG NA <l:$151, c:$150>
N055 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 1 REG NA $45
/--* t17 int
+--* t18 int
N057 ( 6, 6) [000019] -c--GO------ t19 = * ADD int REG NA <l:$155, c:$154>
N059 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 ecx REG ecx $80
/--* t15 ref
N061 ( 2, 2) [000093] -c---------- t93 = * LEA(b+12) byref REG NA
/--* t93 byref
+--* t19 int
N063 (???,???) [000181] -A--GO------ * STOREIND int REG NA
N065 (???,???) [000182] ------------ IL_OFFSET void IL offset: 0x2a REG NA
N067 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V00 this u:1 ecx (last use) REG ecx $80
/--* t22 ref
N069 ( 2, 2) [000097] -c---------- t97 = * LEA(b+8) byref REG NA
N071 ( 1, 1) [000023] ------------ t23 = LCL_VAR int V01 loc0 u:1 eax REG eax <l:$145, c:$144>
/--* t97 byref
+--* t23 int
N073 (???,???) [000183] -A--GO------ * STOREIND int REG NA
N075 (???,???) [000184] ------------ IL_OFFSET void IL offset: 0x31 REG NA
N077 ( 1, 1) [000118] ------------ t118 = LCL_VAR ref V02 loc1 u:1 edx (last use) REG edx <l:$1c2, c:$200>
N079 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V01 loc0 u:1 eax (last use) REG eax <l:$145, c:$144>
/--* t118 ref
+--* t121 int
N081 ( 4, 4) [000117] -------N---- t117 = * LEA(b+(i*4)+8) byref REG eax
/--* t117 byref
N083 ( 13, 12) [000166] DA--G------- * STORE_LCL_VAR byref V09 cse0 d:1 eax REG eax
N085 ( 3, 2) [000167] ------------ t167 = LCL_VAR byref V09 cse0 u:1 eax Zero Fseq[Value] REG eax <l:$c6, c:$c5>
/--* t167 byref
N087 ( 19, 16) [000124] ---XG------- t124 = * IND ref REG ecx <l:$341, c:$204>
/--* t124 ref
N089 ( 23, 19) [000125] DA-XG------- * STORE_LCL_VAR ref V07 tmp2 d:1 ecx REG ecx
N091 (???,???) [000185] ------------ IL_OFFSET void IL offset: 0x39 REG NA
N093 (???,???) [000186] ------------ IL_OFFSET void IL offset: 0x40 REG NA
N095 ( 3, 2) [000169] ------------ t169 = LCL_VAR byref V09 cse0 u:1 eax (last use) Zero Fseq[Value] REG eax $300
N097 ( 1, 1) [000175] ------------ t175 = CNS_INT ref null REG edx $VN.Null
/--* t169 byref
+--* t175 ref
N099 (???,???) [000187] -A-XG------- * STOREIND ref REG NA
N101 (???,???) [000188] ------------ IL_OFFSET void IL offset: 0x50 REG NA
N103 ( 3, 2) [000070] ------------ t70 = LCL_VAR ref V07 tmp2 u:1 ecx (last use) REG ecx <l:$340, c:$204>
/--* t70 ref
N105 ( 4, 3) [000071] ------------ * RETURN ref REG NA $208
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
N109 (???,???) [000189] ------------ IL_OFFSET void IL offset: 0x16 REG NA
N111 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V00 this u:1 ecx (last use) REG ecx $80
/--* t82 ref
N113 (???,???) [000192] ------------ t192 = * PUTARG_REG ref REG ecx
/--* t192 ref this in ecx
N115 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack REG NA $VN.Void
-------------------------------------------------------------------------------------------------------------------
Final allocation
-------------------------------+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |esi |edi |
-------------------------------+----+----+----+----+----+
0.#0 V0 Parm Alloc ecx | |V0 a| | | |
1.#1 BB1 PredBB0 | |V0 a| | | |
9.#2 V0 Use Keep ecx | |V0 a| | | |
10.#3 I6 Def Alloc eax |I6 a|V0 a| | | |
13.#4 I6 Use * Keep eax |I6 i|V0 a| | | |
14.#5 I7 Def Alloc eax |I7 a|V0 a| | | |
15.#6 I7 Use * Keep eax |I7 i|V0 a| | | |
16.#7 V1 Def Alloc eax |V1 a|V0 a| | | |
23.#8 V0 Use Keep ecx |V1 a|V0 a| | | |
24.#9 I8 Def Alloc edx |V1 a|V0 a|I8 a| | |
25.#10 I8 Use * Keep edx |V1 a|V0 a|I8 i| | |
26.#11 V2 Def Alloc edx |V1 a|V0 a|V2 a| | |
33.#12 V2 Use Keep edx |V1 a|V0 a|V2 a| | |
34.#13 I9 Def Alloc esi |V1 a|V0 a|V2 a|I9 a| |
35.#14 I9 Use * Keep esi |V1 a|V0 a|V2 a|I9 i| |
36.#15 V10 Def Alloc esi |V1 a|V0 a|V2 a|V10a| |
41.#16 V10 Use * Keep esi |V1 a|V0 a|V2 a|V10i| |
41.#17 V1 Use Keep eax |V1 a|V0 a|V2 a| | |
-------------------------------+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |esi |edi |
-------------------------------+----+----+----+----+----+
45.#18 BB2 PredBB1 |V1 a|V0 a|V2 a| | |
63.#19 V0 Use Keep ecx |V1 a|V0 a|V2 a| | |
73.#20 V0 Use * Keep ecx |V1 a|V0 i|V2 a| | |
73.#21 V1 Use Keep eax |V1 a| |V2 a| | |
81.#22 V2 Use * Keep edx |V1 a| |V2 i| | |
81.#23 V1 Use * Keep eax |V1 i| | | | |
82.#24 I10 Def Alloc eax |I10a| | | | |
83.#25 I10 Use * Keep eax |I10i| | | | |
84.#26 V9 Def Alloc eax |V9 a| | | | |
87.#27 V9 Use Keep eax |V9 a| | | | |
88.#28 I11 Def Alloc ecx |V9 a|I11a| | | |
89.#29 I11 Use * Keep ecx |V9 a|I11i| | | |
90.#30 V7 Def Alloc ecx |V9 a|V7 a| | | |
98.#31 C12 Def Alloc edx |V9 a|V7 a|C12a| | |
99.#32 V9 Use * Keep eax |V9 i|V7 a|C12a| | |
99.#33 C12 Use * Keep edx | |V7 a|C12i| | |
105.#34 eax Fixd Keep eax | |V7 a| | | |
105.#35 V7 Use * Copy eax |V7 i|V7 i| | | |
-------------------------------+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |esi |edi |
-------------------------------+----+----+----+----+----+
107.#36 BB6 PredBB1 | |V0 a| | | |
113.#37 ecx Fixd Keep ecx | |V0 a| | | |
113.#38 V0 Use * Keep ecx | |V0 i| | | |
114.#39 ecx Fixd Keep ecx | | | | | |
114.#40 I13 Def Alloc ecx | |I13a| | | |
115.#41 ecx Fixd Keep ecx | |I13a| | | |
115.#42 I13 Use * Keep ecx | |I13i| | | |
116.#43 eax Kill Keep eax | | | | | |
116.#44 ecx Kill Keep ecx | | | | | |
116.#45 edx Kill Keep edx | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 8
Total Reg Cand Vars: 6
Total number of Intervals: 13
Total number of RefPositions: 45
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V00(ecx)
BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
=====
N003. IL_OFFSET IL offset: 0x0
N005. V00(ecx)
N007. STK = LEA(b+8) ; ecx
N009. eax = IND ; STK
N011. CNS_INT -1
N013. eax = ADD ; eax
* N015. V01(eax); eax
N017. IL_OFFSET IL offset: 0x9
N019. V00(ecx)
N021. STK = LEA(b+4) ; ecx
N023. edx = IND ; STK
* N025. V02(edx); edx
N027. IL_OFFSET IL offset: 0x10
N029. V02(edx)
N031. STK = LEA(b+4) ; edx
N033. esi = IND ; STK
* N035. V10(esi); esi
N037. V10(esi*)
N039. V01(eax)
N041. LE ; esi*,eax
N043. JTRUE
Var=Reg end of BB01: V00=ecx V01=eax V02=edx
BB02 [01C..052) (return), preds={BB01} succs={}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB02: V00=ecx V01=eax V02=edx
N047. IL_OFFSET IL offset: 0x1c
N049. V00(STK)
N051. LEA(b+12)
N053. IND
N055. CNS_INT 1
N057. ADD
N059. V00(ecx)
N061. STK = LEA(b+12); ecx
N063. STOREIND ; STK
N065. IL_OFFSET IL offset: 0x2a
N067. V00(ecx*)
N069. STK = LEA(b+8) ; ecx*
N071. V01(eax)
N073. STOREIND ; STK,eax
N075. IL_OFFSET IL offset: 0x31
N077. V02(edx*)
N079. V01(eax*)
N081. eax = LEA(b+(i*4)+8); edx*,eax*
* N083. V09(eax); eax
N085. V09(eax)
N087. ecx = IND ; eax
* N089. V07(ecx); ecx
N091. IL_OFFSET IL offset: 0x39
N093. IL_OFFSET IL offset: 0x40
N095. V09(eax*)
N097. edx = CNS_INT null
N099. STOREIND ; eax*,edx
N101. IL_OFFSET IL offset: 0x50
N103. V07(ecx*)
N105. RETURN ; ecx*
Var=Reg end of BB02: none
BB06 [016..01C) (throw), preds={BB01} succs={}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB06: V00=ecx
N109. IL_OFFSET IL offset: 0x16
N111. V00(ecx*)
N113. ecx = PUTARG_REG; ecx*
N115. CALL ; ecx
Var=Reg end of BB06: none
*************** Finishing PHASE Linear scan register alloc
*************** In genGenerateCode()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen LIR
BB02 [0002] 1 BB01 1 [01C..052) (return) i label target idxlen LIR
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V00(ecx)
Modified regs: [eax ecx edx esi]
Callee-saved registers pushed: 1 [esi]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
; Final local variable assignments
;
; V00 this [V00,T00] ( 8, 7 ) ref -> ecx this class-hnd
; V01 loc0 [V01,T01] ( 4, 4 ) int -> eax
; V02 loc1 [V02,T03] ( 3, 3 ) ref -> edx class-hnd
;* V03 loc2 [V03 ] ( 0, 0 ) struct ( 4) zero-ref
;* V04 loc3 [V04 ] ( 0, 0 ) struct ( 4) zero-ref ld-addr-op
;* V05 tmp0 [V05,T02] ( 0, 0 ) int -> zero-ref "impRuntimeLookup slot"
;* V06 tmp1 [V06 ] ( 0, 0 ) int -> zero-ref "spilling Runtime Lookup tree"
; V07 tmp2 [V07,T05] ( 2, 2 ) ref -> ecx V03.Value(offs=0x00) P-INDEP "field V03.Value (fldOffset=0x0)"
;* V08 tmp3 [V08,T07] ( 0, 0 ) ref -> zero-ref V04.Value(offs=0x00) P-INDEP "field V04.Value (fldOffset=0x0)"
; V09 cse0 [V09,T04] ( 3, 3 ) byref -> eax "CSE - aggressive"
; V10 cse1 [V10,T06] ( 2, 2 ) int -> esi "CSE - aggressive"
;
; Lcl frame size = 0
Setting stack level from -572662307 to 0
=============== Generating BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06} flags=0x00000000.40230020: i label target idxlen LIR
BB01 IN (1)={V00 } + ByrefExposed + GcHeap
OUT(3)={V00 V01 V02} + ByrefExposed + GcHeap
Recording Var Locations at start of BB01
V00(ecx)
Change life 00000000 {} -> 00000001 {V00}
V00 in reg ecx is becoming live [------]
Live regs: 00000000 {} => 00000002 {ecx}
Live regs: (unchanged) 00000002 {ecx}
GC regs: (unchanged) 00000002 {ecx}
Byref regs: (unchanged) 00000000 {}
L_M50390_BB01:
Label: IG02, GCvars=00000000 {}, gcrefRegs=00000002 {ecx}, byrefRegs=00000000 {}
Scope info: begin block BB01, IL range [000..016)
Scope info: open scopes =
0 (V00 this) [000..052)
Added IP mapping: 0x0000 STACK_EMPTY (G_M50390_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000177] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N005 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V00 this u:1 ecx REG ecx $80
/--* t0 ref
Generating: N007 ( 2, 2) [000088] -c---------- t88 = * LEA(b+8) byref REG NA
/--* t88 byref
Generating: N009 ( 4, 4) [000001] ---XG------- t1 = * IND int REG eax <l:$143, c:$142>
IN0001: mov eax, dword ptr [ecx+8]
Generating: N011 ( 1, 1) [000002] -c---------- t2 = CNS_INT int -1 REG NA $41
/--* t1 int
+--* t2 int
Generating: N013 ( 6, 6) [000003] ---XG------- t3 = * ADD int REG eax <l:$147, c:$146>
IN0002: dec eax
/--* t3 int
Generating: N015 ( 6, 6) [000005] DA-XG------- * STORE_LCL_VAR int V01 loc0 d:1 eax REG eax
V01 in reg eax is becoming live [000005]
Live regs: 00000002 {ecx} => 00000003 {eax ecx}
Live vars: {V00} => {V00 V01}
Added IP mapping: 0x0009 STACK_EMPTY (G_M50390_IG02,ins#2,ofs#4)
Generating: N017 (???,???) [000178] ------------ IL_OFFSET void IL offset: 0x9 REG NA
Generating: N019 ( 1, 1) [000006] ------------ t6 = LCL_VAR ref V00 this u:1 ecx REG ecx $80
/--* t6 ref
Generating: N021 ( 2, 2) [000090] -c---------- t90 = * LEA(b+4) byref REG NA
/--* t90 byref
Generating: N023 ( 4, 4) [000007] n---GO------ t7 = * IND ref REG edx <l:$1c4, c:$1c3>
IN0003: mov edx, gword ptr [ecx+4]
GC regs: 00000002 {ecx} => 00000006 {ecx edx}
/--* t7 ref
Generating: N025 ( 4, 4) [000009] DA--GO------ * STORE_LCL_VAR ref V02 loc1 d:1 edx REG edx
GC regs: 00000006 {ecx edx} => 00000002 {ecx}
V02 in reg edx is becoming live [000009]
Live regs: 00000003 {eax ecx} => 00000007 {eax ecx edx}
Live vars: {V00 V01} => {V00 V01 V02}
GC regs: 00000002 {ecx} => 00000006 {ecx edx}
Added IP mapping: 0x0010 STACK_EMPTY (G_M50390_IG02,ins#3,ofs#7)
Generating: N027 (???,???) [000179] ------------ IL_OFFSET void IL offset: 0x10 REG NA
Generating: N029 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V02 loc1 u:1 edx REG edx <l:$1c2, c:$200>
/--* t11 ref
Generating: N031 (???,???) [000191] -c---------- t191 = * LEA(b+4) ref REG NA
/--* t191 ref
Generating: N033 ( 3, 3) [000012] ---X-------- t12 = * IND int REG esi <l:$149, c:$148>
IN0004: mov esi, dword ptr [edx+4]
/--* t12 int
Generating: N035 ( 7, 6) [000171] DA-X-------- * STORE_LCL_VAR int V10 cse1 d:1 esi REG esi
V10 in reg esi is becoming live [000171]
Live regs: 00000007 {eax ecx edx} => 00000047 {eax ecx edx esi}
Live vars: {V00 V01 V02} => {V00 V01 V02 V10}
Generating: N037 ( 3, 2) [000172] ------------ t172 = LCL_VAR int V10 cse1 u:1 esi (last use) REG esi <l:$149, c:$148>
Generating: N039 ( 1, 1) [000010] ------------ t10 = LCL_VAR int V01 loc0 u:1 eax REG eax <l:$145, c:$144>
/--* t172 int
+--* t10 int
Generating: N041 ( 12, 10) [000013] N--X---N-U-- * LE void REG NA <l:$14d, c:$14c>
V10 in reg esi is becoming dead [000172]
Live regs: 00000047 {eax ecx edx esi} => 00000007 {eax ecx edx}
Live vars: {V00 V01 V02 V10} => {V00 V01 V02}
IN0005: cmp esi, eax
Generating: N043 ( 14, 12) [000014] ---X-------- * JTRUE void REG NA
IN0006: jbe L_M50390_BB06
Scope info: end block BB01, IL range [000..016)
Scope info: open scopes =
0 (V00 this) [000..052)
=============== Generating BB02 [01C..052) (return), preds={BB01} succs={} flags=0x00000004.40230020: i label target idxlen LIR
BB02 IN (3)={V00 V01 V02} + ByrefExposed + GcHeap
OUT(0)={ }
Recording Var Locations at start of BB02
V00(ecx) V01(eax) V02(edx)
Liveness not changing: 0000000B {V00 V01 V02}
Live regs: 00000000 {} => 00000007 {eax ecx edx}
GC regs: 00000000 {} => 00000006 {ecx edx}
Byref regs: (unchanged) 00000000 {}
L_M50390_BB02:
G_M50390_IG02: ; offs=000000H, funclet=00, bbWeight=1
Label: IG03, GCvars=00000000 {}, gcrefRegs=00000006 {ecx edx}, byrefRegs=00000000 {}
Scope info: begin block BB02, IL range [01C..052)
Scope info: open scopes =
0 (V00 this) [000..052)
1 (V01 loc0) [000..052)
2 (V02 loc1) [000..052)
Added IP mapping: 0x001C STACK_EMPTY (G_M50390_IG03,ins#0,ofs#0) label
Generating: N047 (???,???) [000180] ------------ IL_OFFSET void IL offset: 0x1c REG NA
Generating: N049 ( 1, 1) [000016] -c---------- t16 = LCL_VAR ref V00 this u:1 ecx REG NA $80
/--* t16 ref
Generating: N051 ( 2, 2) [000095] -c---------- t95 = * LEA(b+12) byref REG NA
/--* t95 byref
Generating: N053 ( 4, 4) [000017] nc--GO------ t17 = * IND int REG NA <l:$151, c:$150>
Generating: N055 ( 1, 1) [000018] -c---------- t18 = CNS_INT int 1 REG NA $45
/--* t17 int
+--* t18 int
Generating: N057 ( 6, 6) [000019] -c--GO------ t19 = * ADD int REG NA <l:$155, c:$154>
Generating: N059 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 ecx REG ecx $80
/--* t15 ref
Generating: N061 ( 2, 2) [000093] -c---------- t93 = * LEA(b+12) byref REG NA
/--* t93 byref
+--* t19 int
Generating: N063 (???,???) [000181] -A--GO------ * STOREIND int REG NA
IN0007: inc dword ptr [ecx+12]
Added IP mapping: 0x002A STACK_EMPTY (G_M50390_IG03,ins#1,ofs#3)
Generating: N065 (???,???) [000182] ------------ IL_OFFSET void IL offset: 0x2a REG NA
Generating: N067 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V00 this u:1 ecx (last use) REG ecx $80
/--* t22 ref
Generating: N069 ( 2, 2) [000097] -c---------- t97 = * LEA(b+8) byref REG NA
Generating: N071 ( 1, 1) [000023] ------------ t23 = LCL_VAR int V01 loc0 u:1 eax REG eax <l:$145, c:$144>
/--* t97 byref
+--* t23 int
Generating: N073 (???,???) [000183] -A--GO------ * STOREIND int REG NA
V00 in reg ecx is becoming dead [000022]
Live regs: 00000007 {eax ecx edx} => 00000005 {eax edx}
Live vars: {V00 V01 V02} => {V01 V02}
GC regs: 00000006 {ecx edx} => 00000004 {edx}
IN0008: mov dword ptr [ecx+8], eax
Added IP mapping: 0x0031 STACK_EMPTY (G_M50390_IG03,ins#2,ofs#6)
Generating: N075 (???,???) [000184] ------------ IL_OFFSET void IL offset: 0x31 REG NA
Generating: N077 ( 1, 1) [000118] ------------ t118 = LCL_VAR ref V02 loc1 u:1 edx (last use) REG edx <l:$1c2, c:$200>
Generating: N079 ( 1, 1) [000121] ------------ t121 = LCL_VAR int V01 loc0 u:1 eax (last use) REG eax <l:$145, c:$144>
/--* t118 ref
+--* t121 int
Generating: N081 ( 4, 4) [000117] -------N---- t117 = * LEA(b+(i*4)+8) byref REG eax
V02 in reg edx is becoming dead [000118]
Live regs: 00000005 {eax edx} => 00000001 {eax}
Live vars: {V01 V02} => {V01}
GC regs: 00000004 {edx} => 00000000 {}
V01 in reg eax is becoming dead [000121]
Live regs: 00000001 {eax} => 00000000 {}
Live vars: {V01} => {}
IN0009: lea eax, bword ptr [edx+4*eax+8]
Byref regs: 00000000 {} => 00000001 {eax}
/--* t117 byref
Generating: N083 ( 13, 12) [000166] DA--G------- * STORE_LCL_VAR byref V09 cse0 d:1 eax REG eax
Byref regs: 00000001 {eax} => 00000000 {}
V09 in reg eax is becoming live [000166]
Live regs: 00000000 {} => 00000001 {eax}
Live vars: {} => {V09}
Byref regs: 00000000 {} => 00000001 {eax}
Generating: N085 ( 3, 2) [000167] ------------ t167 = LCL_VAR byref V09 cse0 u:1 eax Zero Fseq[Value] REG eax <l:$c6, c:$c5>
/--* t167 byref
Generating: N087 ( 19, 16) [000124] ---XG------- t124 = * IND ref REG ecx <l:$341, c:$204>
IN000a: mov ecx, gword ptr [eax]
GC regs: 00000000 {} => 00000002 {ecx}
/--* t124 ref
Generating: N089 ( 23, 19) [000125] DA-XG------- * STORE_LCL_VAR ref V07 tmp2 d:1 ecx REG ecx
GC regs: 00000002 {ecx} => 00000000 {}
V07 in reg ecx is becoming live [000125]
Live regs: 00000001 {eax} => 00000003 {eax ecx}
Live vars: {V09} => {V07 V09}
GC regs: 00000000 {} => 00000002 {ecx}
Added IP mapping: 0x0039 STACK_EMPTY (G_M50390_IG03,ins#4,ofs#12)
Generating: N091 (???,???) [000185] ------------ IL_OFFSET void IL offset: 0x39 REG NA
Added IP mapping: 0x0040 STACK_EMPTY (G_M50390_IG03,ins#4,ofs#12)
Generating: N093 (???,???) [000186] ------------ IL_OFFSET void IL offset: 0x40 REG NA
Generating: N095 ( 3, 2) [000169] ------------ t169 = LCL_VAR byref V09 cse0 u:1 eax (last use) Zero Fseq[Value] REG eax $300
Generating: N097 ( 1, 1) [000175] ------------ t175 = CNS_INT ref null REG edx $VN.Null
IN000b: xor edx, edx
GC regs: 00000002 {ecx} => 00000006 {ecx edx}
/--* t169 byref
+--* t175 ref
Generating: N099 (???,???) [000187] -A-XG------- * STOREIND ref REG NA
V09 in reg eax is becoming dead [000169]
Live regs: 00000003 {eax ecx} => 00000002 {ecx}
Live vars: {V07 V09} => {V07}
Byref regs: 00000001 {eax} => 00000000 {}
GC regs: 00000006 {ecx edx} => 00000002 {ecx}
IN000c: mov gword ptr [eax], edx
Added IP mapping: 0x0050 STACK_EMPTY (G_M50390_IG03,ins#6,ofs#16)
Generating: N101 (???,???) [000188] ------------ IL_OFFSET void IL offset: 0x50 REG NA
Generating: N103 ( 3, 2) [000070] ------------ t70 = LCL_VAR ref V07 tmp2 u:1 ecx (last use) REG ecx <l:$340, c:$204>
/--* t70 ref
Generating: N105 ( 4, 3) [000071] ------------ * RETURN ref REG NA $208
V07 in reg ecx is becoming dead [000070]
Live regs: 00000002 {ecx} => 00000000 {}
Live vars: {V07} => {}
GC regs: 00000002 {ecx} => 00000000 {}
IN000d: mov eax, ecx
Scope info: end block BB02, IL range [01C..052)
Scope info: ending scope, LVnum=1 [000..052)
Scope info: ending scope, LVnum=2 [000..052)
Scope info: ending scope, LVnum=3 [000..052)
siEndScope: Failed to end scope for V03
Scope info: ending scope, LVnum=4 [000..052)
siEndScope: Failed to end scope for V04
Scope info: ending scope, LVnum=0 [000..052)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M50390_IG03,ins#7,ofs#18) label
Reserving epilog IG for block BB02
G_M50390_IG03: ; offs=000012H, funclet=00, bbWeight=1
*************** After placeholder IG creation
G_M50390_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M50390_IG02: ; offs=000000H, size=0012H, gcrefRegs=00000002 {ecx}, byrefRegs=00000000 {}, byref
G_M50390_IG03: ; offs=000012H, size=0012H, gcrefRegs=00000006 {ecx edx}, byrefRegs=00000000 {}, byref
G_M50390_IG04: ; epilog placeholder, next placeholder=<END>, BB02 [0002], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000002 {ecx}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000006 {ecx edx}, InitByrefRegs=00000000 {}
G_M50390_IG05: ; offs=000124H, size=0000H, gcrefRegs=00000000 {} <-- Current IG
=============== Generating BB06 [016..01C) (throw), preds={BB01} succs={} flags=0x00000004.400b1020: i rare label target gcsafe LIR
BB06 IN (1)={V00} + ByrefExposed + GcHeap
OUT(0)={ }
Recording Var Locations at start of BB06
V00(ecx)
Change life 00000000 {} -> 00000001 {V00}
V00 in reg ecx is becoming live [------]
Live regs: 00000000 {} => 00000002 {ecx}
Live regs: (unchanged) 00000002 {ecx}
GC regs: (unchanged) 00000002 {ecx}
Byref regs: (unchanged) 00000000 {}
L_M50390_BB06:
Label: IG05, GCvars=00000000 {}, gcrefRegs=00000002 {ecx}, byrefRegs=00000000 {}
Scope info: begin block BB06, IL range [016..01C)
Scope info: open scopes =
0 (V00 this) [000..052)
Added IP mapping: 0x0016 STACK_EMPTY (G_M50390_IG05,ins#0,ofs#0) label
Generating: N109 (???,???) [000189] ------------ IL_OFFSET void IL offset: 0x16 REG NA
Generating: N111 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V00 this u:1 ecx (last use) REG ecx $80
/--* t82 ref
Generating: N113 (???,???) [000192] ------------ t192 = * PUTARG_REG ref REG ecx
V00 in reg ecx is becoming dead [000082]
Live regs: 00000002 {ecx} => 00000000 {}
Live vars: {V00} => {}
GC regs: 00000002 {ecx} => 00000000 {}
GC regs: 00000000 {} => 00000002 {ecx}
/--* t192 ref this in ecx
Generating: N115 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack REG NA $VN.Void
GC regs: 00000002 {ecx} => 00000000 {}
Call: GCvars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN000e: call Stack`1:ThrowForEmptyStack():this
Scope info: end block BB06, IL range [016..01C)
Scope info: open scopes =
<none>
IN000f: int3
Liveness not changing: 00000000 {}
# compCycleEstimate = 113, compSizeEstimate = 95 Stack`1:Pop():RefAsValueType`1:this
; Final local variable assignments
;
; V00 this [V00,T00] ( 8, 7 ) ref -> ecx this class-hnd
; V01 loc0 [V01,T01] ( 4, 4 ) int -> eax
; V02 loc1 [V02,T03] ( 3, 3 ) ref -> edx class-hnd
;* V03 loc2 [V03 ] ( 0, 0 ) struct ( 4) zero-ref
;* V04 loc3 [V04 ] ( 0, 0 ) struct ( 4) zero-ref ld-addr-op
;* V05 tmp0 [V05,T02] ( 0, 0 ) int -> zero-ref "impRuntimeLookup slot"
;* V06 tmp1 [V06 ] ( 0, 0 ) int -> zero-ref "spilling Runtime Lookup tree"
; V07 tmp2 [V07,T05] ( 2, 2 ) ref -> ecx V03.Value(offs=0x00) P-INDEP "field V03.Value (fldOffset=0x0)"
;* V08 tmp3 [V08,T07] ( 0, 0 ) ref -> zero-ref V04.Value(offs=0x00) P-INDEP "field V04.Value (fldOffset=0x0)"
; V09 cse0 [V09,T04] ( 3, 3 ) byref -> eax "CSE - aggressive"
; V10 cse1 [V10,T06] ( 2, 2 ) int -> esi "CSE - aggressive"
;
; Lcl frame size = 0
*************** Before prolog / epilog generation
G_M50390_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M50390_IG02: ; offs=000000H, size=0012H, gcrefRegs=00000002 {ecx}, byrefRegs=00000000 {}, byref
G_M50390_IG03: ; offs=000012H, size=0012H, gcrefRegs=00000006 {ecx edx}, byrefRegs=00000000 {}, byref
G_M50390_IG04: ; epilog placeholder, next placeholder=<END>, BB02 [0002], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000002 {ecx}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000006 {ecx edx}, InitByrefRegs=00000000 {}
G_M50390_IG05: ; offs=000124H, size=0000H, gcrefRegs=00000000 {} <-- Current IG
Recording Var Locations at start of BB01
V00(ecx)
G_M50390_IG05: ; offs=000124H, funclet=00, bbWeight=0
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M50390_IG01,ins#0,ofs#0) label
__prolog:
IN0010: push ebp
IN0011: mov ebp, esp
IN0012: push esi
*************** In genFnPrologCalleeRegArgs() for int regs
*************** In genEnregisterIncomingStackArgs()
G_M50390_IG01: ; offs=000000H, funclet=00, bbWeight=1
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=00000000 {}, gcRegGCrefSetCur=00000006 {ecx edx}, gcRegByrefSetCur=00000000 {}
IN0013: pop esi
IN0014: pop ebp
IN0015: ret
G_M50390_IG04: ; offs=000024H, funclet=00, bbWeight=1
0 prologs, 1 epilogs
*************** After prolog / epilog generation
G_M50390_IG01: ; func=00, offs=000000H, size=0004H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M50390_IG02: ; offs=000004H, size=0012H, gcrefRegs=00000002 {ecx}, byrefRegs=00000000 {}, byref
G_M50390_IG03: ; offs=000016H, size=0012H, gcrefRegs=00000006 {ecx edx}, byrefRegs=00000000 {}, byref
G_M50390_IG04: ; offs=000028H, size=0003H, epilog, nogc, extend
G_M50390_IG05: ; offs=00002BH, size=0006H, gcVars=00000000 {}, gcrefRegs=00000002 {ecx}, byrefRegs=00000000 {}, gcvars, byref
*************** In emitJumpDistBind()
Binding: IN0006: 000000 jbe L_M50390_BB06
Binding L_M50390_BB06to G_M50390_IG05
Estimate of fwd jump [02DB519C/006]: 0010 -> 002B = 0019
Shrinking jump [02DB519C/006]
Adjusted offset of BB03 from 0016 to 0012
Adjusted offset of BB04 from 0028 to 0024
Adjusted offset of BB05 from 002B to 0027
Total shrinkage = 4, min extra jump size = 4294967295
*************** Finishing PHASE Generate code
*************** Starting PHASE Emit code
Hot code size = 0x2D bytes
Cold code size = 0x0 bytes
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M50390_IG01: ; func=00, offs=000000H, size=0004H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0010: 000000 55 push ebp
IN0011: 000001 8BEC mov ebp, esp
IN0012: 000003 56 push esi
;; bbWeight=1 PerfScore 2.25
G_M50390_IG02: ; func=00, offs=000004H, size=000EH, gcrefRegs=00000002 {ecx}, byrefRegs=00000000 {}, byref, isz
New gcrReg live regs=00000002 {ecx}
IN0001: 000004 8B4108 mov eax, dword ptr [ecx+8]
IN0002: 000007 48 dec eax
gcrReg +[edx]
IN0003: 000008 8B5104 mov edx, gword ptr [ecx+4]
IN0004: 00000B 8B7204 mov esi, dword ptr [edx+4]
IN0005: 00000E 3BF0 cmp esi, eax
IN0006: 000010 7615 jbe SHORT G_M50390_IG05
;; bbWeight=1 PerfScore 7.50
G_M50390_IG03: ; func=00, offs=000012H, size=0012H, gcrefRegs=00000006 {ecx edx}, byrefRegs=00000000 {}, byref
IN0007: 000012 FF410C inc dword ptr [ecx+12]
IN0008: 000015 894108 mov dword ptr [ecx+8], eax
byrReg +[eax]
IN0009: 000018 8D448208 lea eax, bword ptr [edx+4*eax+8]
IN000a: 00001C 8B08 mov ecx, gword ptr [eax]
IN000b: 00001E 33D2 xor edx, edx
IN000c: 000020 8910 mov gword ptr [eax], edx
byrReg -[eax]
gcrReg +[eax]
IN000d: 000022 8BC1 mov eax, ecx
;; bbWeight=1 PerfScore 10.50
G_M50390_IG04: ; func=00, offs=000024H, size=0003H, epilog, nogc, extend
IN0013: 000024 5E pop esi
IN0014: 000025 5D pop ebp
IN0015: 000026 C3 ret
;; bbWeight=1 PerfScore 2.00
G_M50390_IG05: ; func=00, offs=000027H, size=0006H, gcVars=00000000 {}, gcrefRegs=00000002 {ecx}, byrefRegs=00000000 {}, gcvars, byref
New gcrReg live regs=00000002 {ecx}
New gcrReg live regs=00000000 {}
IN000e: 000027 E8DCF8FFFF call Stack`1:ThrowForEmptyStack():this
IN000f: 00002C CC int3
;; bbWeight=0 PerfScore 0.00Allocated method code size = 45 , actual size = 45
; Total bytes of code 45, prolog size 4, PerfScore 26.75, (MethodHash=b85a3b29) for method Stack`1:Pop():RefAsValueType`1:this
; ============================================================
*************** After end code gen, before unwindEmit()
G_M50390_IG01: ; func=00, offs=000000H, size=0004H, bbWeight=1 PerfScore 2.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0010: 000000 push ebp
IN0011: 000001 mov ebp, esp
IN0012: 000003 push esi
G_M50390_IG02: ; offs=000004H, size=000EH, bbWeight=1 PerfScore 7.50, gcrefRegs=00000002 {ecx}, byrefRegs=00000000 {}, byref, isz
IN0001: 000004 mov eax, dword ptr [ecx+8]
IN0002: 000007 dec eax
IN0003: 000008 mov edx, gword ptr [ecx+4]
IN0004: 00000B mov esi, dword ptr [edx+4]
IN0005: 00000E cmp esi, eax
IN0006: 000010 jbe SHORT G_M50390_IG05
G_M50390_IG03: ; offs=000012H, size=0012H, bbWeight=1 PerfScore 10.50, gcrefRegs=00000006 {ecx edx}, byrefRegs=00000000 {}, byref
IN0007: 000012 inc dword ptr [ecx+12]
IN0008: 000015 mov dword ptr [ecx+8], eax
IN0009: 000018 lea eax, bword ptr [edx+4*eax+8]
IN000a: 00001C mov ecx, gword ptr [eax]
IN000b: 00001E xor edx, edx
IN000c: 000020 mov gword ptr [eax], edx
IN000d: 000022 mov eax, ecx
G_M50390_IG04: ; offs=000024H, size=0003H, bbWeight=1 PerfScore 2.00, epilog, nogc, extend
IN0013: 000024 pop esi
IN0014: 000025 pop ebp
IN0015: 000026 ret
G_M50390_IG05: ; offs=000027H, size=0006H, bbWeight=0 PerfScore 0.00, gcVars=00000000 {}, gcrefRegs=00000002 {ecx}, byrefRegs=00000000 {}, gcvars, byref
IN000e: 000027 call Stack`1:ThrowForEmptyStack():this
IN000f: 00002C int3
*************** Finishing PHASE Emit code
*************** Starting PHASE Emit GC+EH tables
*************** In genIPmappingGen()
IP mapping count : 11
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000004 ( STACK_EMPTY )
IL offs 0x0009 : 0x00000008 ( STACK_EMPTY )
IL offs 0x0010 : 0x0000000B ( STACK_EMPTY )
IL offs 0x001C : 0x00000012 ( STACK_EMPTY )
IL offs 0x002A : 0x00000015 ( STACK_EMPTY )
IL offs 0x0031 : 0x00000018 ( STACK_EMPTY )
IL offs 0x0040 : 0x0000001E ( STACK_EMPTY )
IL offs 0x0050 : 0x00000022 ( STACK_EMPTY )
IL offs EPILOG : 0x00000024 ( STACK_EMPTY )
IL offs 0x0016 : 0x00000027 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 4
*************** Variable debug info
4 live ranges
0( UNKNOWN) : From 00000000h to 00000004h, in ecx
0( UNKNOWN) : From 00000004h to 00000015h, in ecx
2( UNKNOWN) : From 00000012h to 00000018h, in edx
1( UNKNOWN) : From 00000012h to 00000018h, in eax
*************** In gcInfoBlockHdrSave()
GCINFO: untrckVars = 0
GCINFO: trackdLcls = 0
GCINFO: untrckVars = 0
GCINFO: trackdLcls = 0
*************** In gcInfoBlockHdrSave()
GCINFO: methodSize = 002D
GCINFO: prologSize = 0004
GCINFO: epilogSize = 0003
GCINFO: untrckVars = 0
GCINFO: trackdLcls = 0
GC Info for method Stack`1:Pop():RefAsValueType`1:this
GC info size = 10
Method info block:
method size = 002D
prolog size = 4
epilog size = 3
epilog count = 1
epilog end = no
callee-saved regs = ESI EBP
ebp frame = yes
fully interruptible= no
double align = no
arguments size = 0 DWORDs
stack frame size = 0 DWORDs
untracked count = 0
var ptr tab count = 0
epilog # 0 at 0024
2D BD A5 BB BD |
BF CF 01 24 |
Pointer table:
FF |
*************** Finishing PHASE Emit GC+EH tables
Method code size: 45
Allocations for Stack`1:Pop():RefAsValueType`1:this (MethodHash=b85a3b29)
count: 1569, size: 87323, max = 3072
allocateMemory: 131072, nraUsed: 90488
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 6436 | 7.37%
ASTNode | 17832 | 20.42%
InstDesc | 2124 | 2.43%
ImpStack | 192 | 0.22%
BasicBlock | 1964 | 2.25%
fgArgInfo | 132 | 0.15%
fgArgInfoPtrArr | 12 | 0.01%
FlowList | 240 | 0.27%
TreeStatementList | 112 | 0.13%
SiScope | 220 | 0.25%
DominatorMemory | 196 | 0.22%
LSRA | 1668 | 1.91%
LSRA_Interval | 672 | 0.77%
LSRA_RefPosition | 2024 | 2.32%
Reachability | 8 | 0.01%
SSA | 580 | 0.66%
ValueNumber | 15099 | 17.29%
LvaTable | 1424 | 1.63%
UnwindInfo | 0 | 0.00%
hashBv | 104 | 0.12%
bitset | 1176 | 1.35%
FixedBitVect | 32 | 0.04%
Generic | 1238 | 1.42%
LocalAddressVisitor | 320 | 0.37%
FieldSeqStore | 192 | 0.22%
ZeroOffsetFieldMap | 152 | 0.17%
ArrayInfoMap | 188 | 0.22%
MemoryPhiArg | 0 | 0.00%
CSE | 1352 | 1.55%
GC | 12 | 0.01%
CorSig | 104 | 0.12%
Inlining | 1056 | 1.21%
ArrayStack | 128 | 0.15%
DebugInfo | 380 | 0.44%
DebugOnly | 28689 | 32.85%
Codegen | 592 | 0.68%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 237 | 0.27%
RangeCheck | 0 | 0.00%
CopyProp | 396 | 0.45%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 0 | 0.00%
ClassLayout | 40 | 0.05%
TailMergeThrows | 0 | 0.00%
EarlyProp | 0 | 0.00%
****** DONE compiling Stack`1:Pop():RefAsValueType`1:this
ERRORLEVEL=100
Raw
ex.diff.d
c:\repos\runtime4\artifacts\tests\coreclr\Windows_NT.x86.release\Tests\Core_Root\corerun.exe ex.exe
Compiling 0 CastHelpers::StelemRef, IL size = 86, hash=0x93aaa786 FullOpts
Compiling 1 CastHelpers::LdelemaRef, IL size = 42, hash=0xffd2fc9e FullOpts
Compiling 2 SpanHelpers::IndexOf, IL size = 705, hash=0xdb3370c7 FullOpts
Compiling 3 Utf16Utility::GetPointerToFirstInvalidChar, IL size = 972, hash=0x137a51fe FullOpts
Compiling 4 Vector128::CreateScalarUnsafe, IL size = 21, hash=0xcd46d192 FullOpts
Compiling 5 Vector128::AsUInt32, IL size = 7, hash=0x8f8eda53 FullOpts
Compiling 6 Vector128::AsUInt16, IL size = 7, hash=0x7bc35b55 FullOpts
Compiling 7 Vector128::AsByte, IL size = 7, hash=0x9ea1d9de FullOpts
Compiling 8 Sse41::get_IsSupported, IL size = 6, hash=0x6da8cf37 FullOpts
Compiling 9 ASCIIUtility::NarrowUtf16ToAscii, IL size = 637, hash=0x150d5dc8 FullOpts
Compiling 10 X::Main, IL size = 51, hash=0x17874944 FullOpts
Compiling 11 EmptyArray`1::.cctor, IL size = 12, hash=0xaece4604 Tier-1/FullOpts switched to MinOpts
Compiling 12 Stack`1::Push, IL size = 60, hash=0x3bffc3a2 FullOpts
Compiling 13 Stack`1::PushWithResize, IL size = 80, hash=0xa06e2af2 FullOpts
Compiling 14 Array::Resize, IL size = 66, hash=0x16e8e9e0 FullOpts
****** START compiling Stack`1:Pop():RefAsValueType`1:this (MethodHash=b85a3b29)
Generating code for Windows x86
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
IL to import:
IL_0000 02 ldarg.0
IL_0001 7b 54 02 00 0a ldfld 0xA000254
IL_0006 17 ldc.i4.1
IL_0007 59 sub
IL_0008 0a stloc.0
IL_0009 02 ldarg.0
IL_000a 7b 53 02 00 0a ldfld 0xA000253
IL_000f 0b stloc.1
IL_0010 06 ldloc.0
IL_0011 07 ldloc.1
IL_0012 8e ldlen
IL_0013 69 conv.i4
IL_0014 37 06 blt.un.s 6 (IL_001c)
IL_0016 02 ldarg.0
IL_0017 28 59 02 00 0a call 0xA000259
IL_001c 02 ldarg.0
IL_001d 02 ldarg.0
IL_001e 7b 55 02 00 0a ldfld 0xA000255
IL_0023 17 ldc.i4.1
IL_0024 58 add
IL_0025 7d 55 02 00 0a stfld 0xA000255
IL_002a 02 ldarg.0
IL_002b 06 ldloc.0
IL_002c 7d 54 02 00 0a stfld 0xA000254
IL_0031 07 ldloc.1
IL_0032 06 ldloc.0
IL_0033 a3 11 00 00 1b ldelem 0x1B000011
IL_0038 0c stloc.2
IL_0039 28 0b 00 00 2b call 0x2B00000B
IL_003e 2c 10 brfalse.s 16 (IL_0050)
IL_0040 07 ldloc.1
IL_0041 06 ldloc.0
IL_0042 12 03 ldloca.s 0x3
IL_0044 fe 15 11 00 00 1b initobj 0x1B000011
IL_004a 09 ldloc.3
IL_004b a4 11 00 00 1b stelem 0x1B000011
IL_0050 08 ldloc.2
IL_0051 2a ret
lvaSetClass: setting class for V00 to (08A6A8B8) Stack`1
'this' passed in register ecx
lvaSetClass: setting class for V02 to (08A6AD18) (null)
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 int
; V02 loc1 ref class-hnd
; V03 loc2 struct ( 4)
; V04 loc3 struct ( 4)
*************** In compInitDebuggingInfo() for Stack`1:Pop():RefAsValueType`1:this
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 5
VarNum LVNum Name Beg End
0: 00h 00h V00 this 000h 052h
1: 01h 01h V01 loc0 000h 052h
2: 02h 02h V02 loc1 000h 052h
3: 03h 03h V03 loc2 000h 052h
4: 04h 04h V04 loc3 000h 052h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Stack`1:Pop():RefAsValueType`1:this
Marked V01 as a single def local
Marked V02 as a single def local
Marked V03 as a single def local
Jump targets:
IL_001c
IL_0050
New Basic Block BB01 [0000] created.
BB01 [000..016)
New Basic Block BB02 [0001] created.
BB02 [016..01C)
New Basic Block BB03 [0002] created.
BB03 [01C..040)
New Basic Block BB04 [0003] created.
BB04 [040..050)
New Basic Block BB05 [0004] created.
BB05 [050..052)
IL Code Size,Instr 82, 38, Basic Block count 5, Local Variable Num,Ref count 5, 19 for method Stack`1:Pop():RefAsValueType`1:this
OPTIONS: opts.MinOpts() == false
Basic block list for 'Stack`1:Pop():RefAsValueType`1:this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond )
BB02 [0001] 1 1 [016..01C)
BB03 [0002] 2 1 [01C..040)-> BB05 ( cond )
BB04 [0003] 1 1 [040..050)
BB05 [0004] 2 1 [050..052) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
Compiling 15 Stack`1::Pop, IL size = 82, hash=0xb85a3b29 FullOpts
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
*************** Starting PHASE Importation
*************** In impImport() for Stack`1:Pop():RefAsValueType`1:this
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Stack`1:Pop():RefAsValueType`1:this'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldfld 0A000254
[ 1] 6 (0x006) ldc.i4.1 1
[ 2] 7 (0x007) sub
[ 1] 8 (0x008) stloc.0
STMT00000 (IL 0x000... ???)
[000005] -A-XG------- * ASG int
[000004] D------N---- +--* LCL_VAR int V01 loc0
[000003] ---XG------- \--* SUB int
[000001] ---XG------- +--* FIELD int _size
[000000] ------------ | \--* LCL_VAR ref V00 this
[000002] ------------ \--* CNS_INT int 1
[ 0] 9 (0x009) ldarg.0
[ 1] 10 (0x00a) ldfld 0A000253
[ 1] 15 (0x00f) stloc.1Querying runtime about current class of field Stack`1._array (declared as (null))
Field's current class not available
STMT00001 (IL 0x009... ???)
[000009] -A-XG------- * ASG ref
[000008] D------N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG------- \--* FIELD ref _array
[000006] ------------ \--* LCL_VAR ref V00 this
[ 0] 16 (0x010) ldloc.0
[ 1] 17 (0x011) ldloc.1
[ 2] 18 (0x012) ldlen
[ 2] 19 (0x013) conv.i4
[ 2] 20 (0x014) blt.un.s
STMT00002 (IL 0x010... ???)
[000014] ---X-------- * JTRUE void
[000013] N--X-----U-- \--* LT int
[000010] ------------ +--* LCL_VAR int V01 loc0
[000012] ---X-------- \--* ARR_LENGTH int
[000011] ------------ \--* LCL_VAR ref V02 loc1
impImportBlockPending for BB02
impImportBlockPending for BB03
Importing BB03 (PC=028) of 'Stack`1:Pop():RefAsValueType`1:this'
[ 0] 28 (0x01c) ldarg.0
[ 1] 29 (0x01d) ldarg.0
[ 2] 30 (0x01e) ldfld 0A000255
[ 2] 35 (0x023) ldc.i4.1 1
[ 3] 36 (0x024) add
[ 2] 37 (0x025) stfld 0A000255
STMT00003 (IL 0x01C... ???)
[000021] -A-XG------- * ASG int
[000020] ---XG--N---- +--* FIELD int _version
[000015] ------------ | \--* LCL_VAR ref V00 this
[000019] ---XG------- \--* ADD int
[000017] ---XG------- +--* FIELD int _version
[000016] ------------ | \--* LCL_VAR ref V00 this
[000018] ------------ \--* CNS_INT int 1
[ 0] 42 (0x02a) ldarg.0
[ 1] 43 (0x02b) ldloc.0
[ 2] 44 (0x02c) stfld 0A000254
STMT00004 (IL 0x02A... ???)
[000025] -A-XG------- * ASG int
[000024] ---XG--N---- +--* FIELD int _size
[000022] ------------ | \--* LCL_VAR ref V00 this
[000023] ------------ \--* LCL_VAR int V01 loc0
[ 0] 49 (0x031) ldloc.1
[ 1] 50 (0x032) ldloc.0
[ 2] 51 (0x033) ldelem 1B000011
[ 1] 56 (0x038) stloc.2
STMT00005 (IL 0x031... ???)
[000033] -A-XG------- * ASG struct (copy)
[000031] D----------- +--* LCL_VAR struct<RefAsValueType`1, 4> V03 loc2
[000030] ---XG------- \--* OBJ struct<RefAsValueType`1, 4>
[000029] ---XG------- \--* ADDR byref
[000028] ---XG------- \--* INDEX struct
[000026] ------------ +--* LCL_VAR ref V02 loc1
[000027] ------------ \--* LCL_VAR int V01 loc0
[ 0] 57 (0x039) call 2B00000B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0
Named Intrinsic System.Runtime.CompilerServices.RuntimeHelpersIsReferenceOrContainsReferences: Not recognized
lvaGrabTemp returning 5 (V05 tmp0) called for impRuntimeLookup slot.
STMT00006 (IL 0x039... ???)
[000038] -A-X-------- * ASG int
[000037] D------N---- +--* LCL_VAR int V05 tmp0
[000036] #--X-------- \--* IND int
[000035] ------------ \--* LCL_VAR ref V00 this
lvaGrabTemp returning 6 (V06 tmp1) called for spilling Runtime Lookup tree.
STMT00007 (IL ???... ???)
[000063] -AC-G------- * ASG int
[000062] D------N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G------- \--* QMARK int
[000051] Q----------- if +--* NE int
[000047] n----------- | +--* IND int
[000046] ------------ | | \--* ADD int
[000044] #----------- | | +--* IND int
[000043] #----------- | | | \--* IND int
[000042] ------------ | | | \--* ADD int
[000040] ------------ | | | +--* LCL_VAR int V05 tmp0
[000041] ------------ | | | \--* CNS_INT int 32
[000045] ------------ | | \--* CNS_INT int 12
[000050] ------------ | \--* CNS_INT int 0
[000060] --C-G------- if \--* COLON int
[000049] --C-G------- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] ------------ arg0 | +--* LCL_VAR int V05 tmp0
[000048] ------------ arg1 | \--* CNS_INT(h) int 0x8A93EB8 token
[000052] n----------- then \--* IND int
[000053] ------------ \--* ADD int
[000054] #----------- +--* IND int
[000055] #----------- | \--* IND int
[000056] ------------ | \--* ADD int
[000057] ------------ | +--* LCL_VAR int V05 tmp0
[000058] ------------ | \--* CNS_INT int 32
[000059] ------------ \--* CNS_INT int 12
STMT00008 (IL ???... ???)
[000034] I-C-G------- * CALL int RuntimeHelpers.IsReferenceOrContainsReferences (exactContextHnd=0x08A6B810)
[000065] ------------ arg0 \--* RUNTIMELOOKUP int 0x8a6b854 method
[000064] ------------ \--* LCL_VAR int V06 tmp1
[ 1] 62 (0x03e) brfalse.s
STMT00009 (IL ???... ???)
[000069] --C--------- * JTRUE void
[000068] --C--------- \--* EQ int
[000066] --C--------- +--* RET_EXPR int (inl return from call [000034])
[000067] ------------ \--* CNS_INT int 0
impImportBlockPending for BB04
impImportBlockPending for BB05
Importing BB05 (PC=080) of 'Stack`1:Pop():RefAsValueType`1:this'
[ 0] 80 (0x050) ldloc.2
[ 1] 81 (0x051) ret
impFixupStructReturnType: retyping
[000070] ------------ * LCL_VAR struct<RefAsValueType`1, 4> V03 loc2
impFixupStructReturnType: result of retyping is
[000070] ------------ * LCL_FLD ref V03 loc2 [+0]
STMT00010 (IL 0x050... ???)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_FLD ref V03 loc2 [+0]
Importing BB04 (PC=064) of 'Stack`1:Pop():RefAsValueType`1:this'
[ 0] 64 (0x040) ldloc.1
[ 1] 65 (0x041) ldloc.0
[ 2] 66 (0x042) ldloca.s 3
[ 3] 68 (0x044) initobj 1B000011
STMT00011 (IL 0x040... ???)
[000077] IA---------- * ASG struct (init)
[000074] D------N---- +--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
[000076] ------------ \--* CNS_INT int 0
[ 2] 74 (0x04a) ldloc.3
[ 3] 75 (0x04b) stelem 1B000011
STMT00012 (IL ???... ???)
[000081] -A-XG------- * ASG struct (copy)
[000079] ---XG------- +--* INDEX struct
[000072] ------------ | +--* LCL_VAR ref V02 loc1
[000073] ------------ | \--* LCL_VAR int V01 loc0
[000078] ------------ \--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
impImportBlockPending for BB05
Importing BB02 (PC=022) of 'Stack`1:Pop():RefAsValueType`1:this'
[ 0] 22 (0x016) ldarg.0
[ 1] 23 (0x017) call 0A000259
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
STMT00013 (IL 0x016... ???)
[000083] I-C-G------- * CALL void Stack`1.ThrowForEmptyStack (exactContextHnd=0x08A6A8A0)
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
impImportBlockPending for BB03
*************** Finishing PHASE Importation
*************** Starting PHASE Indirect call transform
*************** in fgTransformIndirectCalls(root)
-- no candidates to transform
*************** Finishing PHASE Indirect call transform
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import
*************** Starting PHASE Morph - Init
New BlockSet epoch 1, # of blocks (including unused BB00): 6, bitset array size: 1 (short)
*************** Finishing PHASE Morph - Init
*************** In fgDebugCheckBBlist
*************** Starting PHASE Morph - Inlining
*************** In fgInline()
Querying runtime about current class of field Stack`1._array (declared as (null))
Field's current class not available
Expanding INLINE_CANDIDATE in statement STMT00013 in BB02:
STMT00013 (IL 0x016...0x017)
[000083] I-C-G------- * CALL void Stack`1.ThrowForEmptyStack (exactContextHnd=0x08A6A8A0)
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
thisArg: is a local var
[000082] ------------ * LCL_VAR ref V00 this
INLINER: inlineInfo.tokenLookupContextHandle for Stack`1:ThrowForEmptyStack():this set to 0x08A6A8A0:
Invoking compiler for the inlinee method Stack`1:ThrowForEmptyStack():this :
IL to import:
IL_0000 28 16 00 00 06 call 0x6000016
IL_0005 73 51 00 00 0a newobj 0xA000051
IL_000a 7a throw
INLINER impTokenLookupContextHandle for Stack`1:ThrowForEmptyStack():this is 0x08A6A8A0.
*************** In fgFindBasicBlocks() for Stack`1:ThrowForEmptyStack():this
Jump targets:
none
New Basic Block BB06 [0005] created.
BB06 [000..00B)
Basic block list for 'Stack`1:ThrowForEmptyStack():this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB06 [0005] 1 0 [000..00B) (throw ) rare
-----------------------------------------------------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'Stack`1:Pop():RefAsValueType`1:this' calling 'Stack`1:ThrowForEmptyStack():this'
INLINER: during 'fgInline' result 'failed this callee' reason 'does not return'
Expanding INLINE_CANDIDATE in statement STMT00008 in BB03:
STMT00008 (IL ???... ???)
[000034] I-C-G------- * CALL int RuntimeHelpers.IsReferenceOrContainsReferences (exactContextHnd=0x08A6B810)
[000065] ------------ arg0 \--* RUNTIMELOOKUP int 0x8a6b854 method
[000064] ------------ \--* LCL_VAR int V06 tmp1
INLINER: inlineInfo.tokenLookupContextHandle for RuntimeHelpers:IsReferenceOrContainsReferences():bool set to 0x08A6B810:
Invoking compiler for the inlinee method RuntimeHelpers:IsReferenceOrContainsReferences():bool :
IL to import:
IL_0000 17 ldc.i4.1
IL_0001 2a ret
INLINER impTokenLookupContextHandle for RuntimeHelpers:IsReferenceOrContainsReferences():bool is 0x08A6B810.
*************** In fgFindBasicBlocks() for RuntimeHelpers:IsReferenceOrContainsReferences():bool
Jump targets:
none
New Basic Block BB07 [0005] created.
BB07 [000..002)
Basic block list for 'RuntimeHelpers:IsReferenceOrContainsReferences():bool'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB07 [0005] 1 1 [000..002) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Inline @[000034] Starting PHASE Pre-import
*************** Inline @[000034] Finishing PHASE Pre-import
*************** Inline @[000034] Starting PHASE Importation
*************** In impImport() for RuntimeHelpers:IsReferenceOrContainsReferences():bool
impImportBlockPending for BB07
Importing BB07 (PC=000) of 'RuntimeHelpers:IsReferenceOrContainsReferences():bool'
[ 0] 0 (0x000) ldc.i4.1 1
[ 1] 1 (0x001) ret
Inlinee Return expression (before normalization) =>
[000084] ------------ * CNS_INT int 1
Inlinee Return expression (after normalization) =>
[000085] ------------ * CAST int <- bool <- int
[000084] ------------ \--* CNS_INT int 1
** Note: inlinee IL was partially imported -- imported 0 of 2 bytes of method IL
*************** Inline @[000034] Finishing PHASE Importation
*************** Inline @[000034] Starting PHASE Indirect call transform
*************** in fgTransformIndirectCalls(inlinee)
-- no candidates to transform
*************** Inline @[000034] Finishing PHASE Indirect call transform
*************** Inline @[000034] Starting PHASE Post-import
*************** Inline @[000034] Finishing PHASE Post-import
----------- Statements (and blocks) added due to the inlining of call [000034] -----------
Inlinee method body:Inlinee ignores runtime lookup generics context
fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000034] is
[000085] ------------ * CAST int <- bool <- int
[000084] ------------ \--* CNS_INT int 1
Successfully inlined RuntimeHelpers:IsReferenceOrContainsReferences():bool (2 IL bytes) (depth 1) [below ALWAYS_INLINE size]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Stack`1:Pop():RefAsValueType`1:this' calling 'RuntimeHelpers:IsReferenceOrContainsReferences():bool'
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size'
Folding operator with constant nodes into a constant:
[000085] ------------ * CAST int <- bool <- int
[000084] ------------ \--* CNS_INT int 1
Bashed to int constant:
[000085] ------------ * CNS_INT int 1
Replacing the return expression placeholder [000066] with [000085]
[000066] --C--------- * RET_EXPR int (inl return from call [000085])
Inserting the inline return expression
[000085] ------------ * CNS_INT int 1
Folding operator with constant nodes into a constant:
[000068] --C--------- * EQ int
[000085] ------------ +--* CNS_INT int 1
[000067] ------------ \--* CNS_INT int 0
Bashed to int constant:
[000068] ------------ * CNS_INT int 0
... found foldable jtrue at [000069] in BB03
*************** After fgInline()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i idxlen
BB02 [0001] 1 1 [016..01C) i
BB03 [0002] 2 1 [01C..040) i idxlen
BB04 [0003] 1 1 [040..050) i idxlen
BB05 [0004] 1 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01
STMT00000 (IL 0x000...0x008)
[000005] -A-XG------- * ASG int
[000004] D------N---- +--* LCL_VAR int V01 loc0
[000003] ---XG------- \--* SUB int
[000001] ---XG------- +--* FIELD int _size
[000000] ------------ | \--* LCL_VAR ref V00 this
[000002] ------------ \--* CNS_INT int 1
***** BB01
STMT00001 (IL 0x009...0x00F)
[000009] -A-XG------- * ASG ref
[000008] D------N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG------- \--* FIELD ref _array
[000006] ------------ \--* LCL_VAR ref V00 this
***** BB01
STMT00002 (IL 0x010...0x014)
[000014] ---X-------- * JTRUE void
[000013] N--X-----U-- \--* LT int
[000010] ------------ +--* LCL_VAR int V01 loc0
[000012] ---X-------- \--* ARR_LENGTH int
[000011] ------------ \--* LCL_VAR ref V02 loc1
------------ BB02 [016..01C), preds={} succs={BB03}
***** BB02
STMT00013 (IL 0x016...0x017)
[000083] --C-G------- * CALL void Stack`1.ThrowForEmptyStack
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
------------ BB03 [01C..040), preds={} succs={BB04}
***** BB03
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG------- * ASG int
[000020] ---XG--N---- +--* FIELD int _version
[000015] ------------ | \--* LCL_VAR ref V00 this
[000019] ---XG------- \--* ADD int
[000017] ---XG------- +--* FIELD int _version
[000016] ------------ | \--* LCL_VAR ref V00 this
[000018] ------------ \--* CNS_INT int 1
***** BB03
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG------- * ASG int
[000024] ---XG--N---- +--* FIELD int _size
[000022] ------------ | \--* LCL_VAR ref V00 this
[000023] ------------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00005 (IL 0x031...0x038)
[000033] -A-XG------- * ASG struct (copy)
[000031] D----------- +--* LCL_VAR struct<RefAsValueType`1, 4> V03 loc2
[000030] ---XG------- \--* OBJ struct<RefAsValueType`1, 4>
[000029] ---XG------- \--* ADDR byref
[000028] ---XG------- \--* INDEX struct
[000026] ------------ +--* LCL_VAR ref V02 loc1
[000027] ------------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00006 (IL 0x039...0x03E)
[000038] -A-X-------- * ASG int
[000037] D------N---- +--* LCL_VAR int V05 tmp0
[000036] #--X-------- \--* IND int
[000035] ------------ \--* LCL_VAR ref V00 this
***** BB03
STMT00007 (IL ???... ???)
[000063] -AC-G------- * ASG int
[000062] D------N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G------- \--* QMARK int
[000051] Q----------- if +--* NE int
[000047] n----------- | +--* IND int
[000046] ------------ | | \--* ADD int
[000044] #----------- | | +--* IND int
[000043] #----------- | | | \--* IND int
[000042] ------------ | | | \--* ADD int
[000040] ------------ | | | +--* LCL_VAR int V05 tmp0
[000041] ------------ | | | \--* CNS_INT int 32
[000045] ------------ | | \--* CNS_INT int 12
[000050] ------------ | \--* CNS_INT int 0
[000060] --C-G------- if \--* COLON int
[000049] --C-G------- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] ------------ arg0 | +--* LCL_VAR int V05 tmp0
[000048] ------------ arg1 | \--* CNS_INT(h) int 0x8A93EB8 token
[000052] n----------- then \--* IND int
[000053] ------------ \--* ADD int
[000054] #----------- +--* IND int
[000055] #----------- | \--* IND int
[000056] ------------ | \--* ADD int
[000057] ------------ | +--* LCL_VAR int V05 tmp0
[000058] ------------ | \--* CNS_INT int 32
[000059] ------------ \--* CNS_INT int 12
***** BB03
STMT00009 (IL ???... ???)
[000069] ------------ * NOP void
------------ BB04 [040..050), preds={} succs={BB05}
***** BB04
STMT00011 (IL 0x040...0x045)
[000077] IA---------- * ASG struct (init)
[000074] D------N---- +--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
[000076] ------------ \--* CNS_INT int 0
***** BB04
STMT00012 (IL ???...0x04B)
[000081] -A-XG------- * ASG struct (copy)
[000079] ---XG------- +--* INDEX struct
[000072] ------------ | +--* LCL_VAR ref V02 loc1
[000073] ------------ | \--* LCL_VAR int V01 loc0
[000078] ------------ \--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
------------ BB05 [050..052) (return), preds={} succs={}
***** BB05
STMT00010 (IL 0x050...0x051)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_FLD ref V03 loc2 [+0]
-------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
**************** Inline Tree
Inlines into 0600029B Stack`1:Pop():RefAsValueType`1:this
[0 IL=0023 TR=000083 060002A0] [FAILED: does not return] Stack`1:ThrowForEmptyStack():this
[1 IL=0057 TR=000034 06003C89] [below ALWAYS_INLINE size] RuntimeHelpers:IsReferenceOrContainsReferences():bool
Budget: initialTime=306, finalTime=292, initialBudget=3060, currentBudget=3060
Budget: initialSize=2000, finalSize=2000
*************** Finishing PHASE Morph - Inlining
Trees before Allocate Objects
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i idxlen
BB02 [0001] 1 1 [016..01C) i
BB03 [0002] 2 1 [01C..040) i idxlen
BB04 [0003] 1 1 [040..050) i idxlen
BB05 [0004] 1 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01
STMT00000 (IL 0x000...0x008)
[000005] -A-XG------- * ASG int
[000004] D------N---- +--* LCL_VAR int V01 loc0
[000003] ---XG------- \--* SUB int
[000001] ---XG------- +--* FIELD int _size
[000000] ------------ | \--* LCL_VAR ref V00 this
[000002] ------------ \--* CNS_INT int 1
***** BB01
STMT00001 (IL 0x009...0x00F)
[000009] -A-XG------- * ASG ref
[000008] D------N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG------- \--* FIELD ref _array
[000006] ------------ \--* LCL_VAR ref V00 this
***** BB01
STMT00002 (IL 0x010...0x014)
[000014] ---X-------- * JTRUE void
[000013] N--X-----U-- \--* LT int
[000010] ------------ +--* LCL_VAR int V01 loc0
[000012] ---X-------- \--* ARR_LENGTH int
[000011] ------------ \--* LCL_VAR ref V02 loc1
------------ BB02 [016..01C), preds={} succs={BB03}
***** BB02
STMT00013 (IL 0x016...0x017)
[000083] --C-G------- * CALL void Stack`1.ThrowForEmptyStack
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
------------ BB03 [01C..040), preds={} succs={BB04}
***** BB03
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG------- * ASG int
[000020] ---XG--N---- +--* FIELD int _version
[000015] ------------ | \--* LCL_VAR ref V00 this
[000019] ---XG------- \--* ADD int
[000017] ---XG------- +--* FIELD int _version
[000016] ------------ | \--* LCL_VAR ref V00 this
[000018] ------------ \--* CNS_INT int 1
***** BB03
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG------- * ASG int
[000024] ---XG--N---- +--* FIELD int _size
[000022] ------------ | \--* LCL_VAR ref V00 this
[000023] ------------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00005 (IL 0x031...0x038)
[000033] -A-XG------- * ASG struct (copy)
[000031] D----------- +--* LCL_VAR struct<RefAsValueType`1, 4> V03 loc2
[000030] ---XG------- \--* OBJ struct<RefAsValueType`1, 4>
[000029] ---XG------- \--* ADDR byref
[000028] ---XG------- \--* INDEX struct
[000026] ------------ +--* LCL_VAR ref V02 loc1
[000027] ------------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00006 (IL 0x039...0x03E)
[000038] -A-X-------- * ASG int
[000037] D------N---- +--* LCL_VAR int V05 tmp0
[000036] #--X-------- \--* IND int
[000035] ------------ \--* LCL_VAR ref V00 this
***** BB03
STMT00007 (IL ???... ???)
[000063] -AC-G------- * ASG int
[000062] D------N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G------- \--* QMARK int
[000051] Q----------- if +--* NE int
[000047] n----------- | +--* IND int
[000046] ------------ | | \--* ADD int
[000044] #----------- | | +--* IND int
[000043] #----------- | | | \--* IND int
[000042] ------------ | | | \--* ADD int
[000040] ------------ | | | +--* LCL_VAR int V05 tmp0
[000041] ------------ | | | \--* CNS_INT int 32
[000045] ------------ | | \--* CNS_INT int 12
[000050] ------------ | \--* CNS_INT int 0
[000060] --C-G------- if \--* COLON int
[000049] --C-G------- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] ------------ arg0 | +--* LCL_VAR int V05 tmp0
[000048] ------------ arg1 | \--* CNS_INT(h) int 0x8A93EB8 token
[000052] n----------- then \--* IND int
[000053] ------------ \--* ADD int
[000054] #----------- +--* IND int
[000055] #----------- | \--* IND int
[000056] ------------ | \--* ADD int
[000057] ------------ | +--* LCL_VAR int V05 tmp0
[000058] ------------ | \--* CNS_INT int 32
[000059] ------------ \--* CNS_INT int 12
***** BB03
STMT00009 (IL ???... ???)
[000069] ------------ * NOP void
------------ BB04 [040..050), preds={} succs={BB05}
***** BB04
STMT00011 (IL 0x040...0x045)
[000077] IA---------- * ASG struct (init)
[000074] D------N---- +--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
[000076] ------------ \--* CNS_INT int 0
***** BB04
STMT00012 (IL ???...0x04B)
[000081] -A-XG------- * ASG struct (copy)
[000079] ---XG------- +--* INDEX struct
[000072] ------------ | +--* LCL_VAR ref V02 loc1
[000073] ------------ | \--* LCL_VAR int V01 loc0
[000078] ------------ \--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
------------ BB05 [050..052) (return), preds={} succs={}
***** BB05
STMT00010 (IL 0x050...0x051)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_FLD ref V03 loc2 [+0]
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Allocate Objects
*** ObjectAllocationPhase: no newobjs in this method; punting
*************** Finishing PHASE Allocate Objects
Trees after Allocate Objects
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i idxlen
BB02 [0001] 1 1 [016..01C) i
BB03 [0002] 2 1 [01C..040) i idxlen
BB04 [0003] 1 1 [040..050) i idxlen
BB05 [0004] 1 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01
STMT00000 (IL 0x000...0x008)
[000005] -A-XG------- * ASG int
[000004] D------N---- +--* LCL_VAR int V01 loc0
[000003] ---XG------- \--* SUB int
[000001] ---XG------- +--* FIELD int _size
[000000] ------------ | \--* LCL_VAR ref V00 this
[000002] ------------ \--* CNS_INT int 1
***** BB01
STMT00001 (IL 0x009...0x00F)
[000009] -A-XG------- * ASG ref
[000008] D------N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG------- \--* FIELD ref _array
[000006] ------------ \--* LCL_VAR ref V00 this
***** BB01
STMT00002 (IL 0x010...0x014)
[000014] ---X-------- * JTRUE void
[000013] N--X-----U-- \--* LT int
[000010] ------------ +--* LCL_VAR int V01 loc0
[000012] ---X-------- \--* ARR_LENGTH int
[000011] ------------ \--* LCL_VAR ref V02 loc1
------------ BB02 [016..01C), preds={} succs={BB03}
***** BB02
STMT00013 (IL 0x016...0x017)
[000083] --C-G------- * CALL void Stack`1.ThrowForEmptyStack
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
------------ BB03 [01C..040), preds={} succs={BB04}
***** BB03
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG------- * ASG int
[000020] ---XG--N---- +--* FIELD int _version
[000015] ------------ | \--* LCL_VAR ref V00 this
[000019] ---XG------- \--* ADD int
[000017] ---XG------- +--* FIELD int _version
[000016] ------------ | \--* LCL_VAR ref V00 this
[000018] ------------ \--* CNS_INT int 1
***** BB03
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG------- * ASG int
[000024] ---XG--N---- +--* FIELD int _size
[000022] ------------ | \--* LCL_VAR ref V00 this
[000023] ------------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00005 (IL 0x031...0x038)
[000033] -A-XG------- * ASG struct (copy)
[000031] D----------- +--* LCL_VAR struct<RefAsValueType`1, 4> V03 loc2
[000030] ---XG------- \--* OBJ struct<RefAsValueType`1, 4>
[000029] ---XG------- \--* ADDR byref
[000028] ---XG------- \--* INDEX struct
[000026] ------------ +--* LCL_VAR ref V02 loc1
[000027] ------------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00006 (IL 0x039...0x03E)
[000038] -A-X-------- * ASG int
[000037] D------N---- +--* LCL_VAR int V05 tmp0
[000036] #--X-------- \--* IND int
[000035] ------------ \--* LCL_VAR ref V00 this
***** BB03
STMT00007 (IL ???... ???)
[000063] -AC-G------- * ASG int
[000062] D------N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G------- \--* QMARK int
[000051] Q----------- if +--* NE int
[000047] n----------- | +--* IND int
[000046] ------------ | | \--* ADD int
[000044] #----------- | | +--* IND int
[000043] #----------- | | | \--* IND int
[000042] ------------ | | | \--* ADD int
[000040] ------------ | | | +--* LCL_VAR int V05 tmp0
[000041] ------------ | | | \--* CNS_INT int 32
[000045] ------------ | | \--* CNS_INT int 12
[000050] ------------ | \--* CNS_INT int 0
[000060] --C-G------- if \--* COLON int
[000049] --C-G------- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] ------------ arg0 | +--* LCL_VAR int V05 tmp0
[000048] ------------ arg1 | \--* CNS_INT(h) int 0x8A93EB8 token
[000052] n----------- then \--* IND int
[000053] ------------ \--* ADD int
[000054] #----------- +--* IND int
[000055] #----------- | \--* IND int
[000056] ------------ | \--* ADD int
[000057] ------------ | +--* LCL_VAR int V05 tmp0
[000058] ------------ | \--* CNS_INT int 32
[000059] ------------ \--* CNS_INT int 12
***** BB03
STMT00009 (IL ???... ???)
[000069] ------------ * NOP void
------------ BB04 [040..050), preds={} succs={BB05}
***** BB04
STMT00011 (IL 0x040...0x045)
[000077] IA---------- * ASG struct (init)
[000074] D------N---- +--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
[000076] ------------ \--* CNS_INT int 0
***** BB04
STMT00012 (IL ???...0x04B)
[000081] -A-XG------- * ASG struct (copy)
[000079] ---XG------- +--* INDEX struct
[000072] ------------ | +--* LCL_VAR ref V02 loc1
[000073] ------------ | \--* LCL_VAR int V01 loc0
[000078] ------------ \--* LCL_VAR struct<RefAsValueType`1, 4> V04 loc3
------------ BB05 [050..052) (return), preds={} succs={}
***** BB05
STMT00010 (IL 0x050...0x051)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_FLD ref V03 loc2 [+0]
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i idxlen
BB02 [0001] 1 1 [016..01C) i
BB03 [0002] 2 1 [01C..040) i idxlen
BB04 [0003] 1 1 [040..050) i idxlen
BB05 [0004] 1 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try
*************** Starting PHASE Remove empty finally
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally
*************** Starting PHASE Merge callfinally chains
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains
*************** Starting PHASE Clone finally
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally
*************** Starting PHASE Compute preds
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i idxlen
BB02 [0001] 1 1 [016..01C) i
BB03 [0002] 2 1 [01C..040) i idxlen
BB04 [0003] 1 1 [040..050) i idxlen
BB05 [0004] 1 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
New BlockSet epoch 2, # of blocks (including unused BB00): 6, bitset array size: 1 (short)
*************** In fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i idxlen
BB02 [0001] 1 1 [016..01C) i
BB03 [0002] 2 1 [01C..040) i idxlen
BB04 [0003] 1 1 [040..050) i idxlen
BB05 [0004] 1 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 1 [016..01C) i
BB03 [0002] 2 BB01,BB02 1 [01C..040) i label target idxlen
BB04 [0003] 1 BB03 1 [040..050) i idxlen
BB05 [0004] 1 BB04 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Compute preds
*************** Starting PHASE Update flow graph early pass
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 1 [016..01C) i
BB03 [0002] 2 BB01,BB02 1 [01C..040) i label target idxlen
BB04 [0003] 1 BB03 1 [040..050) i idxlen
BB05 [0004] 1 BB04 1 [050..052) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
Compacting blocks BB03 and BB04:
*************** In fgDebugCheckBBlist
Compacting blocks BB03 and BB05:
*************** In fgDebugCheckBBlist
After updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 1 [016..01C) i
BB03 [0002] 2 BB01,BB02 1 [01C..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Update flow graph early pass
*************** Starting PHASE Morph - Promote Structs
*************** In fgPromoteStructs()
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 int
; V02 loc1 ref class-hnd
; V03 loc2 struct ( 4)
; V04 loc3 struct ( 4) ld-addr-op
; V05 tmp0 int "impRuntimeLookup slot"
; V06 tmp1 int "spilling Runtime Lookup tree"
Promoting struct local V03 (RefAsValueType`1):
lvaGrabTemp returning 7 (V07 tmp2) (a long lifetime temp) called for field V03.Value (fldOffset=0x0).
Promoting struct local V04 (RefAsValueType`1):
lvaGrabTemp returning 8 (V08 tmp3) (a long lifetime temp) called for field V04.Value (fldOffset=0x0).
lvaTable after fgPromoteStructs
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 int
; V02 loc1 ref class-hnd
; V03 loc2 struct ( 4)
; V04 loc3 struct ( 4) ld-addr-op
; V05 tmp0 int "impRuntimeLookup slot"
; V06 tmp1 int "spilling Runtime Lookup tree"
; V07 tmp2 ref V03.Value(offs=0x00) P-INDEP "field V03.Value (fldOffset=0x0)"
; V08 tmp3 ref V04.Value(offs=0x00) P-INDEP "field V04.Value (fldOffset=0x0)"
*************** Finishing PHASE Morph - Promote Structs
*************** Starting PHASE Morph - Structs/AddrExp
*************** In fgMarkAddressExposedLocals()
LocalAddressVisitor visiting statement:
STMT00000 (IL 0x000...0x008)
[000005] -A-XG------- * ASG int
[000004] D------N---- +--* LCL_VAR int V01 loc0
[000003] ---XG------- \--* SUB int
[000001] ---XG------- +--* FIELD int _size
[000000] ------------ | \--* LCL_VAR ref V00 this
[000002] ------------ \--* CNS_INT int 1
LocalAddressVisitor visiting statement:
STMT00001 (IL 0x009...0x00F)
[000009] -A-XG------- * ASG ref
[000008] D------N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG------- \--* FIELD ref _array
[000006] ------------ \--* LCL_VAR ref V00 this
LocalAddressVisitor visiting statement:
STMT00002 (IL 0x010...0x014)
[000014] ---X-------- * JTRUE void
[000013] N--X-----U-- \--* LT int
[000010] ------------ +--* LCL_VAR int V01 loc0
[000012] ---X-------- \--* ARR_LENGTH int
[000011] ------------ \--* LCL_VAR ref V02 loc1
LocalAddressVisitor visiting statement:
STMT00013 (IL 0x016...0x017)
[000083] --C-G------- * CALL void Stack`1.ThrowForEmptyStack
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
LocalAddressVisitor visiting statement:
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG------- * ASG int
[000020] ---XG--N---- +--* FIELD int _version
[000015] ------------ | \--* LCL_VAR ref V00 this
[000019] ---XG------- \--* ADD int
[000017] ---XG------- +--* FIELD int _version
[000016] ------------ | \--* LCL_VAR ref V00 this
[000018] ------------ \--* CNS_INT int 1
LocalAddressVisitor visiting statement:
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG------- * ASG int
[000024] ---XG--N---- +--* FIELD int _size
[000022] ------------ | \--* LCL_VAR ref V00 this
[000023] ------------ \--* LCL_VAR int V01 loc0
LocalAddressVisitor visiting statement:
STMT00005 (IL 0x031...0x038)
[000033] -A-XG------- * ASG struct (copy)
[000031] D----------- +--* LCL_VAR struct<RefAsValueType`1, 4>(P) V03 loc2
+--* ref V03.Value (offs=0x00) -> V07 tmp2
[000030] ---XG------- \--* OBJ struct<RefAsValueType`1, 4>
[000029] ---XG------- \--* ADDR byref
[000028] ---XG------- \--* INDEX struct
[000026] ------------ +--* LCL_VAR ref V02 loc1
[000027] ------------ \--* LCL_VAR int V01 loc0
LocalAddressVisitor visiting statement:
STMT00006 (IL 0x039...0x03E)
[000038] -A-X-------- * ASG int
[000037] D------N---- +--* LCL_VAR int V05 tmp0
[000036] #--X-------- \--* IND int
[000035] ------------ \--* LCL_VAR ref V00 this
LocalAddressVisitor visiting statement:
STMT00007 (IL ???... ???)
[000063] -AC-G------- * ASG int
[000062] D------N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G------- \--* QMARK int
[000051] Q----------- if +--* NE int
[000047] n----------- | +--* IND int
[000046] ------------ | | \--* ADD int
[000044] #----------- | | +--* IND int
[000043] #----------- | | | \--* IND int
[000042] ------------ | | | \--* ADD int
[000040] ------------ | | | +--* LCL_VAR int V05 tmp0
[000041] ------------ | | | \--* CNS_INT int 32
[000045] ------------ | | \--* CNS_INT int 12
[000050] ------------ | \--* CNS_INT int 0
[000060] --C-G------- if \--* COLON int
[000049] --C-G------- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] ------------ arg0 | +--* LCL_VAR int V05 tmp0
[000048] ------------ arg1 | \--* CNS_INT(h) int 0x8A93EB8 token
[000052] n----------- then \--* IND int
[000053] ------------ \--* ADD int
[000054] #----------- +--* IND int
[000055] #----------- | \--* IND int
[000056] ------------ | \--* ADD int
[000057] ------------ | +--* LCL_VAR int V05 tmp0
[000058] ------------ | \--* CNS_INT int 32
[000059] ------------ \--* CNS_INT int 12
LocalAddressVisitor visiting statement:
STMT00009 (IL ???... ???)
[000069] ------------ * NOP void
LocalAddressVisitor visiting statement:
STMT00011 (IL 0x040...0x045)
[000077] IA---------- * ASG struct (init)
[000074] D------N---- +--* LCL_VAR struct<RefAsValueType`1, 4>(P) V04 loc3
+--* ref V04.Value (offs=0x00) -> V08 tmp3
[000076] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00012 (IL ???...0x04B)
[000081] -A-XG------- * ASG struct (copy)
[000079] ---XG------- +--* INDEX struct
[000072] ------------ | +--* LCL_VAR ref V02 loc1
[000073] ------------ | \--* LCL_VAR int V01 loc0
[000078] ------------ \--* LCL_VAR struct<RefAsValueType`1, 4>(P) V04 loc3
\--* ref V04.Value (offs=0x00) -> V08 tmp3
LocalAddressVisitor visiting statement:
STMT00010 (IL 0x050...0x051)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_FLD ref V03 loc2 [+0]
\--* ref V03.Value (offs=0x00) -> V07 tmp2
Replacing the GT_LCL_FLD in promoted struct with local var V07
LocalAddressVisitor modified statement:
STMT00010 (IL 0x050...0x051)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_VAR ref V07 tmp2
*************** Finishing PHASE Morph - Structs/AddrExp
*************** Starting PHASE Morph - ByRefs
*************** Finishing PHASE Morph - ByRefs
*************** Starting PHASE Morph - Global
*************** In fgMorphBlocks()
Morphing BB01 of 'Stack`1:Pop():RefAsValueType`1:this'
fgMorphTree BB01, STMT00000 (before)
[000005] -A-XG------- * ASG int
[000004] D------N---- +--* LCL_VAR int V01 loc0
[000003] ---XG------- \--* SUB int
[000001] ---XG------- +--* FIELD int _size
[000000] ------------ | \--* LCL_VAR ref V00 this
[000002] ------------ \--* CNS_INT int 1
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000001] ---XG------- * IND int
[000088] -----+------ \--* ADD byref
[000000] -----+------ +--* LCL_VAR ref V00 this
[000087] -----+------ \--* CNS_INT int 8 field offset Fseq[_size]
GenTreeNode creates assertion:
[000001] ---XG------- * IND int
In BB01 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001
fgMorphTree BB01, STMT00000 (after)
[000005] -A-XG+------ * ASG int
[000004] D----+-N---- +--* LCL_VAR int V01 loc0
[000003] ---XG+------ \--* ADD int
[000001] ---XG+------ +--* IND int
[000088] -----+------ | \--* ADD byref
[000000] -----+------ | +--* LCL_VAR ref V00 this
[000087] -----+------ | \--* CNS_INT int 8 field offset Fseq[_size]
[000002] -----+------ \--* CNS_INT int -1
fgMorphTree BB01, STMT00001 (before)
[000009] -A-XG------- * ASG ref
[000008] D------N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG------- \--* FIELD ref _array
[000006] ------------ \--* LCL_VAR ref V00 this
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000007] ---XG------- * IND ref
[000090] -----+------ \--* ADD byref
[000006] -----+------ +--* LCL_VAR ref V00 this
[000089] -----+------ \--* CNS_INT int 4 field offset Fseq[_array]
fgMorphTree BB01, STMT00001 (after)
[000009] -A-XG+------ * ASG ref
[000008] D----+-N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG+------ \--* IND ref
[000090] -----+------ \--* ADD byref
[000006] -----+------ +--* LCL_VAR ref V00 this
[000089] -----+------ \--* CNS_INT int 4 field offset Fseq[_array]
fgMorphTree BB01, STMT00002 (before)
[000014] ---X-------- * JTRUE void
[000013] N--X-----U-- \--* LT int
[000010] ------------ +--* LCL_VAR int V01 loc0
[000012] ---X-------- \--* ARR_LENGTH int
[000011] ------------ \--* LCL_VAR ref V02 loc1
GenTreeNode creates assertion:
[000012] ---X-------- * ARR_LENGTH int
In BB01 New Local Constant Assertion: V02 != null index=#02, mask=0000000000000002
Morphing BB02 of 'Stack`1:Pop():RefAsValueType`1:this'
fgMorphTree BB02, STMT00013 (before)
[000083] --C-G------- * CALL void Stack`1.ThrowForEmptyStack
[000082] ------------ this in ecx \--* LCL_VAR ref V00 this
Initializing arg info for 83.CALL:
ArgTable for 83.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 82.LCL_VAR ref, 1 reg: ecx, align=1]
Morphing args for 83.CALL:
Sorting the arguments:
Deferred argument ('ecx'):
[000082] -----+------ * LCL_VAR ref V00 this
Replaced with placeholder node:
[000091] ----------L- * ARGPLACE ref
Shuffled argument table: ecx
ArgTable for 83.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 82.LCL_VAR ref, 1 reg: ecx, align=1, lateArgInx=0, processed]
fgMorphTree BB02, STMT00013 (after)
[000083] --CXG+------ * CALL void Stack`1.ThrowForEmptyStack
[000082] -----+------ this in ecx \--* LCL_VAR ref V00 this
Converting BB02 to BBJ_THROW
Morphing BB03 of 'Stack`1:Pop():RefAsValueType`1:this'
fgMorphTree BB03, STMT00003 (before)
[000021] -A-XG------- * ASG int
[000020] ---XG--N---- +--* FIELD int _version
[000015] ------------ | \--* LCL_VAR ref V00 this
[000019] ---XG------- \--* ADD int
[000017] ---XG------- +--* FIELD int _version
[000016] ------------ | \--* LCL_VAR ref V00 this
[000018] ------------ \--* CNS_INT int 1
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000020] ---XG--N---- * IND int
[000093] -----+------ \--* ADD byref
[000015] -----+------ +--* LCL_VAR ref V00 this
[000092] -----+------ \--* CNS_INT int 12 field offset Fseq[_version]
GenTreeNode creates assertion:
[000020] ---XG--N---- * IND int
In BB03 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000017] ---XG------- * IND int
[000095] -----+------ \--* ADD byref
[000016] -----+------ +--* LCL_VAR ref V00 this
[000094] -----+------ \--* CNS_INT int 12 field offset Fseq[_version]
fgMorphTree BB03, STMT00003 (after)
[000021] -A-XG+------ * ASG int
[000020] ---XG+-N---- +--* IND int
[000093] -----+------ | \--* ADD byref
[000015] -----+------ | +--* LCL_VAR ref V00 this
[000092] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000019] ---XG+------ \--* ADD int
[000017] ---XG+------ +--* IND int
[000095] -----+------ | \--* ADD byref
[000016] -----+------ | +--* LCL_VAR ref V00 this
[000094] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000018] -----+------ \--* CNS_INT int 1
fgMorphTree BB03, STMT00004 (before)
[000025] -A-XG------- * ASG int
[000024] ---XG--N---- +--* FIELD int _size
[000022] ------------ | \--* LCL_VAR ref V00 this
[000023] ------------ \--* LCL_VAR int V01 loc0
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000024] ---XG--N---- * IND int
[000097] -----+------ \--* ADD byref
[000022] -----+------ +--* LCL_VAR ref V00 this
[000096] -----+------ \--* CNS_INT int 8 field offset Fseq[_size]
fgMorphTree BB03, STMT00004 (after)
[000025] -A-XG+------ * ASG int
[000024] ---XG+-N---- +--* IND int
[000097] -----+------ | \--* ADD byref
[000022] -----+------ | +--* LCL_VAR ref V00 this
[000096] -----+------ | \--* CNS_INT int 8 field offset Fseq[_size]
[000023] -----+------ \--* LCL_VAR int V01 loc0
fgMorphTree BB03, STMT00005 (before)
[000033] -A-XG------- * ASG struct (copy)
[000031] D----------- +--* LCL_VAR struct<RefAsValueType`1, 4>(P) V03 loc2
+--* ref V03.Value (offs=0x00) -> V07 tmp2
[000030] ---XG------- \--* OBJ struct<RefAsValueType`1, 4>
[000029] ---XG------- \--* ADDR byref
[000028] ---XG------- \--* INDEX struct
[000026] ------------ +--* LCL_VAR ref V02 loc1
[000027] ------------ \--* LCL_VAR int V01 loc0
GenTreeNode creates assertion:
[000100] ---X-------- * ARR_LENGTH int
In BB03 New Local Constant Assertion: V02 != null index=#02, mask=0000000000000002
fgMorphCopyBlock:block assignment to morph:
[000033] -A-XG------- * ASG struct (copy)
[000031] D----+-N---- +--* LCL_VAR struct<RefAsValueType`1, 4>(P) V03 loc2
+--* ref V03.Value (offs=0x00) -> V07 tmp2
[000030] ---XG+------ \--* OBJ struct<RefAsValueType`1, 4>
[000107] ---XG+------ \--* COMMA byref
[000101] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void
[000027] -----+------ | +--* LCL_VAR int V01 loc0
[000100] ---X-+------ | \--* ARR_LENGTH int
[000026] -----+------ | \--* LCL_VAR ref V02 loc1
[000108] ----G------- \--* ADDR byref
[000028] a---G+-N---- \--* IND struct
[000106] -----+------ \--* ADD byref
[000098] -----+------ +--* LCL_VAR ref V02 loc1
[000105] -----+------ \--* ADD int
[000103] -----+------ +--* LSH int
[000099] i----+------ | +--* LCL_VAR int V01 loc0
[000102] -----+-N---- | \--* CNS_INT int 2
[000104] -----+------ \--* CNS_INT int 8 Fseq[#FirstElem]
(destDoFldAsg=true) using field by field assignments.
fgAddFieldSeqForZeroOffset for Fseq[Value]
addr (Before)
[000110] ---XG------- COMMA byref
(After)
[000110] ---XG------- COMMA byref Zero Fseq[Value]
fgMorphCopyBlock (after):
[000125] -A-XG+------ * ASG ref
[000109] D------N---- +--* LCL_VAR ref V07 tmp2
[000124] ---XG------- \--* IND ref
[000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
[000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
[000113] ------------ | +--* LCL_VAR int V01 loc0
[000111] ---X-------- | \--* ARR_LENGTH int
[000112] ------------ | \--* LCL_VAR ref V02 loc1
[000115] ----G------- \--* ADDR byref
[000116] a---G--N---- \--* IND struct
[000117] ------------ \--* ADD byref
[000118] ------------ +--* LCL_VAR ref V02 loc1
[000119] ------------ \--* ADD int
[000120] ------------ +--* LSH int
[000121] i----------- | +--* LCL_VAR int V01 loc0
[000122] -------N---- | \--* CNS_INT int 2
[000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
fgMorphTree BB03, STMT00005 (after)
[000125] -A-XG+------ * ASG ref
[000109] D------N---- +--* LCL_VAR ref V07 tmp2
[000124] ---XG------- \--* IND ref
[000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
[000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
[000113] ------------ | +--* LCL_VAR int V01 loc0
[000111] ---X-------- | \--* ARR_LENGTH int
[000112] ------------ | \--* LCL_VAR ref V02 loc1
[000115] ----G------- \--* ADDR byref
[000116] a---G--N---- \--* IND struct
[000117] ------------ \--* ADD byref
[000118] ------------ +--* LCL_VAR ref V02 loc1
[000119] ------------ \--* ADD int
[000120] ------------ +--* LSH int
[000121] i----------- | +--* LCL_VAR int V01 loc0
[000122] -------N---- | \--* CNS_INT int 2
[000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
fgMorphTree BB03, STMT00006 (before)
[000038] -A-X-------- * ASG int
[000037] D------N---- +--* LCL_VAR int V05 tmp0
[000036] #--X-------- \--* IND int
[000035] ------------ \--* LCL_VAR ref V00 this
Non-null prop for index #01 in BB03:
[000036] #--X-------- * IND int
fgMorphTree BB03, STMT00007 (before)
[000063] -AC-G------- * ASG int
[000062] D------N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G------- \--* QMARK int
[000051] Q----------- if +--* NE int
[000047] n----------- | +--* IND int
[000046] ------------ | | \--* ADD int
[000044] #----------- | | +--* IND int
[000043] #----------- | | | \--* IND int
[000042] ------------ | | | \--* ADD int
[000040] ------------ | | | +--* LCL_VAR int V05 tmp0
[000041] ------------ | | | \--* CNS_INT int 32
[000045] ------------ | | \--* CNS_INT int 12
[000050] ------------ | \--* CNS_INT int 0
[000060] --C-G------- if \--* COLON int
[000049] --C-G------- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] ------------ arg0 | +--* LCL_VAR int V05 tmp0
[000048] ------------ arg1 | \--* CNS_INT(h) int 0x8A93EB8 token
[000052] n----------- then \--* IND int
[000053] ------------ \--* ADD int
[000054] #----------- +--* IND int
[000055] #----------- | \--* IND int
[000056] ------------ | \--* ADD int
[000057] ------------ | +--* LCL_VAR int V05 tmp0
[000058] ------------ | \--* CNS_INT int 32
[000059] ------------ \--* CNS_INT int 12
Initializing arg info for 49.CALL:
ArgTable for 49.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 39.LCL_VAR int, 1 reg: ecx, align=1]
fgArgTabEntry[arg 1 48.CNS_INT int, 1 reg: edx, align=1]
Morphing args for 49.CALL:
Sorting the arguments:
Deferred argument ('ecx'):
[000039] -----+------ * LCL_VAR int V05 tmp0
Replaced with placeholder node:
[000126] ----------L- * ARGPLACE int
Deferred argument ('edx'):
[000048] -----+------ * CNS_INT(h) int 0x8A93EB8 token
Replaced with placeholder node:
[000127] ----------L- * ARGPLACE int
Shuffled argument table: ecx edx
ArgTable for 49.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 39.LCL_VAR int, 1 reg: ecx, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 48.CNS_INT int, 1 reg: edx, align=1, lateArgInx=1, processed]
fgMorphTree BB03, STMT00007 (after)
[000063] -AC-G+------ * ASG int
[000062] D----+-N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G+------ \--* QMARK int
[000051] J----+-N---- if +--* NE int
[000047] n----+------ | +--* IND int
[000046] -----+------ | | \--* ADD int
[000044] #----+------ | | +--* IND int
[000043] #----+------ | | | \--* IND int
[000042] -----+------ | | | \--* ADD int
[000040] -----+------ | | | +--* LCL_VAR int V05 tmp0
[000041] -----+------ | | | \--* CNS_INT int 32
[000045] -----+------ | | \--* CNS_INT int 12
[000050] -----+------ | \--* CNS_INT int 0
[000060] --C-G+?----- if \--* COLON int
[000049] --C-G+?----- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] -----+?----- arg0 in ecx | +--* LCL_VAR int V05 tmp0
[000048] -----+?----- arg1 in edx | \--* CNS_INT(h) int 0x8A93EB8 token
[000052] n----+?----- then \--* IND int
[000053] -----+?----- \--* ADD int
[000054] #----+?----- +--* IND int
[000055] #----+?----- | \--* IND int
[000056] -----+?----- | \--* ADD int
[000057] -----+?----- | +--* LCL_VAR int V05 tmp0
[000058] -----+?----- | \--* CNS_INT int 32
[000059] -----+?----- \--* CNS_INT int 12
fgMorphTree BB03, STMT00009 (before)
[000069] ------------ * NOP void
fgMorphTree BB03, STMT00011 (before)
[000077] IA---------- * ASG struct (init)
[000074] D------N---- +--* LCL_VAR struct<RefAsValueType`1, 4>(P) V04 loc3
+--* ref V04.Value (offs=0x00) -> V08 tmp3
[000076] ------------ \--* CNS_INT int 0
fgMorphInitBlock: using field by field initialization.
GenTreeNode creates assertion:
[000130] -A---------- * ASG ref
In BB03 New Local Constant Assertion: V08 == null index=#03, mask=0000000000000004
fgMorphInitBlock (after):
[000130] -A---+------ * ASG ref
[000128] D------N---- +--* LCL_VAR ref V08 tmp3
[000129] ------------ \--* CNS_INT ref null
The assignment [000130] using V08 removes: Constant Assertion: V08 == null
GenTreeNode creates assertion:
[000130] -A---+------ * ASG ref
In BB03 New Local Constant Assertion: V08 == null index=#03, mask=0000000000000004
fgMorphTree BB03, STMT00011 (after)
[000130] -A---+------ * ASG ref
[000128] D------N---- +--* LCL_VAR ref V08 tmp3
[000129] ------------ \--* CNS_INT ref null
fgMorphTree BB03, STMT00012 (before)
[000081] -A-XG------- * ASG struct (copy)
[000079] ---XG------- +--* INDEX struct
[000072] ------------ | +--* LCL_VAR ref V02 loc1
[000073] ------------ | \--* LCL_VAR int V01 loc0
[000078] ------------ \--* LCL_VAR struct<RefAsValueType`1, 4>(P) V04 loc3
\--* ref V04.Value (offs=0x00) -> V08 tmp3
fgMorphCopyBlock:block assignment to morph:
[000081] -A-XG------- * ASG struct (copy)
[000142] ---XG+------ +--* OBJ struct<RefAsValueType`1, 4>
[000140] ---XG+------ | \--* COMMA byref
[000134] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void
[000073] -----+------ | | +--* LCL_VAR int V01 loc0
[000133] ---X-+------ | | \--* ARR_LENGTH int
[000072] -----+------ | | \--* LCL_VAR ref V02 loc1
[000141] ----G+------ | \--* ADDR byref
[000079] a---G+------ | \--* IND struct
[000139] -----+------ | \--* ADD byref
[000131] -----+------ | +--* LCL_VAR ref V02 loc1
[000138] -----+------ | \--* ADD int
[000136] -----+------ | +--* LSH int
[000132] i----+------ | | +--* LCL_VAR int V01 loc0
[000135] -----+-N---- | | \--* CNS_INT int 2
[000137] -----+------ | \--* CNS_INT int 8 Fseq[#FirstElem]
[000078] -----+------ \--* LCL_VAR struct<RefAsValueType`1, 4>(P) V04 loc3
\--* ref V04.Value (offs=0x00) -> V08 tmp3
(srcDoFldAsg=true) using field by field assignments.
fgAddFieldSeqForZeroOffset for Fseq[Value]
addr (Before)
[000143] ---XG------- COMMA byref
(After)
[000143] ---XG------- COMMA byref Zero Fseq[Value]
fgMorphCopyBlock (after):
[000159] -A-XG+------ * ASG ref
[000157] *--XG--N---- +--* IND ref
[000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
[000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000146] ------------ | | +--* LCL_VAR int V01 loc0
[000144] ---X-------- | | \--* ARR_LENGTH int
[000145] ------------ | | \--* LCL_VAR ref V02 loc1
[000148] ----G------- | \--* ADDR byref
[000149] a---G------- | \--* IND struct
[000150] ------------ | \--* ADD byref
[000151] ------------ | +--* LCL_VAR ref V02 loc1
[000152] ------------ | \--* ADD int
[000153] ------------ | +--* LSH int
[000154] i----------- | | +--* LCL_VAR int V01 loc0
[000155] -------N---- | | \--* CNS_INT int 2
[000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
[000158] ------------ \--* LCL_VAR ref V08 tmp3
fgMorphTree BB03, STMT00012 (after)
[000159] -A-XG+------ * ASG ref
[000157] *--XG--N---- +--* IND ref
[000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
[000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000146] ------------ | | +--* LCL_VAR int V01 loc0
[000144] ---X-------- | | \--* ARR_LENGTH int
[000145] ------------ | | \--* LCL_VAR ref V02 loc1
[000148] ----G------- | \--* ADDR byref
[000149] a---G------- | \--* IND struct
[000150] ------------ | \--* ADD byref
[000151] ------------ | +--* LCL_VAR ref V02 loc1
[000152] ------------ | \--* ADD int
[000153] ------------ | +--* LSH int
[000154] i----------- | | +--* LCL_VAR int V01 loc0
[000155] -------N---- | | \--* CNS_INT int 2
[000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
[000158] ------------ \--* LCL_VAR ref V08 tmp3
fgMorphTree BB03, STMT00010 (before)
[000071] ------------ * RETURN ref
[000070] ------------ \--* LCL_VAR ref V07 tmp2
Expanding top-level qmark in BB03 (before)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB03 [0002] 1 BB01 1 [01C..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB03 [01C..052) (return), preds={BB01} succs={}
***** BB03
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG+------ * ASG int
[000020] ---XG+-N---- +--* IND int
[000093] -----+------ | \--* ADD byref
[000015] -----+------ | +--* LCL_VAR ref V00 this
[000092] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000019] ---XG+------ \--* ADD int
[000017] ---XG+------ +--* IND int
[000095] -----+------ | \--* ADD byref
[000016] -----+------ | +--* LCL_VAR ref V00 this
[000094] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000018] -----+------ \--* CNS_INT int 1
***** BB03
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG+------ * ASG int
[000024] ---XG+-N---- +--* IND int
[000097] -----+------ | \--* ADD byref
[000022] -----+------ | +--* LCL_VAR ref V00 this
[000096] -----+------ | \--* CNS_INT int 8 field offset Fseq[_size]
[000023] -----+------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00005 (IL 0x031...0x038)
[000125] -A-XG+------ * ASG ref
[000109] D------N---- +--* LCL_VAR ref V07 tmp2
[000124] ---XG------- \--* IND ref
[000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
[000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
[000113] ------------ | +--* LCL_VAR int V01 loc0
[000111] ---X-------- | \--* ARR_LENGTH int
[000112] ------------ | \--* LCL_VAR ref V02 loc1
[000115] ----G------- \--* ADDR byref
[000116] a---G--N---- \--* IND struct
[000117] ------------ \--* ADD byref
[000118] ------------ +--* LCL_VAR ref V02 loc1
[000119] ------------ \--* ADD int
[000120] ------------ +--* LSH int
[000121] i----------- | +--* LCL_VAR int V01 loc0
[000122] -------N---- | \--* CNS_INT int 2
[000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
***** BB03
STMT00006 (IL 0x039...0x03E)
[000038] -A---+------ * ASG int
[000037] D----+-N---- +--* LCL_VAR int V05 tmp0
[000036] #----+------ \--* IND int
[000035] -----+------ \--* LCL_VAR ref V00 this
***** BB03
STMT00007 (IL ???... ???)
[000063] -AC-G+------ * ASG int
[000062] D----+-N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G+------ \--* QMARK int
[000051] J----+-N---- if +--* NE int
[000047] n----+------ | +--* IND int
[000046] -----+------ | | \--* ADD int
[000044] #----+------ | | +--* IND int
[000043] #----+------ | | | \--* IND int
[000042] -----+------ | | | \--* ADD int
[000040] -----+------ | | | +--* LCL_VAR int V05 tmp0
[000041] -----+------ | | | \--* CNS_INT int 32
[000045] -----+------ | | \--* CNS_INT int 12
[000050] -----+------ | \--* CNS_INT int 0
[000060] --C-G+?----- if \--* COLON int
[000049] --C-G+?----- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] -----+?----- arg0 in ecx | +--* LCL_VAR int V05 tmp0
[000048] -----+?----- arg1 in edx | \--* CNS_INT(h) int 0x8A93EB8 token
[000052] n----+?----- then \--* IND int
[000053] -----+?----- \--* ADD int
[000054] #----+?----- +--* IND int
[000055] #----+?----- | \--* IND int
[000056] -----+?----- | \--* ADD int
[000057] -----+?----- | +--* LCL_VAR int V05 tmp0
[000058] -----+?----- | \--* CNS_INT int 32
[000059] -----+?----- \--* CNS_INT int 12
***** BB03
STMT00011 (IL 0x040...0x045)
[000130] -A---+------ * ASG ref
[000128] D------N---- +--* LCL_VAR ref V08 tmp3
[000129] ------------ \--* CNS_INT ref null
***** BB03
STMT00012 (IL ???...0x04B)
[000159] -A-XG+------ * ASG ref
[000157] *--XG--N---- +--* IND ref
[000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
[000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000146] ------------ | | +--* LCL_VAR int V01 loc0
[000144] ---X-------- | | \--* ARR_LENGTH int
[000145] ------------ | | \--* LCL_VAR ref V02 loc1
[000148] ----G------- | \--* ADDR byref
[000149] a---G------- | \--* IND struct
[000150] ------------ | \--* ADD byref
[000151] ------------ | +--* LCL_VAR ref V02 loc1
[000152] ------------ | \--* ADD int
[000153] ------------ | +--* LSH int
[000154] i----------- | | +--* LCL_VAR int V01 loc0
[000155] -------N---- | | \--* CNS_INT int 2
[000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
[000158] ------------ \--* LCL_VAR ref V08 tmp3
***** BB03
STMT00010 (IL 0x050...0x051)
[000071] -----+------ * RETURN ref
[000070] -----+------ \--* LCL_VAR ref V07 tmp2
-------------------------------------------------------------------------------------------------------------------
New Basic Block BB06 [0006] created.
New Basic Block BB07 [0007] created.
New Basic Block BB08 [0008] created.
New Basic Block BB09 [0009] created.
Removing statement STMT00007 (IL ???... ???)
[000063] -AC-G+------ * ASG int
[000062] D----+-N---- +--* LCL_VAR int V06 tmp1
[000061] --C-G+------ \--* QMARK int
[000051] J----+-N---- if +--* EQ int
[000047] n----+------ | +--* IND int
[000046] -----+------ | | \--* ADD int
[000044] #----+------ | | +--* IND int
[000043] #----+------ | | | \--* IND int
[000042] -----+------ | | | \--* ADD int
[000040] -----+------ | | | +--* LCL_VAR int V05 tmp0
[000041] -----+------ | | | \--* CNS_INT int 32
[000045] -----+------ | | \--* CNS_INT int 12
[000050] -----+------ | \--* CNS_INT int 0
[000060] --C-G+?----- if \--* COLON int
[000049] --C-G+?----- else +--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] -----+?----- arg0 in ecx | +--* LCL_VAR int V05 tmp0
[000048] -----+?----- arg1 in edx | \--* CNS_INT(h) int 0x8A93EB8 token
[000052] n----+?----- then \--* IND int
[000053] -----+?----- \--* ADD int
[000054] #----+?----- +--* IND int
[000055] #----+?----- | \--* IND int
[000056] -----+?----- | \--* ADD int
[000057] -----+?----- | +--* LCL_VAR int V05 tmp0
[000058] -----+?----- | \--* CNS_INT int 32
[000059] -----+?----- \--* CNS_INT int 12
in BB03 as useless:
Expanding top-level qmark in BB03 (after)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB03 [0002] 1 BB01 1 [01C..040) i label target idxlen
BB07 [0007] 1 BB03 1 [???..???)-> BB08 ( cond ) i
BB09 [0009] 1 BB07 0.50 [???..???)-> BB06 (always) i
BB08 [0008] 1 BB07 0.50 [???..???) i label target
BB06 [0006] 2 BB08,BB09 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB03 [01C..040), preds={BB01} succs={BB07}
***** BB03
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG+------ * ASG int
[000020] ---XG+-N---- +--* IND int
[000093] -----+------ | \--* ADD byref
[000015] -----+------ | +--* LCL_VAR ref V00 this
[000092] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000019] ---XG+------ \--* ADD int
[000017] ---XG+------ +--* IND int
[000095] -----+------ | \--* ADD byref
[000016] -----+------ | +--* LCL_VAR ref V00 this
[000094] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000018] -----+------ \--* CNS_INT int 1
***** BB03
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG+------ * ASG int
[000024] ---XG+-N---- +--* IND int
[000097] -----+------ | \--* ADD byref
[000022] -----+------ | +--* LCL_VAR ref V00 this
[000096] -----+------ | \--* CNS_INT int 8 field offset Fseq[_size]
[000023] -----+------ \--* LCL_VAR int V01 loc0
***** BB03
STMT00005 (IL 0x031...0x038)
[000125] -A-XG+------ * ASG ref
[000109] D------N---- +--* LCL_VAR ref V07 tmp2
[000124] ---XG------- \--* IND ref
[000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
[000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
[000113] ------------ | +--* LCL_VAR int V01 loc0
[000111] ---X-------- | \--* ARR_LENGTH int
[000112] ------------ | \--* LCL_VAR ref V02 loc1
[000115] ----G------- \--* ADDR byref
[000116] a---G--N---- \--* IND struct
[000117] ------------ \--* ADD byref
[000118] ------------ +--* LCL_VAR ref V02 loc1
[000119] ------------ \--* ADD int
[000120] ------------ +--* LSH int
[000121] i----------- | +--* LCL_VAR int V01 loc0
[000122] -------N---- | \--* CNS_INT int 2
[000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
***** BB03
STMT00006 (IL 0x039...0x03E)
[000038] -A---+------ * ASG int
[000037] D----+-N---- +--* LCL_VAR int V05 tmp0
[000036] #----+------ \--* IND int
[000035] -----+------ \--* LCL_VAR ref V00 this
------------ BB07 [???..???) -> BB08 (cond), preds={BB03} succs={BB09,BB08}
***** BB07
STMT00014 (IL ???... ???)
[000160] ------------ * JTRUE void
[000051] J----+-N---- \--* EQ int
[000047] n----+------ +--* IND int
[000046] -----+------ | \--* ADD int
[000044] #----+------ | +--* IND int
[000043] #----+------ | | \--* IND int
[000042] -----+------ | | \--* ADD int
[000040] -----+------ | | +--* LCL_VAR int V05 tmp0
[000041] -----+------ | | \--* CNS_INT int 32
[000045] -----+------ | \--* CNS_INT int 12
[000050] -----+------ \--* CNS_INT int 0
------------ BB09 [???..???) -> BB06 (always), preds={BB07} succs={BB06}
***** BB09
STMT00015 (IL ???... ???)
[000162] -A---------- * ASG int
[000161] D------N---- +--* LCL_VAR int V06 tmp1
[000052] n----+?----- \--* IND int
[000053] -----+?----- \--* ADD int
[000054] #----+?----- +--* IND int
[000055] #----+?----- | \--* IND int
[000056] -----+?----- | \--* ADD int
[000057] -----+?----- | +--* LCL_VAR int V05 tmp0
[000058] -----+?----- | \--* CNS_INT int 32
[000059] -----+?----- \--* CNS_INT int 12
------------ BB08 [???..???), preds={BB07} succs={BB06}
***** BB08
STMT00016 (IL ???... ???)
[000164] -AC-G------- * ASG int
[000163] D------N---- +--* LCL_VAR int V06 tmp1
[000049] --C-G+?----- \--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] -----+?----- arg0 in ecx +--* LCL_VAR int V05 tmp0
[000048] -----+?----- arg1 in edx \--* CNS_INT(h) int 0x8A93EB8 token
------------ BB06 [040..052) (return), preds={BB08,BB09} succs={}
***** BB06
STMT00011 (IL 0x040...0x045)
[000130] -A---+------ * ASG ref
[000128] D------N---- +--* LCL_VAR ref V08 tmp3
[000129] ------------ \--* CNS_INT ref null
***** BB06
STMT00012 (IL ???...0x04B)
[000159] -A-XG+------ * ASG ref
[000157] *--XG--N---- +--* IND ref
[000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
[000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000146] ------------ | | +--* LCL_VAR int V01 loc0
[000144] ---X-------- | | \--* ARR_LENGTH int
[000145] ------------ | | \--* LCL_VAR ref V02 loc1
[000148] ----G------- | \--* ADDR byref
[000149] a---G------- | \--* IND struct
[000150] ------------ | \--* ADD byref
[000151] ------------ | +--* LCL_VAR ref V02 loc1
[000152] ------------ | \--* ADD int
[000153] ------------ | +--* LSH int
[000154] i----------- | | +--* LCL_VAR int V01 loc0
[000155] -------N---- | | \--* CNS_INT int 2
[000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
[000158] ------------ \--* LCL_VAR ref V08 tmp3
***** BB06
STMT00010 (IL 0x050...0x051)
[000071] -----+------ * RETURN ref
[000070] -----+------ \--* LCL_VAR ref V07 tmp2
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Morph - Global
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie
*************** Starting PHASE Mark GC poll blocks
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare gcsafe
BB03 [0002] 1 BB01 1 [01C..040) i label target idxlen
BB07 [0007] 1 BB03 1 [???..???)-> BB08 ( cond ) i
BB09 [0009] 1 BB07 0.50 [???..???)-> BB06 (always) i
BB08 [0008] 1 BB07 0.50 [???..???) i label target
BB06 [0006] 2 BB08,BB09 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB07 to BB04
Renumber BB09 to BB05
Renumber BB08 to BB06
Renumber BB06 to BB07
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare gcsafe
BB03 [0002] 1 BB01 1 [01C..040) i label target idxlen
BB04 [0007] 1 BB03 1 [???..???)-> BB06 ( cond ) i
BB05 [0009] 1 BB04 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB04 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 3, # of blocks (including unused BB00): 8, bitset array size: 1 (short)
*************** Finishing PHASE Mark GC poll blocks
*************** Starting PHASE Compute edge weights (1, false)
*************** In fgComputeBlockAndEdgeWeights()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare gcsafe
BB03 [0002] 1 BB01 1 [01C..040) i label target idxlen
BB04 [0007] 1 BB03 1 [???..???)-> BB06 ( cond ) i
BB05 [0009] 1 BB04 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB04 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
fgComputeEdgeWeights() was able to compute exact edge weights for all of the 7 edges, using 1 passes.
Edge weights into BB02 :BB01 (0)
Edge weights into BB03 :BB01 (100)
Edge weights into BB04 :BB03 (100)
Edge weights into BB05 :BB04 (50)
Edge weights into BB06 :BB04 (50)
Edge weights into BB07 :BB06 (50), BB05 (50)
*************** Finishing PHASE Compute edge weights (1, false)
*************** Starting PHASE Merge throw blocks
*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.
*************** Finishing PHASE Merge throw blocks
*************** Starting PHASE Optimize layout
*************** In optOptimizeLayout()
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare gcsafe
BB03 [0002] 1 BB01 1 [01C..040) i label target idxlen
BB04 [0007] 1 BB03 1 [???..???)-> BB06 ( cond ) i
BB05 [0009] 1 BB04 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB04 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
Compacting blocks BB03 and BB04:
*************** In fgDebugCheckBBlist
After updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare gcsafe
BB03 [0002] 1 BB01 1 [01C..040)-> BB06 ( cond ) i label target idxlen
BB05 [0009] 1 BB03 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB03 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** In fgRelocateEHRegions()
*************** In fgReorderBlocks()
Initial BasicBlocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB03 ( cond ) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare gcsafe
BB03 [0002] 1 BB01 1 [01C..040)-> BB06 ( cond ) i label target idxlen
BB05 [0009] 1 BB03 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB03 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
-----------------------------------------------------------------------------------------------------------------------------------------
Decided to reverse conditional branch at block BB01 branch to BB03 since it falls into a rarely run block
Relocated rarely run block BB02 by reversing conditional jump at BB01
Relocated block [BB02..BB02] inserted after BB07 at the end of method
After this change in fgReorderBlocks the BB graph is:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB02 ( cond ) i label target idxlen
BB03 [0002] 1 BB01 1 [01C..040)-> BB06 ( cond ) i label target idxlen
BB05 [0009] 1 BB03 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB03 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB02 ( cond ) i label target idxlen
BB03 [0002] 1 BB01 1 [01C..040)-> BB06 ( cond ) i label target idxlen
BB05 [0009] 1 BB03 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB03 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize layout
*************** Starting PHASE Compute blocks reachability
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB02 ( cond ) i label target idxlen
BB03 [0002] 1 BB01 1 [01C..040)-> BB06 ( cond ) i label target idxlen
BB05 [0009] 1 BB03 0.50 [???..???)-> BB07 (always) i
BB06 [0008] 1 BB03 0.50 [???..???) i label target
BB07 [0006] 2 BB06,BB05 1 [040..052) (return) i label target idxlen
BB02 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB05 to BB03
Renumber BB06 to BB04
Renumber BB07 to BB05
Renumber BB02 to BB06
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.50 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.50 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 4, # of blocks (including unused BB00): 7, bitset array size: 1 (short)
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
BB02 : BB01 BB02
BB03 : BB01 BB02 BB03
BB04 : BB01 BB02 BB04
BB05 : BB01 BB02 BB03 BB04 BB05
BB06 : BB01 BB06
After computing reachability:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.50 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.50 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
BB02: BB02 BB01
BB03: BB03 BB02 BB01
BB04: BB04 BB02 BB01
BB05: BB05 BB02 BB01
BB06: BB06 BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB06 BB02
BB02 : BB05 BB04 BB03
After numbering the dominator tree:
BB01: pre=01, post=06
BB02: pre=03, post=05
BB03: pre=06, post=04
BB04: pre=05, post=03
BB05: pre=04, post=02
BB06: pre=02, post=01
*************** Finishing PHASE Compute blocks reachability
*************** Starting PHASE Optimize loops
*************** In optOptimizeLoops()
After optSetBlockWeights:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize loops
*************** Starting PHASE Clone loops
*************** In optCloneLoops()
*************** Finishing PHASE Clone loops
*************** Starting PHASE Unroll loops
*************** Finishing PHASE Unroll loops
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
*** marking local variables in block BB01 (weight=1 )
STMT00000 (IL 0x000...0x008)
[000005] -A-XG+------ * ASG int
[000004] D----+-N---- +--* LCL_VAR int V01 loc0
[000003] ---XG+------ \--* ADD int
[000001] ---XG+------ +--* IND int
[000088] -----+------ | \--* ADD byref
[000000] -----+------ | +--* LCL_VAR ref V00 this
[000087] -----+------ | \--* CNS_INT int 8 field offset Fseq[_size]
[000002] -----+------ \--* CNS_INT int -1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 1, refCntWtd = 1
STMT00001 (IL 0x009...0x00F)
[000009] -A-XG+------ * ASG ref
[000008] D----+-N---- +--* LCL_VAR ref V02 loc1
[000007] ---XG+------ \--* IND ref
[000090] -----+------ \--* ADD byref
[000006] -----+------ +--* LCL_VAR ref V00 this
[000089] -----+------ \--* CNS_INT int 4 field offset Fseq[_array]
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 2, refCntWtd = 2
STMT00002 (IL 0x010...0x014)
[000014] ---X-+------ * JTRUE void
[000013] N--X-+-N-U-- \--* GE int
[000010] -----+------ +--* LCL_VAR int V01 loc0
[000012] ---X-+------ \--* ARR_LENGTH int
[000011] -----+------ \--* LCL_VAR ref V02 loc1
New refCnts for V01: refCnt = 2, refCntWtd = 2
New refCnts for V02: refCnt = 2, refCntWtd = 2
*** marking local variables in block BB02 (weight=1 )
STMT00003 (IL 0x01C...0x025)
[000021] -A-XG+------ * ASG int
[000020] ---XG+-N---- +--* IND int
[000093] -----+------ | \--* ADD byref
[000015] -----+------ | +--* LCL_VAR ref V00 this
[000092] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000019] ---XG+------ \--* ADD int
[000017] ---XG+------ +--* IND int
[000095] -----+------ | \--* ADD byref
[000016] -----+------ | +--* LCL_VAR ref V00 this
[000094] -----+------ | \--* CNS_INT int 12 field offset Fseq[_version]
[000018] -----+------ \--* CNS_INT int 1
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 4, refCntWtd = 4
STMT00004 (IL 0x02A...0x02C)
[000025] -A-XG+------ * ASG int
[000024] ---XG+-N---- +--* IND int
[000097] -----+------ | \--* ADD byref
[000022] -----+------ | +--* LCL_VAR ref V00 this
[000096] -----+------ | \--* CNS_INT int 8 field offset Fseq[_size]
[000023] -----+------ \--* LCL_VAR int V01 loc0
New refCnts for V00: refCnt = 5, refCntWtd = 5
New refCnts for V01: refCnt = 3, refCntWtd = 3
STMT00005 (IL 0x031...0x038)
[000125] -A-XG+------ * ASG ref
[000109] D------N---- +--* LCL_VAR ref V07 tmp2
[000124] ---XG------- \--* IND ref
[000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
[000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
[000113] ------------ | +--* LCL_VAR int V01 loc0
[000111] ---X-------- | \--* ARR_LENGTH int
[000112] ------------ | \--* LCL_VAR ref V02 loc1
[000115] ----G------- \--* ADDR byref
[000116] a---G--N---- \--* IND struct
[000117] ------------ \--* ADD byref
[000118] ------------ +--* LCL_VAR ref V02 loc1
[000119] ------------ \--* ADD int
[000120] ------------ +--* LSH int
[000121] i----------- | +--* LCL_VAR int V01 loc0
[000122] -------N---- | \--* CNS_INT int 2
[000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
New refCnts for V07: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 4, refCntWtd = 4
New refCnts for V02: refCnt = 3, refCntWtd = 3
New refCnts for V02: refCnt = 4, refCntWtd = 4
New refCnts for V01: refCnt = 5, refCntWtd = 5
STMT00006 (IL 0x039...0x03E)
[000038] -A---+------ * ASG int
[000037] D----+-N---- +--* LCL_VAR int V05 tmp0
[000036] #----+------ \--* IND int
[000035] -----+------ \--* LCL_VAR ref V00 this
New refCnts for V05: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 6, refCntWtd = 6
STMT00014 (IL ???... ???)
[000160] ------------ * JTRUE void
[000051] J----+-N---- \--* EQ int
[000047] n----+------ +--* IND int
[000046] -----+------ | \--* ADD int
[000044] #----+------ | +--* IND int
[000043] #----+------ | | \--* IND int
[000042] -----+------ | | \--* ADD int
[000040] -----+------ | | +--* LCL_VAR int V05 tmp0
[000041] -----+------ | | \--* CNS_INT int 32
[000045] -----+------ | \--* CNS_INT int 12
[000050] -----+------ \--* CNS_INT int 0
New refCnts for V05: refCnt = 2, refCntWtd = 4
*** marking local variables in block BB03 (weight=0.25)
STMT00015 (IL ???... ???)
[000162] -A---------- * ASG int
[000161] D------N---- +--* LCL_VAR int V06 tmp1
[000052] n----+?----- \--* IND int
[000053] -----+?----- \--* ADD int
[000054] #----+?----- +--* IND int
[000055] #----+?----- | \--* IND int
[000056] -----+?----- | \--* ADD int
[000057] -----+?----- | +--* LCL_VAR int V05 tmp0
[000058] -----+?----- | \--* CNS_INT int 32
[000059] -----+?----- \--* CNS_INT int 12
New refCnts for V06: refCnt = 1, refCntWtd = 0.50
New refCnts for V05: refCnt = 3, refCntWtd = 4.50
*** marking local variables in block BB04 (weight=0.25)
STMT00016 (IL ???... ???)
[000164] -AC-G------- * ASG int
[000163] D------N---- +--* LCL_VAR int V06 tmp1
[000049] --C-G+?----- \--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000039] -----+?----- arg0 in ecx +--* LCL_VAR int V05 tmp0
[000048] -----+?----- arg1 in edx \--* CNS_INT(h) int 0x8A93EB8 token
New refCnts for V06: refCnt = 2, refCntWtd = 1
New refCnts for V05: refCnt = 4, refCntWtd = 5
*** marking local variables in block BB05 (weight=1 )
STMT00011 (IL 0x040...0x045)
[000130] -A---+------ * ASG ref
[000128] D------N---- +--* LCL_VAR ref V08 tmp3
[000129] ------------ \--* CNS_INT ref null
New refCnts for V08: refCnt = 1, refCntWtd = 1
STMT00012 (IL ???...0x04B)
[000159] -A-XG+------ * ASG ref
[000157] *--XG--N---- +--* IND ref
[000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
[000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000146] ------------ | | +--* LCL_VAR int V01 loc0
[000144] ---X-------- | | \--* ARR_LENGTH int
[000145] ------------ | | \--* LCL_VAR ref V02 loc1
[000148] ----G------- | \--* ADDR byref
[000149] a---G------- | \--* IND struct
[000150] ------------ | \--* ADD byref
[000151] ------------ | +--* LCL_VAR ref V02 loc1
[000152] ------------ | \--* ADD int
[000153] ------------ | +--* LSH int
[000154] i----------- | | +--* LCL_VAR int V01 loc0
[000155] -------N---- | | \--* CNS_INT int 2
[000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
[000158] ------------ \--* LCL_VAR ref V08 tmp3
New refCnts for V01: refCnt = 6, refCntWtd = 6
New refCnts for V02: refCnt = 5, refCntWtd = 5
New refCnts for V02: refCnt = 6, refCntWtd = 6
New refCnts for V01: refCnt = 7, refCntWtd = 7
New refCnts for V08: refCnt = 2, refCntWtd = 2
STMT00010 (IL 0x050...0x051)
[000071] -----+------ * RETURN ref
[000070] -----+------ \--* LCL_VAR ref V07 tmp2
New refCnts for V07: refCnt = 2, refCntWtd = 2
*** marking local variables in block BB06 (weight=0 )
STMT00013 (IL 0x016...0x017)
[000083] --CXG+------ * CALL void Stack`1.ThrowForEmptyStack
[000082] -----+------ this in ecx \--* LCL_VAR ref V00 this
New refCnts for V00: refCnt = 7, refCntWtd = 6
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 8, refCntWtd = 7
New refCnts for V00: refCnt = 9, refCntWtd = 8
*************** In optAddCopies()
*************** Finishing PHASE Mark local vars
*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize bools
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 17 tree nodes
*************** Finishing PHASE Set block order
Trees before Build SSA representation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0
N006 ( 6, 6) [000003] ---XG------- \--* ADD int
N004 ( 4, 4) [000001] ---XG------- +--* IND int
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1
N004 ( 4, 4) [000007] ---XG------- \--* IND ref
N003 ( 2, 2) [000090] -------N---- \--* ADD byref
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array]
***** BB01
STMT00002 (IL 0x010...0x014)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int
N010 ( 4, 4) [000020] ---XG--N---- +--* IND int
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N006 ( 6, 6) [000019] ---XG------- \--* ADD int
N004 ( 4, 4) [000017] ---XG------- +--* IND int
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int
N004 ( 4, 4) [000024] ---XG--N---- +--* IND int
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0
***** BB02
STMT00005 (IL 0x031...0x038)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2
N015 ( 20, 22) [000124] ---XG------- \--* IND ref
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct
N011 ( 4, 4) [000117] -------N---- \--* ADD byref
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1
N010 ( 3, 3) [000119] -------N---- \--* ADD int
N008 ( 2, 2) [000120] -------N---- +--* LSH int
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0
N002 ( 3, 2) [000036] #----O------ \--* IND int
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int
N008 ( 10, 9) [000047] n----------- +--* IND int
N007 ( 8, 7) [000046] -------N---- | \--* ADD int
N005 ( 7, 6) [000044] #----------- | +--* IND int
N004 ( 4, 4) [000043] #----------- | | \--* IND int
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00015 (IL ???... ???)
N010 ( 14, 12) [000162] -A------R--- * ASG int
N009 ( 3, 2) [000161] D------N---- +--* LCL_VAR int V06 tmp1
N008 ( 10, 9) [000052] n-----?----- \--* IND int
N007 ( 8, 7) [000053] ------?N---- \--* ADD int
N005 ( 7, 6) [000054] #-----?----- +--* IND int
N004 ( 4, 4) [000055] #-----?----- | \--* IND int
N003 ( 2, 2) [000056] ------?N---- | \--* ADD int
N001 ( 1, 1) [000057] ------?----- | +--* LCL_VAR int V05 tmp0
N002 ( 1, 1) [000058] ------?----- | \--* CNS_INT int 32
N006 ( 1, 1) [000059] ------?----- \--* CNS_INT int 12
------------ BB04 [???..???), preds={BB02} succs={BB05}
***** BB04
STMT00016 (IL ???... ???)
N007 ( 20, 15) [000164] -AC-G---R--- * ASG int
N006 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V06 tmp1
N005 ( 16, 12) [000049] --C-G-?----- \--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000039] ------?----- arg0 in ecx +--* LCL_VAR int V05 tmp0
N004 ( 1, 4) [000048] ------?----- arg1 in edx \--* CNS_INT(h) int 0x8A93EB8 token
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null
***** BB05
STMT00012 (IL ???...0x04B)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1
N013 ( 9, 9) [000148] ----G------- | \--* ADDR byref
N012 ( 5, 5) [000149] a---G------- | \--* IND struct
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1
N010 ( 3, 3) [000152] -------N---- | \--* ADD int
N008 ( 2, 2) [000153] -------N---- | +--* LSH int
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 7.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB06 BB02
BB02 : BB05 BB04 BB03
*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Tracked variable (7 out of 9) table:
V00 this [ ref]: refCnt = 9, refCntWtd = 8
V01 loc0 [ int]: refCnt = 7, refCntWtd = 7
V02 loc1 [ ref]: refCnt = 6, refCntWtd = 6
V05 tmp0 [ int]: refCnt = 4, refCntWtd = 5
V07 tmp2 [ ref]: refCnt = 2, refCntWtd = 2
V08 tmp3 [ ref]: refCnt = 2, refCntWtd = 2
V06 tmp1 [ int]: refCnt = 2, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 } + ByrefExposed + GcHeap
DEF(2)={ V01 V02}
BB02 USE(3)={V00 V01 V02 } + ByrefExposed + GcHeap
DEF(2)={ V05 V07} + ByrefExposed + GcHeap
BB03 USE(1)={V05 } + ByrefExposed + GcHeap
DEF(1)={ V06}
BB04 USE(1)={V05 }
DEF(1)={ V06}
BB05 USE(3)={V01 V02 V07 } + ByrefExposed + GcHeap
DEF(1)={ V08} + ByrefExposed + GcHeap
BB06 USE(1)={V00} + ByrefExposed + GcHeap
DEF(0)={ } + ByrefExposed* + GcHeap*
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00 } + ByrefExposed + GcHeap
OUT(3)={V00 V01 V02} + ByrefExposed + GcHeap
BB02 IN (3)={V00 V01 V02 } + ByrefExposed + GcHeap
OUT(4)={ V01 V02 V05 V07} + ByrefExposed + GcHeap
BB03 IN (4)={V01 V02 V05 V07} + ByrefExposed + GcHeap
OUT(3)={V01 V02 V07} + ByrefExposed + GcHeap
BB04 IN (4)={V01 V02 V05 V07} + ByrefExposed + GcHeap
OUT(3)={V01 V02 V07} + ByrefExposed + GcHeap
BB05 IN (3)={V01 V02 V07} + ByrefExposed + GcHeap
OUT(0)={ }
BB06 IN (1)={V00} + ByrefExposed + GcHeap
OUT(0)={ }
top level assign
removing stmt with no side effects
Removing statement STMT00015 (IL ???... ???)
N010 ( 14, 12) [000162] -A------R--- * ASG int
N009 ( 3, 2) [000161] D------N---- +--* LCL_VAR int V06 tmp1
N008 ( 10, 9) [000052] n-----?----- \--* IND int
N007 ( 8, 7) [000053] ------?N---- \--* ADD int
N005 ( 7, 6) [000054] #-----?----- +--* IND int
N004 ( 4, 4) [000055] #-----?----- | \--* IND int
N003 ( 2, 2) [000056] ------?N---- | \--* ADD int
N001 ( 1, 1) [000057] ------?----- | +--* LCL_VAR int V05 tmp0
N002 ( 1, 1) [000058] ------?----- | \--* CNS_INT int 32
N006 ( 1, 1) [000059] ------?----- \--* CNS_INT int 12
in BB03 as useless:
BB03 becomes empty
BB04 - Dead assignment has side effects...
N007 ( 20, 15) [000164] -AC-G---R--- * ASG int
N006 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V06 tmp1
N005 ( 16, 12) [000049] --C-G-?----- \--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000039] ------?----- arg0 in ecx +--* LCL_VAR int V05 tmp0
N004 ( 1, 4) [000048] ------?----- arg1 in edx \--* CNS_INT(h) int 0x8A93EB8 token
top level assign
removing stmt with no side effects
Removing statement STMT00016 (IL ???... ???)
N007 ( 20, 15) [000164] -AC-G---R--- * ASG int
N006 ( 3, 2) [000163] D------N---- +--* LCL_VAR int V06 tmp1
N005 ( 16, 12) [000049] --C-G-?----- \--* CALL help int HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000039] ------?----- arg0 in ecx +--* LCL_VAR int V05 tmp0
N004 ( 1, 4) [000048] ------?----- arg1 in edx \--* CNS_INT(h) int 0x8A93EB8 token
in BB04 as useless:
BB04 becomes empty
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 } + ByrefExposed + GcHeap
DEF(2)={ V01 V02}
BB02 USE(3)={V00 V01 V02 } + ByrefExposed + GcHeap
DEF(2)={ V05 V07} + ByrefExposed + GcHeap
BB03 USE(0)={}
DEF(0)={}
BB04 USE(0)={}
DEF(0)={}
BB05 USE(3)={V01 V02 V07 } + ByrefExposed + GcHeap
DEF(1)={ V08} + ByrefExposed + GcHeap
BB06 USE(1)={V00} + ByrefExposed + GcHeap
DEF(0)={ } + ByrefExposed* + GcHeap*
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00 } + ByrefExposed + GcHeap
OUT(3)={V00 V01 V02} + ByrefExposed + GcHeap
BB02 IN (3)={V00 V01 V02 } + ByrefExposed + GcHeap
OUT(3)={ V01 V02 V07} + ByrefExposed + GcHeap
BB03 IN (3)={V01 V02 V07} + ByrefExposed + GcHeap
OUT(3)={V01 V02 V07} + ByrefExposed + GcHeap
BB04 IN (3)={V01 V02 V07} + ByrefExposed + GcHeap
OUT(3)={V01 V02 V07} + ByrefExposed + GcHeap
BB05 IN (3)={V01 V02 V07} + ByrefExposed + GcHeap
OUT(0)={ }
BB06 IN (1)={V00} + ByrefExposed + GcHeap
OUT(0)={ }
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1
N006 ( 6, 6) [000003] ---XG------- \--* ADD int
N004 ( 4, 4) [000001] ---XG------- +--* IND int
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1
N004 ( 4, 4) [000007] ---XG------- \--* IND ref
N003 ( 2, 2) [000090] -------N---- \--* ADD byref
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array]
***** BB01
STMT00002 (IL 0x010...0x014)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N006 ( 6, 6) [000019] ---XG------- \--* ADD int
N004 ( 4, 4) [000017] ---XG------- +--* IND int
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1
***** BB02
STMT00005 (IL 0x031...0x038)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1
N015 ( 20, 22) [000124] ---XG------- \--* IND ref
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct
N011 ( 4, 4) [000117] -------N---- \--* ADD byref
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1
N010 ( 3, 3) [000119] -------N---- \--* ADD int
N008 ( 2, 2) [000120] -------N---- +--* LSH int
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1
N002 ( 3, 2) [000036] #----O------ \--* IND int
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use)
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int
N008 ( 10, 9) [000047] n----------- +--* IND int
N007 ( 8, 7) [000046] -------N---- | \--* ADD int
N005 ( 7, 6) [000044] #----------- | +--* IND int
N004 ( 4, 4) [000043] #----------- | | \--* IND int
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use)
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null
***** BB05
STMT00012 (IL ???...0x04B)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000148] ----G------- | \--* ADDR byref
N012 ( 5, 5) [000149] a---G------- | \--* IND struct
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use)
N010 ( 3, 3) [000152] -------N---- | \--* ADD int
N008 ( 2, 2) [000153] -------N---- | +--* LSH int
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use)
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use)
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use)
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1
N006 ( 6, 6) [000003] ---XG------- \--* ADD int
N004 ( 4, 4) [000001] ---XG------- +--* IND int
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1
N004 ( 4, 4) [000007] ---XG------- \--* IND ref
N003 ( 2, 2) [000090] -------N---- \--* ADD byref
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array]
***** BB01
STMT00002 (IL 0x010...0x014)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N006 ( 6, 6) [000019] ---XG------- \--* ADD int
N004 ( 4, 4) [000017] ---XG------- +--* IND int
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1
***** BB02
STMT00005 (IL 0x031...0x038)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1
N015 ( 20, 22) [000124] ---XG------- \--* IND ref
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct
N011 ( 4, 4) [000117] -------N---- \--* ADD byref
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1
N010 ( 3, 3) [000119] -------N---- \--* ADD int
N008 ( 2, 2) [000120] -------N---- +--* LSH int
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1
N002 ( 3, 2) [000036] #----O------ \--* IND int
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use)
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int
N008 ( 10, 9) [000047] n----------- +--* IND int
N007 ( 8, 7) [000046] -------N---- | \--* ADD int
N005 ( 7, 6) [000044] #----------- | +--* IND int
N004 ( 4, 4) [000043] #----------- | | \--* IND int
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use)
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null
***** BB05
STMT00012 (IL ???...0x04B)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000148] ----G------- | \--* ADDR byref
N012 ( 5, 5) [000149] a---G------- | \--* IND struct
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use)
N010 ( 3, 3) [000152] -------N---- | \--* ADD int
N008 ( 2, 2) [000153] -------N---- | +--* LSH int
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use)
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use)
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use)
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Early Value Propagation
*************** In optEarlyProp()
After optEarlyProp:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1
N006 ( 6, 6) [000003] ---XG------- \--* ADD int
N004 ( 4, 4) [000001] ---XG------- +--* IND int
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1
N004 ( 4, 4) [000007] ---XG------- \--* IND ref
N003 ( 2, 2) [000090] -------N---- \--* ADD byref
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array]
***** BB01
STMT00002 (IL 0x010...0x014)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N006 ( 6, 6) [000019] ---XG------- \--* ADD int
N004 ( 4, 4) [000017] ---XG------- +--* IND int
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1
***** BB02
STMT00005 (IL 0x031...0x038)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1
N015 ( 20, 22) [000124] ---XG------- \--* IND ref
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct
N011 ( 4, 4) [000117] -------N---- \--* ADD byref
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1
N010 ( 3, 3) [000119] -------N---- \--* ADD int
N008 ( 2, 2) [000120] -------N---- +--* LSH int
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1
N002 ( 3, 2) [000036] #----O------ \--* IND int
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use)
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int
N008 ( 10, 9) [000047] n----------- +--* IND int
N007 ( 8, 7) [000046] -------N---- | \--* ADD int
N005 ( 7, 6) [000044] #----------- | +--* IND int
N004 ( 4, 4) [000043] #----------- | | \--* IND int
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use)
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null
***** BB05
STMT00012 (IL ???...0x04B)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000148] ----G------- | \--* ADDR byref
N012 ( 5, 5) [000149] a---G------- | \--* IND struct
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use)
N010 ( 3, 3) [000152] -------N---- | \--* ADD int
N008 ( 2, 2) [000153] -------N---- | +--* LSH int
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use)
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use)
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use)
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Early Value Propagation
*************** Starting PHASE Do value numbering
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $81
The SSA definition for ByrefExposed (#1) at start of BB01 is $81 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB01 is $81 {InitVal($41)}
***** BB01, STMT00000(before)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1
N006 ( 6, 6) [000003] ---XG------- \--* ADD int
N004 ( 4, 4) [000001] ---XG------- +--* IND int
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1
N001 [000000] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
N002 [000087] CNS_INT 8 field offset Fseq[_size] => $42 {IntCns 8}
N003 [000088] ADD => $c0 {ADD($42, $80)}
VNApplySelectors:
VNForHandle(_size) is $100, fieldType is int
VNForMapSelect($81, $100):int returns $140 {$81[$100]}
VNForMapSelect($140, $80):int returns $141 {$140[$80]}
N004 [000001] IND => <l:$143 {norm=$141 {$140[$80]}, exc=$1c0 {NullPtrExc($80)}}, c:$142 {norm=$180 {180}, exc=$1c0 {NullPtrExc($80)}}>
N005 [000002] CNS_INT -1 => $41 {IntCns -1}
N006 [000003] ADD => <l:$147 {norm=$145 {ADD($41, $141)}, exc=$1c0 {NullPtrExc($80)}}, c:$146 {norm=$144 {ADD($41, $180)}, exc=$1c0 {NullPtrExc($80)}}>
N007 [000004] LCL_VAR V01 loc0 d:1 => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
N008 [000005] ASG => <l:$147 {norm=$145 {ADD($41, $141)}, exc=$1c0 {NullPtrExc($80)}}, c:$146 {norm=$144 {ADD($41, $180)}, exc=$1c0 {NullPtrExc($80)}}>
***** BB01, STMT00000(after)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int <l:$147, c:$146>
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1 <l:$145, c:$144>
N006 ( 6, 6) [000003] ---XG------- \--* ADD int <l:$147, c:$146>
N004 ( 4, 4) [000001] ---XG------- +--* IND int <l:$143, c:$142>
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1 $41
---------
***** BB01, STMT00001(before)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1
N004 ( 4, 4) [000007] ---XG------- \--* IND ref
N003 ( 2, 2) [000090] -------N---- \--* ADD byref
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array]
N001 [000006] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
N002 [000089] CNS_INT 4 field offset Fseq[_array] => $43 {IntCns 4}
N003 [000090] ADD => $c1 {ADD($43, $80)}
VNApplySelectors:
VNForHandle(_array) is $101, fieldType is ref
VNForMapSelect($81, $101):ref returns $1c1 {$81[$101]}
VNForMapSelect($1c1, $80):ref returns $1c2 {$1c1[$80]}
N004 [000007] IND => <l:$1c4 {norm=$1c2 {$1c1[$80]}, exc=$1c0 {NullPtrExc($80)}}, c:$1c3 {norm=$200 {200}, exc=$1c0 {NullPtrExc($80)}}>
N005 [000008] LCL_VAR V02 loc1 d:1 => <l:$1c2 {$1c1[$80]}, c:$200 {200}>
N006 [000009] ASG => <l:$1c4 {norm=$1c2 {$1c1[$80]}, exc=$1c0 {NullPtrExc($80)}}, c:$1c3 {norm=$200 {200}, exc=$1c0 {NullPtrExc($80)}}>
***** BB01, STMT00001(after)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1 <l:$1c2, c:$200>
N004 ( 4, 4) [000007] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000090] -------N---- \--* ADD byref $c1
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array] $43
---------
***** BB01, STMT00002(before)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1
N001 [000011] LCL_VAR V02 loc1 u:1 => <l:$1c2 {$1c1[$80]}, c:$200 {200}>
N002 [000012] ARR_LENGTH => <l:$149 {norm=$241 {ARR_LENGTH($1c2)}, exc=$1c6 {NullPtrExc($1c2)}}, c:$148 {norm=$240 {ARR_LENGTH($200)}, exc=$1c5 {NullPtrExc($200)}}>
N003 [000010] LCL_VAR V01 loc0 u:1 => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
N004 [000013] LE => <l:$14d {norm=$14b {LE_UN($241, $145)}, exc=$1c6 {NullPtrExc($1c2)}}, c:$14c {norm=$14a {LE_UN($240, $144)}, exc=$1c5 {NullPtrExc($200)}}>
***** BB01, STMT00002(after)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int <l:$14d, c:$14c>
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int <l:$149, c:$148>
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
finish(BB01).
Succ(BB02).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB06).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#1) at start of BB06 is $81 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB06 is $81 {InitVal($41)}
***** BB06, STMT00013(before)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use)
N001 [000091] ARGPLACE => $202 {202}
N002 [000082] LCL_VAR V00 this u:1 (last use) => $80 {InitVal($40)}
fgCurMemoryVN[GcHeap] assigned for CALL at [000083] to VN: $203.
N003 [000083] CALL => $VN.Void
***** BB06, STMT00013(after)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use) $80
finish(BB06).
The SSA definition for ByrefExposed (#1) at start of BB02 is $81 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB02 is $81 {InitVal($41)}
***** BB02, STMT00003(before)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N006 ( 6, 6) [000019] ---XG------- \--* ADD int
N004 ( 4, 4) [000017] ---XG------- +--* IND int
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version]
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1
N001 [000016] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
N002 [000094] CNS_INT 12 field offset Fseq[_version] => $44 {IntCns 12}
N003 [000095] ADD => $c2 {ADD($44, $80)}
VNApplySelectors:
VNForHandle(_version) is $102, fieldType is int
VNForMapSelect($81, $102):int returns $14e {$81[$102]}
VNForMapSelect($14e, $80):int returns $14f {$14e[$80]}
N004 [000017] IND => <l:$151 {norm=$14f {$14e[$80]}, exc=$1c0 {NullPtrExc($80)}}, c:$150 {norm=$182 {182}, exc=$1c0 {NullPtrExc($80)}}>
N005 [000018] CNS_INT 1 => $45 {IntCns 1}
N006 [000019] ADD => <l:$155 {norm=$153 {ADD($45, $14f)}, exc=$1c0 {NullPtrExc($80)}}, c:$154 {norm=$152 {ADD($45, $182)}, exc=$1c0 {NullPtrExc($80)}}>
N007 [000015] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
N008 [000092] CNS_INT 12 field offset Fseq[_version] => $44 {IntCns 12}
N009 [000093] ADD => $c2 {ADD($44, $80)}
VNApplySelectors:
VNForHandle(_version) is $102, fieldType is int
VNForMapSelect($81, $102):int returns $14e {$81[$102]}
VNForMapSelect($14e, $80):int returns $14f {$14e[$80]}
VNForMapStore($14e, $80, $153):int returns $280 {$14e[$80 := $153]}
VNApplySelectorsAssign:
VNForHandle(_version) is $102, fieldType is int
VNForMapStore($81, $102, $280):int returns $281 {$81[$102 := $280]}
fgCurMemoryVN[GcHeap] assigned for StoreField at [000021] to VN: $281.
N011 [000021] ASG => $VN.Void
***** BB02, STMT00003(after)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int $VN.Void
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int $153
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref $c2
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N006 ( 6, 6) [000019] ---XG------- \--* ADD int <l:$155, c:$154>
N004 ( 4, 4) [000017] ---XG------- +--* IND int <l:$151, c:$150>
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref $c2
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1 $45
---------
***** BB02, STMT00004(before)
N006 ( 6, 6) [000025] -A-XG------- * ASG int
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size]
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1
N001 [000022] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
N002 [000096] CNS_INT 8 field offset Fseq[_size] => $42 {IntCns 8}
N003 [000097] ADD => $c0 {ADD($42, $80)}
N005 [000023] LCL_VAR V01 loc0 u:1 => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
VNApplySelectors:
VNForHandle(_size) is $100, fieldType is int
AX2: $100 != $102 ==> select([$281]store($81, $102, $280), $100) ==> select($81, $100).
VNForMapSelect($281, $100):int returns $140 {$81[$100]}
VNForMapSelect($140, $80):int returns $141 {$140[$80]}
VNForMapStore($140, $80, $145):int returns $282 {$140[$80 := $145]}
VNApplySelectorsAssign:
VNForHandle(_size) is $100, fieldType is int
VNForMapStore($281, $100, $282):int returns $283 {$281[$100 := $282]}
fgCurMemoryVN[GcHeap] assigned for StoreField at [000025] to VN: $283.
N006 [000025] ASG => $VN.Void
***** BB02, STMT00004(after)
N006 ( 6, 6) [000025] -A-XG------- * ASG int $VN.Void
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int $145
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
---------
***** BB02, STMT00005(before)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1
N015 ( 20, 22) [000124] ---XG------- \--* IND ref
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct
N011 ( 4, 4) [000117] -------N---- \--* ADD byref
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1
N010 ( 3, 3) [000119] -------N---- \--* ADD int
N008 ( 2, 2) [000120] -------N---- +--* LSH int
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem]
N001 [000113] LCL_VAR V01 loc0 u:1 => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
N002 [000112] LCL_VAR V02 loc1 u:1 => <l:$1c2 {$1c1[$80]}, c:$200 {200}>
N003 [000111] ARR_LENGTH => <l:$149 {norm=$241 {ARR_LENGTH($1c2)}, exc=$1c6 {NullPtrExc($1c2)}}, c:$148 {norm=$240 {ARR_LENGTH($200)}, exc=$1c5 {NullPtrExc($200)}}>
N004 [000114] ARR_BOUNDS_CHECK_Rng => <l:$1d0 {norm=$3 {3}, exc=$1ce( {NullPtrExc($1c2)}, {IndexOutOfRangeExc($145, $241)})}, c:$1cf {norm=$3 {3}, exc=$1cd( {NullPtrExc($200)}, {IndexOutOfRangeExc($144, $240)})}>
N005 [000118] LCL_VAR V02 loc1 u:1 => <l:$1c2 {$1c1[$80]}, c:$200 {200}>
N006 [000121] LCL_VAR V01 loc0 u:1 => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
N007 [000122] CNS_INT 2 => $46 {IntCns 2}
N008 [000120] LSH => <l:$157 {LSH($145, $46)}, c:$156 {LSH($144, $46)}>
N009 [000123] CNS_INT 8 Fseq[#FirstElem] => $42 {IntCns 8}
N010 [000119] ADD => <l:$159 {ADD($42, $157)}, c:$158 {ADD($42, $156)}>
N011 [000117] ADD => <l:$c4 {ADD($159, $1c2)}, c:$c3 {ADD($158, $200)}>
VNForHandle(arrElemType: RefAsValueType`1) is $103
Relabeled IND_ARR_INDEX address node [000117] with l:$300: {PtrToArrElem($103, $1c2, $145, $0)}
AX2: $103 != $100 ==> select([$283]store($281, $100, $282), $103) ==> select($281, $103).
AX2: $103 != $102 ==> select([$281]store($81, $102, $280), $103) ==> select($81, $103).
VNForMapSelect($283, $103):ref returns $1d1 {$81[$103]}
VNForMapSelect($1d1, $1c2):ref returns $1d2 {$1d1[$1c2]}
VNForMapSelect($1d2, $145):struct returns $340 {$1d2[$145]}
hAtArrType $1d1 is MapSelect(curGcHeap($283), RefAsValueType`1[]).
hAtArrTypeAtArr $1d2 is MapSelect(hAtArrType($1d1), arr=$1c2).
wholeElem $340 is MapSelect(hAtArrTypeAtArr($1d2), ind=$145).
N012 [000116] IND => <l:$340 {$1d2[$145]}, c:$380 {380}>
N013 [000115] ADDR => $300 {PtrToArrElem($103, $1c2, $145, $0)}
N014 [000110] COMMA => <l:$c6 {norm=$300 {PtrToArrElem($103, $1c2, $145, $0)}, exc=$1ce( {NullPtrExc($1c2)}, {IndexOutOfRangeExc($145, $241)})}, c:$c5 {norm=$300 {PtrToArrElem($103, $1c2, $145, $0)}, exc=$1cd( {NullPtrExc($200)}, {IndexOutOfRangeExc($144, $240)})}>
AX2: $103 != $100 ==> select([$283]store($281, $100, $282), $103) ==> select($281, $103).
AX2: $103 != $102 ==> select([$281]store($81, $102, $280), $103) ==> select($81, $103).
VNForMapSelect($283, $103):ref returns $1d1 {$81[$103]}
VNForMapSelect($1d1, $1c2):ref returns $1d2 {$1d1[$1c2]}
VNForMapSelect($1d2, $145):struct returns $340 {$1d2[$145]}
hAtArrType $1d1 is MapSelect(curGcHeap($283), RefAsValueType`1[]).
hAtArrTypeAtArr $1d2 is MapSelect(hAtArrType($1d1), arr=$1c2).
wholeElem $340 is MapSelect(hAtArrTypeAtArr($1d2), ind=$145).
selectedElem is $341 after applying selectors.
N015 [000124] IND => <l:$341 {norm=$340 {$1d2[$145]}, exc=$1ce( {NullPtrExc($1c2)}, {IndexOutOfRangeExc($145, $241)})}, c:$204 {204}>
N016 [000109] LCL_VAR V07 tmp2 d:1 => <l:$340 {$1d2[$145]}, c:$204 {204}>
N017 [000125] ASG => <l:$341 {norm=$340 {$1d2[$145]}, exc=$1ce( {NullPtrExc($1c2)}, {IndexOutOfRangeExc($145, $241)})}, c:$204 {204}>
***** BB02, STMT00005(after)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N015 ( 20, 22) [000124] ---XG------- \--* IND ref <l:$341, c:$204>
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref $300
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct <l:$340, c:$380>
N011 ( 4, 4) [000117] -------N---- \--* ADD byref $300
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N010 ( 3, 3) [000119] -------N---- \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000120] -------N---- +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
---------
***** BB02, STMT00006(before)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1
N002 ( 3, 2) [000036] #----O------ \--* IND int
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use)
N001 [000035] LCL_VAR V00 this u:1 (last use) => $80 {InitVal($40)}
VNForMapSelect($2, $80):ref returns $1d3 {$VN.ReadOnlyHeap[$80]}
VNForMapSelect($2, $80):ref returns $1d3 {$VN.ReadOnlyHeap[$80]}
N002 [000036] IND => $1d3 {$VN.ReadOnlyHeap[$80]}
N003 [000037] LCL_VAR V05 tmp0 d:1 => $1d3 {$VN.ReadOnlyHeap[$80]}
N004 [000038] ASG => $1d3 {$VN.ReadOnlyHeap[$80]}
***** BB02, STMT00006(after)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int $1d3
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1 $1d3
N002 ( 3, 2) [000036] #----O------ \--* IND int $1d3
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use) $80
---------
***** BB02, STMT00014(before)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int
N008 ( 10, 9) [000047] n----------- +--* IND int
N007 ( 8, 7) [000046] -------N---- | \--* ADD int
N005 ( 7, 6) [000044] #----------- | +--* IND int
N004 ( 4, 4) [000043] #----------- | | \--* IND int
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use)
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0
N001 [000040] LCL_VAR V05 tmp0 u:1 (last use) => $1d3 {$VN.ReadOnlyHeap[$80]}
N002 [000041] CNS_INT 32 => $47 {IntCns 32}
N003 [000042] ADD => $15b {ADD($47, $1d3)}
VNForMapSelect($2, $15b):ref returns $1d4 {$VN.ReadOnlyHeap[$15b]}
VNForMapSelect($2, $15b):ref returns $1d4 {$VN.ReadOnlyHeap[$15b]}
N004 [000043] IND => $1d4 {$VN.ReadOnlyHeap[$15b]}
VNForMapSelect($2, $1d4):ref returns $1d5 {$VN.ReadOnlyHeap[$1d4]}
VNForMapSelect($2, $1d4):ref returns $1d5 {$VN.ReadOnlyHeap[$1d4]}
N005 [000044] IND => $1d5 {$VN.ReadOnlyHeap[$1d4]}
N006 [000045] CNS_INT 12 => $44 {IntCns 12}
N007 [000046] ADD => $15c {ADD($44, $1d5)}
N008 [000047] IND => <l:$284 {ByrefExposedLoad($48, $15c, $283)}, c:$184 {184}>
N009 [000050] CNS_INT 0 => $40 {IntCns 0}
N010 [000051] EQ => <l:$15e {EQ($284, $40)}, c:$15d {EQ($184, $40)}>
***** BB02, STMT00014(after)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int <l:$15e, c:$15d>
N008 ( 10, 9) [000047] n----------- +--* IND int <l:$284, c:$184>
N007 ( 8, 7) [000046] -------N---- | \--* ADD int $15c
N005 ( 7, 6) [000044] #----------- | +--* IND int $1d5
N004 ( 4, 4) [000043] #----------- | | \--* IND int $1d4
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int $15b
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use) $1d3
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32 $47
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12 $44
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40
finish(BB02).
Succ(BB03).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB04).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#3) at start of BB04 is $283 {$281[$100 := $282]}
The SSA definition for GcHeap (#3) at start of BB04 is $283 {$281[$100 := $282]}
finish(BB04).
Succ(BB05).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
The SSA definition for ByrefExposed (#3) at start of BB03 is $283 {$281[$100 := $282]}
The SSA definition for GcHeap (#3) at start of BB03 is $283 {$281[$100 := $282]}
finish(BB03).
Succ(BB05).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#3) at start of BB05 is $283 {$281[$100 := $282]}
The SSA definition for GcHeap (#3) at start of BB05 is $283 {$281[$100 := $282]}
***** BB05, STMT00011(before)
N003 ( 5, 4) [000130] -A------R--- * ASG ref
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null
N001 [000129] CNS_INT null => $VN.Null
N002 [000128] LCL_VAR V08 tmp3 d:1 => $VN.Null
N003 [000130] ASG => $VN.Null
***** BB05, STMT00011(after)
N003 ( 5, 4) [000130] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1 $VN.Null
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null $VN.Null
---------
***** BB05, STMT00012(before)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value]
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1
N013 ( 9, 9) [000148] ----G------- | \--* ADDR byref
N012 ( 5, 5) [000149] a---G------- | \--* IND struct
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use)
N010 ( 3, 3) [000152] -------N---- | \--* ADD int
N008 ( 2, 2) [000153] -------N---- | +--* LSH int
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use)
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem]
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use)
N001 [000146] LCL_VAR V01 loc0 u:1 => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
N002 [000145] LCL_VAR V02 loc1 u:1 => <l:$1c2 {$1c1[$80]}, c:$200 {200}>
N003 [000144] ARR_LENGTH => <l:$149 {norm=$241 {ARR_LENGTH($1c2)}, exc=$1c6 {NullPtrExc($1c2)}}, c:$148 {norm=$240 {ARR_LENGTH($200)}, exc=$1c5 {NullPtrExc($200)}}>
N004 [000147] ARR_BOUNDS_CHECK_Rng => <l:$1d0 {norm=$3 {3}, exc=$1ce( {NullPtrExc($1c2)}, {IndexOutOfRangeExc($145, $241)})}, c:$1cf {norm=$3 {3}, exc=$1cd( {NullPtrExc($200)}, {IndexOutOfRangeExc($144, $240)})}>
N005 [000151] LCL_VAR V02 loc1 u:1 (last use) => <l:$1c2 {$1c1[$80]}, c:$200 {200}>
N006 [000154] LCL_VAR V01 loc0 u:1 (last use) => <l:$145 {ADD($41, $141)}, c:$144 {ADD($41, $180)}>
N007 [000155] CNS_INT 2 => $46 {IntCns 2}
N008 [000153] LSH => <l:$157 {LSH($145, $46)}, c:$156 {LSH($144, $46)}>
N009 [000156] CNS_INT 8 Fseq[#FirstElem] => $42 {IntCns 8}
N010 [000152] ADD => <l:$159 {ADD($42, $157)}, c:$158 {ADD($42, $156)}>
N011 [000150] ADD => <l:$c4 {ADD($159, $1c2)}, c:$c3 {ADD($158, $200)}>
VNForHandle(arrElemType: RefAsValueType`1) is $103
Relabeled IND_ARR_INDEX address node [000150] with l:$300: {PtrToArrElem($103, $1c2, $145, $0)}
AX2: $103 != $100 ==> select([$283]store($281, $100, $282), $103) ==> select($281, $103).
AX2: $103 != $102 ==> select([$281]store($81, $102, $280), $103) ==> select($81, $103).
VNForMapSelect($283, $103):ref returns $1d1 {$81[$103]}
VNForMapSelect($1d1, $1c2):ref returns $1d2 {$1d1[$1c2]}
VNForMapSelect($1d2, $145):struct returns $340 {$1d2[$145]}
hAtArrType $1d1 is MapSelect(curGcHeap($283), RefAsValueType`1[]).
hAtArrTypeAtArr $1d2 is MapSelect(hAtArrType($1d1), arr=$1c2).
wholeElem $340 is MapSelect(hAtArrTypeAtArr($1d2), ind=$145).
N012 [000149] IND => <l:$340 {$1d2[$145]}, c:$381 {381}>
N013 [000148] ADDR => $300 {PtrToArrElem($103, $1c2, $145, $0)}
N014 [000143] COMMA => <l:$c6 {norm=$300 {PtrToArrElem($103, $1c2, $145, $0)}, exc=$1ce( {NullPtrExc($1c2)}, {IndexOutOfRangeExc($145, $241)})}, c:$c5 {norm=$300 {PtrToArrElem($103, $1c2, $145, $0)}, exc=$1cd( {NullPtrExc($200)}, {IndexOutOfRangeExc($144, $240)})}>
N016 [000158] LCL_VAR V08 tmp3 u:1 (last use) => $VN.Null
Tree [000159] assigns to an array element:
AX2: $103 != $100 ==> select([$283]store($281, $100, $282), $103) ==> select($281, $103).
AX2: $103 != $102 ==> select([$281]store($81, $102, $280), $103) ==> select($81, $103).
VNForMapSelect($283, $103):ref returns $1d1 {$81[$103]}
VNForMapSelect($1d1, $1c2):ref returns $1d2 {$1d1[$1c2]}
VNForMapSelect($1d2, $145):struct returns $340 {$1d2[$145]}
*** Mismatched types in fgValueNumberArrIndexAssign
hAtArrType $1d1 is MapSelect(curGcHeap($283), RefAsValueType`1[]).
hAtArrTypeAtArr $1d2 is MapSelect(hAtArrType($1d1), arr=$1c2)
hAtArrTypeAtArrAtInx $340 is MapSelect(hAtArrTypeAtArr($1d2), inx=$145):struct
newValAtArrType $207 is {207}
VNForMapStore($283, $103, $207):ref returns $3c0 {$283[$103 := $207]}
fgCurMemoryVN[GcHeap] assigned for ArrIndexAssign (case 1) at [000159] to VN: $3c0.
N017 [000159] ASG => $VN.Void
***** BB05, STMT00012(after)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref $VN.Void
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref $VN.Null
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000148] ----G------- | \--* ADDR byref $300
N012 ( 5, 5) [000149] a---G------- | \--* IND struct <l:$340, c:$381>
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref $300
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N010 ( 3, 3) [000152] -------N---- | \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000153] -------N---- | +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use) $VN.Null
---------
***** BB05, STMT00010(before)
N002 ( 4, 3) [000071] ------------ * RETURN ref
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use)
N001 [000070] LCL_VAR V07 tmp2 u:1 (last use) => <l:$340 {$1d2[$145]}, c:$204 {204}>
N002 [000071] RETURN => $208 {208}
***** BB05, STMT00010(after)
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
finish(BB05).
*************** Finishing PHASE Do value numbering
*************** Starting PHASE Hoist loop code
*************** Finishing PHASE Hoist loop code
*************** Starting PHASE VN based copy prop
*************** In optVnCopyProp()
Copy Assertion for BB01
curSsaName stack: { }
Live vars: {V00} => {V00 V01}
Live vars: {V00 V01} => {V00 V01 V02}
Copy Assertion for BB06
curSsaName stack: { 0-[000000]:V00 1-[000004]:V01 2-[000008]:V02 }
Live vars: {V00} => {}
Copy Assertion for BB02
curSsaName stack: { 0-[000000]:V00 1-[000004]:V01 2-[000008]:V02 }
Live vars: {V00 V01 V02} => {V00 V01 V02 V07}
Live vars: {V00 V01 V02 V07} => {V01 V02 V07}
Live vars: {V01 V02 V07} => {V01 V02 V05 V07}
Live vars: {V01 V02 V05 V07} => {V01 V02 V07}
Copy Assertion for BB05
curSsaName stack: { 0-[000000]:V00 1-[000004]:V01 2-[000008]:V02 5-[000037]:V05 7-[000109]:V07 }
Live vars: {V01 V02 V07} => {V01 V02 V07 V08}
Live vars: {V01 V02 V07 V08} => {V01 V07 V08}
Live vars: {V01 V07 V08} => {V07 V08}
Live vars: {V07 V08} => {V07}
Live vars: {V07} => {}
Copy Assertion for BB04
curSsaName stack: { 0-[000000]:V00 1-[000004]:V01 2-[000008]:V02 5-[000037]:V05 7-[000109]:V07 }
Copy Assertion for BB03
curSsaName stack: { 0-[000000]:V00 1-[000004]:V01 2-[000008]:V02 5-[000037]:V05 7-[000109]:V07 }
*************** Finishing PHASE VN based copy prop
*************** Starting PHASE Optimize Valnum CSEs
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..016)-> BB06 ( cond ) i label target idxlen
BB02 [0002] 1 BB01 1 [01C..040)-> BB04 ( cond ) i label target idxlen
BB03 [0009] 1 BB02 0.25 [???..???)-> BB05 (always) i
BB04 [0008] 1 BB02 0.25 [???..???) i label target
BB05 [0006] 2 BB04,BB03 1 [040..052) (return) i label target idxlen
BB06 [0001] 1 BB01 0 [016..01C) (throw ) i rare label target gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int <l:$147, c:$146>
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1 <l:$145, c:$144>
N006 ( 6, 6) [000003] ---XG------- \--* ADD int <l:$147, c:$146>
N004 ( 4, 4) [000001] ---XG------- +--* IND int <l:$143, c:$142>
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1 $41
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1 <l:$1c2, c:$200>
N004 ( 4, 4) [000007] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000090] -------N---- \--* ADD byref $c1
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array] $43
***** BB01
STMT00002 (IL 0x010...0x014)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int <l:$14d, c:$14c>
N002 ( 3, 3) [000012] ---X-------- +--* ARR_LENGTH int <l:$149, c:$148>
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int $VN.Void
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int $153
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref $c2
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N006 ( 6, 6) [000019] ---XG------- \--* ADD int <l:$155, c:$154>
N004 ( 4, 4) [000017] ---XG------- +--* IND int <l:$151, c:$150>
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref $c2
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1 $45
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int $VN.Void
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int $145
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
***** BB02
STMT00005 (IL 0x031...0x038)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N015 ( 20, 22) [000124] ---XG------- \--* IND ref <l:$341, c:$204>
N014 ( 17, 20) [000110] ---XG------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) [000111] ---X-------- | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref $300
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct <l:$340, c:$380>
N011 ( 4, 4) [000117] -------N---- \--* ADD byref $300
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N010 ( 3, 3) [000119] -------N---- \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000120] -------N---- +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int $1d3
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1 $1d3
N002 ( 3, 2) [000036] #----O------ \--* IND int $1d3
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use) $80
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int <l:$15e, c:$15d>
N008 ( 10, 9) [000047] n----------- +--* IND int <l:$284, c:$184>
N007 ( 8, 7) [000046] -------N---- | \--* ADD int $15c
N005 ( 7, 6) [000044] #----------- | +--* IND int $1d5
N004 ( 4, 4) [000043] #----------- | | \--* IND int $1d4
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int $15b
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use) $1d3
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32 $47
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12 $44
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1 $VN.Null
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null $VN.Null
***** BB05
STMT00012 (IL ???...0x04B)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref $VN.Void
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref $VN.Null
N014 ( 17, 20) [000143] ---XG------- | \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) [000144] ---X-------- | | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000148] ----G------- | \--* ADDR byref $300
N012 ( 5, 5) [000149] a---G------- | \--* IND struct <l:$340, c:$381>
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref $300
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N010 ( 3, 3) [000152] -------N---- | \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000153] -------N---- | +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use) $VN.Null
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use) $80
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
CSE candidate #01, vn=$241 in BB02, [cost= 3, size= 3]:
N003 ( 3, 3) CSE #01 (use)[000111] ---X-------- * ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
CSE candidate #02, vn=$340 in BB05, [cost= 5, size= 5]:
N012 ( 5, 5) CSE #02 (use)[000149] a---G------- * IND struct <l:$340, c:$381>
N011 ( 4, 4) [000150] -------N---- \--* ADD byref $300
N005 ( 1, 1) [000151] ------------ +--* LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N010 ( 3, 3) [000152] -------N---- \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000153] -------N---- +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000154] i----------- | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
N007 ( 1, 1) [000155] -------N---- | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000156] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
CSE candidate #03, vn=$c6 in BB05, [cost=17, size=20]:
N014 ( 17, 20) CSE #03 (use)[000143] ---XG------- * COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000147] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000146] ------------ | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) CSE #01 (use)[000144] ---X-------- | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000145] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000148] ----G------- \--* ADDR byref $300
N012 ( 5, 5) CSE #02 (use)[000149] a---G------- \--* IND struct <l:$340, c:$381>
N011 ( 4, 4) [000150] -------N---- \--* ADD byref $300
N005 ( 1, 1) [000151] ------------ +--* LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N010 ( 3, 3) [000152] -------N---- \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000153] -------N---- +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000154] i----------- | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
N007 ( 1, 1) [000155] -------N---- | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000156] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
Blocks that generate CSE def/uses
BB01 cseGen = 00000003
BB02 cseGen = 0000003F
BB05 cseGen = 0000003F
Performing DataFlow for ValnumCSE's
StartMerge BB01
:: cseOut = 0000007F
EndMerge BB01
:: cseIn = 00000000
:: cseGen = 00000003
=> cseOut = 00000003
!= preMerge = 0000007F, => true
StartMerge BB02
:: cseOut = 0000007F
Merge BB02 and BB01
:: cseIn = 0000007F
:: cseOut = 0000007F
=> cseIn = 00000003
EndMerge BB02
:: cseIn = 00000003
-- cseKill = 00000015
:: cseGen = 0000003F
=> cseOut = 0000003F
!= preMerge = 0000007F, => true
StartMerge BB06
:: cseOut = 0000007F
Merge BB06 and BB01
:: cseIn = 0000007F
:: cseOut = 0000007F
=> cseIn = 00000003
EndMerge BB06
:: cseIn = 00000003
-- cseKill = 00000015
:: cseGen = 00000000
=> cseOut = 00000001
!= preMerge = 0000007F, => true
StartMerge BB03
:: cseOut = 0000007F
Merge BB03 and BB02
:: cseIn = 0000007F
:: cseOut = 0000007F
=> cseIn = 0000003F
EndMerge BB03
:: cseIn = 0000003F
:: cseGen = 00000000
=> cseOut = 0000003F
!= preMerge = 0000007F, => true
StartMerge BB04
:: cseOut = 0000007F
Merge BB04 and BB02
:: cseIn = 0000007F
:: cseOut = 0000007F
=> cseIn = 0000003F
EndMerge BB04
:: cseIn = 0000003F
:: cseGen = 00000000
=> cseOut = 0000003F
!= preMerge = 0000007F, => true
StartMerge BB05
:: cseOut = 0000007F
Merge BB05 and BB04
:: cseIn = 0000007F
:: cseOut = 0000007F
=> cseIn = 0000003F
Merge BB05 and BB03
:: cseIn = 0000003F
:: cseOut = 0000007F
=> cseIn = 0000003F
EndMerge BB05
:: cseIn = 0000003F
:: cseGen = 0000003F
=> cseOut = 0000003F
!= preMerge = 0000007F, => true
StartMerge BB05
:: cseOut = 0000003F
Merge BB05 and BB04
:: cseIn = 0000003F
:: cseOut = 0000003F
=> cseIn = 0000003F
Merge BB05 and BB03
:: cseIn = 0000003F
:: cseOut = 0000003F
=> cseIn = 0000003F
EndMerge BB05
:: cseIn = 0000003F
:: cseGen = 0000003F
=> cseOut = 0000003F
!= preMerge = 0000003F, => false
After performing DataFlow for ValnumCSE's
BB01 cseIn = 00000000, cseGen = 00000003, cseOut = 00000003
BB02 cseIn = 00000003, cseGen = 0000003F, cseOut = 0000003F
BB03 cseIn = 0000003F, cseGen = 00000000, cseOut = 0000003F
BB04 cseIn = 0000003F, cseGen = 00000000, cseOut = 0000003F
BB05 cseIn = 0000003F, cseGen = 0000003F, cseOut = 0000003F
BB06 cseIn = 00000003, cseGen = 00000000, cseOut = 00000001
Labeling the CSEs with Use/Def information
BB01 [000012] Def of CSE #01 [weight=1 ]
BB02 [000111] Use of CSE #01 [weight=1 ]
BB02 [000110] Def of CSE #03 [weight=1 ]
BB02 [000124] Def of CSE #02 [weight=1 ]
BB05 [000144] Use of CSE #01 [weight=1 ]
BB05 [000149] Use of CSE #02 [weight=1 ]
BB05 [000143] Use of CSE #03 [weight=1 ]
************ Trees at start of optValnumCSE_Heuristic()
------------ BB01 [000..016) -> BB06 (cond), preds={} succs={BB02,BB06}
***** BB01
STMT00000 (IL 0x000...0x008)
N008 ( 6, 6) [000005] -A-XG---R--- * ASG int <l:$147, c:$146>
N007 ( 1, 1) [000004] D------N---- +--* LCL_VAR int V01 loc0 d:1 <l:$145, c:$144>
N006 ( 6, 6) [000003] ---XG------- \--* ADD int <l:$147, c:$146>
N004 ( 4, 4) [000001] ---XG------- +--* IND int <l:$143, c:$142>
N003 ( 2, 2) [000088] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000000] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000087] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000002] ------------ \--* CNS_INT int -1 $41
***** BB01
STMT00001 (IL 0x009...0x00F)
N006 ( 4, 4) [000009] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000008] D------N---- +--* LCL_VAR ref V02 loc1 d:1 <l:$1c2, c:$200>
N004 ( 4, 4) [000007] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000090] -------N---- \--* ADD byref $c1
N001 ( 1, 1) [000006] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000089] ------------ \--* CNS_INT int 4 field offset Fseq[_array] $43
***** BB01
STMT00002 (IL 0x010...0x014)
N005 ( 7, 7) [000014] ---X-------- * JTRUE void
N004 ( 5, 5) [000013] N--X---N-U-- \--* LE int <l:$14d, c:$14c>
N002 ( 3, 3) CSE #01 (def)[000012] ---X-------- +--* ARR_LENGTH int <l:$149, c:$148>
N001 ( 1, 1) [000011] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N003 ( 1, 1) [000010] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
------------ BB02 [01C..040) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00003 (IL 0x01C...0x025)
N011 ( 11, 11) [000021] -A-XG---R--- * ASG int $VN.Void
N010 ( 4, 4) [000020] D--XG--N---- +--* IND int $153
N009 ( 2, 2) [000093] -------N---- | \--* ADD byref $c2
N007 ( 1, 1) [000015] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N008 ( 1, 1) [000092] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N006 ( 6, 6) [000019] ---XG------- \--* ADD int <l:$155, c:$154>
N004 ( 4, 4) [000017] ---XG------- +--* IND int <l:$151, c:$150>
N003 ( 2, 2) [000095] -------N---- | \--* ADD byref $c2
N001 ( 1, 1) [000016] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000094] ------------ | \--* CNS_INT int 12 field offset Fseq[_version] $44
N005 ( 1, 1) [000018] ------------ \--* CNS_INT int 1 $45
***** BB02
STMT00004 (IL 0x02A...0x02C)
N006 ( 6, 6) [000025] -A-XG------- * ASG int $VN.Void
N004 ( 4, 4) [000024] D--XG--N---- +--* IND int $145
N003 ( 2, 2) [000097] -------N---- | \--* ADD byref $c0
N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000096] ------------ | \--* CNS_INT int 8 field offset Fseq[_size] $42
N005 ( 1, 1) [000023] ------------ \--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
***** BB02
STMT00005 (IL 0x031...0x038)
N017 ( 24, 25) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N016 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N015 ( 20, 22) CSE #02 (def)[000124] ---XG------- \--* IND ref <l:$341, c:$204>
N014 ( 17, 20) CSE #03 (def)[000110] ---XG------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) CSE #01 (use)[000111] ---X-------- | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref $300
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct <l:$340, c:$380>
N011 ( 4, 4) [000117] -------N---- \--* ADD byref $300
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N010 ( 3, 3) [000119] -------N---- \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000120] -------N---- +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
***** BB02
STMT00006 (IL 0x039...0x03E)
N004 ( 3, 3) [000038] -A---O--R--- * ASG int $1d3
N003 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V05 tmp0 d:1 $1d3
N002 ( 3, 2) [000036] #----O------ \--* IND int $1d3
N001 ( 1, 1) [000035] ------------ \--* LCL_VAR ref V00 this u:1 (last use) $80
***** BB02
STMT00014 (IL ???... ???)
N011 ( 14, 13) [000160] ------------ * JTRUE void
N010 ( 12, 11) [000051] J------N---- \--* EQ int <l:$15e, c:$15d>
N008 ( 10, 9) [000047] n----------- +--* IND int <l:$284, c:$184>
N007 ( 8, 7) [000046] -------N---- | \--* ADD int $15c
N005 ( 7, 6) [000044] #----------- | +--* IND int $1d5
N004 ( 4, 4) [000043] #----------- | | \--* IND int $1d4
N003 ( 2, 2) [000042] -------N---- | | \--* ADD int $15b
N001 ( 1, 1) [000040] ------------ | | +--* LCL_VAR int V05 tmp0 u:1 (last use) $1d3
N002 ( 1, 1) [000041] ------------ | | \--* CNS_INT int 32 $47
N006 ( 1, 1) [000045] ------------ | \--* CNS_INT int 12 $44
N009 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
------------ BB04 [???..???), preds={BB02} succs={BB05}
------------ BB05 [040..052) (return), preds={BB04,BB03} succs={}
***** BB05
STMT00011 (IL 0x040...0x045)
N003 ( 5, 4) [000130] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000128] D------N---- +--* LCL_VAR ref V08 tmp3 d:1 $VN.Null
N001 ( 1, 1) [000129] ------------ \--* CNS_INT ref null $VN.Null
***** BB05
STMT00012 (IL ???...0x04B)
N017 ( 24, 25) [000159] -A-XG------- * ASG ref $VN.Void
N015 ( 20, 22) [000157] *--XG--N---- +--* IND ref $VN.Null
N014 ( 17, 20) CSE #03 (use)[000143] ---XG------- | \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000147] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000146] ------------ | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) CSE #01 (use)[000144] ---X-------- | | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000145] ------------ | | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000148] ----G------- | \--* ADDR byref $300
N012 ( 5, 5) CSE #02 (use)[000149] a---G------- | \--* IND struct <l:$340, c:$381>
N011 ( 4, 4) [000150] -------N---- | \--* ADD byref $300
N005 ( 1, 1) [000151] ------------ | +--* LCL_VAR ref V02 loc1 u:1 (last use) <l:$1c2, c:$200>
N010 ( 3, 3) [000152] -------N---- | \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000153] -------N---- | +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000154] i----------- | | +--* LCL_VAR int V01 loc0 u:1 (last use) <l:$145, c:$144>
N007 ( 1, 1) [000155] -------N---- | | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000156] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N016 ( 3, 2) [000158] ------------ \--* LCL_VAR ref V08 tmp3 u:1 (last use) $VN.Null
***** BB05
STMT00010 (IL 0x050...0x051)
N002 ( 4, 3) [000071] ------------ * RETURN ref $208
N001 ( 3, 2) [000070] ------------ \--* LCL_VAR ref V07 tmp2 u:1 (last use) <l:$340, c:$204>
------------ BB06 [016..01C) (throw), preds={BB01} succs={}
***** BB06
STMT00013 (IL 0x016...0x017)
N003 ( 15, 8) [000083] --CXG------- * CALL void Stack`1.ThrowForEmptyStack $VN.Void
N002 ( 1, 1) [000082] ------------ this in ecx \--* LCL_VAR ref V00 this u:1 (last use) $80
-------------------------------------------------------------------------------------------------------------------
Aggressive CSE Promotion cutoff is 300
Moderate CSE Promotion cutoff is 100
enregCount is 7
Framesize estimate is 0x0000
We have a small frame
Sorted CSE candidates:
CSE #02, {$340, $4 } useCnt=1: [def=100, use=100, cost= 20 ]
:: N015 ( 20, 22) CSE #02 (def)[000124] ---XG------- * IND ref <l:$341, c:$204>
CSE #03, {$c6 , $1ce} useCnt=1: [def=100, use=100, cost= 17 ]
:: N014 ( 17, 20) CSE #03 (def)[000110] ---XG------- * COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
CSE #01, {$241, $1c6} useCnt=2: [def=100, use=200, cost= 3 ]
:: N002 ( 3, 3) CSE #01 (def)[000012] ---X-------- * ARR_LENGTH int <l:$149, c:$148>
Considering CSE #02 {$340, $4 } [def=100, use=100, cost= 20 ]
CSE Expression :
N015 ( 20, 22) CSE #02 (def)[000124] ---XG------- * IND ref <l:$341, c:$204>
N014 ( 17, 20) CSE #03 (def)[000110] ---XG------- \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000114] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) CSE #01 (use)[000111] ---X-------- | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000112] ------------ | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000115] ----G------- \--* ADDR byref $300
N012 ( 5, 5) [000116] a---G--N---- \--* IND struct <l:$340, c:$380>
N011 ( 4, 4) [000117] -------N---- \--* ADD byref $300
N005 ( 1, 1) [000118] ------------ +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N010 ( 3, 3) [000119] -------N---- \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000120] -------N---- +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000121] i----------- | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N007 ( 1, 1) [000122] -------N---- | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000123] ------------ \--* CNS_INT int 8 Fseq[#FirstElem] $42
Aggressive CSE Promotion (300 >= 300)
cseRefCnt=300, aggressiveRefCnt=300, moderateRefCnt=100
defCnt=100, useCnt=100, cost=20, size=22
def_cost=1, use_cost=1, extra_no_cost=42, extra_yes_cost=0
CSE cost savings check (2042 >= 200) passes
Promoting CSE:
lvaGrabTemp returning 9 (V09 rat0) (a long lifetime temp) called for CSE - aggressive.
CSE #02 is single-def, so associated CSE temp V09 will be in SSA
CSE #02 def at [000124] replaced in BB02 with def of V09
optValnumCSE morphed tree:
N021 ( 31, 30) [000125] -A-XG---R--- * ASG ref <l:$341, c:$204>
N020 ( 3, 2) [000109] D------N---- +--* LCL_VAR ref V07 tmp2 d:1 <l:$340, c:$204>
N019 ( 27, 27) [000168] -A-XG------- \--* COMMA ref <l:$341, c:$204>
N017 ( 24, 25) [000166] -A-XG---R--- +--* ASG ref $VN.Void
N016 ( 3, 2) [000165] D------N---- | +--* LCL_VAR ref V09 cse0 d:1 <l:$341, c:$204>
N015 ( 20, 22) [000124] ---XG------- | \--* IND ref <l:$341, c:$204>
N014 ( 17, 20) CSE #03 (def)[000110] ---XG------- | \--* COMMA byref Zero Fseq[Value] <l:$c6, c:$c5>
N004 ( 8, 11) [000114] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void <l:$1d0, c:$1cf>
N001 ( 1, 1) [000113] ------------ | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N003 ( 3, 3) CSE #01 (use)[000111] ---X-------- | | \--* ARR_LENGTH int <l:$149, c:$148>
N002 ( 1, 1) [000112] ------------ | | \--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N013 ( 9, 9) [000115] ----G------- | \--* ADDR byref $300
N012 ( 5, 5) [000116] a---G--N---- | \--* IND struct <l:$340, c:$380>
N011 ( 4, 4) [000117] -------N---- | \--* ADD byref $300
N005 ( 1, 1) [000118] ------------ | +--* LCL_VAR ref V02 loc1 u:1 <l:$1c2, c:$200>
N010 ( 3, 3) [000119] -------N---- | \--* ADD int <l:$159, c:$158>
N008 ( 2, 2) [000120] -------N---- | +--* LSH int <l:$157, c:$156>
N006 ( 1, 1) [000121] i----------- | | +--* LCL_VAR int V01 loc0 u:1 <l:$145, c:$144>
N007 ( 1, 1) [000122] -------N---- | | \--* CNS_INT int 2 $46
N009 ( 1, 1) [000123] ------------ | \--* CNS_INT int 8 Fseq[#FirstElem] $42
N018 ( 3, 2) [000167] ------------ \--* LCL_VAR ref V09 cse0 u:1 <l:$341, c:$204>
ERRORLEVEL=1073741855
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment