Arathi Hardware Description Language

AHdl.g4

grammar AHdl;

// 语法

module: inputs outputs parts wires EOF;

inputs: INPUTS input (CM input)* CM ES;

outputs: OUTPUTS output (CM output)* CM ES;

parts: PARTS part (CM part)* CM ES;

wires: WIRES wire (CM wire)* CM ES;

input
    : inputPinId
    | inputBusId BL busSize BR
    ;

output
    : outputPinId
    | outputBusId BL busSize BR
    ;

part
    : partType partId+
    ;

wire
    : wireStart TO wireTarget
    ;

wireStart
    : pinValue
    | inputPin
    | inputBus
    | partId DT outputPin
    | partId DT outputBus
    ;

wireTarget
    : outputPin
    | outputBus
    | partId DT inputPin
    | partId DT outputPin
    ;

inputPin
    : inputPinId
    | inputBusId BL pinIndex BR
    ;

inputBus
    : inputBusId
    | inputBusId BL pinRangeStart RG pinRangeEnd BR
    ;

outputPin
    : outputPinId
    | outputBusId BL pinIndex BR
    ;

outputBus
    : outputBusId
    | outputBusId BL pinRangeStart RG pinRangeEnd BR
    ;

inputPinId: id;
inputBusId: id;
outputPinId: id;
outputBusId: id;
partId: id;

busSize: number;
pinValue: number;
pinIndex: number;
pinRangeStart: number;
pinRangeEnd: number;

id: ID;
partType: PART_TYPE;
number: NUMBER;

// 词法

INPUTS: 'Inputs:';
OUTPUTS: 'Outputs:';
PARTS: 'Parts:';
WIRES: 'Wires:';

CM: ',';  // comma
ES: ';';  // end of segment
BL: '[';  // bucket left
BR: ']';  // bucket right
TO: '->'; // link to
DT: '.';  // dot
RG: ':';  // range

ID: [a-z][0-9A-Z_a-z]*;
PART_TYPE: [A-Z][0-9A-Z_a-z]*;
NUMBER: [0=9]+;

WS: [ \t] -> skip;