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M1 Max ATCPHY efuses
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| OUTDATED PLEASE GO TO https://github.com/rqou/linux/tree/atc-m1max | |
| if instance == 0 | |
| AUSPLL_CORE_AUSPLL_CFG_DCO_EFUSE_SPARE.RODCO_ENCAP_EFUSE = efuse 0xa10 >> 25 | |
| AUSPLL_CORE_AUSPLL_CFG_DCO_EFUSE_SPARE.RODCO_BIASADJ_EFUSE = efuse 0xa10 >> 22 | |
| AUSPLL_CORE_AUSPLL_CFG_FRACN_CAN.DLL_CAL_START_CAPCODE_EFUSE = efuse 0xa10 >> 30 | |
| AUSPLL_CORE_AUSPLL_CFG_CLKOUT_DTC_VREG.DTC_VREG_ADJUST_EFUSE = efuse 0xa10 >> 27 | |
| CIO3PLL_CORE_CIO3PLL_CFG_DCO_NCTRL.DCO_COARSEBIN_EFUSE0 = efuse 0xa14 >> 5 | |
| CIO3PLL_CORE_CIO3PLL_CFG_DCO_NCTRL.DCO_COARSEBIN_EFUSE1 = efuse 0xa14 >> 11 | |
| CIO3PLL_CORE_CIO3PLL_CFG_FRACN_CAN.DLL_CAL_START_CAPCODE_EFUSE = efuse 0xa14 >> 17 | |
| CIO3PLL_CORE_CIO3PLL_CFG_CLKOUT_DTC_VREG.DTC_VREG_ADJUST_EFUSE = efuse 0xa14 >> 19 | |
| AUS_CMN_SHM_BLK_VREG_REG_0.VREG_TRIM = efuse 0xa14 >> 0 | |
| if instance == 1 | |
| AUSPLL_CORE_AUSPLL_CFG_DCO_EFUSE_SPARE.RODCO_ENCAP_EFUSE = efuse 0xa18 >> 3 | |
| AUSPLL_CORE_AUSPLL_CFG_DCO_EFUSE_SPARE.RODCO_BIASADJ_EFUSE = efuse 0xa18 >> 0 | |
| AUSPLL_CORE_AUSPLL_CFG_FRACN_CAN.DLL_CAL_START_CAPCODE_EFUSE = efuse 0xa18 >> 8 | |
| AUSPLL_CORE_AUSPLL_CFG_CLKOUT_DTC_VREG.DTC_VREG_ADJUST_EFUSE = efuse 0xa18 >> 5 | |
| CIO3PLL_CORE_CIO3PLL_CFG_DCO_NCTRL.DCO_COARSEBIN_EFUSE0 = efuse 0xa18 >> 15 | |
| CIO3PLL_CORE_CIO3PLL_CFG_DCO_NCTRL.DCO_COARSEBIN_EFUSE1 = efuse 0xa18 >> 21 | |
| CIO3PLL_CORE_CIO3PLL_CFG_FRACN_CAN.DLL_CAL_START_CAPCODE_EFUSE = efuse 0xa18 >> 27 | |
| CIO3PLL_CORE_CIO3PLL_CFG_CLKOUT_DTC_VREG.DTC_VREG_ADJUST_EFUSE = efuse 0xa18 >> 29 | |
| AUS_CMN_SHM_BLK_VREG_REG_0.VREG_TRIM = efuse 0xa18 >> 10 | |
| if instance == 2 | |
| AUSPLL_CORE_AUSPLL_CFG_DCO_EFUSE_SPARE.RODCO_ENCAP_EFUSE = efuse 0xa1c >> 13 | |
| AUSPLL_CORE_AUSPLL_CFG_DCO_EFUSE_SPARE.RODCO_BIASADJ_EFUSE = efuse 0xa1c >> 10 | |
| AUSPLL_CORE_AUSPLL_CFG_FRACN_CAN.DLL_CAL_START_CAPCODE_EFUSE = efuse 0xa1c >> 18 | |
| AUSPLL_CORE_AUSPLL_CFG_CLKOUT_DTC_VREG.DTC_VREG_ADJUST_EFUSE = efuse 0xa1c >> 15 | |
| CIO3PLL_CORE_CIO3PLL_CFG_DCO_NCTRL.DCO_COARSEBIN_EFUSE0 = efuse 0xa1c >> 25 | |
| CIO3PLL_CORE_CIO3PLL_CFG_DCO_NCTRL.DCO_COARSEBIN_EFUSE1 = (efuse 0xa1c >> 31) | ((efuse 0xa20 << 1) & 0b111110) | |
| CIO3PLL_CORE_CIO3PLL_CFG_FRACN_CAN.DLL_CAL_START_CAPCODE_EFUSE = efuse 0xa20 >> 5 | |
| CIO3PLL_CORE_CIO3PLL_CFG_CLKOUT_DTC_VREG.DTC_VREG_ADJUST_EFUSE = efuse 0xa20 >> 7 | |
| AUS_CMN_SHM_BLK_VREG_REG_0.VREG_TRIM = efuse 0xa1c >> 20 | |
| if instance == 3 | |
| AUSPLL_CORE_AUSPLL_CFG_DCO_EFUSE_SPARE.RODCO_ENCAP_EFUSE = efuse 0xa20 >> 23 | |
| AUSPLL_CORE_AUSPLL_CFG_DCO_EFUSE_SPARE.RODCO_BIASADJ_EFUSE = efuse 0xa20 >> 20 | |
| AUSPLL_CORE_AUSPLL_CFG_FRACN_CAN.DLL_CAL_START_CAPCODE_EFUSE = efuse 0xa20 >> 28 | |
| AUSPLL_CORE_AUSPLL_CFG_CLKOUT_DTC_VREG.DTC_VREG_ADJUST_EFUSE = efuse 0xa20 >> 25 | |
| CIO3PLL_CORE_CIO3PLL_CFG_DCO_NCTRL.DCO_COARSEBIN_EFUSE0 = efuse 0xa24 >> 3 | |
| CIO3PLL_CORE_CIO3PLL_CFG_DCO_NCTRL.DCO_COARSEBIN_EFUSE1 = efuse 0xa24 >> 9 | |
| CIO3PLL_CORE_CIO3PLL_CFG_FRACN_CAN.DLL_CAL_START_CAPCODE_EFUSE = efuse 0xa24 >> 15 | |
| CIO3PLL_CORE_CIO3PLL_CFG_CLKOUT_DTC_VREG.DTC_VREG_ADJUST_EFUSE = efuse 0xa24 >> 17 | |
| AUS_CMN_SHM_BLK_VREG_REG_0.VREG_TRIM = (efuse 0xa20 >> 30) | ((efuse 0xa24 << 2) & 0b11100) |
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