stoperica_tb.vhd

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-- Company: 
-- Engineer:
--
-- Create Date:   03:23:17 11/16/2013
-- Design Name:   
-- Module Name:   /home/nikola/xilinx_ws/stoperica/stoperica_tb.vhd
-- Project Name:  stoperica
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: stoperica
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY stoperica_tb IS
END stoperica_tb;
 
ARCHITECTURE behavior OF stoperica_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT stoperica
    PORT(
         iCLK : IN  std_logic;
         iRST : IN  std_logic;
         iSTOP : IN  std_logic;
         iSTART : IN  std_logic;
         iCOUNTINUE : IN  std_logic;
         oSEC : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal iCLK : std_logic := '0';
   signal iRST : std_logic := '0';
   signal iSTOP : std_logic := '0';
   signal iSTART : std_logic := '0';
   signal iCOUNTINUE : std_logic := '0';

 	--Outputs
   signal oSEC : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant iCLK_period : time := 41.6666666 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: stoperica PORT MAP (
          iCLK => iCLK,
          iRST => iRST,
          iSTOP => iSTOP,
          iSTART => iSTART,
          iCOUNTINUE => iCOUNTINUE,
          oSEC => oSEC
        );

   -- Clock process definitions
   iCLK_process :process
   begin
		iCLK <= '0';
		wait for iCLK_period/2;
		iCLK <= '1';
		wait for iCLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for iCLK_period*10;

      -- insert stimulus here 
	  iRST <= '1';
	  iSTART <= '1';
	  wait for iCLK_period;
	  iSTART <= '0';
	  wait for 2 us;
	  iSTART <= '1';
	  wait for iCLK_period;
	  iSTART <= '0';
	  wait for 2.5 us;
	  iSTOP <= '1';
	  wait for iCLK_period;
	  iSTOP <= '0';
	  wait for 2 us;
	  iCOUNTINUE <= '1';
	  wait for 2 us;
	  iCOUNTINUE <= '0';
      wait;
   end process;

END;