Etripator architecture specification (candidate)

pcengine.json

architecture pcengine {
	include: "pcengine.lua",

	wordsize:  8b,
	fetchsize: 8b,

	endian: LSB,

	memory: [
		mem_bss: { name: "work ram",  size:  8KB, start: 0x1f0200 },
		mem_sp:  { name: "stack",     size: 256B, start: 0x1f0100 },
		mem_zp:  { name: "zero page", size: 256B, start: 0x1f0000 }
	],

	register: [
		A:  { name: "A",   size:  8b },
		X:  { name: "X",   size:  8b },
		Y:  { name: "Y",   size:  8b },
		PC: { name: "PC",  size: 16b },
		SP: { name: "SP",  size:  8b },
		S:  { name: "S",   size:  8b },
		M0: { name: "mpr0", size: 8b },
		M1: { name: "mpr1", size: 8b },
		M2: { name: "mpr2", size: 8b },
		M3: { name: "mpr3", size: 8b },
		M4: { name: "mpr4", size: 8b },
		M5: { name: "mpr5", size: 8b },
		M6: { name: "mpr6", size: 8b },
		M7: { name: "mpr7", size: 8b },
	],

	format: [
		fmt_op:          { op: 8b                            },
		fmt_op_b0:       { op: 8b, b0:  8b                   },
		fmt_op_b0_b1:    { op: 8b, b0:  8b, b1:  8b          },
		fmt_op_b0_w0:    { op: 8b, b0:  8b, w0: 16b          },
		fmt_op_w0:       { op: 8b, w0: 16b                   },
		fmt_op_w0_w1_w2: { op: 8b, w0: 16b, w1: 16b, w2: 16b }
	]
 
	instruction: [
		brk: [
			{
				format: op,
				filter: "op==0x00",
				asm: "brk",
				cycles: 8,
				code: [
					"PC = PC + 2",
					"mem_sp[SP  ] = high(PC)",
					"mem_sp[SP+1] = low(PC)",
					"SP = SP + 2",
					"PC = pce_get_word_physical(0xFFF6)",
					"set_t_flag(0)",
					"set_b_flag(1)",
					"set_d_flag(0)",
					"set_i_flag(1)",
				]
			},
		]
		ora: [
			{
				format: op_b0,
				filter: "op=0x01"
				asm: { out: "asl (%imm, X)", args: [b0] },
				cycles: 7,
				code: [
					"zp_offset = (b0 + X) & 0xff",
					"addr = pce_get_byte_zp(zp_offset)",
					"dummy = pce_get_byte_logical(addr)",
					"A = A | dummy",
					"set_t_flag(0)",
					"set_z_flag((A==0) ? 1 : 0)",
					"set_n_flag((A & 0x80) ? 1 : 0)"
				]
			},
			{
				format: op_b0,
				filter: "op=0x05",
				asm: { out: "ora %imm", args: [b0] },
				cycles: 4
			},
			{
			 	format: op_b0,
				filter: "op=0x09",
				asm: { out: "ora  #%imm", args: [b0] },
				cycles: 2
			},
			{
				format: op_w0,
				filter: "op=0x0d",
				asm: { out: "ora %imm", args: [w0] },
				cycles: 5
			},
			{
				format: op_b0,
				filter: "op=0x11",
				asm: { out: "ora (%imm), Y", args: [b0] },
				cycles: 7
			},
			{
				format: op_b0,
				filter: "op=0x12",
				asm: { out: "ora (%imm)", args: [b0] },
				cycles: 7
			}
			{
				format: op_b0,
				filter: "op=0x15",
				asm: { out: "ora %imm, X", args: [b0] },
				cycles: 4
			}
		],
		tsb: [
			{
				format: op_b0,
				filter: "op=0x04",
				asm: { out: "tsb %imm", args: [b0] },
				cycles: 6
			},
			{
				format: op_w0,
				filter: "op=0x0c",
				asm: { out: "tsb %imm", args: [w0] },
				cycles: 7
			}
		],
		asl: [
			{ 
				format: op_b0,
				filter: "op=0x06",
				asm: { out: "asl %imm", args: [b0] },
				cycles: 6
			}
			{
				format: op,
				filter: "op=0x0a",
				asm: { out: "asl A" },
				cycles: 2
			}
			{ 
				format: op_w0,
				filter: "op=0x0e",
				asm: { out: "asl %imm", args: [w0] },
				cycles: 7
			}
		],
		rmb0: [
			{
				format: op_b0,
				filter: "op=0x07",
				asm: { out: "rmb0 %imm", args: [b0] },
				cycles: 7
			}
		],
		bbr0: [
			{
				format: op_b0_b1,
				filter: "op=0x0f",
				asm: { out: "bbr0 %imm, %addr(rel)", args: [b0, b1] },
				cycles: 6
			}
		],
	}
}