Bsingstad

import tensorflow as tf
import numpy as np
import matplotlib.pyplot as plt

def grad_cam(layer_name, data, model):
    grad_model = tf.keras.models.Model(
    [model.inputs], [model.get_layer(layer_name).output, model.output]
)
    last_conv_layer_output, preds = grad_model(data)

Bsingstad

def generate_y():
    while True:
        for i in range(len(y_train)):
            y= y_train[i]
            yield y


def generate_X():
    while True:
        with open("/kaggle/input/physionet-csv-april-2020/ECG_long_signals_train.csv") as f:

Bsingstad

------------------------------------------------
-- A comparator that compares vector A and B  --
-- equal is set to 1 when A and B are equal   --
-- equal is 0 when others                     --
------------------------------------------------
library ieee;                                	
use ieee.std_logic_1164.all;           	
                                             		
entity comp is 
	port (                 	

Bsingstad

def tenBase_to_binary_converter(x):
    y =''
    while (x>=1):
        #print(x)
        if (x % 2) == 0:
            y+='0'
        else:
            y+='1'
        x=x//2
    return y[::-1] #reverses the sting

Bsingstad

-- This example shows how to synchronize a external signal with its own clock
import lirabry;
use.ieee.std_logic.1146.all;

entity synch is
  port(
    inputSignalA  : in std_logic;
    clk           : in std_logic;
    OutputSignalC : out std_logic
    );

Bsingstad

architecture behaviour of edge_detector is
    signal B : std_logic := 0;
    begin
        --edge detector
        p_behav: process (clk)
        begin
            if rising_edge(clk) then
                B <= A;
            end if;
        end process;

Bsingstad

library IEEE;
use IEEE.std_logic_1164.use;

entity register_vhdl is
    port(
        clk         : in std_logic;
        inngang     : in std_logic;
        utgang      : out std_logic;
        LD          : in std_logic
    );

Bsingstad

library IEEE;
use IEEE.std_logic_1164.all;

entity multiplexer is
    port(
    inngangA    : in  std_logic;
    inngangB    : in std_logic;
    inngangC    : in std_logic;
    inngangD    : in std_logic;
    Utgang      : out std_logic;

Bsingstad

entity i2c_master is
    generic(
        GC_SYSTEM_CLK : integer := 50000000;
        GC_I2C_CLK : integer := 2000000  
    );
    port(
        clk : in std_logic;
        rst_n : in std_logic;
        valid : in std_logic;
        addr : in STD_logic_vector(6 downto 0);

Bsingstad

#include <string.h>
#include <stdio.h>
#include <system.h>
#include <altera_avalon_pio_regs.h> 
#include "includes.h"
#include "i2c_avalon_mm_if.h"
#include "adxl345.h"
#include "unistd.h"
#include <sys/alt_irq.h> 
#include <io.h>