References:
- https://static.docs.arm.com/ddi0487/db/DDI0487D_b_armv8_arm.pdf
- https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools
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Plugin
- Implementation of a parser for Aarch64 implementing the standard ARM assembly dialect, mixed with dynasm dynamic register, immediate and label specification.
- Creation of a database of ARM instruction encoding data.
- Implementation of a compiler that combines the parse and instruction data to emit code targetting the runtime ARM backend.
- Add support for relocations in directives.
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Runtime
- Addition of a new backend, based on the x64 backend as both architectures feature PIC and relative jumps smaller than the total address space.
- Implementation of a relocation model for Aarch64.
- Runtime helpers needed to assist in compiling the different kind of immediates Aarch64 assembly supports.
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Tests
- Generation of a test suite that uses the ARM instruction encoding data to generate a large suite of expectedly passing and failing test cases. These will be ran by both dynasm-aarch64 and a reference assembler to ensure compliance of the instruction encoding data.
- A set of custom-written test cases and targeting the relocation infrastructure of the dynasm aarch64 backend which can be tested on an actual aarch64 machine.
- Porting of several of the current x64 examples to aarch64 to demonstrate the readyness of the backend.
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Documentation
- Generating a listing of supported instructions
- Documenting the syntax and functionality of the Aarch64 backend.
Time estimations include the time spent debugging the features after their initial implementation.
This is expected to be quite straightforward, as Aarch64 assembly is significantly simpler than x64 assembly. Some complexity is present due to the presence of operand modifiers, different addressing modes and vector register lane notation.
While the instruction count of ARM is lower and the instructions are fixed width, the encodings themselves feature large amounts of small bitfields. To simplify the process and ensure correctness this instruction listing will be generated by processing the data provided by ARM in their Machine-Readable Architecture specification. This specification is however quite complex, and extracting the needed data in an easy format for the compiler will require all features of the instruction encoding and assembly specification to be processed.
The compiler will validate the parsed assembly data with the data provided by the instruction listing. As Aarch64 assembly has a very rigid encoding format, this is expected to be mostly straightforward validation of the assembly to the instruction listing, and encoding the required data in their bitfields. The major complication here will be handling PC-relative bitfields and emitting their respective relocations.
To support Aarch64 literal pools which are necessary for efficient absolute jumps, support needs to be added for emitting relocations into data directives.
Most of the runtime backend can be ported over directly from the x64 backend. Relocation handling will need to be adjusted to match the output of the compiler, and several runtime helpers need to be added to support fallible conversions for encoding several Aarch64 features (logical immediates, shifted immediates)
A tool to generate a large amount of test cases is needed, as well as integration of another Aarch64 assembler toolchain to validate the results.
These will be written early on while engineering the parser and compiler to ensure all features are operational in their basic forms.
I have a decent amount of experience with ARM assembly (although mostly ARMv7/Thumb) so I do not expect to encounter significant issues during this step.
Based on how long writing documentation for the x64 backend took.