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SpudMac: Cross-Arch x86-64 and Aarch64 GAS Macros with help from CPP
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README.md

SpudMacs: Cross-Architecture GAS & CPP Macros

Introduction

In this gist I present two files, spudmacs.x86-64.S and spucmacs.aarch64.S. These two files contain identically-named and signatured GAS and CPP macros (in the case of derived macros) that achieve the same task in both Aarch64 and x86-64 Assmbly languages. There are two types of macros in both files:

  • Gnu Aassembler Macros (base and derived)
  • C Prerprocessor Macros (Idents and Literals)

These macros aim to make cross-arch assembly programs possible. You can expand on them yourself based on your needs, especially with CPP macros that do not cover all the basis.

There exists between 225 and 228 GAS macros and 123 to 142 CPP macros. They cover common literal numbers and basic instruction idents, and register idents.

These macros follow a strict naming pattern, which I discuss in a bit. The number of registers, of course, differs across these two archs, and some macros across these the two ignore arguments they do not need. For example there is only one clobbered register in x64 (r11) but a64 has a whopping 11 clobbered registers! Or x64 has an exchange instruction where as a64 does not, so the temp argument given to the exchange macro is ignored in x64.

The x64 innards follow AT&T syntax, but to change this you just need to change the base macros. The base macros are some 6 o 8 macros which the derived macros are based on. Also you should note that in making of these macros, I tried to make x86-64 compliant to Aarch64, not the other way around. So in the arguments, operee comes first, then the operand --- and also, it has macros for post and pre-increment of addresses or pair-load nand pair-store.

Below is a table discussing all the macros.

Disclaimer

These macros are not entirely tested. I just managed to test a few. Do not use them without thorough testing please. I am not to be held responsible for failure of the code released in this Gist.

Naming Convention - CPP Macros

Macro Type Prefix
Positive Literal Number IDT_NP*
Negative Literal Number IDT_NN*
Instruction IDT_OP*
Condtional Branchers IDT_COND*
Double Register REG_D*
Word Register REG_W*
Byte Register REG_B*

Naming Convention - GAS Macros

Base Operation Macros

For the sake of mnemonics, let's contract the following:

  • O -> Operator (<opt>)
  • X -> Operand (<opd>)
  • Y -> Operee (<ope>)
  • V -> Value (<val>)
  • T -> Transfer (<N/A>)
  • S -> Shift (shop/shn)
  • N -> Nothing

The base macros are:

Name Action Arguments
mOXNNNNB Operate on oprand <opd>, <opt>
mOXOXNNB Operate on two operands with two operators <opd1>, <opt1>, <opd2>, <opt2>
mOXVTNNB Operate on operand with value, then transfer the value to operand <opd>, <val>, <opt>
mOXYVTNB Operate on operand with value, then transfer the value to opde ope, <opd>, <val>, <opt>
mOXYVSTB Operate on operand with value, the shift the result by shn (operation being shop), and transfed to opde ope, <opd>, <val>, <shop>, <shn>, <opt>
mOXYTNNB Transfer operand to opde with the specified operation <ope>, <opd>, <opt>

We can use these macros to derive a composite of different macros.

Base Memory Macros

As previously stated, SpudMacros try to mimic Aarch64 instructions with x86-64 instructions, not vice versa. Therefore we have pre and post index macros, pair load and store, and offset loading and storing. Aarch64 has ldrb/h/w and strb/h/w for loading and storing from and to the memory but x86-64 just uses movb/h/w/d. In order to achive pre and post indexing, the given index is adderess added to the address in x64.

However, the placement of address and the register changes across the two arches. Therefore we need extra macros for it. We cannot use C Preprocessor to get out of this because at the end there needs to be different macros. GAS' .if directive could help but at the end the derived macros need to change.

For singlet loading and storing, the macros in spudmacs.aarch64.S begin with mMEM* and they have prefixes PIDX, IDXP and OFST for pre/post indexing and offset loading. The arguments are <source/desstination>, <address>, <index/offset> and <operation> where operation can be any of the aforementioned.

In spudmacs.x86-64.S we have mMML* and MMP* with the same suffices for loading and storing.

For pair loading and storing, in A64 we have the same name, exept with mem changed to mmp, and it takes an extra destination --- right after the first one. In X64 we have MPL and MPS.

Base Stack Macros

Since Aarch64 does not have push and pop, we must use memory indexing to load and store to sp. These macros are only hold meaning in Aarch64 as in x86-64 it just uses push for all sizes. They are mPSHBASE and mPOPBASE.

Derived Macros

All derivec macros begin with m. I recommend when calling the macro, as I have done with base macros, to write the initial m in small letters, and the rest in capital letters.

Derived Transfer Macros

Prefix: mTRN*

Suffixes: |Suffix|Operation|Arguments| |*MOVE|Move register opd to register ope|<ope, opd>| |*MOVZ|Zero out ope, and move opd to it|<ope, opd>| |*MOVN|Bitwise-NOT opd and move to ope|<ope, opd>|

Derived Operation Macros

The operation macros come in three types:

  • mTRO*<ope, opd, val> -> Do the operation on opd with val and then move to ope.
  • mINP*<opd, val> Do the operation on opd with val and move to itself
  • mSHL* and mSHR*<ope, opd, val, shn> -> Do the operation on opd with val, then shift left/right by shn and move to ope.

Operations are:

ADD<U/S>, SUB<U/S>, AND<U/S>, ORR<U/S>, XOR<U/S>, and for INP and TRO we have LSHL and LSHR and LROR.

Derived Memory Macros

Macro pattern for memory macros is mmem<l/s><b/h/w/d>/<idxp/pidx/ofst>. And for pair just replace mem with mmp. The arguments to them are <reg, addr, idx> and <reg1, reg2, addr, idx>.

Derived Stack Macros

The pattern for them is m<PSH/POP><BYTE/HWRD/FWRD/DWRD>.

Derived Conditional Jump Macros

There's two types. Single condition and double contition jump. The pattern for single jump is msjcnd<cond>. For double jump it's mpjc<cond1><cond2>. Condition can be one of EQ, NE, CC, CS, PS, NG, GT, GE, LT, LE. PS means positive and NG means negative, the rest are obvious. The arguments to them are, as follows: <label> and <label1, label2> .

MJMP2LBL jumps to label, MCMPREGS<reg1, reg2> compares registers,MTSTPAIR<reg, ope> tests a pair of registers and MTSTSELF<reg> tests registers with itself.

Miscellaneous Derived Macros

MSRSTART<label> and MSRRETURN do the necessary C convenction for entering and exiting subrouting. MSYSCALL does a syscall. MXCHNGRG<reg> exchanges registers and MREGZERO<reg> zeroes out register.

How to Run

The files have an .S extension so when you call gcc or clang on them, they will preprocess. If you wish to use as itself on them, you can do cpp <file> | as.

License

Both files are released under MIT license. You may say small thing such as this may not need a license, and I would say yes, but it makes me feel good to add license to things.

Other Projects

I did not use code generation with this as much as I wanted to. I was not at all aware of the cpp utility and its uses, and I onyl used Python to generate the double condition jump macros. I wish to write an entire x86-64 and Aarch64 Assembly preprocessor in Python.

I have a lot of projects in my Github profile. Are you aware of PoxHash. Or how about Zinteger. In fact what I am going to do next to test out recreating zinteger.py using CPP.

Have a nice day, and take care.

Raw
spudmacs.aarch64.S
// Copyright (c) 2023 Chubak Bidpaa
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
// LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
// OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
// WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define LIT_NZERO #0
#define LIT_NP01 #1
#define LIT_NP02 #2
#define LIT_NP04 #4
#define LIT_NP08 #8
#define LIT_NP16 #16
#define LIT_NP32 #32
#define LIT_NP64 #64
#define LIT_NN01 #-1
#define LIT_NN02 #-2
#define LIT_NN04 #-4
#define LIT_NN08 #-8
#define LIT_NN16 #-16
#define LIT_NN32 #-32
#define LIT_NN64 #-64
#define LIT_NPXF2 #0xff
#define LIT_NPXF4 #0xffff
#define LIT_NPXF6 #0xffffff
#define LIT_NPXF8 #0xffffffff
#define LIT_NPXF10 #0xffffffffff
#define LIT_NPXF12 #0xffffffffffff
#define LIT_NPXF14 #0xffffffffffffff
#define LIT_NPXF16 #0xffffffffffffffff
#define LIT_NNX802 #-0x80
#define LIT_NNX804 #-0x8000
#define LIT_NNX806 #-0x800000
#define LIT_NNX808 #-0x80000000
#define LIT_NNX8010 #-0x8000000000
#define LIT_NNX8012 #-0x800000000000
#define LIT_NNX8014 #-0x80000000000000
#define LIT_NNX8016 #-0x8000000000000000
#define IDT_OPJUMP bl
#define IDT_OPLDDW ldr
#define IDT_OPSTDW str
#define IDT_OPTEST tst
#define IDT_OPMOVE mov
#define IDT_OPADDU add
#define IDT_OPSUBU sub
#define IDT_OPANDU and
#define IDT_OPORRU orr
#define IDT_OPXORU eor
#define IDT_OPORRN orn
#define IDT_OPORRS ors
#define IDT_OPLSHL lsl
#define IDT_OPLSHR lsr
#define IDT_OPLROR ror
#define IDT_OPCOMP cmp
#define IDT_opdTR ret
#define IDT_OPSYSC svc
#define IDT_OPADDS adds
#define IDT_OPSUBS subs
#define IDT_OPANDS ands
#define IDT_OPXORS eors
#define IDT_OPMOVZ movz
#define IDT_OPMOVN movn
#define IDT_OPLDBY ldrb
#define IDT_OPSTBY strb
#define IDT_OPLDHW ldrh
#define IDT_OPSTHW strh
#define IDT_OPLDFW ldrw
#define IDT_OPSTFW strw
#define IDT_OPLDRP ldrp
#define IDT_OPSTRP strp
#define IDT_CONDEQ b.eq
#define IDT_CONDNE b.ne
#define IDT_CONDLT b.lt
#define IDT_CONDGT b.gt
#define IDT_CONDLE b.le
#define IDT_CONDGE b.ge
#define IDT_CONDNG b.mi
#define IDT_CONDPS b.pl
#define IDT_CONDOV b.vs
#define IDT_CONDNV b.vc
#define IDT_CONDCS b.cs
#define IDT_CONDCC b.cc
#define IDT_CONDHI b.hi
#define REG_DSYCNR x8
#define REG_opePTR sp
#define REG_DLNPTR lr
#define REG_DARG01 x0
#define REG_DARG02 x1
#define REG_DARG03 x2
#define REG_DARG04 x3
#define REG_DARG05 x4
#define REG_DARG06 x5
#define REG_DARG07 x6
#define REG_DARG08 x7
#define REG_DSRETR x0
#define REG_DCLB01 x8
#define REG_DCLB02 x9
#define REG_DCLB03 x10
#define REG_DCLB04 x11
#define REG_DCLB05 x12
#define REG_DCLB06 x13
#define REG_DCLB07 x14
#define REG_DCLB08 x15
#define REG_DCLB09 x16
#define REG_DCLB10 x17
#define REG_DCLB11 x18
#define REG_DCSV01 x19
#define REG_DCSV02 x20
#define REG_DCSV03 x21
#define REG_DCSV04 x22
#define REG_DCSV05 x23
#define REG_DCSV06 x24
#define REG_DCSV07 x25
#define REG_DCSV08 x26
#define REG_DCSV09 x27
#define REG_DCSV10 x28
#define REG_DGRNDR xzr
#define REG_WSYCNR w8
#define REG_WARG01 w0
#define REG_WARG02 w1
#define REG_WARG03 w2
#define REG_WARG04 w3
#define REG_WARG05 w4
#define REG_WARG06 w5
#define REG_WARG07 w6
#define REG_WARG08 w7
#define REG_WSRETR w0
#define REG_WCLB01 w8
#define REG_WCLB02 w9
#define REG_WCLB03 w10
#define REG_WCLB04 w11
#define REG_WCLB05 w12
#define REG_WCLB06 w13
#define REG_WCLB07 w14
#define REG_WCLB08 w15
#define REG_WCLB09 w16
#define REG_WCLB10 w17
#define REG_WCLB11 w18
#define REG_WCSV01 w19
#define REG_WCSV02 w20
#define REG_WCSV03 w21
#define REG_WCSV04 w22
#define REG_WCSV05 w23
#define REG_WCSV06 w24
#define REG_WCSV07 w25
#define REG_WCSV08 w26
#define REG_WCSV09 w27
#define REG_WCSV10 w28
#define REG_WGRNDR wzr
.section base_operation_macros
.macro moxnnnnb opd, optr
\optr \opd
.endm
.macro moxoxnnb opd1, optr1, opd2, optr2
\optr1 \opd1
\optr2 \opd2
.endm
.macro ooxyvtnb ope, opd, optr, val
\optr \ope, \opd, \val
.endm
.macro ooxvtnnb opd, val, optr
\optr \opd, \opd, \val
.endm
.macro moxytnnb ope, opd, optr
\optr \ope, \opd
.endm
.macro moxyvstb ope, opd, optr, val, shoptr, shn
\optr \ope, \opd, \val, \shop \shn
.endm
.section base_singlet_macros
.macro mmemidxp reg, addr, idx, optr
\optr \ope, [\addr], \idx
.endm
.macro mmempidx reg, addr, idx, optr
\optr \ope, [\addr, \idx]!
.endm
.macro mmemofst reg, addr, idx, optr
\optr \ope, [\addr, \idx]
.endm
.section base_pair_macros
.macro mmmpidxp reg1, reg2, addr, idx, optr
\optr \ope1, \ope2, [\addr], \idx
.endm
.macro mmmppidx reg1, reg2, addr, idx, optr
\optr \ope1, \ope2, [\addr, \idx]!
.endm
.macro mmmpofst reg1, reg2, addr, idx, optr
\optr \ope1, \ope2, [\addr, \idx]
.endm
.section base_stack_macros
.macro mpshbase reg, optr, idx
\optr \reg, [REG_opePTR, \idx]!
.endm
.macro mpopbase reg, optr, idx
\optr \reg, [REG_opePTR], \idx
.endm
.section transfer_operation_macros
.macro mtrnmove ope, opd
mOXYTNNB \ope, \opd, IDT_OPMOVE
.endm
.macro mtrnmovz ope, opd
mOXYTNNB \ope, \opd, IDT_OPMOVZ
.endm
.macro mtrnmovn ope, opd
mOXYTNNB \ope, \opd, IDT_OPMOVN
.endm
.section inplace_operation_macros
.macro minpaddu opd, val
oOXVTNNB \opd, \val, IDT_OPADDU
.endm
.macro minpadds opd, val
oOXVTNNB \opd, \val, IDT_OPADDS
.endm
.macro minpsubu opd, val
oOXVTNNB \opd, \val, IDT_OPSUBU
.endm
.macro minpsubs opd, val
oOXVTNNB \opd, \val, IDT_OPSUBS
.endm
.macro minpandu opd, val
oOXVTNNB \opd, \val, IDT_OPANDU
.endm
.macro minpands opd, val
oOXVTNNB \opd, \val, IDT_OPADNS
.endm
.macro minporru opd, val
oOXVTNNB \opd, \val, IDT_OPORRU
.endm
.macro minporrs opd, val
oOXVTNNB \opd, \val, IDT_OPORRS
.endm
.macro minpxoru opd, val
oOXVTNNB \opd, \val, IDT_OPXORU
.endm
.macro minpxors opd, val
oOXVTNNB \opd, \val, IDT_OPXORS
.endm
.macro minplshl opd, val
oOXVTNNB \opd, \val, IDT_OPLSHL
.endm
.macro minplshr opd, val
oOXVTNNB \opd, \val, IDT_OPLSHR
.endm
.macro minplror opd, val
oOXVTNNB \opd, \val, IDT_OPLROR
.endm
.section transfer_operation_macros
.macro mtroaddu ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPADDU
.endm
.macro mtroadds ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPADDS
.endm
.macro mtrosubu ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPSUBU
.endm
.macro mtrosubs ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPSUBS
.endm
.macro mtroandu ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPANDU
.endm
.macro mtroands ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPADNS
.endm
.macro mtroorru ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPORRU
.endm
.macro mtroorrs ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPORRS
.endm
.macro mtroxoru ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPXORU
.endm
.macro mtroxors ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPXORS
.endm
.macro mtrolshl ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPLSHL
.endm
.macro mtrolshr ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPLSHR
.endm
.macro mtrolror ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPLROR
.endm
.section operate_and_shift_left_macros
.macro mshladdu ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPADDU, IDT_OPLSHL, \shn
.endm
.macro mshladds ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPADDS, IDT_OPLSHL, \shn
.endm
.macro mshlsubu ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPSUBU, IDT_OPLSHL, \shn
.endm
.macro mshlsubs ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPSUBS, IDT_OPLSHL, \shn
.endm
.macro mshlandu ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPANDU, IDT_OPLSHL, \shn
.endm
.macro mshlands ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPADNS, IDT_OPLSHL, \shn
.endm
.macro mshlorru ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPORRU, IDT_OPLSHL, \shn
.endm
.macro mshlorrs ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPORRS, IDT_OPLSHL, \shn
.endm
.macro mshlxoru ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPXORU, IDT_OPLSHL, \shn
.endm
.macro mshlxors ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPXORS, IDT_OPLSHL, \shn
.endm
.section operate_and_shift_right_macros
.macro mshraddu ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPADDU, IDT_OPSHFR, \shn
.endm
.macro mshradds ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPADDS, IDT_OPSHFR, \shn
.endm
.macro mshrsubu ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPSUBU, IDT_OPSHFR, \shn
.endm
.macro mshrsubs ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPSUBS, IDT_OPSHFR, \shn
.endm
.macro mshrandu ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPANDU, IDT_OPSHFR, \shn
.endm
.macro mshrands ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPADNS, IDT_OPSHFR, \shn
.endm
.macro mshrorru ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPORRU, IDT_OPSHFR, \shn
.endm
.macro mshrorrs ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPORRS, IDT_OPSHFR, \shn
.endm
.macro mshrxoru ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPXORU, IDT_OPSHFR, \shn
.endm
.macro mshrxors ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPXORS, IDT_OPSHFR, \shn
.endm
.section post_index_macros
.macro mmemlbip reg, addr
mMEMIDXP \reg, \addr, LIT_NP01, IDT_OPLDBY
.endm
.macro mmemlhip reg, addr
mMEMIDXP \reg, \addr, LIT_NP02, IDT_OPLDHW
.endm
.macro mmemlwip reg, addr
mMEMIDXP \reg, \addr, LIT_NP04, IDT_OPLDFW
.endm
.macro mmemldip reg, addr
mMEMIDXP \reg, \addr, LIT_NP08, IDT_OPLDDW
.endm
.macro mmemsbip reg, addr
mMEMIDXP \reg, \addr, LIT_NN01, IDT_OPSTBY
.endm
.macro mmemship reg, addr
mMEMIDXP \reg, \addr, LIT_NN02, IDT_OPSTHW
.endm
.macro mmemswip reg, addr
mMEMIDXP \reg, \addr, LIT_NN04, IDT_OPSTFW
.endm
.macro mmemsdip reg, addr
mMEMIDXP \reg, \addr, LIT_NN08, IDT_OPSTDW
.endm
.macro mmemsiip reg, addr, idx
mMEMIDXP \reg, \addr, \idx, IDT_OPSTDW
.endm
.section pre_index_macros
.macro mmemlbpi reg, addr
mMEMIDXP \reg, \addr, LIT_NP01, IDT_OPLDBY
.endm
.macro mmemlhpi reg, addr
mMEMIDXP \reg, \addr, LIT_NP02, IDT_OPLDHW
.endm
.macro mmemlwpi reg, addr
mMEMIDXP \reg, \addr, LIT_NP04, IDT_OPLDFW
.endm
.macro mmemldpi reg, addr
mMEMIDXP \reg, \addr, LIT_NP08, IDT_OPLDDW
.endm
.macro mmemsbpi reg, addr
mMEMIDXP \reg, \addr, LIT_NN01, IDT_OPSTBY
.endm
.macro mmemshpi reg, addr
mMEMIDXP \reg, \addr, LIT_NN02, IDT_OPSTHW
.endm
.macro mmemswpi reg, addr
mMEMIDXP \reg, \addr, LIT_NN04, IDT_OPSTFW
.endm
.macro mmemsdpi reg, addr
mMEMIDXP \reg, \addr, LIT_NN08, IDT_OPSTDW
.endm
.macro mmemsipi reg, addr, idx
mMEMIDXP \reg, \addr, \idx, IDT_OPSTDW
.endm
.section offset_macros
.macro mmemlbof reg, addr, idx
mMEMOFST \reg, \addr, \idx, IDT_OPLDBY
.endm
.macro mmemlhof reg, addr, idx
mMEMOFST \reg, \addr, \idx, IDT_OPLDHW
.endm
.macro mmemlwof reg, addr, idx
mMEMOFST \reg, \addr, \idx, IDT_OPLDFW
.endm
.macro mmemldof reg, addr, idx
mMEMOFST \reg, \addr, \idx, IDT_OPLDDW
.endm
.macro mmemsbof reg, addr, idx
mMEMOFST \reg, \addr, \idx, IDT_OPSTBY
.endm
.macro mmemshof reg, addr, idx
mMEMOFST \reg, \addr, \idx, IDT_OPSTHW
.endm
.macro mmemswof reg, addr, idx
mMEMOFST \reg, \addr, \idx, IDT_OPSTFW
.endm
.macro mmemsdof reg, addr, idx
mMEMOFST \reg, \addr, \idx, IDT_OPSTDW
.endm
.section pair_preindex_macros
.macro mmmlpbpi reg1, reg2, addr
mMMPPIDX \reg, \reg2, \addr, LIT_NP02, IDT_OPLDRP
.endm
.macro mmmlphpi reg1, reg2, addr
mMMPPIDX \reg, \reg2, \addr, LIT_NP04, IDT_OPLDRP
.endm
.macro mmmlpwpi reg1, reg2, addr
mMMPPIDX \reg, \reg2, \addr, LIT_NP08, IDT_OPLDRP
.endm
.macro mmmlpdpi reg1, reg2, addr
mMMPPIDX \reg, \reg2, \addr, LIT_NP16, IDT_OPLDRP
.endm
.macro mmmspbpi reg1, reg2, addr
mMMPPIDX \reg, \reg2, \addr, LIT_NP02, IDT_OPSTRP
.endm
.macro mmmsphpi reg1, reg2, addr
mMMPPIDX \reg, \reg2, \addr, LIT_NP04, IDT_OPSTRP
.endm
.macro mmmspwpi reg1, reg2, addr
mMMPPIDX \reg, \reg2, \addr, LIT_NP08, IDT_OPSTRP
.endm
.macro mmmspdpi reg1, reg2, addr
mMMPPIDX \reg, \reg2, \addr, LIT_NP16, IDT_OPSTRP
.endm
.macro mmmlpipi reg1, reg2, addr, idx
mMMPPIDX \reg, \reg2, \addr, \idx, IDT_OPLDRP
.endm
.macro mmmspipi reg1, reg2, addr, idx
mMMPPIDX \reg, \reg2, \addr, \idx, IDT_OPSTRP
.endm
.section pair_postindex_macros
.macro mmmlpbip reg1, reg2, addr
mMMPIDXP \reg, \reg2, \addr, LIT_NP02, IDT_OPLDRP
.endm
.macro mmmlphip reg1, reg2, addr
mMMPIDXP \reg, \reg2, \addr, LIT_NP04, IDT_OPLDRP
.endm
.macro mmmlpwip reg1, reg2, addr
mMMPIDXP \reg, \reg2, \addr, LIT_NP08, IDT_OPLDRP
.endm
.macro mmmlpdip reg1, reg2, addr
mMMPIDXP \reg, \reg2, \addr, LIT_NP16, IDT_OPLDRP
.endm
.macro mmmspbip reg1, reg2, addr
mMMPIDXP \reg, \reg2, \addr, LIT_NP02, IDT_OPSTRP
.endm
.macro mmmsphip reg1, reg2, addr
mMMPIDXP \reg, \reg2, \addr, LIT_NP04, IDT_OPSTRP
.endm
.macro mmmspwip reg1, reg2, addr
mMMPIDXP \reg, \reg2, \addr, LIT_NP08, IDT_OPSTRP
.endm
.macro mmmspdip reg1, reg2, addr
mMMPIDXP \reg, \reg2, \addr, LIT_NP16, IDT_OPSTRP
.endm
.macro mmmlpiip reg1, reg2, addr, idx
mMMPIDXP \reg, \reg2, \addr, \idx, IDT_OPLDRP
.endm
.macro mmmspiip reg1, reg2, addr, idx
mMMPIDXP \reg, \reg2, \addr, \idx, IDT_OPSTRP
.endm
.section pair_offset_macros
.macro mmmlpofs reg1, reg2, addr, idx
mMMPOFST \reg, \reg2, \addr, \idx, IDT_OPLDRP
.endm
.macro mmmspofs reg1, reg2, addr, idx
mMMPOFST \reg, \reg2, \addr, \idx, IDT_OPSTRP
.endm
.section stack_push_macros
.macro mpshbyte reg
mPSHBASE \reg, IDT_OPSTBY, LIT_NN01
.endm
.macro mpshhwrd reg
mPSHBASE \reg, IDT_OPSTHW, LIT_NN02
.endm
.macro mpshfwrd reg
mPSHBASE \reg, IDT_OPSTFW, LIT_NN04
.endm
.macro mpshdwrd reg
mPSHBASE \reg, IDT_OPSTDW, LIT_NN08
.endm
.section stack_pop_macros
.macro mpopbyte reg
mPOPBASE \reg, IDT_OPLDBY, LIT_NP01
.endm
.macro mpophwrd reg
mPOPBASE \reg, IDT_OPLDHW, LIT_NP02
.endm
.macro mpopfwrd reg
mPOPBASE \reg, IDT_OPLDFW, LIT_NP04
.endm
.macro mpopdwrd reg
mPOPBASE \reg, IDT_OPLDDW, LIT_NP08
.endm
.section branch_compare_macros
.macro mjmp2lbl label
mOXNNNNB \label, IDT_OPJUMP
.endm
.macro mcmpregs reg1, reg2
mOXYTNNB \reg1, \reg2, IDT_OPCOMP
.endm
.macro mtstpair reg1, reg2
mOXYTNNB \reg1, \reg2, IDT_OPTEST
.endm
.macro mtstself reg
mOXYTNNB \reg, \reg, IDT_OPTEST
.endm
.section single_condition_branch_macros
.macro msjcndeq label
mOXNNNNB \label, IDT_CONDEQ
.endm
.macro msjcndne label
mOXNNNNB \label, IDT_CONDNE
.endm
.macro msjcndlt label
mOXNNNNB \label, IDT_CONDLT
.endm
.macro msjcndgt label
mOXNNNNB \label, IDT_CONDGT
.endm
.macro msjcndle label
mOXNNNNB \label, IDT_CONDLE
.endm
.macro msjcndge label
mOXNNNNB \label, IDT_CONDGE
.endm
.macro msjcndng label
mOXNNNNB \label, IDT_CONDNG
.endm
.macro msjcndps label
mOXNNNNB \label, IDT_CONDPS
.endm
.macro msjcndov label
mOXNNNNB \label, IDT_CONDOV
.endm
.macro msjcndnv label
mOXNNNNB \label, IDT_CONDNV
.endm
.macro msjcndcs label
mOXNNNNB \label, IDT_CONDCS
.endm
.macro msjcndcc label
mOXNNNNB \label, IDT_CONDCC
.endm
.macro msjcndhi label`ADD<U/S>`, `ADD<U/S>`, `ADD<U/S>`,
mOXNNNNB \label, IDT_CONDHI
.endm
.section dual_condition_branch_macros
.macro mpjceqne label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDNE
.endm
.macro mpjceqlt label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDLT
.endm
.macro mpjceqgt label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDGT
.endm
.macro mpjceqle label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDLE
.endm
.macro mpjceqge label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDGE
.endm
.macro mpjceqng label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDNG
.endm
.macro mpjceqps label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDPS
.endm
.macro mpjceqov label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDOV
.endm
.macro mpjceqnv label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDNV
.endm
.macro mpjceqcs label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDCS
.endm
.macro mpjceqcc label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDCC
.endm
.macro mpjceqhi label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDHI
.endm
.macro mpjcnelt label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDLT
.endm
.macro mpjcnegt label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDGT
.endm
.macro mpjcnele label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDLE
.endm
.macro mpjcnege label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDGE
.endm
.macro mpjcneng label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDNG
.endm
.macro mpjcneps label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDPS
.endm
.macro mpjcneov label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDOV
.endm
.macro mpjcnenv label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDNV
.endm
.macro mpjcnecs label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDCS
.endm
.macro mpjcnecc label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDCC
.endm
.macro mpjcnehi label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDHI
.endm
.macro mpjcltgt label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDGT
.endm
.macro mpjcltle label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDLE
.endm
.macro mpjcltge label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDGE
.endm
.macro mpjcltng label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDNG
.endm
.macro mpjcltps label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDPS
.endm
.macro mpjcltov label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDOV
.endm
.macro mpjcltnv label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDNV
.endm
.macro mpjcltcs label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDCS
.endm
.macro mpjcltcc label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDCC
.endm
.macro mpjclthi label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDHI
.endm
.macro mpjcgtle label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDLE
.endm
.macro mpjcgtge label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDGE
.endm
.macro mpjcgtng label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDNG
.endm
.macro mpjcgtps label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDPS
.endm
.macro mpjcgtov label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDOV
.endm
.macro mpjcgtnv label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDNV
.endm
.macro mpjcgtcs label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDCS
.endm
.macro mpjcgtcc label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDCC
.endm
.macro mpjcgthi label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDHI
.endm
.macro mpjclege label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDGE
.endm
.macro mpjcleng label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDNG
.endm
.macro mpjcleps label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDPS
.endm
.macro mpjcleov label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDOV
.endm
.macro mpjclenv label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDNV
.endm
.macro mpjclecs label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDCS
.endm
.macro mpjclecc label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDCC
.endm
.macro mpjclehi label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDHI
.endm
.macro mpjcgeng label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDNG
.endm
.macro mpjcgeps label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDPS
.endm
.macro mpjcgeov label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDOV
.endm
.macro mpjcgenv label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDNV
.endm
.macro mpjcgecs label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDCS
.endm
.macro mpjcgecc label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDCC
.endm
.macro mpjcgehi label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDHI
.endm
.macro mpjcngps label1, label2
mOXOXNNB \label1, IDT_CONDNG, \label2, IDT_CONDPS
.endm
.macro mpjcngov label1, label2
mOXOXNNB \label1, IDT_CONDNG, \label2, IDT_CONDOV
.endm
.macro mpjcngnv label1, label2
mOXOXNNB \label1, IDT_CONDNG, \label2, IDT_CONDNV
.endm
.macro mpjcngcs label1, label2
mOXOXNNB \label1, IDT_CONDNG, \label2, IDT_CONDCS
.endm
.macro mpjcngcc label1, label2
mOXOXNNB \label1, IDT_CONDNG, \label2, IDT_CONDCC
.endm
.macro mpjcnghi label1, label2
mOXOXNNB \label1, IDT_CONDNG, \label2, IDT_CONDHI
.endm
.macro mpjcpsov label1, label2
mOXOXNNB \label1, IDT_CONDPS, \label2, IDT_CONDOV
.endm
.macro mpjcpsnv label1, label2
mOXOXNNB \label1, IDT_CONDPS, \label2, IDT_CONDNV
.endm
.macro mpjcpscs label1, label2
mOXOXNNB \label1, IDT_CONDPS, \label2, IDT_CONDCS
.endm
.macro mpjcpscc label1, label2
mOXOXNNB \label1, IDT_CONDPS, \label2, IDT_CONDCC
.endm
.macro mpjcpshi label1, label2
mOXOXNNB \label1, IDT_CONDPS, \label2, IDT_CONDHI
.endm
.macro mpjcovnv label1, label2
mOXOXNNB \label1, IDT_CONDOV, \label2, IDT_CONDNV
.endm
.macro mpjcovcs label1, label2
mOXOXNNB \label1, IDT_CONDOV, \label2, IDT_CONDCS
.endm
.macro mpjcovcc label1, label2
mOXOXNNB \label1, IDT_CONDOV, \label2, IDT_CONDCC
.endm
.macro mpjcovhi label1, label2
mOXOXNNB \label1, IDT_CONDOV, \label2, IDT_CONDHI
.endm
.macro mpjcnvcs label1, label2
mOXOXNNB \label1, IDT_CONDNV, \label2, IDT_CONDCS
.endm
.macro mpjcnvcc label1, label2
mOXOXNNB \label1, IDT_CONDNV, \label2, IDT_CONDCC
.endm
.macro mpjcnvhi label1, label2
mOXOXNNB \label1, IDT_CONDNV, \label2, IDT_CONDHI
.endm
.macro mpjccscc label1, label2
mOXOXNNB \label1, IDT_CONDCS, \label2, IDT_CONDCC
.endm
.macro mpjccshi label1, label2
mOXOXNNB \label1, IDT_CONDCS, \label2, IDT_CONDHI
.endm
.macro mpjccchi label1, label2
mOXOXNNB \label1, IDT_CONDCC, \label2, IDT_CONDHI
.endm
.section subroutine_macros
.macro msrstart
mPSHDWRD REG_DLNPTR
.endm
.macro msrretrn
mPOPDWRD REG_DLNPTR
IDT_opdTR
.endm
.macro msyscall
mOXNNNNB LIT_NZERO, IDT_OPSYSC
.endm
.section misc_macros
.macro mregzero reg
mINPXORU \reg, \reg
.endm
.macro mxchngrg reg1, reg2, temp
mPSHDWRD \temp
mtrnMOVE \temp, \reg1
mtrnMOVE \reg1, \reg2
mtrnMOVE \reg2, \temp
mPOPDWRD \temp
.endm
Raw
spudmacs.x86-64.S
// Copyright (c) 2023 Chubak Bidpaa
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
// LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
// OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
// WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define LIT_NZERO $0
#define LIT_NP01 $1
#define LIT_NP02 $2
#define LIT_NP04 $4
#define LIT_NP08 $8
#define LIT_NP16 $16
#define LIT_NP32 $32
#define LIT_NP64 $64
#define LIT_NN01 $-1
#define LIT_NN02 $-2
#define LIT_NN04 $-4
#define LIT_NN08 $-8
#define LIT_NN16 $-16
#define LIT_NN32 $-32
#define LIT_NN64 $-64
#define LIT_NPXF2 $0xff
#define LIT_NPXF4 $0xffff
#define LIT_NPXF6 $0xffffff
#define LIT_NPXF8 $0xffffffff
#define LIT_NPXF10 $0xffffffffff
#define LIT_NPXF12 $0xffffffffffff
#define LIT_NPXF14 $0xffffffffffffff
#define LIT_NPXF16 $0xffffffffffffffff
#define LIT_NNX802 $-0x80
#define LIT_NNX804 $-0x8000
#define LIT_NNX806 $-0x800000
#define LIT_NNX808 $-0x80000000
#define LIT_NNX8010 $-0x8000000000
#define LIT_NNX8012 $-0x800000000000
#define LIT_NNX8014 $-0x80000000000000
#define LIT_NNX8016 $-0x8000000000000000
#define IDT_OPORRS or
#define IDT_OPORRU or
#define IDT_OPPOPP pop
#define IDT_OPTEST tst
#define IDT_OPMOVE mov
#define IDT_OPADDU add
#define IDT_OPSUBU sub
#define IDT_OPANDU and
#define IDT_OPXORU xor
#define IDT_OPORRN not
#define IDT_OPLSHL shl
#define IDT_OPLSHR shr
#define IDT_OPLROR ror
#define IDT_OPCOMP cmp
#define IDT_opdTR ret
#define IDT_OPADDS add
#define IDT_OPSUBS sub
#define IDT_OPANDS and
#define IDT_OPXORS xor
#define IDT_OPMOVN not
#define IDT_OPJUMP jmp
#define IDT_OPMOVZ movz
#define IDT_OPPUSH push
#define IDT_OPXCHG xchg
#define IDT_OPLDBY movlb
#define IDT_OPSTBY movlb
#define IDT_OPLDHW movlh
#define IDT_OPSTHW movlh
#define IDT_OPLDFW movlw
#define IDT_OPSTFW movlw
#define IDT_OPLDRP movld
#define IDT_OPSTRP movld
#define IDT_OPLDDW movld
#define IDT_OPSTDW movld
#define IDT_OPSYSC syscall
#define IDT_CONDEQ je
#define IDT_CONDLT jl
#define IDT_CONDGT jg
#define IDT_CONDOV jo
#define IDT_CONDNG js
#define IDT_CONDCS jc
#define IDT_CONDHI ja
#define IDT_CONDNE jne
#define IDT_CONDLE jle
#define IDT_CONDGE jge
#define IDT_CONDPS jns
#define IDT_CONDNV jno
#define IDT_CONDCC jnc
#define REG_DSYCNR %rax
#define REG_opePTR %rsp
#define REG_DBPPTR %rbp
#define REG_DARG01 %rdi
#define REG_DARG02 %rsi
#define REG_DARG03 %rdx
#define REG_DARG04 %r10
#define REG_DARG05 %r8
#define REG_DARG06 %r9
#define REG_DSRETR %rax
#define REG_DCLB01 %r11
#define REG_DCSV01 %rbx
#define REG_DCSV02 %r12
#define REG_DCSV03 %r13
#define REG_DCSV04 %r14
#define REG_DCSV05 %r15
#define REG_WSYCNR %eax
#define REG_WSTPTR %esp
#define REG_WBPPTR %ebp
#define REG_WARG01 %edi
#define REG_WARG02 %esi
#define REG_WARG03 %edx
#define REG_WARG05 %r8d
#define REG_WARG06 %r9d
#define REG_WSRETR %eax
#define REG_WCSV01 %ebx
#define REG_WCSV02 %r12d
#define REG_WCSV03 %r13d
#define REG_WCSV04 %r14d
#define REG_WCSV05 %r15d
#define REG_WCLB01 %r11d
#define REG_BSYCNR %ax
#define REG_BARG01 %di
#define REG_BARG02 %si
#define REG_BARG03 %dx
#define REG_BSRETR %ax
#define REG_BCSV01 %bx
#define REG_BARG05 %r8b
#define REG_BARG06 %r9b
#define REG_BCSV02 %r12b
#define REG_BCSV03 %r13b
#define REG_BCSV04 %r14b
#define REG_BCSV05 %r15b
#define REG_BCLB01 %r11b
.section base_operation_macros
.macro moxnnnnb opd, optr
\optr \opd
.endm
.macro moxoxnnb opd1, optr1, opd2, optr2
\optr1 \opd1
\optr2 \opd2
.endm
.macro ooxyvtnb ope, opd, optr, val
mov \opd, \ope
\optr \val, \ope
.endm
.macro ooxvtnnb opd, val, optr
\optr \val, \opd
.endm
.macro moxytnnb ope, opd, optr
\optr \opd, \ope
.endm
.macro moxyvstb ope, opd, optr, val, shoptr, shn
movz \opd, \ope
\optr \val, \ope
\shoptr \shn, \ope
.endm
.section single_load_memory_base_macros
.macro mmmlidxp reg, addr, idx, optr
\optr (\addr, \idx, 1), \ope
add \idx, \addr
.endm
.macro mmmlpidx reg, addr, idx, optr
add \idx, \addr
\optr (\addr, \idx, 1), \ope
.endm
.macro mmmlofst reg, addr, idx, optr
\optr (\addr, \idx, 1), \ope
.endm
.section single_store_memory_base_macros
.macro mmmlidxp reg, addr, idx, optr
\optr \ope, (\addr, \idx, 1)
add \idx, \addr
.endm
.macro mmmlpidx reg, addr, idx, optr
add \idx, \addr
\optr \ope, (\addr, \idx, 1)
.endm
.macro mmmlofst reg, addr, idx, optr
\optr \ope, (\addr, \idx, 1)
.endm
.section pair_load_memory_base_macros
.macro mmplidxp reg1, reg2, addr, idx, optr
\optr (\addr, \idx, 1), \ope1
add \idx, \addr
\optr (\addr, \idx, 1), \ope2
add \idx, \addr
.endm
.macro mmplpidx reg1, reg2, addr, idx, optr
add \idx, \addr
\optr (\addr, \idx, 1), \ope1
add \idx, \addr
\optr (\addr, \idx, 1), \ope2
.endm
.altmacro
.macro mmplofst reg1, reg2, addr, idx, optr
\optr (\addr, \idx, 1), \ope1
\optr (\addr, %idx + %idx, 1), \ope1
.endm
.section pair_load_memory_base_macros
.macro mmpsidxp reg1, reg2, addr, idx, optr
\optr \ope1, (\addr, \idx, 1)
add \idx, \addr
\optr \ope2, (\addr, \idx, 1)
add \idx, \addr
.endm
.macro mmpspidx reg1, reg2, addr, idx, optr
add \idx, \addr
\optr \ope1, (\addr, \idx, 1)
add \idx, \addr
\optr \ope2, (\addr, \idx, 1)
.endm
.altmacro
.macro mmpsofst reg1, reg2, addr, idx, optr
\optr \ope1, (\addr, \idx, 1)
\optr \ope1, (\addr, %idx + %idx, 1)
.endm
.section base_stack_macros
.macro mpshbase reg, optr, idx
IDT_OPPUSH \reg
.endm
.macro mpopbase reg, optr, idx
IDT_OPPOP \reg
.endm
.section transfer_operation_macros
.macro mtrnmove ope, opd
mOXYTNNB \ope, \opd, IDT_OPMOVE
.endm
.macro mtrnmovz ope, opd
mOXYTNNB \ope, \opd, IDT_OPMOVZ
.endm
.macro mtrnmovn ope, opd
mOXYTNNB \ope, \opd, IDT_OPMOVN
.endm
.section inplace_operation_macros
.macro minpaddu opd, val
oOXVTNNB \opd, \val, IDT_OPADDU
.endm
.macro minpadds opd, val
oOXVTNNB \opd, \val, IDT_OPADDS
.endm
.macro minpsubu opd, val
oOXVTNNB \opd, \val, IDT_OPSUBU
.endm
.macro minpsubs opd, val
oOXVTNNB \opd, \val, IDT_OPSUBS
.endm
.macro minpandu opd, val
oOXVTNNB \opd, \val, IDT_OPANDU
.endm
.macro minpands opd, val
oOXVTNNB \opd, \val, IDT_OPADNS
.endm
.macro minporru opd, val
oOXVTNNB \opd, \val, IDT_OPORRU
.endm
.macro minporrs opd, val
oOXVTNNB \opd, \val, IDT_OPORRS
.endm
.macro minpxoru opd, val
oOXVTNNB \opd, \val, IDT_OPXORU
.endm
.macro minpxors opd, val
oOXVTNNB \opd, \val, IDT_OPXORS
.endm
.macro minplshl opd, val
oOXVTNNB \opd, \val, IDT_OPLSHL
.endm
.macro minplshr opd, val
oOXVTNNB \opd, \val, IDT_OPLSHR
.endm
.macro minplror opd, val
oOXVTNNB \opd, \val, IDT_OPLROR
.endm
.section transfer_operation_macros
.macro mtroaddu ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPADDU
.endm
.macro mtroadds ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPADDS
.endm
.macro mtrosubu ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPSUBU
.endm
.macro mtrosubs ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPSUBS
.endm
.macro mtroandu ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPANDU
.endm
.macro mtroands ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPADNS
.endm
.macro mtroorru ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPORRU
.endm
.macro mtroorrs ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPORRS
.endm
.macro mtroxoru ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPXORU
.endm
.macro mtroxors ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPXORS
.endm
.macro mtrolshl ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPLSHL
.endm
.macro mtrolshr ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPLSHR
.endm
.macro mtrolror ope, opd, val
oOXYVTNB \ope, \opd, \val, IDT_OPLROR
.endm
.section operate_and_shift_left_macros
.macro mshladdu ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPADDU, IDT_OPLSHL, \shn
.endm
.macro mshladds ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPADDS, IDT_OPLSHL, \shn
.endm
.macro mshlsubu ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPSUBU, IDT_OPLSHL, \shn
.endm
.macro mshlsubs ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPSUBS, IDT_OPLSHL, \shn
.endm
.macro mshlandu ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPANDU, IDT_OPLSHL, \shn
.endm
.macro mshlands ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPADNS, IDT_OPLSHL, \shn
.endm
.macro mshlorru ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPORRU, IDT_OPLSHL, \shn
.endm
.macro mshlorrs ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPORRS, IDT_OPLSHL, \shn
.endm
.macro mshlxoru ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPXORU, IDT_OPLSHL, \shn
.endm
.macro mshlxors ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPXORS, IDT_OPLSHL, \shn
.endm
.section operate_and_shift_right_macros
.macro mshraddu ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPADDU, IDT_OPSHFR, \shn
.endm
.macro mshradds ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPADDS, IDT_OPSHFR, \shn
.endm
.macro mshrsubu ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPSUBU, IDT_OPSHFR, \shn
.endm
.macro mshrsubs ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPSUBS, IDT_OPSHFR, \shn
.endm
.macro mshrandu ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPANDU, IDT_OPSHFR, \shn
.endm
.macro mshrands ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPADNS, IDT_OPSHFR, \shn
.endm
.macro mshrorru ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPORRU, IDT_OPSHFR, \shn
.endm
.macro mshrorrs ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPORRS, IDT_OPSHFR, \shn
.endm
.macro mshrxoru ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPXORU, IDT_OPSHFR, \shn
.endm
.macro mshrxors ope, opd, val, shn
mOXYVSTB \ope, \opd, \val, IDT_OPXORS, IDT_OPSHFR, \shn
.endm
.section post_index_macros
.macro mmemlbip reg, addr
mMMLIDXP \reg, \addr, LIT_NP01, IDT_OPLDBY
.endm
.macro mmemlhip reg, addr
mMMLIDXP \reg, \addr, LIT_NP02, IDT_OPLDHW
.endm
.macro mmemlwip reg, addr
mMMLIDXP \reg, \addr, LIT_NP04, IDT_OPLDFW
.endm
.macro mmemldip reg, addr
mMMLIDXP \reg, \addr, LIT_NP08, IDT_OPLDDW
.endm
.macro mmemliip reg, addr, idx
mMMLIDXP \reg, \addr, \idx, IDT_OPSTDW
.endm
.macro mmemsbip reg, addr
mMMSIDXP \reg, \addr, LIT_NN01, IDT_OPSTBY
.endm
.macro mmemship reg, addr
mMMSIDXP \reg, \addr, LIT_NN02, IDT_OPSTHW
.endm
.macro mmemswip reg, addr
mMMSIDXP \reg, \addr, LIT_NN04, IDT_OPSTFW
.endm
.macro mmemsdip reg, addr
mMMSIDXP \reg, \addr, LIT_NN08, IDT_OPSTDW
.endm
.macro mmemsiip reg, addr, idx
mMMSIDXP \reg, \addr, \idx, IDT_OPSTDW
.endm
.section pre_index_macros
.macro mmemlbpi reg, addr
mMMLIDXP \reg, \addr, LIT_NP01, IDT_OPLDBY
.endm
.macro mmemlhpi reg, addr
mMMLIDXP \reg, \addr, LIT_NP02, IDT_OPLDHW
.endm
.macro mmemlwpi reg, addr
mMMLIDXP \reg, \addr, LIT_NP04, IDT_OPLDFW
.endm
.macro mmemldpi reg, addr
mMMLIDXP \reg, \addr, LIT_NP08, IDT_OPLDDW
.endm
.macro mmemlipi reg, addr, idx
mMMLIDXP \reg, \addr, \idx, IDT_OPLDDW
.endm
.macro mmemsbpi reg, addr
mMMSIDXP \reg, \addr, LIT_NN01, IDT_OPSTBY
.endm
.macro mmemshpi reg, addr
mMMSIDXP \reg, \addr, LIT_NN02, IDT_OPSTHW
.endm
.macro mmemswpi reg, addr
mMMSIDXP \reg, \addr, LIT_NN04, IDT_OPSTFW
.endm
.macro mmemsdpi reg, addr
mMMSIDXP \reg, \addr, LIT_NN08, IDT_OPSTDW
.endm
.macro mmemsipi reg, addr, idx
mMMSIDXP \reg, \addr, \idx, IDT_OPSTDW
.endm
.section offset_macros
.macro mmemlbof reg, addr, idx
mMMLOFST \reg, \addr, \idx, IDT_OPLDBY
.endm
.macro mmemlhof reg, addr, idx
mMMLOFST \reg, \addr, \idx, IDT_OPLDHW
.endm
.macro mmemlwof reg, addr, idx
mMMLOFST \reg, \addr, \idx, IDT_OPLDFW
.endm
.macro mmemldof reg, addr, idx
mMMLOFST \reg, \addr, \idx, IDT_OPLDDW
.endm
.macro mmemsbof reg, addr, idx
mMMSOFST \reg, \addr, \idx, IDT_OPSTBY
.endm
.macro mmemshof reg, addr, idx
mMMSOFST \reg, \addr, \idx, IDT_OPSTHW
.endm
.macro mmemswof reg, addr, idx
mMMSOFST \reg, \addr, \idx, IDT_OPSTFW
.endm
.macro mmemsdof reg, addr, idx
mMMSOFST \reg, \addr, \idx, IDT_OPSTDW
.endm
.section pair_preindex_macros
.macro mmmlpbpi reg1, reg2, addr
mMPLPIDX \reg, \reg2, \addr, LIT_NP02, IDT_OPLDRP
.endm
.macro mmmlphpi reg1, reg2, addr
mMPLPIDX \reg, \reg2, \addr, LIT_NP04, IDT_OPLDRP
.endm
.macro mmmlpwpi reg1, reg2, addr
mMPLPIDX \reg, \reg2, \addr, LIT_NP08, IDT_OPLDRP
.endm
.macro mmmlpdpi reg1, reg2, addr
mMPLPIDX \reg, \reg2, \addr, LIT_NP16, IDT_OPLDRP
.endm
.macro mmmlpipi reg1, reg2, addr, idx
mMPSPIDX \reg, \reg2, \addr, \idx, IDT_OPLDRP
.endm
.macro mmmspbpi reg1, reg2, addr
mMPLPIDX \reg, \reg2, \addr, LIT_NP02, IDT_OPSTRP
.endm
.macro mmmsphpi reg1, reg2, addr
mMPSPIDX \reg, \reg2, \addr, LIT_NP04, IDT_OPSTRP
.endm
.macro mmmspwpi reg1, reg2, addr
mMPSPIDX \reg, \reg2, \addr, LIT_NP08, IDT_OPSTRP
.endm
.macro mmmspdpi reg1, reg2, addr
mMPSPIDX \reg, \reg2, \addr, LIT_NP16, IDT_OPSTRP
.endm
.macro mmmspipi reg1, reg2, addr, idx
mMPSPIDX \reg, \reg2, \addr, \idx, IDT_OPSTRP
.endm
.section pair_postindex_macros
.macro mmmlpbip reg1, reg2, addr
mMPLIDXP \reg, \reg2, \addr, LIT_NP02, IDT_OPLDRP
.endm
.macro mmmlphip reg1, reg2, addr
mMPLIDXP \reg, \reg2, \addr, LIT_NP04, IDT_OPLDRP
.endm
.macro mmmlpwip reg1, reg2, addr
mMPLIDXP \reg, \reg2, \addr, LIT_NP08, IDT_OPLDRP
.endm
.macro mmmlpdip reg1, reg2, addr
mMPLIDXP \reg, \reg2, \addr, LIT_NP16, IDT_OPLDRP
.endm
.macro mmmlpiip reg1, reg2, addr, idx
mMPSIDXP \reg, \reg2, \addr, \idx, IDT_OPLDRP
.endm
.macro mmmspbip reg1, reg2, addr
mMPSIDXP \reg, \reg2, \addr, LIT_NP02, IDT_OPSTRP
.endm
.macro mmmsphip reg1, reg2, addr
mMPSIDXP \reg, \reg2, \addr, LIT_NP04, IDT_OPSTRP
.endm
.macro mmmspwip reg1, reg2, addr
mMPSIDXP \reg, \reg2, \addr, LIT_NP08, IDT_OPSTRP
.endm
.macro mmmspdip reg1, reg2, addr
mMPSIDXP \reg, \reg2, \addr, LIT_NP16, IDT_OPSTRP
.endm
.macro mmmspiip reg1, reg2, addr, idx
mMPSIDXP \reg, \reg2, \addr, \idx, IDT_OPSTRP
.endm
.section pair_offset_macros
.macro mmmlpofs reg1, reg2, addr, idx
mMPLOFST \reg, \reg2, \addr, \idx, IDT_OPLDRP
.endm
.macro mmmspofs reg1, reg2, addr, idx
mMPSOFST \reg, \reg2, \addr, \idx, IDT_OPSTRP
.endm
.section stack_push_macros
.macro mpshbyte reg
mPSHBASE \reg, IDT_OPSTBY, LIT_NN01
.endm
.macro mpshhwrd reg
mPSHBASE \reg, IDT_OPSTHW, LIT_NN02
.endm
.macro mpshfwrd reg
mPSHBASE \reg, IDT_OPSTFW, LIT_NN04
.endm
.macro mpshdwrd reg
mPSHBASE \reg, IDT_OPSTDW, LIT_NN08
.endm
.section stack_pop_macros
.macro mpopbyte reg
mPOPBASE \reg, IDT_OPLDBY, LIT_NP01
.endm
.macro mpophwrd reg
mPOPBASE \reg, IDT_OPLDHW, LIT_NP02
.endm
.macro mpopfwrd reg
mPOPBASE \reg, IDT_OPLDFW, LIT_NP04
.endm
.macro mpopdwrd reg
mPOPBASE \reg, IDT_OPLDDW, LIT_NP08
.endm
.section branch_compare_macros
.macro mjmp2lbl label
mOXNNNNB \label, IDT_OPJUMP
.endm
.macro mcmpregs reg1, reg2
mOXYTNNB \reg1, \reg2, IDT_OPCOMP
.endm
.macro mtstpair reg1, reg2
mOXYTNNB \reg1, \reg2, IDT_OPTEST
.endm
.macro mtstself reg
mOXYTNNB \reg, \reg, IDT_OPTEST
.endm
.section single_condition_branch_macros
.macro msjcndeq label
mOXNNNNB \label, IDT_CONDEQ
.endm
.macro msjcndne label
mOXNNNNB \label, IDT_CONDNE
.endm
.macro msjcndlt label
mOXNNNNB \label, IDT_CONDLT
.endm
.macro msjcndgt label
mOXNNNNB \label, IDT_CONDGT
.endm
.macro msjcndle label
mOXNNNNB \label, IDT_CONDLE
.endm
.macro msjcndge label
mOXNNNNB \label, IDT_CONDGE
.endm
.macro msjcndng label
mOXNNNNB \label, IDT_CONDNG
.endm
.macro msjcndps label
mOXNNNNB \label, IDT_CONDPS
.endm
.macro msjcndov label
mOXNNNNB \label, IDT_CONDOV
.endm
.macro msjcndnv label
mOXNNNNB \label, IDT_CONDNV
.endm
.macro msjcndcs label
mOXNNNNB \label, IDT_CONDCS
.endm
.macro msjcndcc label
mOXNNNNB \label, IDT_CONDCC
.endm
.macro msjcndhi label
mOXNNNNB \label, IDT_CONDHI
.endm
.section dual_condition_branch_macros
.macro mpjceqne label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDNE
.endm
.macro mpjceqlt label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDLT
.endm
.macro mpjceqgt label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDGT
.endm
.macro mpjceqle label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDLE
.endm
.macro mpjceqge label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDGE
.endm
.macro mpjceqng label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDNG
.endm
.macro mpjceqps label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDPS
.endm
.macro mpjceqov label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDOV
.endm
.macro mpjceqnv label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDNV
.endm
.macro mpjceqcs label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDCS
.endm
.macro mpjceqcc label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDCC
.endm
.macro mpjceqhi label1, label2
mOXOXNNB \label1, IDT_CONDEQ, \label2, IDT_CONDHI
.endm
.macro mpjcnelt label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDLT
.endm
.macro mpjcnegt label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDGT
.endm
.macro mpjcnele label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDLE
.endm
.macro mpjcnege label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDGE
.endm
.macro mpjcneng label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDNG
.endm
.macro mpjcneps label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDPS
.endm
.macro mpjcneov label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDOV
.endm
.macro mpjcnenv label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDNV
.endm
.macro mpjcnecs label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDCS
.endm
.macro mpjcnecc label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDCC
.endm
.macro mpjcnehi label1, label2
mOXOXNNB \label1, IDT_CONDNE, \label2, IDT_CONDHI
.endm
.macro mpjcltgt label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDGT
.endm
.macro mpjcltle label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDLE
.endm
.macro mpjcltge label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDGE
.endm
.macro mpjcltng label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDNG
.endm
.macro mpjcltps label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDPS
.endm
.macro mpjcltov label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDOV
.endm
.macro mpjcltnv label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDNV
.endm
.macro mpjcltcs label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDCS
.endm
.macro mpjcltcc label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDCC
.endm
.macro mpjclthi label1, label2
mOXOXNNB \label1, IDT_CONDLT, \label2, IDT_CONDHI
.endm
.macro mpjcgtle label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDLE
.endm
.macro mpjcgtge label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDGE
.endm
.macro mpjcgtng label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDNG
.endm
.macro mpjcgtps label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDPS
.endm
.macro mpjcgtov label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDOV
.endm
.macro mpjcgtnv label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDNV
.endm
.macro mpjcgtcs label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDCS
.endm
.macro mpjcgtcc label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDCC
.endm
.macro mpjcgthi label1, label2
mOXOXNNB \label1, IDT_CONDGT, \label2, IDT_CONDHI
.endm
.macro mpjclege label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDGE
.endm
.macro mpjcleng label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDNG
.endm
.macro mpjcleps label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDPS
.endm
.macro mpjcleov label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDOV
.endm
.macro mpjclenv label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDNV
.endm
.macro mpjclecs label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDCS
.endm
.macro mpjclecc label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDCC
.endm
.macro mpjclehi label1, label2
mOXOXNNB \label1, IDT_CONDLE, \label2, IDT_CONDHI
.endm
.macro mpjcgeng label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDNG
.endm
.macro mpjcgeps label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDPS
.endm
.macro mpjcgeov label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDOV
.endm
.macro mpjcgenv label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDNV
.endm
.macro mpjcgecs label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDCS
.endm
.macro mpjcgecc label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDCC
.endm
.macro mpjcgehi label1, label2
mOXOXNNB \label1, IDT_CONDGE, \label2, IDT_CONDHI
.endm
.macro mpjcngps label1, label2
mOXOXNNB \label1, IDT_CONDNG, \label2, IDT_CONDPS
.endm
.macro mpjcngov label1, label2
mOXOXNNB \label1, IDT_CONDNG, \label2, IDT_CONDOV
.endm
.macro mpjcngnv label1, label2
mOXOXNNB \label1, IDT_CONDNG, \label2, IDT_CONDNV
.endm
.macro mpjcngcs label1, label2
mOXOXNNB \label1, IDT_CONDNG, \label2, IDT_CONDCS
.endm
.macro mpjcngcc label1, label2
mOXOXNNB \label1, IDT_CONDNG, \label2, IDT_CONDCC
.endm
.macro mpjcnghi label1, label2
mOXOXNNB \label1, IDT_CONDNG, \label2, IDT_CONDHI
.endm
.macro mpjcpsov label1, label2
mOXOXNNB \label1, IDT_CONDPS, \label2, IDT_CONDOV
.endm
.macro mpjcpsnv label1, label2
mOXOXNNB \label1, IDT_CONDPS, \label2, IDT_CONDNV
.endm
.macro mpjcpscs label1, label2
mOXOXNNB \label1, IDT_CONDPS, \label2, IDT_CONDCS
.endm
.macro mpjcpscc label1, label2
mOXOXNNB \label1, IDT_CONDPS, \label2, IDT_CONDCC
.endm
.macro mpjcpshi label1, label2
mOXOXNNB \label1, IDT_CONDPS, \label2, IDT_CONDHI
.endm
.macro mpjcovnv label1, label2
mOXOXNNB \label1, IDT_CONDOV, \label2, IDT_CONDNV
.endm
.macro mpjcovcs label1, label2
mOXOXNNB \label1, IDT_CONDOV, \label2, IDT_CONDCS
.endm
.macro mpjcovcc label1, label2
mOXOXNNB \label1, IDT_CONDOV, \label2, IDT_CONDCC
.endm
.macro mpjcovhi label1, label2
mOXOXNNB \label1, IDT_CONDOV, \label2, IDT_CONDHI
.endm
.macro mpjcnvcs label1, label2
mOXOXNNB \label1, IDT_CONDNV, \label2, IDT_CONDCS
.endm
.macro mpjcnvcc label1, label2
mOXOXNNB \label1, IDT_CONDNV, \label2, IDT_CONDCC
.endm
.macro mpjcnvhi label1, label2
mOXOXNNB \label1, IDT_CONDNV, \label2, IDT_CONDHI
.endm
.macro mpjccscc label1, label2
mOXOXNNB \label1, IDT_CONDCS, \label2, IDT_CONDCC
.endm
.macro mpjccshi label1, label2
mOXOXNNB \label1, IDT_CONDCS, \label2, IDT_CONDHI
.endm
.macro mpjccchi label1, label2
mOXOXNNB \label1, IDT_CONDCC, \label2, IDT_CONDHI
.endm
.section subroutine_macros
.macro msrstart
mPSHDWRD REG_DBPPTR
mtrnMOVE REG_DBPPTR, REG_DSPPTR
.endm
.macro msrretrn
mPOPDWRD REG_BPNPTR
IDT_opdTR
.endm
.macro msyscall
IDT_OPSYSC
.endm
.section misc_macros
.macro mregzero reg
mINPXORU \reg, \reg
.endm
.macro mxchngrg reg1, reg2, temp
IDT_OPXCHG \reg1, \reg2
.endm
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