i2s clock generation and shifting loop

i2s.py

#
# xmit_reg is a Signal(16) as are left_dr and right_dr
#
      self.sync += [                                                
            mclk.eq(~mclk),    # running at 1/2 the clock rate (25MHz)
            # @posedge of MCLK
            If(mclk == 0,       
                If(sticks == 15, 
                    sticks.eq(0),  
                    sclk.eq(~sclk),   
                    # @negedge of SCLK
                    If(sclk == 1,                       
                        shift_count.eq(shift_count + 1),
                        # generate LRCLK      
                        If(shift_count == 15, 
                            shift_count.eq(0),   
                            lrclk.eq(~lrclk),
                        ),
                        # shift out bits
                        If(shift_count == 0,
                            If(lrclk == 1,           
                                xmit_reg.eq(left_dr),
                            ).Else(                   
                                xmit_reg.eq(right_dr),
                            )                     
                        ).Else(
                            xmit_reg.eq((xmit_reg[:-1] << 1) | xmit_reg[-1]),
                        ),
                    ),
                ).Else( sticks.eq(sticks + 1)),
            )
        ]