A sketch of what I'm kind of trying to implement

example.py

#
# "generic" multi-phase clock module
#
from amaranth import *

class SysClock(Elaboratable):
    """
        This builds a clock divider

        Input is a clock, output is a multi-phase
        clock. (instantiated with 4 phases)
 
                  +--+  +--+  +--+  +--+  +--+  
        clk_in:   |  |  |  |  |  |  |  |  |  |
                --+  +--+  +--+  +--+  +--+  +--  
                  +--+                    +--+
        ph0:      |  |                    |  |
                --+  +--------------------+  +--
                        +--+          
        ph1:            |  |         
                --------+  +--------------------
                              +--+    
        ph2:                  |  |    
                --------------+  +---------------
                                    +--+   
        ph3:                        |  |    
                --------------------+  +-----------
    """
    def __init__(self, phases):

        # one signal for each phase
        self.clk = Signal(phases)

    def elaborate(self, clk_in, ph_out):
    """
        Bind the phase outputs to various signals
    """
        m = Module()

        if (len(ph_out) != len(self.clk)):
            print("SysClock: Number of phases doesn't match")
            return None

        # wire up phases
        for i in range(0, len(self.clk)):
            m.d.comb += ph_out[i].eq(self.clk.eq(i))

        m.d.sync += self.clk.eq(self.clk + 1)

# What I would like to be able to do:
#

if (__name__ == "main"):
        c = Clock(2) # 2 phase clock
        p = ICEBreakerPlatfom()
    ph[0] = p.request_resource("pmod1", 0)
        ph[1] = p.request_resource("pmod1", 1)
        m = c.elaborate(p.sysclk,ph)
        ... now my module generates a 2 phase clock on two pins
        ... connector.