patches for linux kernel to get a radeon gpu somewhat working on a raspberry pi

fbdev.patch

From 5f0a783bb2a819e53dea669128fc3508b4296210 Mon Sep 17 00:00:00 2001
From: Coreforge <BC549b@gmail.com>
Date: Thu, 4 Mar 2021 00:05:51 +0100
Subject: [PATCH 2/2] changes to fbdev to remove 64bit accesses (not replaced
 properly yet, just temporary to get it to work. Should only cause every other
 pixel to be missing though, not only every fourth one being present)

---
 drivers/video/fbdev/core/cfbfillrect.c |  5 +++--
 drivers/video/fbdev/core/cfbimgblt.c   | 24 ++++++++++++++++--------
 2 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/video/fbdev/core/cfbfillrect.c b/drivers/video/fbdev/core/cfbfillrect.c
index ba9f58b2a5e8..f809b46cbe3d 100644
--- a/drivers/video/fbdev/core/cfbfillrect.c
+++ b/drivers/video/fbdev/core/cfbfillrect.c
@@ -23,8 +23,9 @@
 #  define FB_WRITEL fb_writel
 #  define FB_READL  fb_readl
 #else
-#  define FB_WRITEL fb_writeq
-#  define FB_READL  fb_readq
+//this is temporary, writeq or two writel without enough delay in between lock up
+#  define FB_WRITEL fb_writel
+#  define FB_READL  fb_readl
 #endif
 
     /*
diff --git a/drivers/video/fbdev/core/cfbimgblt.c b/drivers/video/fbdev/core/cfbimgblt.c
index 436494fba15a..cbb3c4d77c04 100644
--- a/drivers/video/fbdev/core/cfbimgblt.c
+++ b/drivers/video/fbdev/core/cfbimgblt.c
@@ -360,21 +360,29 @@ static inline void fast_imageblit32(const struct fb_image *image,
 		while (j >= 8) {
 			u8 bits = *src;
 			end_mask = tab[(bits >> 7) & 1];
-			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			memset_io(dst++,(end_mask & eorx) ^ bgx,4);
 			end_mask = tab[(bits >> 6) & 1];
-			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			//FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			memset_io(dst++,(end_mask & eorx) ^ bgx,4);
 			end_mask = tab[(bits >> 5) & 1];
-			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			//FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			memset_io(dst++,(end_mask & eorx) ^ bgx,4);
 			end_mask = tab[(bits >> 4) & 1];
-			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			//FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			memset_io(dst++,(end_mask & eorx) ^ bgx,4);
+			//printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 			end_mask = tab[(bits >> 3) & 1];
-			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			//FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			memset_io(dst++,(end_mask & eorx) ^ bgx,4);
 			end_mask = tab[(bits >> 2) & 1];
-			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			//FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			memset_io(dst++,(end_mask & eorx) ^ bgx,4);
 			end_mask = tab[(bits >> 1) & 1];
-			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			//FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			memset_io(dst++,(end_mask & eorx) ^ bgx,4);
 			end_mask = tab[bits & 1];
-			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			//FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
+			memset_io(dst++,(end_mask & eorx) ^ bgx,4);
 			src++;
 			j -= 8;
 		}
-- 
2.25.1

radeon.patch

From caa6a27a9aae7562a9b1885a1d127e6db8124499 Mon Sep 17 00:00:00 2001
From: Coreforge <BC549b@gmail.com>
Date: Wed, 3 Mar 2021 23:57:37 +0100
Subject: [PATCH 1/2] removing some 64bit accesses from the radeon driver to
 get it somewhat working

---
 drivers/gpu/drm/radeon/evergreen.c   |  3 ++-
 drivers/gpu/drm/radeon/radeon_bios.c |  7 +++++-
 drivers/gpu/drm/radeon/radeon_fb.c   | 32 ++++++++++++++++++++++++++--
 3 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 14d90dc376e7..98491726768b 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4955,7 +4955,8 @@ static void evergreen_uvd_init(struct radeon_device *rdev)
 static void evergreen_uvd_start(struct radeon_device *rdev)
 {
 	int r;
-
+	printk("disablign UVD (locks up otherwise)\n");
+	return;
 	if (!rdev->has_uvd)
 		return;
 
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index bb29cf02974d..569f33893b9b 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -101,7 +101,12 @@ static bool radeon_read_bios(struct radeon_device *rdev)
 		pci_unmap_rom(rdev->pdev, bios);
 		return false;
 	}
-	memcpy_fromio(rdev->bios, bios, size);
+	//memcpy_fromio(rdev->bios, bios, size);
+	int pos;
+	for(pos = 0;pos < size; pos++){
+		//memcpy_fromio(rdev->bios+pos,bios+pos,1);
+		rdev->bios[pos] = __raw_readb(bios+pos);
+	}
 	pci_unmap_rom(rdev->pdev, bios);
 	return true;
 }
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index fc4212633bdf..3a15bbb251c5 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -208,6 +208,34 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
 	return ret;
 }
 
+//memset_io with only 32-bit accesses
+void memset_io_pcie(volatile void __iomem *dst, int c, size_t count)
+{
+	u64 qc = (u8)c;
+
+	qc |= qc << 8;
+	qc |= qc << 16;
+	qc |= qc << 32;
+
+	while (count && !IS_ALIGNED((unsigned long)dst, 8)) {
+		__raw_writeb(c, dst);
+		dst++;
+		count--;
+	}
+
+	while (count >= 4) {
+		__raw_writel(qc, dst);
+		dst += 8;
+		count -= 8;
+	}
+
+	while (count) {
+		__raw_writeb(c, dst);
+		dst++;
+		count--;
+	}
+}
+
 static int radeonfb_create(struct drm_fb_helper *helper,
 			   struct drm_fb_helper_surface_size *sizes)
 {
@@ -260,8 +288,8 @@ static int radeonfb_create(struct drm_fb_helper *helper,
 
 	/* setup helper */
 	rfbdev->helper.fb = fb;
-
-	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));
+	//use 32bit accesses
+	memset_io_pcie(rbo->kptr, 0x0, radeon_bo_size(rbo));
 
 	info->fbops = &radeonfb_ops;
 
-- 
2.25.1