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May 25, 2019 23:53
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/* | |
* wiegand_thief.c | |
* | |
*/ | |
#define F_CPU 16000000UL | |
#include <avr/io.h> | |
#include <avr/interrupt.h> | |
#include <stdlib.h> | |
#include <stdio.h> | |
#include <util/delay.h> | |
#define MAX_BUFLEN 255 | |
#define BAUD 9600 // define baud | |
#define BAUDRATE ((F_CPU)/(BAUD*16UL)-1) // set baud rate value for UBRR | |
// function to initialize UART | |
void uart_init (void) | |
{ | |
UBRR0H = (BAUDRATE>>8); // shift the register right by 8 bits | |
UBRR0L = BAUDRATE; // set baud rate | |
UCSR0B|= (1<<TXEN0)|(1<<RXEN0); // enable receiver and transmitter | |
UCSR0C = (3<<UCSZ00); | |
} | |
int uart_transmit(char data ) | |
{ | |
while (!( UCSR0A & (1<<UDRE0))); // wait while register is free | |
UDR0 = data; // load data in the register | |
return 0; | |
} | |
unsigned char uart_receive( void ) | |
{ | |
while ( !(UCSR0A & (1<<RXC0)) ); | |
return UDR0; | |
} | |
int main(void) | |
{ | |
uint8_t buf[255]; | |
uint8_t buflen = 0; | |
uint8_t in_c = 0; | |
uint16_t idle_count = 0; | |
DDRC &= ~((1<<0)|(1<<1)); | |
DDRB |= (1<<5); | |
uart_init(); | |
FILE mystdio = FDEV_SETUP_STREAM(uart_transmit, uart_receive, _FDEV_SETUP_RW); | |
stdout = &mystdio; | |
stdin = &mystdio; | |
_delay_ms(500); | |
PORTB |= (1 << 5); | |
_delay_ms(500); | |
PORTB &= ~(1 << 5); | |
printf("r"); | |
while (1) | |
{ | |
in_c = PINC & 0b11; | |
if(in_c == 0b10) | |
{ | |
buf[buflen++] = 0; | |
while(1) | |
{ | |
in_c = PINC & 0b11; | |
if(in_c == 0b11) | |
{ | |
break; | |
} | |
idle_count = 0; | |
} | |
} | |
else if(in_c == 0b01) | |
{ | |
buf[buflen++] = 1; | |
while(1) | |
{ | |
in_c = PINC & 0b11; | |
if(in_c == 0b11) | |
{ | |
break; | |
} | |
idle_count = 0; | |
} | |
} | |
if(buflen != 0) | |
{ | |
idle_count += 1; | |
} | |
if(idle_count == 0xFFFF && buflen != 0) | |
{ | |
PORTB |= (1 << 5); | |
_delay_ms(500); | |
PORTB &= ~(1 << 5); | |
printf("c"); | |
int i = 0; | |
for(i = 0;i < buflen;i++) | |
{ | |
printf("%d",buf[i]); | |
} | |
printf("r"); | |
idle_count = 0; | |
buflen = 0; | |
} | |
} | |
} |
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